Cargo.toml

@@ -11,7 +11,6 @@ members = [
   "board-tests",
   "bootloader",
   "flashloader",
-  "vorago-shared-periphs",
 ]
 exclude = [
   "flashloader/slot-a-blinky",

bootloader/Cargo.toml

@@ -16,11 +16,9 @@ static_assertions = "1"
 
 [dependencies.va108xx-hal]
 version = "0.11"
-path = "../va108xx-hal"
 
 [dependencies.vorago-reb1]
 version = "0.8"
-path = "../vorago-reb1"
 
 [features]
 default = []

bootloader/src/main.rs

@@ -104,11 +104,11 @@ fn main() -> ! {
         rtt_init_print!();
         rprintln!("-- VA108xx bootloader --");
     }
-    let dp = pac::Peripherals::take().unwrap();
+    let mut dp = pac::Peripherals::take().unwrap();
     let cp = cortex_m::Peripherals::take().unwrap();
-    let mut timer = CountdownTimer::new(CLOCK_FREQ, dp.tim0);
+    let mut timer = CountdownTimer::new(&mut dp.sysconfig, CLOCK_FREQ, dp.tim0);
 
-    let mut nvm = M95M01::new(CLOCK_FREQ, dp.spic);
+    let mut nvm = M95M01::new(&mut dp.sysconfig, CLOCK_FREQ, dp.spic);
 
     if FLASH_SELF {
         let mut first_four_bytes: [u8; 4] = [0; 4];
@@ -186,7 +186,7 @@ fn check_own_crc(
     sysconfig: &pac::Sysconfig,
     cp: &cortex_m::Peripherals,
     nvm: &mut NvmWrapper,
-    timer: &mut CountdownTimer,
+    timer: &mut CountdownTimer<pac::Tim0>,
 ) {
     let crc_exp = unsafe { (BOOTLOADER_CRC_ADDR as *const u16).read_unaligned().to_be() };
     // I'd prefer to use [core::slice::from_raw_parts], but that is problematic
@@ -276,7 +276,7 @@ fn boot_app(
     syscfg: &pac::Sysconfig,
     cp: &cortex_m::Peripherals,
     app_sel: AppSel,
-    timer: &mut CountdownTimer,
+    timer: &mut CountdownTimer<pac::Tim0>,
 ) -> ! {
     if DEBUG_PRINTOUTS && RTT_PRINTOUT {
         rprintln!("booting app {:?}", app_sel);

examples/embassy/Cargo.toml

@@ -29,7 +29,7 @@ embassy-executor = { version = "0.7", features = [
   "executor-interrupt"
 ]}
 
-va108xx-hal = { version = "0.11", path = "../../va108xx-hal", features = ["defmt"] }
+va108xx-hal = { version = "0.11", features = ["defmt"] }
 va108xx-embassy = { version = "0.2" }
 
 [features]

examples/embassy/src/bin/async-gpio.rs

@@ -12,10 +12,11 @@ use embassy_sync::channel::{Receiver, Sender};
 use embassy_sync::{blocking_mutex::raw::ThreadModeRawMutex, channel::Channel};
 use embassy_time::{Duration, Instant, Timer};
 use embedded_hal_async::digital::Wait;
-use va108xx_hal::gpio::asynch::{on_interrupt_for_async_gpio_for_port, InputPinAsync};
-use va108xx_hal::gpio::{Input, Output, PinState, Port};
-use va108xx_hal::pins::{PinsA, PinsB};
+use va108xx_hal::gpio::{
+    on_interrupt_for_async_gpio_for_port, InputDynPinAsync, InputPinAsync, PinsB, Port,
+};
 use va108xx_hal::{
+    gpio::{DynPin, PinsA},
     pac::{self, interrupt},
     prelude::*,
 };
@@ -70,28 +71,30 @@ async fn main(spawner: Spawner) {
         dp.tim22,
     );
 
-    let porta = PinsA::new(dp.porta);
-    let portb = PinsB::new(dp.portb);
-    let mut led0 = Output::new(porta.pa10, PinState::Low);
-    let out_pa0 = Output::new(porta.pa0, PinState::Low);
-    let in_pa1 = Input::new_floating(porta.pa1);
-    let out_pb22 = Output::new(portb.pb22, PinState::Low);
-    let in_pb23 = Input::new_floating(portb.pb23);
+    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let portb = PinsB::new(&mut dp.sysconfig, dp.portb);
+    let mut led0 = porta.pa10.into_readable_push_pull_output();
+    let out_pa0 = porta.pa0.into_readable_push_pull_output();
+    let in_pa1 = porta.pa1.into_floating_input();
+    let out_pb22 = portb.pb22.into_readable_push_pull_output();
+    let in_pb23 = portb.pb23.into_floating_input();
 
     let in_pa1_async = InputPinAsync::new(in_pa1, pac::Interrupt::OC10);
-    let in_pb23_async = InputPinAsync::new(in_pb23, PB22_TO_PB23_IRQ);
+    let out_pa0_dyn = out_pa0.downgrade();
+    let in_pb23_async = InputDynPinAsync::new(in_pb23.downgrade(), PB22_TO_PB23_IRQ).unwrap();
+    let out_pb22_dyn = out_pb22.downgrade();
 
     spawner
         .spawn(output_task(
             "PA0 to PA1",
-            out_pa0,
+            out_pa0_dyn,
             CHANNEL_PA0_PA1.receiver(),
         ))
         .unwrap();
     spawner
         .spawn(output_task(
             "PB22 to PB23",
-            out_pb22,
+            out_pb22_dyn,
             CHANNEL_PB22_TO_PB23.receiver(),
         ))
         .unwrap();
@@ -204,7 +207,7 @@ async fn check_pin_to_pin_async_ops(
 #[embassy_executor::task(pool_size = 2)]
 async fn output_task(
     ctx: &'static str,
-    mut out: Output,
+    mut out: DynPin,
     receiver: Receiver<'static, ThreadModeRawMutex, GpioCmd, 3>,
 ) {
     loop {
@@ -213,25 +216,25 @@ async fn output_task(
         match next_cmd.cmd_type {
             GpioCmdType::SetHigh => {
                 defmt::info!("{}: Set output high", ctx);
-                out.set_high();
+                out.set_high().unwrap();
             }
             GpioCmdType::SetLow => {
                 defmt::info!("{}: Set output low", ctx);
-                out.set_low();
+                out.set_low().unwrap();
             }
             GpioCmdType::RisingEdge => {
                 defmt::info!("{}: Rising edge", ctx);
-                if !out.is_set_low() {
-                    out.set_low();
+                if !out.is_low().unwrap() {
+                    out.set_low().unwrap();
                 }
-                out.set_high();
+                out.set_high().unwrap();
             }
             GpioCmdType::FallingEdge => {
                 defmt::info!("{}: Falling edge", ctx);
-                if !out.is_set_high() {
-                    out.set_high();
+                if !out.is_high().unwrap() {
+                    out.set_high().unwrap();
                 }
-                out.set_low();
+                out.set_low().unwrap();
             }
         }
     }

examples/embassy/src/bin/async-uart-rx.rs

@@ -24,9 +24,8 @@ use embedded_io::Write;
 use embedded_io_async::Read;
 use heapless::spsc::{Consumer, Producer, Queue};
 use va108xx_hal::{
-    gpio::{Output, PinState},
+    gpio::PinsA,
     pac::{self, interrupt},
-    pins::PinsA,
     prelude::*,
     uart::{
         self, on_interrupt_rx_overwriting,
@@ -63,34 +62,34 @@ async fn main(spawner: Spawner) {
         dp.tim22,
     );
 
-    let porta = PinsA::new(dp.porta);
-    let mut led0 = Output::new(porta.pa10, PinState::Low);
-    let mut led1 = Output::new(porta.pa7, PinState::Low);
-    let mut led2 = Output::new(porta.pa6, PinState::Low);
+    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let mut led0 = porta.pa10.into_readable_push_pull_output();
+    let mut led1 = porta.pa7.into_readable_push_pull_output();
+    let mut led2 = porta.pa6.into_readable_push_pull_output();
 
-    let tx_uart_a = porta.pa9;
-    let rx_uart_a = porta.pa8;
+    let tx_uart_a = porta.pa9.into_funsel_2();
+    let rx_uart_a = porta.pa8.into_funsel_2();
 
     let uarta = uart::Uart::new_with_interrupt(
+        &mut dp.sysconfig,
         50.MHz(),
         dp.uarta,
         (tx_uart_a, rx_uart_a),
-        115200.Hz().into(),
+        115200.Hz(),
         InterruptConfig::new(pac::Interrupt::OC2, true, true),
-    )
-    .unwrap();
+    );
 
-    let tx_uart_b = porta.pa3;
-    let rx_uart_b = porta.pa2;
+    let tx_uart_b = porta.pa3.into_funsel_2();
+    let rx_uart_b = porta.pa2.into_funsel_2();
 
     let uartb = uart::Uart::new_with_interrupt(
+        &mut dp.sysconfig,
         50.MHz(),
         dp.uartb,
         (tx_uart_b, rx_uart_b),
-        115200.Hz().into(),
+        115200.Hz(),
         InterruptConfig::new(pac::Interrupt::OC3, true, true),
-    )
-    .unwrap();
+    );
     let (mut tx_uart_a, rx_uart_a) = uarta.split();
     let (tx_uart_b, rx_uart_b) = uartb.split();
     let (prod_uart_a, cons_uart_a) = QUEUE_UART_A.take().split();
@@ -124,7 +123,7 @@ async fn main(spawner: Spawner) {
 }
 
 #[embassy_executor::task]
-async fn uart_b_task(mut async_rx: RxAsyncOverwriting<256>, mut tx: Tx) {
+async fn uart_b_task(mut async_rx: RxAsyncOverwriting<pac::Uartb, 256>, mut tx: Tx<pac::Uartb>) {
     let mut buf = [0u8; 256];
     loop {
         defmt::info!("Current time UART B: {}", Instant::now().as_secs());
@@ -145,7 +144,7 @@ async fn uart_b_task(mut async_rx: RxAsyncOverwriting<256>, mut tx: Tx) {
 fn OC2() {
     let mut prod =
         critical_section::with(|cs| PRODUCER_UART_A.borrow(cs).borrow_mut().take().unwrap());
-    let errors = on_interrupt_rx(Bank::Uart0, &mut prod);
+    let errors = on_interrupt_rx(Bank::A, &mut prod);
     critical_section::with(|cs| *PRODUCER_UART_A.borrow(cs).borrow_mut() = Some(prod));
     // In a production app, we could use a channel to send the errors to the main task.
     if let Err(errors) = errors {
@@ -158,7 +157,7 @@ fn OC2() {
 fn OC3() {
     let mut prod =
         critical_section::with(|cs| PRODUCER_UART_B.borrow(cs).borrow_mut().take().unwrap());
-    let errors = on_interrupt_rx_overwriting(Bank::Uart1, &mut prod, &CONSUMER_UART_B);
+    let errors = on_interrupt_rx_overwriting(Bank::B, &mut prod, &CONSUMER_UART_B);
     critical_section::with(|cs| *PRODUCER_UART_B.borrow(cs).borrow_mut() = Some(prod));
     // In a production app, we could use a channel to send the errors to the main task.
     if let Err(errors) = errors {

examples/embassy/src/bin/async-uart-tx.rs

@@ -17,9 +17,8 @@ use embassy_executor::Spawner;
 use embassy_time::{Duration, Instant, Ticker};
 use embedded_io_async::Write;
 use va108xx_hal::{
-    gpio::{Output, PinState},
+    gpio::PinsA,
     pac::{self, interrupt},
-    pins::PinsA,
     prelude::*,
     uart::{self, on_interrupt_tx, Bank, TxAsync},
     InterruptConfig,
@@ -50,23 +49,22 @@ async fn main(_spawner: Spawner) {
         dp.tim22,
     );
 
-    let porta = PinsA::new(dp.porta);
+    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let mut led0 = porta.pa10.into_readable_push_pull_output();
+    let mut led1 = porta.pa7.into_readable_push_pull_output();
+    let mut led2 = porta.pa6.into_readable_push_pull_output();
 
-    let mut led0 = Output::new(porta.pa10, PinState::Low);
-    let mut led1 = Output::new(porta.pa7, PinState::Low);
-    let mut led2 = Output::new(porta.pa6, PinState::Low);
-
-    let tx = porta.pa9;
-    let rx = porta.pa8;
+    let tx = porta.pa9.into_funsel_2();
+    let rx = porta.pa8.into_funsel_2();
 
     let uarta = uart::Uart::new_with_interrupt(
+        &mut dp.sysconfig,
         50.MHz(),
         dp.uarta,
         (tx, rx),
-        115200.Hz().into(),
+        115200.Hz(),
         InterruptConfig::new(pac::Interrupt::OC2, true, true),
-    )
-    .unwrap();
+    );
     let (tx, _rx) = uarta.split();
     let mut async_tx = TxAsync::new(tx);
     let mut ticker = Ticker::every(Duration::from_secs(1));
@@ -91,5 +89,5 @@ async fn main(_spawner: Spawner) {
 #[interrupt]
 #[allow(non_snake_case)]
 fn OC2() {
-    on_interrupt_tx(Bank::Uart0);
+    on_interrupt_tx(Bank::A);
 }

examples/embassy/src/main.rs

@@ -12,12 +12,7 @@ cfg_if::cfg_if! {
     }
 }
 
-use va108xx_hal::{
-    gpio::{Output, PinState},
-    pac,
-    pins::PinsA,
-    prelude::*,
-};
+use va108xx_hal::{gpio::PinsA, pac, prelude::*};
 
 const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
 
@@ -40,6 +35,8 @@ async fn main(_spawner: Spawner) {
             );
         } else {
             va108xx_embassy::init_with_custom_irqs(
+                &mut dp.sysconfig,
+                &dp.irqsel,
                 SYSCLK_FREQ,
                 dp.tim23,
                 dp.tim22,
@@ -49,10 +46,10 @@ async fn main(_spawner: Spawner) {
         }
     }
 
-    let porta = PinsA::new(dp.porta);
-    let mut led0 = Output::new(porta.pa10, PinState::Low);
-    let mut led1 = Output::new(porta.pa7, PinState::Low);
-    let mut led2 = Output::new(porta.pa6, PinState::Low);
+    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let mut led0 = porta.pa10.into_readable_push_pull_output();
+    let mut led1 = porta.pa7.into_readable_push_pull_output();
+    let mut led2 = porta.pa6.into_readable_push_pull_output();
     let mut ticker = Ticker::every(Duration::from_secs(1));
     loop {
         ticker.next().await;

examples/rtic/Cargo.toml

@@ -8,9 +8,8 @@ cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7"
 embedded-hal = "1"
 embedded-io = "0.6"
-defmt-rtt = "0.4"
-defmt = "1"
-panic-probe = { version = "1", features = ["defmt"] }
+rtt-target = "0.6"
+panic-rtt-target = "0.2"
 
 # Even though we do not use this directly, we need to activate this feature explicitely
 # so that RTIC compiles because thumv6 does not have CAS operations natively.
@@ -23,5 +22,5 @@ rtic-sync = { version = "1.3", features = ["defmt-03"] }
 once_cell = {version = "1", default-features = false, features = ["critical-section"]}
 ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
 
-va108xx-hal = { version = "0.11", path = "../../va108xx-hal" }
-vorago-reb1 = { version = "0.8", path = "../../vorago-reb1" }
+va108xx-hal = { version = "0.11" }
+vorago-reb1 = { version = "0.8" }

examples/rtic/src/bin/blinky-button-rtic.rs

@@ -4,29 +4,34 @@
 
 #[rtic::app(device = pac)]
 mod app {
+    use panic_rtt_target as _;
     use rtic_example::SYSCLK_FREQ;
-    // Import panic provider.
-    use panic_probe as _;
-    // Import global logger.
-    use defmt_rtt as _;
+    use rtt_target::{rprintln, rtt_init_default, set_print_channel};
     use va108xx_hal::{
         clock::{set_clk_div_register, FilterClkSel},
-        gpio::{FilterType, InterruptEdge},
+        gpio::{FilterType, InterruptEdge, PinsA},
         pac,
-        pins::PinsA,
-        timer::InterruptConfig,
+        prelude::*,
+        timer::{default_ms_irq_handler, set_up_ms_tick, InterruptConfig},
     };
     use vorago_reb1::button::Button;
     use vorago_reb1::leds::Leds;
 
     rtic_monotonics::systick_monotonic!(Mono, 1_000);
 
-    #[derive(Debug, PartialEq, defmt::Format)]
+    #[derive(Debug, PartialEq)]
     pub enum PressMode {
         Toggle,
         Keep,
     }
 
+    #[derive(Debug, PartialEq)]
+    pub enum CfgMode {
+        Prompt,
+        Fixed,
+    }
+
+    const CFG_MODE: CfgMode = CfgMode::Fixed;
     // You can change the press mode here
     const DEFAULT_MODE: PressMode = PressMode::Toggle;
 
@@ -42,35 +47,53 @@ mod app {
 
     #[init]
     fn init(cx: init::Context) -> (Shared, Local) {
-        defmt::println!("-- Vorago Button IRQ Example --");
+        let channels = rtt_init_default!();
+        set_print_channel(channels.up.0);
+        rprintln!("-- Vorago Button IRQ Example --");
         Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
 
-        let mode = DEFAULT_MODE;
-        defmt::info!("Using {:?} mode", mode);
+        let mode = match CFG_MODE {
+            // Ask mode from user via RTT
+            CfgMode::Prompt => prompt_mode(channels.down.0),
+            // Use mode hardcoded in `DEFAULT_MODE`
+            CfgMode::Fixed => DEFAULT_MODE,
+        };
+        rprintln!("Using {:?} mode", mode);
 
         let mut dp = cx.device;
-        let pinsa = PinsA::new(dp.porta);
+        let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
         let edge_irq = match mode {
             PressMode::Toggle => InterruptEdge::HighToLow,
             PressMode::Keep => InterruptEdge::BothEdges,
         };
 
         // Configure an edge interrupt on the button and route it to interrupt vector 15
-        let mut button = Button::new(pinsa.pa11);
+        let mut button = Button::new(pinsa.pa11.into_floating_input());
 
         if mode == PressMode::Toggle {
             // This filter debounces the switch for edge based interrupts
-            button.configure_filter_type(FilterType::FilterFourCycles, FilterClkSel::Clk1);
+            button.configure_filter_type(FilterType::FilterFourClockCycles, FilterClkSel::Clk1);
             set_clk_div_register(&mut dp.sysconfig, FilterClkSel::Clk1, 50_000);
         }
         button.configure_and_enable_edge_interrupt(
             edge_irq,
             InterruptConfig::new(pac::interrupt::OC15, true, true),
         );
-        let mut leds = Leds::new(pinsa.pa10, pinsa.pa7, pinsa.pa6);
+        let mut leds = Leds::new(
+            pinsa.pa10.into_push_pull_output(),
+            pinsa.pa7.into_push_pull_output(),
+            pinsa.pa6.into_push_pull_output(),
+        );
         for led in leds.iter_mut() {
             led.off();
         }
+        set_up_ms_tick(
+            InterruptConfig::new(pac::Interrupt::OC0, true, true),
+            &mut dp.sysconfig,
+            Some(&mut dp.irqsel),
+            50.MHz(),
+            dp.tim0,
+        );
         (Shared {}, Local { leds, button, mode })
     }
 
@@ -95,4 +118,26 @@ mod app {
             leds[0].on();
         }
     }
+
+    #[task(binds = OC0)]
+    fn ms_tick(_cx: ms_tick::Context) {
+        default_ms_irq_handler();
+    }
+
+    fn prompt_mode(mut down_channel: rtt_target::DownChannel) -> PressMode {
+        rprintln!("Using prompt mode");
+        rprintln!("Please enter the mode [0: Toggle, 1: Keep]");
+        let mut read_buf: [u8; 16] = [0; 16];
+        let mut read;
+        loop {
+            read = down_channel.read(&mut read_buf);
+            for &byte in &read_buf[..read] {
+                match byte as char {
+                    '0' => return PressMode::Toggle,
+                    '1' => return PressMode::Keep,
+                    _ => continue, // Ignore other characters
+                }
+            }
+        }
+    }
 }

examples/rtic/src/bin/rtic-empty.rs

@@ -4,10 +4,8 @@
 
 #[rtic::app(device = pac)]
 mod app {
-    // Import panic provider.
-    use panic_probe as _;
-    // Import global logger.
-    use defmt_rtt as _;
+    use panic_rtt_target as _;
+    use rtt_target::{rprintln, rtt_init_default};
     use va108xx_hal::pac;
 
     #[local]
@@ -18,7 +16,8 @@ mod app {
 
     #[init]
     fn init(_ctx: init::Context) -> (Shared, Local) {
-        defmt::println!("-- Vorago RTIC template --");
+        rtt_init_default!();
+        rprintln!("-- Vorago RTIC template --");
         (Shared {}, Local {})
     }
 

examples/rtic/src/bin/uart-echo-rtic.rs

@@ -1,4 +1,4 @@
-//! More complex UART application on UART PA8 (TX) and PA9 (RX).
+//! More complex UART application
 //!
 //! Uses the IRQ capabilities of the VA10820 peripheral and the RTIC framework to poll the UART in
 //! a non-blocking way. All received data will be sent back to the sender.
@@ -14,16 +14,14 @@ const RX_RING_BUF_SIZE: usize = 1024;
 mod app {
     use super::*;
     use embedded_io::Write;
+    use panic_rtt_target as _;
     use ringbuf::traits::{Consumer, Observer, Producer};
     use rtic_example::SYSCLK_FREQ;
-    // Import panic provider.
-    use panic_probe as _;
-    // Import global logger.
-    use defmt_rtt as _;
     use rtic_monotonics::Monotonic;
+    use rtt_target::{rprintln, rtt_init_print};
     use va108xx_hal::{
+        gpio::PinsA,
         pac,
-        pins::PinsA,
         prelude::*,
         uart::{self, RxWithInterrupt, Tx},
         InterruptConfig,
@@ -31,8 +29,8 @@ mod app {
 
     #[local]
     struct Local {
-        rx: RxWithInterrupt,
-        tx: Tx,
+        rx: RxWithInterrupt<pac::Uarta>,
+        tx: Tx<pac::Uarta>,
     }
 
     #[shared]
@@ -44,23 +42,24 @@ mod app {
 
     #[init]
     fn init(cx: init::Context) -> (Shared, Local) {
-        defmt::println!("-- VA108xx UART Echo with IRQ example application--");
+        rtt_init_print!();
+        rprintln!("-- VA108xx UART Echo with IRQ example application--");
 
         Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
 
-        let dp = cx.device;
-        let gpioa = PinsA::new(dp.porta);
-        let tx = gpioa.pa9;
-        let rx = gpioa.pa8;
+        let mut dp = cx.device;
+        let gpioa = PinsA::new(&mut dp.sysconfig, dp.porta);
+        let tx = gpioa.pa9.into_funsel_2();
+        let rx = gpioa.pa8.into_funsel_2();
 
         let irq_uart = uart::Uart::new_with_interrupt(
+            &mut dp.sysconfig,
             SYSCLK_FREQ,
             dp.uarta,
             (tx, rx),
-            115200.Hz().into(),
+            115200.Hz(),
             InterruptConfig::new(pac::Interrupt::OC3, true, true),
-        )
-        .unwrap();
+        );
         let (tx, rx) = irq_uart.split();
         let mut rx = rx.into_rx_with_irq();
 
@@ -105,7 +104,7 @@ mod app {
         }
         if ringbuf_full {
             // Could also drop oldest data, but that would require the consumer to be shared.
-            defmt::println!("buffer full, data was dropped");
+            rprintln!("buffer full, data was dropped");
         }
     }
 

examples/rtic/src/main.rs

@@ -5,24 +5,21 @@
 #[rtic::app(device = pac, dispatchers = [OC31, OC30, OC29])]
 mod app {
     use cortex_m::asm;
+    use panic_rtt_target as _;
     use rtic_example::SYSCLK_FREQ;
     use rtic_monotonics::systick::prelude::*;
     use rtic_monotonics::Monotonic;
-    // Import panic provider.
-    use panic_probe as _;
-    // Import global logger.
-    use defmt_rtt as _;
+    use rtt_target::{rprintln, rtt_init_print};
     use va108xx_hal::{
-        gpio::{Output, PinState},
+        gpio::{OutputReadablePushPull, Pin, PinsA, PA10, PA6, PA7},
         pac,
-        pins::PinsA,
     };
 
     #[local]
     struct Local {
-        led0: Output,
-        led1: Output,
-        led2: Output,
+        led0: Pin<PA10, OutputReadablePushPull>,
+        led1: Pin<PA7, OutputReadablePushPull>,
+        led2: Pin<PA6, OutputReadablePushPull>,
     }
 
     #[shared]
@@ -31,15 +28,16 @@ mod app {
     rtic_monotonics::systick_monotonic!(Mono, 1_000);
 
     #[init]
-    fn init(cx: init::Context) -> (Shared, Local) {
-        defmt::println!("-- Vorago VA108xx RTIC template --");
+    fn init(mut cx: init::Context) -> (Shared, Local) {
+        rtt_init_print!();
+        rprintln!("-- Vorago VA108xx RTIC template --");
 
         Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
 
-        let porta = PinsA::new(cx.device.porta);
-        let led0 = Output::new(porta.pa10, PinState::Low);
-        let led1 = Output::new(porta.pa7, PinState::Low);
-        let led2 = Output::new(porta.pa6, PinState::Low);
+        let porta = PinsA::new(&mut cx.device.sysconfig, cx.device.porta);
+        let led0 = porta.pa10.into_readable_push_pull_output();
+        let led1 = porta.pa7.into_readable_push_pull_output();
+        let led2 = porta.pa6.into_readable_push_pull_output();
         blinky::spawn().ok();
         (Shared {}, Local { led0, led1, led2 })
     }
@@ -58,7 +56,7 @@ mod app {
     )]
     async fn blinky(cx: blinky::Context) {
         loop {
-            defmt::println!("toggling LEDs");
+            rprintln!("toggling LEDs");
             cx.local.led0.toggle();
             cx.local.led1.toggle();
             cx.local.led2.toggle();

examples/simple/Cargo.toml

@@ -7,21 +7,17 @@ edition = "2021"
 cortex-m = {version = "0.7", features = ["critical-section-single-core"]}
 cortex-m-rt = "0.7"
 panic-halt = "1"
+panic-rtt-target = "0.2"
 critical-section = "1"
-defmt-rtt = "0.4"
-defmt = "1"
-panic-probe = { version = "1", features = ["defmt"] }
+rtt-target = "0.6"
 embedded-hal = "1"
 embedded-hal-nb = "1"
 embedded-io = "0.6"
 cortex-m-semihosting = "0.5.0"
-portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
 
 [dependencies.va108xx-hal]
 version = "0.11"
-path = "../../va108xx-hal"
 features = ["defmt"]
 
 [dependencies.vorago-reb1]
-path = "../../vorago-reb1"
 version = "0.8"

examples/simple/examples/blinky.rs

@@ -10,37 +10,52 @@ use cortex_m_rt::entry;
 use embedded_hal::delay::DelayNs;
 use panic_halt as _;
 use va108xx_hal::{
-    gpio::{Output, PinState},
-    pac::{self},
-    pins::PinsA,
+    gpio::PinsA,
+    pac::{self, interrupt},
     prelude::*,
-    timer::CountdownTimer,
+    timer::DelayMs,
+    timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer},
+    InterruptConfig,
 };
 
 #[entry]
 fn main() -> ! {
-    let dp = pac::Peripherals::take().unwrap();
-    let mut delay = CountdownTimer::new(50.MHz(), dp.tim1);
-    let porta = PinsA::new(dp.porta);
-    let mut led1 = Output::new(porta.pa10, PinState::Low);
-    let mut led2 = Output::new(porta.pa7, PinState::Low);
-    let mut led3 = Output::new(porta.pa6, PinState::Low);
+    let mut dp = pac::Peripherals::take().unwrap();
+    let mut delay_ms = DelayMs::new(set_up_ms_tick(
+        InterruptConfig::new(interrupt::OC0, true, true),
+        &mut dp.sysconfig,
+        Some(&mut dp.irqsel),
+        50.MHz(),
+        dp.tim0,
+    ))
+    .unwrap();
+    let mut delay_tim1 = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim1);
+    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let mut led1 = porta.pa10.into_readable_push_pull_output();
+    let mut led2 = porta.pa7.into_readable_push_pull_output();
+    let mut led3 = porta.pa6.into_readable_push_pull_output();
     for _ in 0..10 {
         led1.set_low();
         led2.set_low();
         led3.set_low();
-        delay.delay_ms(200);
+        delay_ms.delay_ms(200);
         led1.set_high();
         led2.set_high();
         led3.set_high();
-        delay.delay_ms(200);
+        delay_tim1.delay_ms(200);
     }
     loop {
         led1.toggle();
-        delay.delay_ms(200);
+        delay_ms.delay_ms(200);
         led2.toggle();
-        delay.delay_ms(200);
+        delay_tim1.delay_ms(200);
         led3.toggle();
-        delay.delay_ms(200);
+        delay_ms.delay_ms(200);
     }
 }
+
+#[interrupt]
+#[allow(non_snake_case)]
+fn OC0() {
+    default_ms_irq_handler()
+}

examples/simple/examples/cascade.rs

@@ -10,33 +10,43 @@ use core::cell::RefCell;
 use cortex_m::interrupt::Mutex;
 use cortex_m_rt::entry;
 use embedded_hal::delay::DelayNs;
-// Import panic provider.
-use panic_probe as _;
-// Import logger.
-use defmt_rtt as _;
+use panic_rtt_target as _;
+use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{
     pac::{self, interrupt},
     prelude::*,
-    timer::{CascadeCtrl, CascadeSource, CountdownTimer, InterruptConfig},
+    timer::{
+        default_ms_irq_handler, set_up_ms_delay_provider, CascadeCtrl, CascadeSource,
+        CountdownTimer, Event, InterruptConfig,
+    },
 };
 
-static CSD_TGT_1: Mutex<RefCell<Option<CountdownTimer>>> = Mutex::new(RefCell::new(None));
-static CSD_TGT_2: Mutex<RefCell<Option<CountdownTimer>>> = Mutex::new(RefCell::new(None));
+static CSD_TGT_1: Mutex<RefCell<Option<CountdownTimer<pac::Tim4>>>> =
+    Mutex::new(RefCell::new(None));
+static CSD_TGT_2: Mutex<RefCell<Option<CountdownTimer<pac::Tim5>>>> =
+    Mutex::new(RefCell::new(None));
 
 #[entry]
 fn main() -> ! {
-    defmt::println!("-- VA108xx Cascade example application--");
+    rtt_init_print!();
+    rprintln!("-- VA108xx Cascade example application--");
 
-    let dp = pac::Peripherals::take().unwrap();
-    let mut delay = CountdownTimer::new(50.MHz(), dp.tim0);
+    let mut dp = pac::Peripherals::take().unwrap();
+    let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
 
     // Will be started periodically to trigger a cascade
-    let mut cascade_triggerer = CountdownTimer::new(50.MHz(), dp.tim3).auto_disable(true);
-    cascade_triggerer.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC1, true, false));
-    cascade_triggerer.enable();
+    let mut cascade_triggerer =
+        CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim3).auto_disable(true);
+    cascade_triggerer.listen(
+        Event::TimeOut,
+        InterruptConfig::new(pac::Interrupt::OC1, true, false),
+        Some(&mut dp.irqsel),
+        Some(&mut dp.sysconfig),
+    );
 
     // First target for cascade
-    let mut cascade_target_1 = CountdownTimer::new(50.MHz(), dp.tim4).auto_deactivate(true);
+    let mut cascade_target_1 =
+        CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim4).auto_deactivate(true);
     cascade_target_1
         .cascade_0_source(CascadeSource::Tim(3))
         .expect("Configuring cascade source for TIM4 failed");
@@ -50,13 +60,19 @@ fn main() -> ! {
     // Normally it should already be sufficient to activate IRQ in the CTRL
     // register but a full interrupt is use here to display print output when
     // the timer expires
-    cascade_target_1.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC2, true, false));
+    cascade_target_1.listen(
+        Event::TimeOut,
+        InterruptConfig::new(pac::Interrupt::OC2, true, false),
+        Some(&mut dp.irqsel),
+        Some(&mut dp.sysconfig),
+    );
     // The counter will only activate when the cascade signal is coming in so
     // it is okay to call start here to set the reset value
     cascade_target_1.start(1.Hz());
 
     // Activated by first cascade target
-    let mut cascade_target_2 = CountdownTimer::new(50.MHz(), dp.tim5).auto_deactivate(true);
+    let mut cascade_target_2 =
+        CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim5).auto_deactivate(true);
     // Set TIM4 as cascade source
     cascade_target_2
         .cascade_1_source(CascadeSource::Tim(4))
@@ -70,7 +86,12 @@ fn main() -> ! {
     // Normally it should already be sufficient to activate IRQ in the CTRL
     // register but a full interrupt is use here to display print output when
     // the timer expires
-    cascade_target_2.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC3, true, false));
+    cascade_target_2.listen(
+        Event::TimeOut,
+        InterruptConfig::new(pac::Interrupt::OC3, true, false),
+        Some(&mut dp.irqsel),
+        Some(&mut dp.sysconfig),
+    );
     // The counter will only activate when the cascade signal is coming in so
     // it is okay to call start here to set the reset value
     cascade_target_2.start(1.Hz());
@@ -88,29 +109,34 @@ fn main() -> ! {
         CSD_TGT_2.borrow(cs).replace(Some(cascade_target_2));
     });
     loop {
-        defmt::info!("-- Triggering cascade in 0.5 seconds --");
+        rprintln!("-- Triggering cascade in 0.5 seconds --");
         cascade_triggerer.start(2.Hz());
         delay.delay_ms(5000);
     }
 }
 
+#[interrupt]
+fn OC0() {
+    default_ms_irq_handler()
+}
+
 #[interrupt]
 fn OC1() {
     static mut IDX: u32 = 0;
-    defmt::info!("{}: Cascade triggered timed out", &IDX);
+    rprintln!("{}: Cascade triggered timed out", &IDX);
     *IDX += 1;
 }
 
 #[interrupt]
 fn OC2() {
     static mut IDX: u32 = 0;
-    defmt::info!("{}: First cascade target timed out", &IDX);
+    rprintln!("{}: First cascade target timed out", &IDX);
     *IDX += 1;
 }
 
 #[interrupt]
 fn OC3() {
     static mut IDX: u32 = 0;
-    defmt::info!("{}: Second cascade target timed out", &IDX);
+    rprintln!("{}: Second cascade target timed out", &IDX);
     *IDX += 1;
 }

examples/simple/examples/pwm.rs

@@ -1,36 +1,39 @@
 //! Simple PWM example
-//!
-//! Outputs a PWM waveform on pin PA3.
 #![no_main]
 #![no_std]
 
 use cortex_m_rt::entry;
 use embedded_hal::{delay::DelayNs, pwm::SetDutyCycle};
-// Import panic provider.
-use panic_probe as _;
-// Import logger.
-use defmt_rtt as _;
+use panic_rtt_target as _;
+use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{
+    gpio::PinsA,
     pac,
-    pins::PinsA,
     prelude::*,
-    pwm::{self, get_duty_from_percent, PwmA, PwmB, PwmPin},
-    timer::CountdownTimer,
+    pwm::{self, get_duty_from_percent, PwmA, PwmB, ReducedPwmPin},
+    timer::set_up_ms_delay_provider,
 };
 
 #[entry]
 fn main() -> ! {
-    defmt::println!("-- VA108xx PWM example application--");
-    let dp = pac::Peripherals::take().unwrap();
-    let pinsa = PinsA::new(dp.porta);
-    let mut pwm = pwm::PwmPin::new(50.MHz(), (pinsa.pa3, dp.tim3), 10.Hz()).unwrap();
-    let mut delay = CountdownTimer::new(50.MHz(), dp.tim0);
+    rtt_init_print!();
+    rprintln!("-- VA108xx PWM example application--");
+    let mut dp = pac::Peripherals::take().unwrap();
+    let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let mut pwm = pwm::PwmPin::new(
+        &mut dp.sysconfig,
+        50.MHz(),
+        (pinsa.pa3.into_funsel_1(), dp.tim3),
+        10.Hz(),
+    );
+    let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
     let mut current_duty_cycle = 0.0;
     pwm.set_duty_cycle(get_duty_from_percent(current_duty_cycle))
         .unwrap();
     pwm.enable();
 
     // Delete type information, increased code readibility for the rest of the code
+    let mut reduced_pin = ReducedPwmPin::from(pwm);
     loop {
         let mut counter = 0;
         // Increase duty cycle continuously
@@ -39,10 +42,11 @@ fn main() -> ! {
             current_duty_cycle += 0.02;
             counter += 1;
             if counter % 10 == 0 {
-                defmt::info!("current duty cycle: {}", current_duty_cycle);
+                rprintln!("current duty cycle: {}", current_duty_cycle);
             }
 
-            pwm.set_duty_cycle(get_duty_from_percent(current_duty_cycle))
+            reduced_pin
+                .set_duty_cycle(get_duty_from_percent(current_duty_cycle))
                 .unwrap();
         }
 
@@ -51,7 +55,7 @@ fn main() -> ! {
         current_duty_cycle = 0.0;
         let mut upper_limit = 1.0;
         let mut lower_limit = 0.0;
-        let mut pwmb: PwmPin<PwmB> = PwmPin::from(pwm);
+        let mut pwmb: ReducedPwmPin<PwmB> = ReducedPwmPin::from(reduced_pin);
         pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit));
         pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit));
         while lower_limit < 0.5 {
@@ -60,9 +64,9 @@ fn main() -> ! {
             upper_limit -= 0.01;
             pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit));
             pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit));
-            defmt::info!("Lower limit: {}", pwmb.pwmb_lower_limit());
-            defmt::info!("Upper limit: {}", pwmb.pwmb_upper_limit());
+            rprintln!("Lower limit: {}", pwmb.pwmb_lower_limit());
+            rprintln!("Upper limit: {}", pwmb.pwmb_upper_limit());
         }
-        pwm = PwmPin::<PwmA>::from(pwmb);
+        reduced_pin = ReducedPwmPin::<PwmA>::from(pwmb);
     }
 }

examples/simple/examples/rtt-log.rs

@@ -0,0 +1,20 @@
+//! Code to test RTT logger functionality
+#![no_main]
+#![no_std]
+
+use cortex_m_rt::entry;
+use panic_rtt_target as _;
+use rtt_target::{rprintln, rtt_init_print};
+use va108xx_hal as _;
+
+#[entry]
+fn main() -> ! {
+    rtt_init_print!();
+    rprintln!("-- VA108XX RTT example --");
+    let mut counter = 0;
+    loop {
+        rprintln!("{}: Hello, world!", counter);
+        counter += 1;
+        cortex_m::asm::delay(25_000_000);
+    }
+}

examples/simple/examples/spi.rs

@@ -1,21 +1,23 @@
 //! SPI example application
 #![no_main]
 #![no_std]
+
+use core::cell::RefCell;
+
 use cortex_m_rt::entry;
 use embedded_hal::{
     delay::DelayNs,
     spi::{Mode, SpiBus, MODE_0},
 };
-// Import panic provider.
-use panic_probe as _;
-// Import logger.
-use defmt_rtt as _;
+use panic_rtt_target as _;
+use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{
-    pac,
-    pins::{PinsA, PinsB},
+    gpio::{PinsA, PinsB},
+    pac::{self, interrupt},
     prelude::*,
-    spi::{self, configure_pin_as_hw_cs_pin, Spi, SpiClkConfig, TransferConfig},
-    timer::CountdownTimer,
+    spi::{self, Spi, SpiBase, SpiClkConfig, TransferConfigWithHwcs},
+    timer::{default_ms_irq_handler, set_up_ms_tick},
+    InterruptConfig,
 };
 
 #[derive(PartialEq, Debug)]
@@ -41,14 +43,23 @@ const FILL_WORD: u8 = 0x0f;
 
 #[entry]
 fn main() -> ! {
-    defmt::println!("-- VA108xx SPI example application--");
-    let dp = pac::Peripherals::take().unwrap();
-    let mut delay = CountdownTimer::new(50.MHz(), dp.tim0);
+    rtt_init_print!();
+    rprintln!("-- VA108xx SPI example application--");
+    let mut dp = pac::Peripherals::take().unwrap();
+    let mut delay = set_up_ms_tick(
+        InterruptConfig::new(interrupt::OC0, true, true),
+        &mut dp.sysconfig,
+        Some(&mut dp.irqsel),
+        50.MHz(),
+        dp.tim0,
+    );
 
     let spi_clk_cfg = SpiClkConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz())
         .expect("creating SPI clock config failed");
-    let pinsa = PinsA::new(dp.porta);
-    let pinsb = PinsB::new(dp.portb);
+    let spia_ref: RefCell<Option<SpiBase<pac::Spia, u8>>> = RefCell::new(None);
+    let spib_ref: RefCell<Option<SpiBase<pac::Spib, u8>>> = RefCell::new(None);
+    let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let pinsb = PinsB::new(&mut dp.sysconfig, dp.portb);
 
     let mut spi_cfg = spi::SpiConfig::default();
     if EXAMPLE_SEL == ExampleSelect::Loopback {
@@ -56,82 +67,158 @@ fn main() -> ! {
     }
 
     // Set up the SPI peripheral
-    let mut spi = match SPI_BUS_SEL {
+    match SPI_BUS_SEL {
         SpiBusSelect::SpiAPortA => {
-            let (sck, mosi, miso) = (pinsa.pa31, pinsa.pa30, pinsa.pa29);
-            let mut spia = Spi::new(50.MHz(), dp.spia, (sck, miso, mosi), spi_cfg).unwrap();
+            let (sck, mosi, miso) = (
+                pinsa.pa31.into_funsel_1(),
+                pinsa.pa30.into_funsel_1(),
+                pinsa.pa29.into_funsel_1(),
+            );
+            let mut spia = Spi::new(
+                &mut dp.sysconfig,
+                50.MHz(),
+                dp.spia,
+                (sck, miso, mosi),
+                spi_cfg,
+            );
             spia.set_fill_word(FILL_WORD);
-            spia
+            spia_ref.borrow_mut().replace(spia.downgrade());
         }
         SpiBusSelect::SpiAPortB => {
-            let (sck, mosi, miso) = (pinsb.pb9, pinsb.pb8, pinsb.pb7);
-            let mut spia = Spi::new(50.MHz(), dp.spia, (sck, miso, mosi), spi_cfg).unwrap();
+            let (sck, mosi, miso) = (
+                pinsb.pb9.into_funsel_2(),
+                pinsb.pb8.into_funsel_2(),
+                pinsb.pb7.into_funsel_2(),
+            );
+            let mut spia = Spi::new(
+                &mut dp.sysconfig,
+                50.MHz(),
+                dp.spia,
+                (sck, miso, mosi),
+                spi_cfg,
+            );
             spia.set_fill_word(FILL_WORD);
-            spia
+            spia_ref.borrow_mut().replace(spia.downgrade());
         }
         SpiBusSelect::SpiBPortB => {
-            let (sck, mosi, miso) = (pinsb.pb5, pinsb.pb4, pinsb.pb3);
-            let mut spib = Spi::new(50.MHz(), dp.spib, (sck, miso, mosi), spi_cfg).unwrap();
+            let (sck, mosi, miso) = (
+                pinsb.pb5.into_funsel_1(),
+                pinsb.pb4.into_funsel_1(),
+                pinsb.pb3.into_funsel_1(),
+            );
+            let mut spib = Spi::new(
+                &mut dp.sysconfig,
+                50.MHz(),
+                dp.spib,
+                (sck, miso, mosi),
+                spi_cfg,
+            );
             spib.set_fill_word(FILL_WORD);
-            spib
+            spib_ref.borrow_mut().replace(spib.downgrade());
         }
-    };
+    }
     // Configure transfer specific properties here
     match SPI_BUS_SEL {
         SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
-            let transfer_cfg = TransferConfig {
-                clk_cfg: Some(spi_clk_cfg),
-                mode: Some(SPI_MODE),
-                sod: true,
-                blockmode: BLOCKMODE,
-                bmstall: true,
-                hw_cs: None,
-            };
-            spi.cfg_transfer(&transfer_cfg);
+            if let Some(ref mut spi) = *spia_ref.borrow_mut() {
+                let transfer_cfg = TransferConfigWithHwcs::new_no_hw_cs(
+                    Some(spi_clk_cfg),
+                    Some(SPI_MODE),
+                    BLOCKMODE,
+                    true,
+                    false,
+                );
+                spi.cfg_transfer(&transfer_cfg);
+            }
         }
         SpiBusSelect::SpiBPortB => {
-            let hw_cs_pin = configure_pin_as_hw_cs_pin(pinsb.pb2);
-            let transfer_cfg = TransferConfig {
-                clk_cfg: Some(spi_clk_cfg),
-                mode: Some(SPI_MODE),
-                sod: false,
-                blockmode: BLOCKMODE,
-                bmstall: true,
-                hw_cs: Some(hw_cs_pin),
-            };
-            spi.cfg_transfer(&transfer_cfg);
+            if let Some(ref mut spi) = *spib_ref.borrow_mut() {
+                let hw_cs_pin = pinsb.pb2.into_funsel_1();
+                let transfer_cfg = TransferConfigWithHwcs::new(
+                    Some(spi_clk_cfg),
+                    Some(SPI_MODE),
+                    Some(hw_cs_pin),
+                    BLOCKMODE,
+                    true,
+                    false,
+                );
+                spi.cfg_transfer(&transfer_cfg);
+            }
         }
     }
 
     // Application logic
     loop {
         let mut reply_buf: [u8; 8] = [0; 8];
-        // Can't really verify correct reply here.
-        spi.write(&[0x42]).expect("write failed");
-        // Because of the loopback mode, we should get back the fill word here.
-        spi.read(&mut reply_buf[0..1]).unwrap();
-        assert_eq!(reply_buf[0], FILL_WORD);
-        delay.delay_ms(500_u32);
+        match SPI_BUS_SEL {
+            SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
+                if let Some(ref mut spi) = *spia_ref.borrow_mut() {
+                    // Can't really verify correct reply here.
+                    spi.write(&[0x42]).expect("write failed");
+                    // Because of the loopback mode, we should get back the fill word here.
+                    spi.read(&mut reply_buf[0..1]).unwrap();
+                    assert_eq!(reply_buf[0], FILL_WORD);
+                    delay.delay_ms(500_u32);
 
-        let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
-        spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
-        assert_eq!(tx_buf, reply_buf[0..3]);
-        defmt::info!(
-            "Received reply: {}, {}, {}",
-            reply_buf[0],
-            reply_buf[1],
-            reply_buf[2]
-        );
-        delay.delay_ms(500_u32);
+                    let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
+                    spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
+                    assert_eq!(tx_buf, reply_buf[0..3]);
+                    rprintln!(
+                        "Received reply: {}, {}, {}",
+                        reply_buf[0],
+                        reply_buf[1],
+                        reply_buf[2]
+                    );
+                    delay.delay_ms(500_u32);
 
-        let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
-        spi.transfer_in_place(&mut tx_rx_buf).unwrap();
-        defmt::info!(
-            "Received reply: {}, {}, {}",
-            tx_rx_buf[0],
-            tx_rx_buf[1],
-            tx_rx_buf[2]
-        );
-        assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
+                    let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
+                    spi.transfer_in_place(&mut tx_rx_buf).unwrap();
+                    rprintln!(
+                        "Received reply: {}, {}, {}",
+                        tx_rx_buf[0],
+                        tx_rx_buf[1],
+                        tx_rx_buf[2]
+                    );
+                    assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
+                }
+            }
+            SpiBusSelect::SpiBPortB => {
+                if let Some(ref mut spi) = *spib_ref.borrow_mut() {
+                    // Can't really verify correct reply here.
+                    spi.write(&[0x42]).expect("write failed");
+                    // Because of the loopback mode, we should get back the fill word here.
+                    spi.read(&mut reply_buf[0..1]).unwrap();
+                    assert_eq!(reply_buf[0], FILL_WORD);
+                    delay.delay_ms(500_u32);
+
+                    let tx_buf: [u8; 3] = [0x01, 0x02, 0x03];
+                    spi.transfer(&mut reply_buf[0..3], &tx_buf).unwrap();
+                    assert_eq!(tx_buf, reply_buf[0..3]);
+                    rprintln!(
+                        "Received reply: {}, {}, {}",
+                        reply_buf[0],
+                        reply_buf[1],
+                        reply_buf[2]
+                    );
+                    delay.delay_ms(500_u32);
+
+                    let mut tx_rx_buf: [u8; 3] = [0x03, 0x02, 0x01];
+                    spi.transfer_in_place(&mut tx_rx_buf).unwrap();
+                    rprintln!(
+                        "Received reply: {}, {}, {}",
+                        tx_rx_buf[0],
+                        tx_rx_buf[1],
+                        tx_rx_buf[2]
+                    );
+                    assert_eq!(&tx_rx_buf[0..3], &[0x03, 0x02, 0x01]);
+                }
+            }
+        }
     }
 }
+
+#[interrupt]
+#[allow(non_snake_case)]
+fn OC0() {
+    default_ms_irq_handler()
+}

examples/simple/examples/timer-ticks.rs

@@ -2,19 +2,19 @@
 #![no_main]
 #![no_std]
 
+use core::cell::Cell;
 use cortex_m_rt::entry;
-use embedded_hal::delay::DelayNs;
-// Import panic provider.
-use panic_probe as _;
-// Import logger.
-use defmt_rtt as _;
-use portable_atomic::AtomicU32;
+use critical_section::Mutex;
+use panic_rtt_target as _;
+use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{
     clock::{get_sys_clock, set_sys_clock},
     pac::{self, interrupt},
     prelude::*,
     time::Hertz,
-    timer::{CountdownTimer, InterruptConfig},
+    timer::{
+        default_ms_irq_handler, set_up_ms_tick, CountdownTimer, Event, InterruptConfig, MS_COUNTER,
+    },
 };
 
 #[allow(dead_code)]
@@ -23,15 +23,14 @@ enum LibType {
     Hal,
 }
 
-static MS_COUNTER: AtomicU32 = AtomicU32::new(0);
-static SEC_COUNTER: AtomicU32 = AtomicU32::new(0);
+static SEC_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
 
 #[entry]
 fn main() -> ! {
-    let dp = pac::Peripherals::take().unwrap();
-    let mut delay = CountdownTimer::new(50.MHz(), dp.tim2);
+    rtt_init_print!();
+    let mut dp = pac::Peripherals::take().unwrap();
     let mut last_ms = 0;
-    defmt::info!("-- Vorago system ticks using timers --");
+    rprintln!("-- Vorago system ticks using timers --");
     set_sys_clock(50.MHz());
     let lib_type = LibType::Hal;
     match lib_type {
@@ -67,24 +66,34 @@ fn main() -> ! {
             }
         }
         LibType::Hal => {
-            let mut ms_timer = CountdownTimer::new(get_sys_clock().unwrap(), dp.tim0);
-            ms_timer.enable_interrupt(InterruptConfig::new(interrupt::OC0, true, true));
-            ms_timer.start(1.kHz());
-            let mut second_timer = CountdownTimer::new(get_sys_clock().unwrap(), dp.tim1);
-            second_timer.enable_interrupt(InterruptConfig::new(interrupt::OC1, true, true));
+            set_up_ms_tick(
+                InterruptConfig::new(interrupt::OC0, true, true),
+                &mut dp.sysconfig,
+                Some(&mut dp.irqsel),
+                50.MHz(),
+                dp.tim0,
+            );
+            let mut second_timer =
+                CountdownTimer::new(&mut dp.sysconfig, get_sys_clock().unwrap(), dp.tim1);
+            second_timer.listen(
+                Event::TimeOut,
+                InterruptConfig::new(interrupt::OC1, true, true),
+                Some(&mut dp.irqsel),
+                Some(&mut dp.sysconfig),
+            );
             second_timer.start(1.Hz());
         }
     }
     loop {
-        let current_ms = MS_COUNTER.load(portable_atomic::Ordering::Relaxed);
+        let current_ms = critical_section::with(|cs| MS_COUNTER.borrow(cs).get());
         if current_ms - last_ms >= 1000 {
             // To prevent drift.
             last_ms += 1000;
-            defmt::info!("MS counter: {}", current_ms);
-            let second = SEC_COUNTER.load(portable_atomic::Ordering::Relaxed);
-            defmt::info!("Second counter: {}", second);
+            rprintln!("MS counter: {}", current_ms);
+            let second = critical_section::with(|cs| SEC_COUNTER.borrow(cs).get());
+            rprintln!("Second counter: {}", second);
         }
-        delay.delay_ms(50);
+        cortex_m::asm::delay(10000);
     }
 }
 
@@ -98,11 +107,15 @@ fn unmask_irqs() {
 #[interrupt]
 #[allow(non_snake_case)]
 fn OC0() {
-    MS_COUNTER.fetch_add(1, portable_atomic::Ordering::Relaxed);
+    default_ms_irq_handler()
 }
 
 #[interrupt]
 #[allow(non_snake_case)]
 fn OC1() {
-    SEC_COUNTER.fetch_add(1, portable_atomic::Ordering::Relaxed);
+    critical_section::with(|cs| {
+        let mut sec = SEC_COUNTER.borrow(cs).get();
+        sec += 1;
+        SEC_COUNTER.borrow(cs).set(sec);
+    });
 }

examples/simple/examples/uart.rs

@@ -13,23 +13,27 @@
 use cortex_m_rt::entry;
 use embedded_hal_nb::{nb, serial::Read};
 use embedded_io::Write as _;
-// Import panic provider.
-use panic_probe as _;
-// Import logger.
-use defmt_rtt as _;
-use va108xx_hal::{pac, pins::PinsA, prelude::*, uart};
+use panic_rtt_target as _;
+use rtt_target::{rprintln, rtt_init_print};
+use va108xx_hal::{gpio::PinsA, pac, prelude::*, uart};
 
 #[entry]
 fn main() -> ! {
-    defmt::println!("-- VA108xx UART example application--");
+    rtt_init_print!();
+    rprintln!("-- VA108xx UART example application--");
 
-    let dp = pac::Peripherals::take().unwrap();
+    let mut dp = pac::Peripherals::take().unwrap();
 
-    let gpioa = PinsA::new(dp.porta);
-    let tx = gpioa.pa9;
-    let rx = gpioa.pa8;
-    let uart = uart::Uart::new_without_interrupt(50.MHz(), dp.uarta, (tx, rx), 115200.Hz().into())
-        .unwrap();
+    let gpioa = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let tx = gpioa.pa9.into_funsel_2();
+    let rx = gpioa.pa8.into_funsel_2();
+    let uart = uart::Uart::new_without_interrupt(
+        &mut dp.sysconfig,
+        50.MHz(),
+        dp.uarta,
+        (tx, rx),
+        115200.Hz(),
+    );
 
     let (mut tx, mut rx) = uart.split();
     writeln!(tx, "Hello World\r").unwrap();

examples/simple/src/main.rs

@@ -3,7 +3,7 @@
 #![no_std]
 
 use cortex_m_rt::entry;
-use panic_probe as _;
+use panic_rtt_target as _;
 use va108xx_hal as _;
 
 #[entry]

flashloader/Cargo.toml

@@ -29,7 +29,6 @@ rtic-sync = {version = "1", features = ["defmt-03"]}
 
 [dependencies.va108xx-hal]
 version = "0.11"
-path = "../va108xx-hal"
 features = ["defmt"]
 
 [dependencies.vorago-reb1]

flashloader/image-loader.py

@@ -2,15 +2,16 @@
 from typing import List, Tuple
 from spacepackets.ecss.defs import PusService
 from spacepackets.ecss.tm import PusTm
+from tmtccmd.com import ComInterface
 import toml
 import struct
 import logging
 import argparse
 import time
 import enum
-from com_interface import ComInterface
-from com_interface.serial_base import SerialCfg
-from com_interface.serial_cobs import SerialCobsComIF
+from tmtccmd.com.serial_base import SerialCfg
+from tmtccmd.com.serial_cobs import SerialCobsComIF
+from tmtccmd.com.ser_utils import prompt_com_port
 from crcmod.predefined import PredefinedCrc
 from spacepackets.ecss.tc import PusTc
 from spacepackets.ecss.pus_verificator import PusVerificator, StatusField
@@ -100,7 +101,15 @@ class ImageLoader:
         )
         self.verificator.add_tc(action_tc)
         self.com_if.send(bytes(action_tc.pack()))
-        self.await_for_command_copletion("boot image selection command")
+        data_available = self.com_if.data_available(0.4)
+        if not data_available:
+            _LOGGER.warning("no reply received for boot image selection command")
+        for reply in self.com_if.receive():
+            result = self.verificator.add_tm(
+                Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0))
+            )
+            if result is not None and result.completed:
+                _LOGGER.info("received boot image selection command confirmation")
 
     def handle_ping_cmd(self):
         _LOGGER.info("Sending ping command")
@@ -113,26 +122,16 @@ class ImageLoader:
         )
         self.verificator.add_tc(ping_tc)
         self.com_if.send(bytes(ping_tc.pack()))
-        self.await_for_command_copletion("ping command")
 
-    def await_for_command_copletion(self, context: str):
-        done = False
-        now = time.time()
-        while time.time() - now < 2.0:
-            if not self.com_if.data_available():
-                time.sleep(0.2)
-                continue
-            for reply in self.com_if.receive():
-                result = self.verificator.add_tm(
-                    Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0))
-                )
-                if result is not None and result.completed:
-                    _LOGGER.info(f"received {context} reply")
-                    done = True
-            if done:
-                break
-        if not done:
-            _LOGGER.warning(f"no {context} reply received")
+        data_available = self.com_if.data_available(0.4)
+        if not data_available:
+            _LOGGER.warning("no ping reply received")
+        for reply in self.com_if.receive():
+            result = self.verificator.add_tm(
+                Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0))
+            )
+            if result is not None and result.completed:
+                _LOGGER.info("received ping completion reply")
 
     def handle_corruption_cmd(self, target: Target):
         if target == Target.BOOTLOADER:
@@ -301,12 +300,12 @@ def main() -> int:
             if "serial_port" in parsed_toml:
                 serial_port = parsed_toml["serial_port"]
     if serial_port is None:
-        serial_port = input("Please specify the serial port manually: ")
+        serial_port = prompt_com_port()
     serial_cfg = SerialCfg(
         com_if_id="ser_cobs",
         serial_port=serial_port,
         baud_rate=BAUD_RATE,
-        polling_frequency=0.1,
+        serial_timeout=0.1,
     )
     verificator = PusVerificator()
     com_if = SerialCobsComIF(serial_cfg)

flashloader/loader.toml

@@ -1 +1 @@
-serial_port = "/dev/ttyUSB1"
+serial_port = "/dev/ttyUSB0"

flashloader/requirements.txt

@@ -1,5 +1,5 @@
-spacepackets == 0.28
-com-interface == 0.1
+spacepackets == 0.24
+tmtccmd == 8.0.2
 toml == 0.10
 pyelftools == 0.31
 crcmod == 1.7

flashloader/src/main.rs

@@ -68,7 +68,7 @@ mod app {
     use spacepackets::ecss::{
         tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket,
     };
-    use va108xx_hal::pins::PinsA;
+    use va108xx_hal::gpio::PinsA;
     use va108xx_hal::uart::IrqContextTimeoutOrMaxSize;
     use va108xx_hal::{pac, uart, InterruptConfig};
     use vorago_reb1::m95m01::M95M01;
@@ -83,8 +83,8 @@ mod app {
 
     #[local]
     struct Local {
-        uart_rx: uart::RxWithInterrupt,
-        uart_tx: uart::Tx,
+        uart_rx: uart::RxWithInterrupt<pac::Uarta>,
+        uart_tx: uart::Tx<pac::Uarta>,
         rx_context: IrqContextTimeoutOrMaxSize,
         verif_reporter: VerificationReportCreator,
         nvm: M95M01,
@@ -108,18 +108,18 @@ mod app {
         let mut dp = cx.device;
         let nvm = M95M01::new(&mut dp.sysconfig, SYSCLK_FREQ, dp.spic);
 
-        let gpioa = PinsA::new(dp.porta);
-        let tx = gpioa.pa9;
-        let rx = gpioa.pa8;
+        let gpioa = PinsA::new(&mut dp.sysconfig, dp.porta);
+        let tx = gpioa.pa9.into_funsel_2();
+        let rx = gpioa.pa8.into_funsel_2();
 
         let irq_uart = uart::Uart::new_with_interrupt(
+            &mut dp.sysconfig,
             SYSCLK_FREQ,
             dp.uarta,
             (tx, rx),
-            UART_BAUDRATE.Hz().into(),
+            UART_BAUDRATE.Hz(),
             InterruptConfig::new(pac::Interrupt::OC0, true, true),
-        )
-        .unwrap();
+        );
         let (tx, rx) = irq_uart.split();
         // Unwrap is okay, we explicitely set the interrupt ID.
         let mut rx = rx.into_rx_with_irq();
@@ -451,7 +451,7 @@ mod app {
                 cx.local.encoded_buf[send_size + 1] = 0;
                 cx.local
                     .uart_tx
-                    .write_all(&cx.local.encoded_buf[0..send_size + 2])
+                    .write(&cx.local.encoded_buf[0..send_size + 2])
                     .unwrap();
                 occupied_len -= 1;
                 Mono::delay(2.millis()).await;

va108xx-embassy/Cargo.toml

@@ -20,7 +20,7 @@ embassy-time-queue-utils = "0.1"
 
 once_cell = { version = "1", default-features = false, features = ["critical-section"] }
 
-va108xx-hal = { version = ">=0.10, <=0.11", path = "../va108xx-hal" }
+va108xx-hal = { version = ">=0.10, <=0.11" }
 
 [target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
 portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }

va108xx-embassy/src/lib.rs

@@ -45,7 +45,7 @@ use va108xx_hal::{
     clock::enable_peripheral_clock,
     enable_nvic_interrupt, pac,
     prelude::*,
-    timer::{enable_tim_clk, get_tim_raw, TimMarker, TimRegInterface},
+    timer::{enable_tim_clk, get_tim_raw, TimRegInterface, ValidTim},
     PeripheralSelect,
 };
 
@@ -109,28 +109,48 @@ pub fn time_driver() -> &'static TimerDriver {
 /// This should be used if the interrupt handler is provided by the library, which is the
 /// default case.
 #[cfg(feature = "irqs-in-lib")]
-pub fn init<TimekeeperTim: TimRegInterface + TimMarker, AlarmTim: TimRegInterface + TimMarker>(
-    sysclk: Hertz,
+pub fn init<TimekeeperTim: TimRegInterface + ValidTim, AlarmTim: TimRegInterface + ValidTim>(
+    syscfg: &mut pac::Sysconfig,
+    irqsel: &pac::Irqsel,
+    sysclk: impl Into<Hertz>,
     timekeeper_tim: TimekeeperTim,
     alarm_tim: AlarmTim,
 ) {
-    TIME_DRIVER.init(sysclk, timekeeper_tim, alarm_tim, TIMEKEEPER_IRQ, ALARM_IRQ)
+    TIME_DRIVER.init(
+        syscfg,
+        irqsel,
+        sysclk,
+        timekeeper_tim,
+        alarm_tim,
+        TIMEKEEPER_IRQ,
+        ALARM_IRQ,
+    )
 }
 
 /// Initialization method for embassy when using custom IRQ handlers.
 ///
 /// Requires an explicit [pac::Interrupt] argument for the timekeeper and alarm IRQs.
 pub fn init_with_custom_irqs<
-    TimekeeperTim: TimRegInterface + TimMarker,
-    AlarmTim: TimRegInterface + TimMarker,
+    TimekeeperTim: TimRegInterface + ValidTim,
+    AlarmTim: TimRegInterface + ValidTim,
 >(
-    sysclk: Hertz,
+    syscfg: &mut pac::Sysconfig,
+    irqsel: &pac::Irqsel,
+    sysclk: impl Into<Hertz>,
     timekeeper_tim: TimekeeperTim,
     alarm_tim: AlarmTim,
     timekeeper_irq: pac::Interrupt,
     alarm_irq: pac::Interrupt,
 ) {
-    TIME_DRIVER.init(sysclk, timekeeper_tim, alarm_tim, timekeeper_irq, alarm_irq)
+    TIME_DRIVER.init(
+        syscfg,
+        irqsel,
+        sysclk,
+        timekeeper_tim,
+        alarm_tim,
+        timekeeper_irq,
+        alarm_irq,
+    )
 }
 
 struct AlarmState {
@@ -160,9 +180,11 @@ pub struct TimerDriver {
 
 impl TimerDriver {
     #[allow(clippy::too_many_arguments)]
-    fn init<TimekeeperTim: TimRegInterface + TimMarker, AlarmTim: TimRegInterface + TimMarker>(
+    fn init<TimekeeperTim: TimRegInterface + ValidTim, AlarmTim: TimRegInterface + ValidTim>(
         &self,
-        sysclk: Hertz,
+        syscfg: &mut pac::Sysconfig,
+        irqsel: &pac::Irqsel,
+        sysclk: impl Into<Hertz>,
         timekeeper_tim: TimekeeperTim,
         alarm_tim: AlarmTim,
         timekeeper_irq: pac::Interrupt,
@@ -171,12 +193,13 @@ impl TimerDriver {
         if ALARM_TIM.get().is_some() || TIMEKEEPER_TIM.get().is_some() {
             return;
         }
-        ALARM_TIM.set(AlarmTim::ID.raw_id()).ok();
-        TIMEKEEPER_TIM.set(TimekeeperTim::ID.raw_id()).ok();
-        enable_peripheral_clock(PeripheralSelect::Irqsel);
-        enable_tim_clk(timekeeper_tim.raw_id());
+        ALARM_TIM.set(AlarmTim::TIM_ID).ok();
+        TIMEKEEPER_TIM.set(TimekeeperTim::TIM_ID).ok();
+        enable_peripheral_clock(syscfg, PeripheralSelect::Irqsel);
+        enable_tim_clk(syscfg, timekeeper_tim.tim_id());
         let timekeeper_reg_block = timekeeper_tim.reg_block();
         let alarm_tim_reg_block = alarm_tim.reg_block();
+        let sysclk = sysclk.into();
         // Initiate scale value here. This is required to convert timer ticks back to a timestamp.
         SCALE.set((sysclk.raw() / TICK_HZ as u32) as u64).unwrap();
         timekeeper_reg_block
@@ -186,10 +209,9 @@ impl TimerDriver {
         timekeeper_reg_block
             .cnt_value()
             .write(|w| unsafe { w.bits(u32::MAX) });
-        let irqsel = unsafe { va108xx_hal::pac::Irqsel::steal() };
         // Switch on. Timekeeping should always be done.
         irqsel
-            .tim0(timekeeper_tim.raw_id() as usize)
+            .tim0(timekeeper_tim.tim_id() as usize)
             .write(|w| unsafe { w.bits(timekeeper_irq as u32) });
         unsafe {
             enable_nvic_interrupt(timekeeper_irq);
@@ -201,7 +223,7 @@ impl TimerDriver {
             .enable()
             .write(|w| unsafe { w.bits(1) });
 
-        enable_tim_clk(alarm_tim.raw_id());
+        enable_tim_clk(syscfg, alarm_tim.tim_id());
 
         // Explicitely disable alarm timer until needed.
         alarm_tim_reg_block.ctrl().modify(|_, w| {
@@ -213,7 +235,7 @@ impl TimerDriver {
             enable_nvic_interrupt(alarm_irq);
         }
         irqsel
-            .tim0(alarm_tim.raw_id() as usize)
+            .tim0(alarm_tim.tim_id() as usize)
             .write(|w| unsafe { w.bits(alarm_irq as u32) });
     }
 

va108xx-hal/Cargo.toml

@@ -15,7 +15,6 @@ cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
 cortex-m-rt = "0.7"
 nb = "1"
 paste = "1"
-vorago-shared-periphs = { path = "../vorago-shared-periphs", features = ["vor1x"] }
 embedded-hal = "1"
 embedded-hal-async = "1"
 embedded-hal-nb = "1"
@@ -43,7 +42,7 @@ portable-atomic = "1"
 [features]
 default = ["rt"]
 rt = ["va108xx/rt"]
-defmt = ["dep:defmt", "fugit/defmt", "embedded-hal/defmt-03", "vorago-shared-periphs/defmt"]
+defmt = ["dep:defmt", "fugit/defmt", "embedded-hal/defmt-03"]
 
 [package.metadata.docs.rs]
 all-features = true

va108xx-hal/src/clock.rs

@@ -2,14 +2,27 @@
 //!
 //! This also includes functionality to enable the peripheral clocks
 use crate::time::Hertz;
+use crate::PeripheralSelect;
 use cortex_m::interrupt::{self, Mutex};
 use once_cell::unsync::OnceCell;
 
-pub use vorago_shared_periphs::gpio::FilterClkSel;
-pub use vorago_shared_periphs::sysconfig::{disable_peripheral_clock, enable_peripheral_clock};
-
 static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
 
+pub type PeripheralClocks = PeripheralSelect;
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum FilterClkSel {
+    SysClk = 0,
+    Clk1 = 1,
+    Clk2 = 2,
+    Clk3 = 3,
+    Clk4 = 4,
+    Clk5 = 5,
+    Clk6 = 6,
+    Clk7 = 7,
+}
+
 /// The Vorago in powered by an external clock which might have different frequencies.
 /// The clock can be set here so it can be used by other software components as well.
 /// The clock can be set exactly once
@@ -50,3 +63,17 @@ pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClkS
         }
     }
 }
+
+#[inline]
+pub fn enable_peripheral_clock(syscfg: &mut va108xx::Sysconfig, clock: PeripheralClocks) {
+    syscfg
+        .peripheral_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
+}
+
+#[inline]
+pub fn disable_peripheral_clock(syscfg: &mut va108xx::Sysconfig, clock: PeripheralClocks) {
+    syscfg
+        .peripheral_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) });
+}

va108xx-hal/src/gpio/asynch.rs

@@ -0,0 +1,366 @@
+//! # Async GPIO functionality for the VA108xx family.
+//!
+//! This module provides the [InputPinAsync] and [InputDynPinAsync] which both implement
+//! the [embedded_hal_async::digital::Wait] trait. These types allow for asynchronous waiting
+//! on GPIO pins. Please note that this module does not specify/declare the interrupt handlers
+//! which must be provided for async support to work. However, it provides the
+//! [on_interrupt_for_async_gpio_for_port] generic interrupt handler. This should be called in all
+//! IRQ functions which handle any GPIO interrupts with the corresponding [Port] argument.
+//!
+//! # Example
+//!
+//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs)
+use core::future::Future;
+
+use embassy_sync::waitqueue::AtomicWaker;
+use embedded_hal_async::digital::Wait;
+use portable_atomic::AtomicBool;
+use va108xx::{self as pac};
+
+use crate::InterruptConfig;
+
+use super::{
+    pin, DynPin, DynPinId, InputConfig, InterruptEdge, InvalidPinTypeError, Pin, PinId, Port,
+    NUM_PINS_PORT_A, NUM_PINS_PORT_B,
+};
+
+static WAKERS_FOR_PORT_A: [AtomicWaker; NUM_PINS_PORT_A] =
+    [const { AtomicWaker::new() }; NUM_PINS_PORT_A];
+static WAKERS_FOR_PORT_B: [AtomicWaker; NUM_PINS_PORT_B] =
+    [const { AtomicWaker::new() }; NUM_PINS_PORT_B];
+static EDGE_DETECTION_PORT_A: [AtomicBool; NUM_PINS_PORT_A] =
+    [const { AtomicBool::new(false) }; NUM_PINS_PORT_A];
+static EDGE_DETECTION_PORT_B: [AtomicBool; NUM_PINS_PORT_B] =
+    [const { AtomicBool::new(false) }; NUM_PINS_PORT_B];
+
+/// Generic interrupt handler for GPIO interrupts on a specific port to support async functionalities
+///
+/// This function should be called in all interrupt handlers which handle any GPIO interrupts
+/// matching the [Port] argument.
+/// The handler will wake the corresponding wakers for the pins that triggered an interrupts
+/// as well as update the static edge detection structures. This allows the pin future tocomplete
+/// complete async operations.
+pub fn on_interrupt_for_async_gpio_for_port(port: Port) {
+    let periphs = unsafe { pac::Peripherals::steal() };
+
+    let (irq_enb, edge_status, wakers, edge_detection) = match port {
+        Port::A => (
+            periphs.porta.irq_enb().read().bits(),
+            periphs.porta.edge_status().read().bits(),
+            WAKERS_FOR_PORT_A.as_ref(),
+            EDGE_DETECTION_PORT_A.as_ref(),
+        ),
+        Port::B => (
+            periphs.portb.irq_enb().read().bits(),
+            periphs.portb.edge_status().read().bits(),
+            WAKERS_FOR_PORT_B.as_ref(),
+            EDGE_DETECTION_PORT_B.as_ref(),
+        ),
+    };
+
+    on_interrupt_for_port(irq_enb, edge_status, wakers, edge_detection);
+}
+
+#[inline]
+fn on_interrupt_for_port(
+    mut irq_enb: u32,
+    edge_status: u32,
+    wakers: &'static [AtomicWaker],
+    edge_detection: &'static [AtomicBool],
+) {
+    while irq_enb != 0 {
+        let bit_pos = irq_enb.trailing_zeros() as usize;
+        let bit_mask = 1 << bit_pos;
+
+        wakers[bit_pos].wake();
+
+        if edge_status & bit_mask != 0 {
+            edge_detection[bit_pos].store(true, core::sync::atomic::Ordering::Relaxed);
+
+            // Clear the processed bit
+            irq_enb &= !bit_mask;
+        }
+    }
+}
+
+/// Input pin future which implements the [Future] trait.
+///
+/// Generally, you want to use the [InputPinAsync] or [InputDynPinAsync] types instead of this
+/// which also implements the [embedded_hal_async::digital::Wait] trait. However, access to this
+/// struture is granted  to allow writing custom async structures.
+pub struct InputPinFuture {
+    pin_id: DynPinId,
+    waker_group: &'static [AtomicWaker],
+    edge_detection_group: &'static [AtomicBool],
+}
+
+impl InputPinFuture {
+    #[inline]
+    pub fn pin_group_to_waker_and_edge_detection_group(
+        group: Port,
+    ) -> (&'static [AtomicWaker], &'static [AtomicBool]) {
+        match group {
+            Port::A => (WAKERS_FOR_PORT_A.as_ref(), EDGE_DETECTION_PORT_A.as_ref()),
+            Port::B => (WAKERS_FOR_PORT_B.as_ref(), EDGE_DETECTION_PORT_B.as_ref()),
+        }
+    }
+
+    pub fn new_with_dyn_pin(
+        pin: &mut DynPin,
+        irq: pac::Interrupt,
+        edge: InterruptEdge,
+    ) -> Result<Self, InvalidPinTypeError> {
+        if !pin.is_input_pin() {
+            return Err(InvalidPinTypeError(pin.mode()));
+        }
+
+        let (waker_group, edge_detection_group) =
+            Self::pin_group_to_waker_and_edge_detection_group(pin.id().port());
+        edge_detection_group[pin.id().num() as usize]
+            .store(false, core::sync::atomic::Ordering::Relaxed);
+        pin.configure_edge_interrupt(edge).unwrap();
+        pin.enable_interrupt(InterruptConfig::new(irq, true, true));
+        Ok(Self {
+            pin_id: pin.id(),
+            waker_group,
+            edge_detection_group,
+        })
+    }
+
+    pub fn new_with_pin<I: PinId, C: InputConfig>(
+        pin: &mut Pin<I, pin::Input<C>>,
+        irq: pac::Interrupt,
+        edge: InterruptEdge,
+    ) -> Self {
+        let (waker_group, edge_detection_group) =
+            Self::pin_group_to_waker_and_edge_detection_group(pin.id().port());
+        edge_detection_group[pin.id().num() as usize]
+            .store(false, core::sync::atomic::Ordering::Relaxed);
+        pin.configure_edge_interrupt(edge);
+        pin.enable_interrupt(InterruptConfig::new(irq, true, true));
+        Self {
+            pin_id: pin.id(),
+            edge_detection_group,
+            waker_group,
+        }
+    }
+}
+
+impl Drop for InputPinFuture {
+    fn drop(&mut self) {
+        // The API ensures that we actually own the pin, so stealing it here is okay.
+        unsafe { DynPin::steal(self.pin_id) }.disable_interrupt(false);
+    }
+}
+
+impl Future for InputPinFuture {
+    type Output = ();
+    fn poll(
+        self: core::pin::Pin<&mut Self>,
+        cx: &mut core::task::Context<'_>,
+    ) -> core::task::Poll<Self::Output> {
+        let idx = self.pin_id.num() as usize;
+        self.waker_group[idx].register(cx.waker());
+        if self.edge_detection_group[idx].swap(false, core::sync::atomic::Ordering::Relaxed) {
+            return core::task::Poll::Ready(());
+        }
+        core::task::Poll::Pending
+    }
+}
+
+pub struct InputDynPinAsync {
+    pin: DynPin,
+    irq: pac::Interrupt,
+}
+
+impl InputDynPinAsync {
+    /// Create a new asynchronous input pin from a [DynPin]. The interrupt ID to be used must be
+    /// passed as well and is used to route and enable the interrupt.
+    ///
+    /// Please note that the interrupt handler itself must be provided by the user and the
+    /// generic [on_interrupt_for_async_gpio_for_port] function must be called inside that function
+    /// for the asynchronous functionality to work.
+    pub fn new(pin: DynPin, irq: pac::Interrupt) -> Result<Self, InvalidPinTypeError> {
+        if !pin.is_input_pin() {
+            return Err(InvalidPinTypeError(pin.mode()));
+        }
+        Ok(Self { pin, irq })
+    }
+
+    /// Asynchronously wait until the pin is high.
+    ///
+    /// This returns immediately if the pin is already high.
+    pub async fn wait_for_high(&mut self) {
+        // Unwrap okay, checked pin in constructor.
+        let fut =
+            InputPinFuture::new_with_dyn_pin(&mut self.pin, self.irq, InterruptEdge::LowToHigh)
+                .unwrap();
+        if self.pin.is_high().unwrap() {
+            return;
+        }
+        fut.await;
+    }
+
+    /// Asynchronously wait until the pin is low.
+    ///
+    /// This returns immediately if the pin is already high.
+    pub async fn wait_for_low(&mut self) {
+        // Unwrap okay, checked pin in constructor.
+        let fut =
+            InputPinFuture::new_with_dyn_pin(&mut self.pin, self.irq, InterruptEdge::HighToLow)
+                .unwrap();
+        if self.pin.is_low().unwrap() {
+            return;
+        }
+        fut.await;
+    }
+
+    /// Asynchronously wait until the pin sees a falling edge.
+    pub async fn wait_for_falling_edge(&mut self) {
+        // Unwrap okay, checked pin in constructor.
+        InputPinFuture::new_with_dyn_pin(&mut self.pin, self.irq, InterruptEdge::HighToLow)
+            .unwrap()
+            .await;
+    }
+
+    /// Asynchronously wait until the pin sees a rising edge.
+    pub async fn wait_for_rising_edge(&mut self) {
+        // Unwrap okay, checked pin in constructor.
+        InputPinFuture::new_with_dyn_pin(&mut self.pin, self.irq, InterruptEdge::LowToHigh)
+            .unwrap()
+            .await;
+    }
+
+    /// Asynchronously wait until the pin sees any edge (either rising or falling).
+    pub async fn wait_for_any_edge(&mut self) {
+        // Unwrap okay, checked pin in constructor.
+        InputPinFuture::new_with_dyn_pin(&mut self.pin, self.irq, InterruptEdge::BothEdges)
+            .unwrap()
+            .await;
+    }
+
+    pub fn release(self) -> DynPin {
+        self.pin
+    }
+}
+
+impl embedded_hal::digital::ErrorType for InputDynPinAsync {
+    type Error = core::convert::Infallible;
+}
+
+impl Wait for InputDynPinAsync {
+    async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_high().await;
+        Ok(())
+    }
+
+    async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_low().await;
+        Ok(())
+    }
+
+    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_rising_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_falling_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_any_edge().await;
+        Ok(())
+    }
+}
+
+pub struct InputPinAsync<I: PinId, C: InputConfig> {
+    pin: Pin<I, pin::Input<C>>,
+    irq: pac::Interrupt,
+}
+
+impl<I: PinId, C: InputConfig> InputPinAsync<I, C> {
+    /// Create a new asynchronous input pin from a typed [Pin]. The interrupt ID to be used must be
+    /// passed as well and is used to route and enable the interrupt.
+    ///
+    /// Please note that the interrupt handler itself must be provided by the user and the
+    /// generic [on_interrupt_for_async_gpio_for_port] function must be called inside that function
+    /// for the asynchronous functionality to work.
+    pub fn new(pin: Pin<I, pin::Input<C>>, irq: pac::Interrupt) -> Self {
+        Self { pin, irq }
+    }
+
+    /// Asynchronously wait until the pin is high.
+    ///
+    /// This returns immediately if the pin is already high.
+    pub async fn wait_for_high(&mut self) {
+        let fut = InputPinFuture::new_with_pin(&mut self.pin, self.irq, InterruptEdge::LowToHigh);
+        if self.pin.is_high() {
+            return;
+        }
+        fut.await;
+    }
+
+    /// Asynchronously wait until the pin is low.
+    ///
+    /// This returns immediately if the pin is already high.
+    pub async fn wait_for_low(&mut self) {
+        let fut = InputPinFuture::new_with_pin(&mut self.pin, self.irq, InterruptEdge::HighToLow);
+        if self.pin.is_low() {
+            return;
+        }
+        fut.await;
+    }
+
+    /// Asynchronously wait until the pin sees falling edge.
+    pub async fn wait_for_falling_edge(&mut self) {
+        // Unwrap okay, checked pin in constructor.
+        InputPinFuture::new_with_pin(&mut self.pin, self.irq, InterruptEdge::HighToLow).await;
+    }
+
+    /// Asynchronously wait until the pin sees rising edge.
+    pub async fn wait_for_rising_edge(&mut self) {
+        // Unwrap okay, checked pin in constructor.
+        InputPinFuture::new_with_pin(&mut self.pin, self.irq, InterruptEdge::LowToHigh).await;
+    }
+
+    /// Asynchronously wait until the pin sees any edge (either rising or falling).
+    pub async fn wait_for_any_edge(&mut self) {
+        InputPinFuture::new_with_pin(&mut self.pin, self.irq, InterruptEdge::BothEdges).await;
+    }
+
+    pub fn release(self) -> Pin<I, pin::Input<C>> {
+        self.pin
+    }
+}
+impl<I: PinId, C: InputConfig> embedded_hal::digital::ErrorType for InputPinAsync<I, C> {
+    type Error = core::convert::Infallible;
+}
+
+impl<I: PinId, C: InputConfig> Wait for InputPinAsync<I, C> {
+    async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_high().await;
+        Ok(())
+    }
+
+    async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_low().await;
+        Ok(())
+    }
+
+    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_rising_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_falling_edge().await;
+        Ok(())
+    }
+
+    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
+        self.wait_for_any_edge().await;
+        Ok(())
+    }
+}

va108xx-hal/src/gpio/dynpin.rs

@@ -0,0 +1,947 @@
+//! # Type-erased, value-level module for GPIO pins
+//!
+//! Although the type-level API is generally preferred, it is not suitable in
+//! all cases. Because each pin is represented by a distinct type, it is not
+//! possible to store multiple pins in a homogeneous data structure. The
+//! value-level API solves this problem by erasing the type information and
+//! tracking the pin at run-time.
+//!
+//! Value-level pins are represented by the [`DynPin`] type. [`DynPin`] has two
+//! fields, `id` and `mode` with types [`DynPinId`] and [`DynPinMode`]
+//! respectively. The implementation of these types closely mirrors the
+//! type-level API.
+//!
+//! Instances of [`DynPin`] cannot be created directly. Rather, they must be
+//! created from their type-level equivalents using [`From`]/[`Into`].
+//!
+//! ```
+//! // Move a pin out of the Pins struct and convert to a DynPin
+//! let pa0: DynPin = pins.pa0.into();
+//! ```
+//!
+//! Conversions between pin modes use a value-level version of the type-level
+//! API.
+//!
+//! ```
+//! // Use one of the literal function names
+//! pa0.into_floating_input();
+//! // Use a method and a DynPinMode variant
+//! pa0.into_mode(DYN_FLOATING_INPUT);
+//! ```
+//!
+//! Because the pin state cannot be tracked at compile-time, many [`DynPin`]
+//! operations become fallible. Run-time checks are inserted to ensure that
+//! users don't try to, for example, set the output level of an input pin.
+//!
+//! Users may try to convert value-level pins back to their type-level
+//! equivalents. However, this option is fallible, because the compiler cannot
+//! guarantee the pin has the correct ID or is in the correct mode at
+//! compile-time. Use [TryFrom]/[TryInto] for this conversion.
+//!
+//! ```
+//! // Convert to a `DynPin`
+//! let pa0: DynPin = pins.pa0.into();
+//! // Change pin mode
+//! pa0.into_floating_input();
+//! // Convert back to a `Pin`
+//! let pa0: Pin<PA0, FloatingInput> = pa0.try_into().unwrap();
+//! ```
+//!
+//! # Embedded HAL traits
+//!
+//! This module implements all of the embedded HAL GPIO traits for [`DynPin`].
+//! However, whereas the type-level API uses
+//! `Error = core::convert::Infallible`, the value-level API can return a real
+//! error. If the [`DynPin`] is not in the correct [`DynPinMode`] for the
+//! operation, the trait functions will return
+//! [InvalidPinTypeError].
+
+use super::{
+    pin::{FilterType, Pin, PinId, PinMode},
+    InputDynPinAsync, InterruptEdge, InterruptLevel, IsMaskedError, PinState, Port,
+};
+use crate::{clock::FilterClkSel, enable_nvic_interrupt, pac, FunSel};
+
+//==================================================================================================
+//  DynPinMode configurations
+//==================================================================================================
+
+/// Value-level `enum` for disabled configurations
+#[derive(PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum DynDisabled {
+    Floating,
+    PullDown,
+    PullUp,
+}
+
+/// Value-level `enum` for input configurations
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum DynInput {
+    Floating,
+    PullDown,
+    PullUp,
+}
+
+/// Value-level `enum` for output configurations
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum DynOutput {
+    PushPull,
+    OpenDrain,
+    ReadablePushPull,
+    ReadableOpenDrain,
+}
+
+pub type DynAlternate = FunSel;
+
+//==============================================================================
+//  Error
+//==============================================================================
+
+/// GPIO error type
+///
+/// [`DynPin`]s are not tracked and verified at compile-time, so run-time
+/// operations are fallible. This `enum` represents the corresponding errors.
+#[derive(Debug, PartialEq, Eq, thiserror::Error)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[error("Invalid pin type for operation: {0:?}")]
+pub struct InvalidPinTypeError(pub DynPinMode);
+
+impl embedded_hal::digital::Error for InvalidPinTypeError {
+    fn kind(&self) -> embedded_hal::digital::ErrorKind {
+        embedded_hal::digital::ErrorKind::Other
+    }
+}
+
+//==================================================================================================
+//  DynPinMode
+//==================================================================================================
+
+/// Value-level `enum` representing pin modes
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum DynPinMode {
+    Input(DynInput),
+    Output(DynOutput),
+    Alternate(DynAlternate),
+}
+
+/// Value-level variant of [`DynPinMode`] for floating input mode
+pub const DYN_FLOATING_INPUT: DynPinMode = DynPinMode::Input(DynInput::Floating);
+/// Value-level variant of [`DynPinMode`] for pull-down input mode
+pub const DYN_PULL_DOWN_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullDown);
+/// Value-level variant of [`DynPinMode`] for pull-up input mode
+pub const DYN_PULL_UP_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullUp);
+
+/// Value-level variant of [`DynPinMode`] for push-pull output mode
+pub const DYN_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::PushPull);
+/// Value-level variant of [`DynPinMode`] for open-drain output mode
+pub const DYN_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::OpenDrain);
+/// Value-level variant of [`DynPinMode`] for readable push-pull output mode
+pub const DYN_RD_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadablePushPull);
+/// Value-level variant of [`DynPinMode`] for readable opendrain output mode
+pub const DYN_RD_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadableOpenDrain);
+
+/// Value-level variant of [`DynPinMode`] for function select 1
+pub const DYN_ALT_FUNC_1: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel1);
+/// Value-level variant of [`DynPinMode`] for function select 2
+pub const DYN_ALT_FUNC_2: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel2);
+/// Value-level variant of [`DynPinMode`] for function select 3
+pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel3);
+
+//==================================================================================================
+//  DynGroup & DynPinId
+//==================================================================================================
+
+pub type DynGroup = Port;
+
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct DynPinId {
+    port: Port,
+    num: u8,
+}
+
+impl DynPinId {
+    pub const fn new(port: Port, num: u8) -> Self {
+        DynPinId { port, num }
+    }
+
+    pub const fn port(&self) -> Port {
+        self.port
+    }
+    pub const fn num(&self) -> u8 {
+        self.num
+    }
+}
+
+//==================================================================================================
+//  ModeFields
+//==================================================================================================
+
+/// Collect all fields needed to set the [`PinMode`](super::PinMode)
+#[derive(Default)]
+struct ModeFields {
+    dir: bool,
+    opendrn: bool,
+    pull_en: bool,
+    /// true for pullup, false for pulldown
+    pull_dir: bool,
+    funsel: u8,
+    enb_input: bool,
+}
+
+impl From<DynPinMode> for ModeFields {
+    #[inline]
+    fn from(mode: DynPinMode) -> Self {
+        let mut fields = Self::default();
+        match mode {
+            DynPinMode::Input(config) => {
+                fields.dir = false;
+                fields.funsel = FunSel::Sel0 as u8;
+                match config {
+                    DynInput::Floating => (),
+                    DynInput::PullUp => {
+                        fields.pull_en = true;
+                        fields.pull_dir = true;
+                    }
+                    DynInput::PullDown => {
+                        fields.pull_en = true;
+                    }
+                }
+            }
+            DynPinMode::Output(config) => {
+                fields.dir = true;
+                fields.funsel = FunSel::Sel0 as u8;
+                match config {
+                    DynOutput::PushPull => (),
+                    DynOutput::OpenDrain => {
+                        fields.opendrn = true;
+                    }
+                    DynOutput::ReadableOpenDrain => {
+                        fields.enb_input = true;
+                        fields.opendrn = true;
+                    }
+                    DynOutput::ReadablePushPull => {
+                        fields.enb_input = true;
+                    }
+                }
+            }
+            DynPinMode::Alternate(config) => {
+                fields.funsel = config as u8;
+            }
+        }
+        fields
+    }
+}
+
+/// Type definition to avoid confusion: These register blocks are identical
+type PortRegisterBlock = pac::porta::RegisterBlock;
+pub type PortReg = pac::ioconfig::Porta;
+
+//==================================================================================================
+//  DynPin
+//==================================================================================================
+
+/// A value-level pin, parameterized by [`DynPinId`] and [`DynPinMode`]
+///
+/// This type acts as a type-erased version of [`Pin`]. Every pin is represented
+/// by the same type, and pins are tracked and distinguished at run-time.
+#[derive(Debug)]
+pub struct DynPin {
+    id: DynPinId,
+    mode: DynPinMode,
+}
+
+impl DynPin {
+    /// Create a new [DynPin]
+    ///
+    /// # Safety
+    ///
+    /// Each [DynPin] must be a singleton. For a given [DynPinId], there
+    /// must be at most one corresponding [`DynPin`] in existence at any given
+    /// time.  Violating this requirement is `unsafe`.
+    #[inline]
+    pub(crate) const unsafe fn new(id: DynPinId, mode: DynPinMode) -> Self {
+        DynPin { id, mode }
+    }
+
+    /// Steals a new [DynPin].
+    ///
+    /// This function will simply set the internal mode to [DYN_FLOATING_INPUT] pin without
+    /// modifying any registers related to the behaviour of the pin. The user should call
+    /// [Self::into_mode] to ensure the correct mode of the pin.
+    ///
+    /// # Safety
+    ///
+    /// Circumvents the HAL's safety guarantees. The caller must ensure that the pin is not
+    /// used cocurrently somewhere else. The caller might also want to call [Self::into_mode]
+    /// to ensure the correct desired state of the pin. It is recommended to create the pin using
+    /// [Pin::downgrade] instead.
+    pub const unsafe fn steal(id: DynPinId) -> Self {
+        DynPin {
+            id,
+            mode: DYN_FLOATING_INPUT,
+        }
+    }
+
+    /// Return a copy of the pin ID
+    #[inline]
+    pub const fn id(&self) -> DynPinId {
+        self.id
+    }
+
+    /// Return a copy of the pin mode
+    #[inline]
+    pub const fn mode(&self) -> DynPinMode {
+        self.mode
+    }
+
+    /// Convert the pin to the requested [`DynPinMode`]
+    #[inline]
+    pub fn into_mode(&mut self, mode: DynPinMode) {
+        self.change_mode(mode);
+        self.mode = mode;
+    }
+
+    #[inline]
+    pub fn is_input_pin(&self) -> bool {
+        matches!(self.mode, DynPinMode::Input(_))
+    }
+
+    #[inline]
+    pub fn is_output_pin(&self) -> bool {
+        matches!(self.mode, DynPinMode::Output(_))
+    }
+
+    #[inline]
+    pub fn into_funsel_1(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_1);
+    }
+
+    #[inline]
+    pub fn into_funsel_2(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_2);
+    }
+
+    #[inline]
+    pub fn into_funsel_3(&mut self) {
+        self.into_mode(DYN_ALT_FUNC_3);
+    }
+
+    /// Configure the pin to operate as a floating input
+    #[inline]
+    pub fn into_floating_input(&mut self) {
+        self.into_mode(DYN_FLOATING_INPUT);
+    }
+
+    /// Configure the pin to operate as a pulled down input
+    #[inline]
+    pub fn into_pull_down_input(&mut self) {
+        self.into_mode(DYN_PULL_DOWN_INPUT);
+    }
+
+    /// Configure the pin to operate as a pulled up input
+    #[inline]
+    pub fn into_pull_up_input(&mut self) {
+        self.into_mode(DYN_PULL_UP_INPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_push_pull_output(&mut self) {
+        self.into_mode(DYN_PUSH_PULL_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_open_drain_output(&mut self) {
+        self.into_mode(DYN_OPEN_DRAIN_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_readable_push_pull_output(&mut self) {
+        self.into_mode(DYN_RD_PUSH_PULL_OUTPUT);
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_readable_open_drain_output(&mut self) {
+        self.into_mode(DYN_RD_OPEN_DRAIN_OUTPUT);
+    }
+
+    #[inline(always)]
+    pub fn is_low(&self) -> Result<bool, InvalidPinTypeError> {
+        self.read_internal().map(|v| !v)
+    }
+
+    #[inline(always)]
+    pub fn is_high(&self) -> Result<bool, InvalidPinTypeError> {
+        self.read_internal()
+    }
+
+    #[inline(always)]
+    pub fn set_low(&mut self) -> Result<(), InvalidPinTypeError> {
+        self.write_internal(false)
+    }
+
+    #[inline(always)]
+    pub fn set_high(&mut self) -> Result<(), InvalidPinTypeError> {
+        self.write_internal(true)
+    }
+
+    /// Toggle the logic level of an output pin
+    #[inline(always)]
+    pub fn toggle(&mut self) -> Result<(), InvalidPinTypeError> {
+        if !self.is_output_pin() {
+            return Err(InvalidPinTypeError(self.mode));
+        }
+        // Safety: TOGOUT is a "mask" register, and we only write the bit for
+        // this pin ID
+        unsafe { self.port_reg().togout().write(|w| w.bits(self.mask_32())) };
+        Ok(())
+    }
+
+    pub fn enable_interrupt(&mut self, irq_cfg: crate::InterruptConfig) {
+        if irq_cfg.route {
+            self.configure_irqsel(irq_cfg.id);
+        }
+        if irq_cfg.enable_in_nvic {
+            unsafe { enable_nvic_interrupt(irq_cfg.id) };
+        }
+
+        // We only manipulate our own bit.
+        self.port_reg()
+            .irq_enb()
+            .modify(|r, w| unsafe { w.bits(r.bits() | self.mask_32()) });
+    }
+
+    pub fn disable_interrupt(&mut self, reset_irqsel: bool) {
+        if reset_irqsel {
+            self.reset_irqsel();
+        }
+        // We only manipulate our own bit.
+        self.port_reg()
+            .irq_enb()
+            .modify(|r, w| unsafe { w.bits(r.bits() & !self.mask_32()) });
+    }
+
+    /// Try to recreate a type-level [`Pin`] from a value-level [`DynPin`]
+    ///
+    /// There is no way for the compiler to know if the conversion will be
+    /// successful at compile-time. We must verify the conversion at run-time
+    /// or refuse to perform it.
+    #[inline]
+    pub fn upgrade<I: PinId, M: PinMode>(self) -> Result<Pin<I, M>, InvalidPinTypeError> {
+        if self.id == I::DYN && self.mode == M::DYN {
+            // The `DynPin` is consumed, so it is safe to replace it with the
+            // corresponding `Pin`
+            return Ok(unsafe { Pin::new() });
+        }
+        Err(InvalidPinTypeError(self.mode))
+    }
+
+    /// Convert the pin into an async pin. The pin can be converted back by calling
+    /// [InputDynPinAsync::release]
+    pub fn into_async_input(
+        self,
+        irq: crate::pac::Interrupt,
+    ) -> Result<InputDynPinAsync, InvalidPinTypeError> {
+        InputDynPinAsync::new(self, irq)
+    }
+
+    /// Configure the IRQSEL peripheral for this particular pin with the given interrupt ID.
+    pub fn configure_irqsel(&mut self, id: pac::Interrupt) {
+        let mut syscfg = unsafe { pac::Sysconfig::steal() };
+        let irqsel = unsafe { pac::Irqsel::steal() };
+        crate::clock::enable_peripheral_clock(&mut syscfg, crate::clock::PeripheralClocks::Irqsel);
+        match self.id().port() {
+            // Set the correct interrupt number in the IRQSEL register
+            super::Port::A => {
+                irqsel
+                    .porta0(self.id().num() as usize)
+                    .write(|w| unsafe { w.bits(id as u32) });
+            }
+            super::Port::B => {
+                irqsel
+                    .portb0(self.id().num as usize)
+                    .write(|w| unsafe { w.bits(id as u32) });
+            }
+        }
+    }
+
+    /// Reset the IRQSEL peripheral value for this particular pin.
+    pub fn reset_irqsel(&mut self) {
+        let mut syscfg = unsafe { pac::Sysconfig::steal() };
+        let irqsel = unsafe { pac::Irqsel::steal() };
+        crate::clock::enable_peripheral_clock(&mut syscfg, crate::clock::PeripheralClocks::Irqsel);
+        match self.id().port() {
+            // Set the correct interrupt number in the IRQSEL register
+            super::Port::A => {
+                irqsel
+                    .porta0(self.id().num() as usize)
+                    .write(|w| unsafe { w.bits(u32::MAX) });
+            }
+            super::Port::B => {
+                irqsel
+                    .portb0(self.id().num as usize)
+                    .write(|w| unsafe { w.bits(u32::MAX) });
+            }
+        }
+    }
+
+    // Get DATAMASK bit for this particular pin
+    #[inline(always)]
+    pub fn datamask(&self) -> bool {
+        (self.port_reg().datamask().read().bits() >> self.id().num) == 1
+    }
+
+    /// Clear DATAMASK bit for this particular pin. This prevents access
+    /// of the corresponding bit for output and input operations
+    #[inline(always)]
+    pub fn clear_datamask(&self) {
+        self.port_reg()
+            .datamask()
+            .modify(|r, w| unsafe { w.bits(r.bits() & !self.mask_32()) });
+    }
+
+    /// Set DATAMASK bit for this particular pin. 1 is the default
+    /// state of the bit and allows access of the corresponding bit
+    #[inline(always)]
+    pub fn set_datamask(&self) {
+        self.port_reg()
+            .datamask()
+            .modify(|r, w| unsafe { w.bits(r.bits() | self.mask_32()) });
+    }
+
+    #[inline]
+    pub fn is_high_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+        self.read_pin_masked()
+    }
+
+    #[inline]
+    pub fn is_low_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+        self.read_pin_masked().map(|v| !v)
+    }
+
+    #[inline]
+    pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+        self.write_pin_masked(true)
+    }
+
+    #[inline]
+    pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+        self.write_pin_masked(false)
+    }
+
+    /// Possible delays in clock cycles:
+    ///  - Delay 1: 1
+    ///  - Delay 2: 2
+    ///  - Delay 1 + Delay 2: 3
+    #[inline]
+    pub fn configure_delay(
+        &mut self,
+        delay_1: bool,
+        delay_2: bool,
+    ) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.configure_delay_internal(delay_1, delay_2);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    #[inline]
+    pub fn configure_pulse_mode(
+        &mut self,
+        enable: bool,
+        default_state: PinState,
+    ) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.configure_pulse_mode_internal(enable, default_state);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    /// See p.37 and p.38 of the programmers guide for more information.
+    #[inline]
+    pub fn configure_filter_type(
+        &mut self,
+        filter: FilterType,
+        clksel: FilterClkSel,
+    ) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) => {
+                self.configure_filter_type_internal(filter, clksel);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    pub fn configure_edge_interrupt(
+        &mut self,
+        edge_type: InterruptEdge,
+    ) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DynPinMode::Output(_) => {
+                self.configure_edge_interrupt_internal(edge_type);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    pub fn configure_level_interrupt(
+        &mut self,
+        level_type: InterruptLevel,
+    ) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DynPinMode::Output(_) => {
+                self.configure_level_interrupt_internal(level_type);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    /// Change the pin mode
+    #[inline]
+    pub(crate) fn change_mode(&mut self, mode: DynPinMode) {
+        let ModeFields {
+            dir,
+            funsel,
+            opendrn,
+            pull_dir,
+            pull_en,
+            enb_input,
+        } = mode.into();
+        let (portreg, iocfg) = (self.port_reg(), self.iocfg_port());
+        iocfg.write(|w| {
+            w.opendrn().bit(opendrn);
+            w.pen().bit(pull_en);
+            w.plevel().bit(pull_dir);
+            w.iewo().bit(enb_input);
+            unsafe { w.funsel().bits(funsel) }
+        });
+        let mask = self.mask_32();
+        unsafe {
+            if dir {
+                portreg.dir().modify(|r, w| w.bits(r.bits() | mask));
+                // Clear output
+                portreg.clrout().write(|w| w.bits(mask));
+            } else {
+                portreg.dir().modify(|r, w| w.bits(r.bits() & !mask));
+            }
+        }
+    }
+
+    #[inline]
+    const fn port_reg(&self) -> &PortRegisterBlock {
+        match self.id().port() {
+            Port::A => unsafe { &(*pac::Porta::ptr()) },
+            Port::B => unsafe { &(*pac::Portb::ptr()) },
+        }
+    }
+
+    #[inline]
+    const fn iocfg_port(&self) -> &PortReg {
+        let ioconfig = unsafe { va108xx::Ioconfig::ptr().as_ref().unwrap() };
+        match self.id().port() {
+            Port::A => ioconfig.porta(self.id().num() as usize),
+            Port::B => ioconfig.portb0(self.id().num() as usize),
+        }
+    }
+
+    #[inline(always)]
+    fn read_internal(&self) -> Result<bool, InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Input(_) | DYN_RD_OPEN_DRAIN_OUTPUT | DYN_RD_PUSH_PULL_OUTPUT => {
+                Ok(self.read_pin())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    #[inline(always)]
+    fn write_internal(&mut self, bit: bool) -> Result<(), InvalidPinTypeError> {
+        match self.mode {
+            DynPinMode::Output(_) => {
+                self.write_pin(bit);
+                Ok(())
+            }
+            _ => Err(InvalidPinTypeError(self.mode)),
+        }
+    }
+
+    #[inline]
+    /// Read the logic level of an output pin
+    pub(crate) fn read_pin(&self) -> bool {
+        let portreg = self.port_reg();
+        ((portreg.datainraw().read().bits() >> self.id().num) & 0x01) == 1
+    }
+
+    /// Read a pin but use the masked version but check whether the datamask for the pin is
+    /// cleared as well
+    #[inline(always)]
+    fn read_pin_masked(&self) -> Result<bool, IsMaskedError> {
+        if !self.datamask() {
+            Err(IsMaskedError)
+        } else {
+            Ok(((self.port_reg().datain().read().bits() >> self.id().num) & 0x01) == 1)
+        }
+    }
+
+    /// Write the logic level of an output pin
+    #[inline(always)]
+    pub(crate) fn write_pin(&mut self, bit: bool) {
+        // Safety: SETOUT is a "mask" register, and we only write the bit for
+        // this pin ID
+        unsafe {
+            if bit {
+                self.port_reg().setout().write(|w| w.bits(self.mask_32()));
+            } else {
+                self.port_reg().clrout().write(|w| w.bits(self.mask_32()));
+            }
+        }
+    }
+
+    /// Write the logic level of an output pin but check whether the datamask for the pin is
+    /// cleared as well
+    #[inline]
+    fn write_pin_masked(&mut self, bit: bool) -> Result<(), IsMaskedError> {
+        if !self.datamask() {
+            Err(IsMaskedError)
+        } else {
+            // Safety: SETOUT is a "mask" register, and we only write the bit for
+            // this pin ID
+            unsafe {
+                if bit {
+                    self.port_reg().setout().write(|w| w.bits(self.mask_32()));
+                } else {
+                    self.port_reg().clrout().write(|w| w.bits(self.mask_32()));
+                }
+                Ok(())
+            }
+        }
+    }
+
+    /// Toggle the logic level of an output pin
+    #[inline(always)]
+    pub fn toggle_with_togout_reg(&mut self) {
+        // Safety: TOGOUT is a "mask" register, and we only write the bit for
+        // this pin ID
+        unsafe { self.port_reg().togout().write(|w| w.bits(self.mask_32())) };
+    }
+
+    /// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure
+    /// When using edge mode, it is possible to generate interrupts on both edges as well
+    #[inline]
+    fn configure_edge_interrupt_internal(&mut self, edge_type: InterruptEdge) {
+        unsafe {
+            self.port_reg()
+                .irq_sen()
+                .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            match edge_type {
+                InterruptEdge::HighToLow => {
+                    self.port_reg()
+                        .irq_evt()
+                        .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+                }
+                InterruptEdge::LowToHigh => {
+                    self.port_reg()
+                        .irq_evt()
+                        .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+                }
+                InterruptEdge::BothEdges => {
+                    self.port_reg()
+                        .irq_edge()
+                        .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+                }
+            }
+        }
+    }
+
+    /// Configure which edge or level type triggers an interrupt
+    #[inline]
+    fn configure_level_interrupt_internal(&mut self, level: InterruptLevel) {
+        unsafe {
+            self.port_reg()
+                .irq_sen()
+                .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            if level == InterruptLevel::Low {
+                self.port_reg()
+                    .irq_evt()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            } else {
+                self.port_reg()
+                    .irq_evt()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            }
+        }
+    }
+
+    /// Only useful for input pins
+    #[inline]
+    fn configure_filter_type_internal(&mut self, filter: FilterType, clksel: FilterClkSel) {
+        self.iocfg_port().modify(|_, w| {
+            // Safety: Only write to register for this Pin ID
+            unsafe {
+                w.flttype().bits(filter as u8);
+                w.fltclk().bits(clksel as u8)
+            }
+        });
+    }
+
+    #[inline]
+    fn configure_pulse_mode_internal(&mut self, enable: bool, default_state: PinState) {
+        let portreg = self.port_reg();
+        unsafe {
+            if enable {
+                portreg
+                    .pulse()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .pulse()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+            if default_state == PinState::Low {
+                portreg
+                    .pulsebase()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            } else {
+                portreg
+                    .pulsebase()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            }
+        }
+    }
+
+    /// Only useful for output pins
+    #[inline]
+    fn configure_delay_internal(&mut self, delay_1: bool, delay_2: bool) {
+        let portreg = self.port_reg();
+        unsafe {
+            if delay_1 {
+                portreg
+                    .delay1()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .delay1()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+            if delay_2 {
+                portreg
+                    .delay2()
+                    .modify(|r, w| w.bits(r.bits() | self.mask_32()));
+            } else {
+                portreg
+                    .delay2()
+                    .modify(|r, w| w.bits(r.bits() & !self.mask_32()));
+            }
+        }
+    }
+
+    // Only serves disambiguation purposes for the Embedded HAL impl
+    #[inline(always)]
+    fn is_low_mut(&mut self) -> Result<bool, InvalidPinTypeError> {
+        self.is_low()
+    }
+
+    // Only serves disambiguation purposes for the Embedded HAL impl
+    #[inline(always)]
+    fn is_high_mut(&mut self) -> Result<bool, InvalidPinTypeError> {
+        self.is_high()
+    }
+
+    #[inline(always)]
+    const fn mask_32(&self) -> u32 {
+        1 << self.id().num()
+    }
+}
+
+//==================================================================================================
+//  Convert between Pin and DynPin
+//==================================================================================================
+
+impl<I: PinId, M: PinMode> From<Pin<I, M>> for DynPin {
+    /// Erase the type-level information in a [`Pin`] and return a value-level
+    /// [`DynPin`]
+    #[inline]
+    fn from(pin: Pin<I, M>) -> Self {
+        pin.downgrade()
+    }
+}
+
+impl<I: PinId, M: PinMode> TryFrom<DynPin> for Pin<I, M> {
+    type Error = InvalidPinTypeError;
+
+    /// Try to recreate a type-level [`Pin`] from a value-level [`DynPin`]
+    ///
+    /// There is no way for the compiler to know if the conversion will be
+    /// successful at compile-time. We must verify the conversion at run-time
+    /// or refuse to perform it.
+    #[inline]
+    fn try_from(pin: DynPin) -> Result<Self, Self::Error> {
+        pin.upgrade()
+    }
+}
+
+//==================================================================================================
+// Embedded HAL traits
+//==================================================================================================
+
+impl embedded_hal::digital::ErrorType for DynPin {
+    type Error = InvalidPinTypeError;
+}
+
+impl embedded_hal::digital::OutputPin for DynPin {
+    #[inline]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self.set_high()
+    }
+    #[inline]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self.set_low()
+    }
+}
+
+impl embedded_hal::digital::InputPin for DynPin {
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        self.is_high_mut()
+    }
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        self.is_low_mut()
+    }
+}
+
+impl embedded_hal::digital::StatefulOutputPin for DynPin {
+    #[inline]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        self.is_high_mut()
+    }
+
+    #[inline]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        self.is_low_mut()
+    }
+
+    #[inline]
+    fn toggle(&mut self) -> Result<(), Self::Error> {
+        self.toggle()
+    }
+}

va108xx-hal/src/gpio/mod.rs

@@ -1,27 +1,74 @@
-//! GPIO support module.
+//! # API for the GPIO peripheral
 //!
-//! Contains abstractions to use the pins provided by the [crate::pins] module as GPIO or
-//! IO peripheral pins.
+//! The implementation of this GPIO module is heavily based on the
+//! [ATSAMD HAL implementation](https://docs.rs/atsamd-hal/latest/atsamd_hal/gpio/index.html).
 //!
-//! The core data structures provided for this are the
+//! This API provides two different submodules, [pin] and [dynpin],
+//! representing two different ways to handle GPIO pins. The default, [pin],
+//! is a type-level API that tracks the state of each pin at compile-time. The
+//! alternative, [dynpin] is a type-erased, value-level API that tracks the
+//! state of each pin at run-time.
 //!
-//! - [Output] for push-pull output pins.
-//! - [Input] for input pins.
-//! - [Flex] for pins with flexible configuration requirements.
-//! - [IoPeriphPin] for IO peripheral pins.
+//! The type-level API is strongly preferred. By representing the state of each
+//! pin within the type system, the compiler can detect logic errors at
+//! compile-time. Furthermore, the type-level API has absolutely zero run-time
+//! cost.
 //!
-//! The [crate::pins] module exposes singletons to access the [Pin]s required by this module
-//! in a type-safe way.
+//! If needed, [dynpin] can be used to erase the type-level differences
+//! between pins. However, by doing so, pins must now be tracked at run-time,
+//! and each pin has a non-zero memory footprint.
 //!
 //! ## Examples
 //!
 //! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
-//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs)
-pub use vorago_shared_periphs::gpio::*;
 
-pub use vorago_shared_periphs::gpio::asynch;
-/// Low-level GPIO access.
-pub use vorago_shared_periphs::gpio::ll;
+//==================================================================================================
+//  Errors, Definitions and Constants
+//==================================================================================================
 
-/// GPIO register definitions.
-pub use vorago_shared_periphs::gpio::regs;
+pub const NUM_PINS_PORT_A: usize = 32;
+pub const NUM_PINS_PORT_B: usize = 24;
+pub const NUM_GPIO_PINS: usize = NUM_PINS_PORT_A + NUM_PINS_PORT_B;
+
+#[derive(Debug, PartialEq, Eq, thiserror::Error)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[error("The pin is masked")]
+pub struct IsMaskedError;
+
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Port {
+    A,
+    B,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum InterruptEdge {
+    HighToLow,
+    LowToHigh,
+    BothEdges,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum InterruptLevel {
+    Low = 0,
+    High = 1,
+}
+
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum PinState {
+    Low = 0,
+    High = 1,
+}
+
+pub mod dynpin;
+pub use dynpin::*;
+
+pub mod pin;
+pub use pin::*;
+
+pub mod asynch;
+pub use asynch::*;

va108xx-hal/src/gpio/pin.rs

@@ -0,0 +1,823 @@
+//! # Type-level module for GPIO pins
+//!
+//! This documentation is strongly based on the
+//! [atsamd documentation](https://docs.rs/atsamd-hal/latest/atsamd_hal/gpio/pin/index.html).
+//!
+//! This module provides a type-level API for GPIO pins. It uses the type system
+//! to track the state of pins at compile-time. Representing GPIO pins in this
+//! manner incurs no run-time overhead. Each [`Pin`] struct is zero-sized, so
+//! there is no data to copy around. Instead, real code is generated as a side
+//! effect of type transformations, and the resulting assembly is nearly
+//! identical to the equivalent, hand-written C.
+//!
+//! To track the state of pins at compile-time, this module uses traits to
+//! represent [type classes] and types as instances of those type classes. For
+//! example, the trait [`InputConfig`] acts as a [type-level enum] of the
+//! available input configurations, and the types [`Floating`], [`PullDown`] and
+//! [`PullUp`] are its type-level variants.
+//!
+//! Type-level [`Pin`]s are parameterized by two type-level enums, [`PinId`] and
+//! [`PinMode`].
+//!
+//! ```
+//! pub struct Pin<I, M>
+//! where
+//!     I: PinId,
+//!     M: PinMode,
+//! {
+//!     // ...
+//! }
+//! ```
+//!
+//! A [PinId] identifies a pin by it's group (A or B) and pin number. Each
+//! [PinId] instance is named according to its datasheet identifier, e.g.
+//! [PA2].
+//!
+//! A [PinMode] represents the various pin modes. The available [PinMode]
+//! variants are [`Input`], [`Output`] and [`Alternate`], each with its own
+//! corresponding configurations.
+//!
+//! It is not possible for users to create new instances of a [`Pin`]. Singleton
+//! instances of each pin are made available to users through the PinsX
+//! struct.
+//!
+//! Example for the pins of PORT A:
+//!
+//! To create the [PinsA] struct, users must supply the PAC
+//! [Port](crate::pac::Porta) peripheral. The [PinsA] struct takes
+//! ownership of the [Porta] and provides the corresponding pins. Each [`Pin`]
+//! within the [PinsA] struct can be moved out and used individually.
+//!
+//!
+//! ```
+//! let mut peripherals = Peripherals::take().unwrap();
+//! let pinsa = PinsA::new(peripherals.PORT);
+//! ```
+//!
+//! Pins can be converted between modes using several different methods.
+//!
+//! ```no_run
+//! // Use one of the literal function names
+//! let pa0 = pinsa.pa0.into_floating_input();
+//! // Use a generic method and one of the `PinMode` variant types
+//! let pa0 = pinsa.pa0.into_mode::<FloatingInput>();
+//! // Specify the target type and use `From`/`Into`
+//! let pa0: Pin<PA0, FloatingInput> = pinsa.pa27.into();
+//! ```
+//!
+//! # Embedded HAL traits
+//!
+//! This module implements all of the embedded HAL GPIO traits for each [`Pin`]
+//! in the corresponding [`PinMode`]s, namely: [embedded_hal::digital::InputPin],
+//! [embedded_hal::digital::OutputPin] and [embedded_hal::digital::StatefulOutputPin].
+use super::dynpin::{DynAlternate, DynInput, DynOutput, DynPinId, DynPinMode};
+use super::{DynPin, InputPinAsync, InterruptEdge, InterruptLevel, PinState, Port};
+use crate::{
+    pac::{Porta, Portb},
+    typelevel::Sealed,
+};
+use core::convert::Infallible;
+use core::marker::PhantomData;
+use core::mem::transmute;
+use paste::paste;
+
+//==================================================================================================
+// Input configuration
+//==================================================================================================
+
+/// Type-level enum for input configurations
+///
+/// The valid options are [Floating], [PullDown] and [PullUp].
+pub trait InputConfig: Sealed {
+    /// Corresponding [DynInput]
+    const DYN: DynInput;
+}
+
+#[derive(Debug)]
+pub enum Floating {}
+#[derive(Debug)]
+pub enum PullDown {}
+#[derive(Debug)]
+pub enum PullUp {}
+
+impl InputConfig for Floating {
+    const DYN: DynInput = DynInput::Floating;
+}
+impl InputConfig for PullDown {
+    const DYN: DynInput = DynInput::PullDown;
+}
+impl InputConfig for PullUp {
+    const DYN: DynInput = DynInput::PullUp;
+}
+
+impl Sealed for Floating {}
+impl Sealed for PullDown {}
+impl Sealed for PullUp {}
+
+/// Type-level variant of [`PinMode`] for floating input mode
+pub type InputFloating = Input<Floating>;
+/// Type-level variant of [`PinMode`] for pull-down input mode
+pub type InputPullDown = Input<PullDown>;
+/// Type-level variant of [`PinMode`] for pull-up input mode
+pub type InputPullUp = Input<PullUp>;
+
+/// Type-level variant of [`PinMode`] for input modes
+///
+/// Type `C` is one of three input configurations: [`Floating`], [`PullDown`] or
+/// [`PullUp`]
+#[derive(Debug)]
+pub struct Input<C: InputConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: InputConfig> Sealed for Input<C> {}
+
+#[derive(Debug, PartialEq, Eq)]
+pub enum FilterType {
+    SystemClock = 0,
+    DirectInputWithSynchronization = 1,
+    FilterOneClockCycle = 2,
+    FilterTwoClockCycles = 3,
+    FilterThreeClockCycles = 4,
+    FilterFourClockCycles = 5,
+}
+
+pub use crate::clock::FilterClkSel;
+
+//==================================================================================================
+// Output configuration
+//==================================================================================================
+
+pub trait OutputConfig: Sealed {
+    const DYN: DynOutput;
+}
+
+pub trait ReadableOutput: Sealed {}
+
+/// Type-level variant of [`OutputConfig`] for a push-pull configuration
+#[derive(Debug)]
+pub enum PushPull {}
+/// Type-level variant of [`OutputConfig`] for an open drain configuration
+#[derive(Debug)]
+pub enum OpenDrain {}
+
+/// Type-level variant of [`OutputConfig`] for a readable push-pull configuration
+#[derive(Debug)]
+pub enum ReadablePushPull {}
+/// Type-level variant of [`OutputConfig`] for a readable open-drain configuration
+#[derive(Debug)]
+pub enum ReadableOpenDrain {}
+
+impl Sealed for PushPull {}
+impl Sealed for OpenDrain {}
+impl Sealed for ReadableOpenDrain {}
+impl Sealed for ReadablePushPull {}
+impl ReadableOutput for ReadableOpenDrain {}
+impl ReadableOutput for ReadablePushPull {}
+
+impl OutputConfig for PushPull {
+    const DYN: DynOutput = DynOutput::PushPull;
+}
+impl OutputConfig for OpenDrain {
+    const DYN: DynOutput = DynOutput::OpenDrain;
+}
+impl OutputConfig for ReadablePushPull {
+    const DYN: DynOutput = DynOutput::ReadablePushPull;
+}
+impl OutputConfig for ReadableOpenDrain {
+    const DYN: DynOutput = DynOutput::ReadableOpenDrain;
+}
+
+/// Type-level variant of [`PinMode`] for output modes
+///
+/// Type `C` is one of four output configurations: [`PushPull`], [`OpenDrain`] or
+/// their respective readable versions
+#[derive(Debug)]
+pub struct Output<C: OutputConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: OutputConfig> Sealed for Output<C> {}
+
+/// Type-level variant of [`PinMode`] for push-pull output mode
+pub type PushPullOutput = Output<PushPull>;
+/// Type-level variant of [`PinMode`] for open drain output mode
+pub type OutputOpenDrain = Output<OpenDrain>;
+
+pub type OutputReadablePushPull = Output<ReadablePushPull>;
+pub type OutputReadableOpenDrain = Output<ReadableOpenDrain>;
+
+//==================================================================================================
+//  Alternate configurations
+//==================================================================================================
+
+/// Type-level enum for alternate peripheral function configurations
+pub trait AlternateConfig: Sealed {
+    const DYN: DynAlternate;
+}
+
+pub enum Funsel1 {}
+pub enum Funsel2 {}
+pub enum Funsel3 {}
+
+impl AlternateConfig for Funsel1 {
+    const DYN: DynAlternate = DynAlternate::Sel1;
+}
+impl AlternateConfig for Funsel2 {
+    const DYN: DynAlternate = DynAlternate::Sel2;
+}
+impl AlternateConfig for Funsel3 {
+    const DYN: DynAlternate = DynAlternate::Sel3;
+}
+
+impl Sealed for Funsel1 {}
+impl Sealed for Funsel2 {}
+impl Sealed for Funsel3 {}
+
+/// Type-level variant of [`PinMode`] for alternate peripheral functions
+///
+/// Type `C` is an [`AlternateConfig`]
+pub struct Alternate<C: AlternateConfig> {
+    cfg: PhantomData<C>,
+}
+
+impl<C: AlternateConfig> Sealed for Alternate<C> {}
+
+pub type AltFunc1 = Alternate<Funsel1>;
+pub type AltFunc2 = Alternate<Funsel2>;
+pub type AltFunc3 = Alternate<Funsel3>;
+
+/// Type alias for the [`PinMode`] at reset
+pub type Reset = InputFloating;
+
+//==================================================================================================
+//  Pin modes
+//==================================================================================================
+
+/// Type-level enum representing pin modes
+///
+/// The valid options are [Input], [Output] and [Alternate].
+pub trait PinMode: Sealed {
+    /// Corresponding [DynPinMode]
+    const DYN: DynPinMode;
+}
+
+impl<C: InputConfig> PinMode for Input<C> {
+    const DYN: DynPinMode = DynPinMode::Input(C::DYN);
+}
+impl<C: OutputConfig> PinMode for Output<C> {
+    const DYN: DynPinMode = DynPinMode::Output(C::DYN);
+}
+impl<C: AlternateConfig> PinMode for Alternate<C> {
+    const DYN: DynPinMode = DynPinMode::Alternate(C::DYN);
+}
+
+//==================================================================================================
+//  Pin IDs
+//==================================================================================================
+
+/// Type-level enum for pin IDs
+pub trait PinId: Sealed {
+    /// Corresponding [DynPinId]
+    const DYN: DynPinId;
+}
+
+macro_rules! pin_id {
+    ($Group:ident, $Id:ident, $NUM:literal) => {
+        // Need paste macro to use ident in doc attribute
+        paste! {
+            #[doc = "Pin ID representing pin " $Id]
+            #[derive(Debug)]
+            pub enum $Id {}
+            impl Sealed for $Id {}
+            impl PinId for $Id {
+                const DYN: DynPinId = DynPinId::new(Port::$Group, $NUM);
+            }
+        }
+    };
+}
+
+//==================================================================================================
+//  Pin
+//==================================================================================================
+
+/// A type-level GPIO pin, parameterized by [PinId] and [PinMode] types
+#[derive(Debug)]
+pub struct Pin<I: PinId, M: PinMode> {
+    inner: DynPin,
+    phantom: PhantomData<(I, M)>,
+}
+
+impl<I: PinId, M: PinMode> Pin<I, M> {
+    /// Create a new [Pin]
+    ///
+    /// # Safety
+    ///
+    /// Each [Pin] must be a singleton. For a given [PinId], there must be
+    /// at most one corresponding [Pin] in existence at any given time.
+    /// Violating this requirement is `unsafe`.
+    #[inline]
+    pub(crate) const unsafe fn new() -> Pin<I, M> {
+        Pin {
+            inner: DynPin::new(I::DYN, M::DYN),
+            phantom: PhantomData,
+        }
+    }
+
+    #[inline]
+    pub const fn id(&self) -> DynPinId {
+        self.inner.id()
+    }
+
+    /// Convert the pin to the requested [`PinMode`]
+    #[inline]
+    pub fn into_mode<N: PinMode>(mut self) -> Pin<I, N> {
+        // Only modify registers if we are actually changing pin mode
+        // This check should compile away
+        if N::DYN != M::DYN {
+            self.inner.change_mode(N::DYN);
+        }
+        // Safe because we drop the existing Pin
+        unsafe { Pin::new() }
+    }
+
+    /// Configure the pin for function select 1. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_1(self) -> Pin<I, AltFunc1> {
+        self.into_mode()
+    }
+
+    /// Configure the pin for function select 2. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_2(self) -> Pin<I, AltFunc2> {
+        self.into_mode()
+    }
+
+    /// Configure the pin for function select 3. See Programmer Guide p.40 for the function table
+    #[inline]
+    pub fn into_funsel_3(self) -> Pin<I, AltFunc3> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a floating input
+    #[inline]
+    pub fn into_floating_input(self) -> Pin<I, InputFloating> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a pulled down input
+    #[inline]
+    pub fn into_pull_down_input(self) -> Pin<I, InputPullDown> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a pulled up input
+    #[inline]
+    pub fn into_pull_up_input(self) -> Pin<I, InputPullUp> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a push-pull output
+    #[inline]
+    pub fn into_push_pull_output(self) -> Pin<I, PushPullOutput> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a readable push-pull output
+    #[inline]
+    pub fn into_readable_push_pull_output(self) -> Pin<I, OutputReadablePushPull> {
+        self.into_mode()
+    }
+
+    /// Configure the pin to operate as a readable open-drain output
+    #[inline]
+    pub fn into_readable_open_drain_output(self) -> Pin<I, OutputReadableOpenDrain> {
+        self.into_mode()
+    }
+
+    #[inline]
+    pub fn is_low(&self) -> bool {
+        !self.inner.read_pin()
+    }
+
+    #[inline]
+    pub fn is_high(&self) -> bool {
+        self.inner.read_pin()
+    }
+
+    #[inline]
+    pub fn datamask(&self) -> bool {
+        self.inner.datamask()
+    }
+
+    #[inline]
+    pub fn clear_datamask(&mut self) {
+        self.inner.clear_datamask()
+    }
+
+    #[inline]
+    pub fn set_datamask(&mut self) {
+        self.inner.set_datamask()
+    }
+
+    #[inline]
+    pub fn is_high_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+        self.inner.is_high_masked()
+    }
+
+    #[inline]
+    pub fn is_low_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
+        self.inner.is_low_masked()
+    }
+
+    #[inline]
+    pub fn downgrade(self) -> DynPin {
+        self.inner
+    }
+
+    // Those only serve for the embedded HAL implementations which have different mutability.
+
+    #[inline]
+    fn is_low_mut(&mut self) -> bool {
+        self.is_low()
+    }
+
+    #[inline]
+    fn is_high_mut(&mut self) -> bool {
+        self.is_high()
+    }
+
+    #[inline]
+    pub fn enable_interrupt(&mut self, irq_cfg: crate::InterruptConfig) {
+        self.inner.enable_interrupt(irq_cfg);
+    }
+
+    #[inline]
+    pub fn disable_interrupt(&mut self, reset_irqsel: bool) {
+        self.inner.disable_interrupt(reset_irqsel);
+    }
+
+    /// Configure the pin for an edge interrupt but does not enable the interrupt.
+    pub fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) {
+        self.inner.configure_edge_interrupt(edge_type).unwrap();
+    }
+
+    /// Configure the pin for a level interrupt but does not enable the interrupt.
+    pub fn configure_level_interrupt(&mut self, level_type: InterruptLevel) {
+        self.inner.configure_level_interrupt(level_type).unwrap();
+    }
+}
+
+//==============================================================================
+//  AnyPin
+//==============================================================================
+
+/// Type class for [`Pin`] types
+///
+/// This trait uses the [`AnyKind`] trait pattern to create a [type class] for
+/// [`Pin`] types. See the `AnyKind` documentation for more details on the
+/// pattern.
+///
+/// ## `v1` Compatibility
+///
+/// Normally, this trait would use `Is<Type = SpecificPin<Self>>` as a super
+/// trait. But doing so would restrict implementations to only the `v2` `Pin`
+/// type in this module. To aid in backwards compatibility, we want to implement
+/// `AnyPin` for the `v1` `Pin` type as well. This is possible for a few
+/// reasons. First, both structs are zero-sized, so there is no meaningful
+/// memory layout to begin with. And even if there were, the `v1` `Pin` type is
+/// a newtype wrapper around a `v2` `Pin`, and single-field structs are
+/// guaranteed to have the same layout as the field, even for `repr(Rust)`.
+///
+/// [`AnyKind`]: crate::typelevel#anykind-trait-pattern
+/// [type class]: crate::typelevel#type-classes
+pub trait AnyPin
+where
+    Self: Sealed,
+    Self: From<SpecificPin<Self>>,
+    Self: Into<SpecificPin<Self>>,
+    Self: AsRef<SpecificPin<Self>>,
+    Self: AsMut<SpecificPin<Self>>,
+{
+    /// [`PinId`] of the corresponding [`Pin`]
+    type Id: PinId;
+    /// [`PinMode`] of the corresponding [`Pin`]
+    type Mode: PinMode;
+}
+
+impl<I, M> Sealed for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+}
+
+impl<I, M> AnyPin for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+    type Id = I;
+    type Mode = M;
+}
+
+/// Type alias to recover the specific [`Pin`] type from an implementation of
+/// [`AnyPin`]
+///
+/// See the [`AnyKind`] documentation for more details on the pattern.
+///
+/// [`AnyKind`]: crate::typelevel#anykind-trait-pattern
+pub type SpecificPin<P> = Pin<<P as AnyPin>::Id, <P as AnyPin>::Mode>;
+
+impl<P: AnyPin> AsRef<P> for SpecificPin<P> {
+    #[inline]
+    fn as_ref(&self) -> &P {
+        // SAFETY: This is guaranteed to be safe, because P == SpecificPin<P>
+        // Transmuting between `v1` and `v2` `Pin` types is also safe, because
+        // both are zero-sized, and single-field, newtype structs are guaranteed
+        // to have the same layout as the field anyway, even for repr(Rust).
+        unsafe { transmute(self) }
+    }
+}
+
+impl<P: AnyPin> AsMut<P> for SpecificPin<P> {
+    #[inline]
+    fn as_mut(&mut self) -> &mut P {
+        // SAFETY: This is guaranteed to be safe, because P == SpecificPin<P>
+        // Transmuting between `v1` and `v2` `Pin` types is also safe, because
+        // both are zero-sized, and single-field, newtype structs are guaranteed
+        // to have the same layout as the field anyway, even for repr(Rust).
+        unsafe { transmute(self) }
+    }
+}
+
+//==================================================================================================
+//  Additional functionality
+//==================================================================================================
+
+impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
+    /// Convert the pin into an async pin. The pin can be converted back by calling
+    /// [InputPinAsync::release]
+    pub fn into_async_input(self, irq: crate::pac::Interrupt) -> InputPinAsync<I, C> {
+        InputPinAsync::new(self, irq)
+    }
+}
+
+impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
+    #[inline]
+    pub fn set_high(&mut self) {
+        self.inner.write_pin(true)
+    }
+
+    #[inline]
+    pub fn set_low(&mut self) {
+        self.inner.write_pin(false)
+    }
+
+    #[inline]
+    pub fn toggle(&mut self) {
+        self.inner.toggle().unwrap()
+    }
+
+    #[inline]
+    pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+        self.inner.set_high_masked()
+    }
+
+    #[inline]
+    pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
+        self.inner.set_low_masked()
+    }
+
+    /// See p.53 of the programmers guide for more information.
+    /// Possible delays in clock cycles:
+    ///  - Delay 1: 1
+    ///  - Delay 2: 2
+    ///  - Delay 1 + Delay 2: 3
+    #[inline]
+    pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool) {
+        self.inner.configure_delay(delay_1, delay_2).unwrap();
+    }
+
+    /// See p.52 of the programmers guide for more information.
+    ///
+    /// When configured for pulse mode, a given pin will set the non-default state for exactly
+    /// one clock cycle before returning to the configured default state
+    pub fn configure_pulse_mode(&mut self, enable: bool, default_state: PinState) {
+        self.inner
+            .configure_pulse_mode(enable, default_state)
+            .unwrap();
+    }
+}
+
+impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
+    /// See p.37 and p.38 of the programmers guide for more information.
+    #[inline]
+    pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
+        self.inner.configure_filter_type(filter, clksel).unwrap();
+    }
+}
+
+//==================================================================================================
+//  Embedded HAL traits
+//==================================================================================================
+
+impl<I, M> embedded_hal::digital::ErrorType for Pin<I, M>
+where
+    I: PinId,
+    M: PinMode,
+{
+    type Error = Infallible;
+}
+
+impl<I: PinId, C: OutputConfig> embedded_hal::digital::OutputPin for Pin<I, Output<C>> {
+    #[inline]
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self.set_high();
+        Ok(())
+    }
+
+    #[inline]
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self.set_low();
+        Ok(())
+    }
+}
+
+impl<I, C> embedded_hal::digital::InputPin for Pin<I, Input<C>>
+where
+    I: PinId,
+    C: InputConfig,
+{
+    #[inline]
+    fn is_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(self.is_high_mut())
+    }
+    #[inline]
+    fn is_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self.is_low_mut())
+    }
+}
+
+impl<I, C> embedded_hal::digital::StatefulOutputPin for Pin<I, Output<C>>
+where
+    I: PinId,
+    C: OutputConfig + ReadableOutput,
+{
+    #[inline]
+    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
+        Ok(self.is_high())
+    }
+    #[inline]
+    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
+        Ok(self.is_low())
+    }
+
+    #[inline]
+    fn toggle(&mut self) -> Result<(), Self::Error> {
+        self.toggle();
+        Ok(())
+    }
+}
+
+//==================================================================================================
+//  Pin definitions
+//==================================================================================================
+
+macro_rules! pins {
+    (
+        $Port:ident, $PinsName:ident, $($Id:ident,)+,
+    ) => {
+        paste!(
+            /// Collection of all the individual [`Pin`]s for a given port (PORTA or PORTB)
+            #[derive(Debug)]
+            pub struct $PinsName {
+                port: $Port,
+                $(
+                    #[doc = "Pin " $Id]
+                    pub [<$Id:lower>]: Pin<$Id, Reset>,
+                )+
+            }
+
+            impl $PinsName {
+                /// Create a new struct containing all the Pins. Passing the IOCONFIG peripheral
+                /// is optional because it might be required to create pin definitions for both
+                /// ports.
+                #[inline]
+                pub fn new(
+                    syscfg: &mut va108xx::Sysconfig,
+                    port: $Port
+                ) -> $PinsName {
+                    syscfg.peripheral_clk_enable().modify(|_, w| {
+                        w.[<$Port:lower>]().set_bit();
+                        w.gpio().set_bit();
+                        w.ioconfig().set_bit()
+                    });
+                    $PinsName {
+                        //iocfg,
+                        port,
+                        // Safe because we only create one `Pin` per `PinId`
+                        $(
+                            [<$Id:lower>]: unsafe { Pin::new() },
+                        )+
+                    }
+                }
+
+                /// Get the peripheral ID
+                /// Safety: Read-only register
+                pub fn get_perid() -> u32 {
+                    let port = unsafe { &(*$Port::ptr()) };
+                    port.perid().read().bits()
+                }
+
+                /// Consumes the Pins struct and returns the port definitions
+                pub fn release(self) -> $Port {
+                    self.port
+                }
+            }
+        );
+    }
+}
+
+macro_rules! declare_pins {
+    (
+        $Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal),)+]
+    ) => {
+        pins!($Port, $PinsName, $($Id,)+,);
+        $(
+            pin_id!($Group, $Id, $NUM);
+        )+
+    }
+}
+
+declare_pins!(
+    A,
+    PinsA,
+    Porta,
+    [
+        (PA0, 0),
+        (PA1, 1),
+        (PA2, 2),
+        (PA3, 3),
+        (PA4, 4),
+        (PA5, 5),
+        (PA6, 6),
+        (PA7, 7),
+        (PA8, 8),
+        (PA9, 9),
+        (PA10, 10),
+        (PA11, 11),
+        (PA12, 12),
+        (PA13, 13),
+        (PA14, 14),
+        (PA15, 15),
+        (PA16, 16),
+        (PA17, 17),
+        (PA18, 18),
+        (PA19, 19),
+        (PA20, 20),
+        (PA21, 21),
+        (PA22, 22),
+        (PA23, 23),
+        (PA24, 24),
+        (PA25, 25),
+        (PA26, 26),
+        (PA27, 27),
+        (PA28, 28),
+        (PA29, 29),
+        (PA30, 30),
+        (PA31, 31),
+    ]
+);
+
+declare_pins!(
+    B,
+    PinsB,
+    Portb,
+    [
+        (PB0, 0),
+        (PB1, 1),
+        (PB2, 2),
+        (PB3, 3),
+        (PB4, 4),
+        (PB5, 5),
+        (PB6, 6),
+        (PB7, 7),
+        (PB8, 8),
+        (PB9, 9),
+        (PB10, 10),
+        (PB11, 11),
+        (PB12, 12),
+        (PB13, 13),
+        (PB14, 14),
+        (PB15, 15),
+        (PB16, 16),
+        (PB17, 17),
+        (PB18, 18),
+        (PB19, 19),
+        (PB20, 20),
+        (PB21, 21),
+        (PB22, 22),
+        (PB23, 23),
+    ]
+);

va108xx-hal/src/i2c.rs

@@ -3,7 +3,9 @@
 //! ## Examples
 //!
 //! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs)
-use crate::{clock::enable_peripheral_clock, pac, sealed::Sealed, time::Hertz, PeripheralSelect};
+use crate::{
+    clock::enable_peripheral_clock, pac, time::Hertz, typelevel::Sealed, PeripheralSelect,
+};
 use core::{marker::PhantomData, ops::Deref};
 use embedded_hal::i2c::{self, Operation, SevenBitAddress, TenBitAddress};
 
@@ -15,13 +17,6 @@ const CLK_100K: Hertz = Hertz::from_raw(100_000);
 const CLK_400K: Hertz = Hertz::from_raw(400_000);
 const MIN_CLK_400K: Hertz = Hertz::from_raw(8_000_000);
 
-#[derive(Debug, PartialEq, Eq, Copy, Clone)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum I2cId {
-    A = 0,
-    B = 1,
-}
-
 #[derive(Debug, PartialEq, Eq, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum FifoEmptyMode {
@@ -118,18 +113,16 @@ pub type I2cRegBlock = pac::i2ca::RegisterBlock;
 
 /// Common trait implemented by all PAC peripheral access structures. The register block
 /// format is the same for all SPI blocks.
-pub trait I2cMarker: Deref<Target = I2cRegBlock> {
-    const ID: I2cId;
+pub trait Instance: Deref<Target = I2cRegBlock> {
+    const IDX: u8;
     const PERIPH_SEL: PeripheralSelect;
-    const PTR: *const I2cRegBlock;
 
     fn ptr() -> *const I2cRegBlock;
 }
 
-impl I2cMarker for pac::I2ca {
-    const ID: I2cId = I2cId::A;
+impl Instance for pac::I2ca {
+    const IDX: u8 = 0;
     const PERIPH_SEL: PeripheralSelect = PeripheralSelect::I2c0;
-    const PTR: *const I2cRegBlock = Self::PTR;
 
     #[inline(always)]
     fn ptr() -> *const I2cRegBlock {
@@ -137,10 +130,9 @@ impl I2cMarker for pac::I2ca {
     }
 }
 
-impl I2cMarker for pac::I2cb {
-    const ID: I2cId = I2cId::B;
+impl Instance for pac::I2cb {
+    const IDX: u8 = 1;
     const PERIPH_SEL: PeripheralSelect = PeripheralSelect::I2c1;
-    const PTR: *const I2cRegBlock = Self::PTR;
 
     #[inline(always)]
     fn ptr() -> *const I2cRegBlock {
@@ -300,26 +292,35 @@ impl Sealed for SlaveConfig {}
 // I2C Base
 //==================================================================================================
 
-pub struct I2cCommon {
-    id: I2cId,
-    reg_block: *const I2cRegBlock,
+pub struct I2cBase<I2C> {
+    i2c: I2C,
     sys_clk: Hertz,
 }
 
-impl I2cCommon {
-    pub fn new<I2c: I2cMarker>(
-        sys_clk: Hertz,
-        _i2c: I2c,
+impl<I2C> I2cBase<I2C> {
+    #[inline]
+    fn unwrap_addr(addr: I2cAddress) -> (u16, u32) {
+        match addr {
+            I2cAddress::Regular(addr) => (addr as u16, 0 << 15),
+            I2cAddress::TenBit(addr) => (addr, 1 << 15),
+        }
+    }
+}
+
+impl<I2c: Instance> I2cBase<I2c> {
+    pub fn new(
+        syscfg: &mut pac::Sysconfig,
+        sysclk: impl Into<Hertz>,
+        i2c: I2c,
         speed_mode: I2cSpeed,
         ms_cfg: Option<&MasterConfig>,
         sl_cfg: Option<&SlaveConfig>,
     ) -> Result<Self, ClockTooSlowForFastI2cError> {
-        enable_peripheral_clock(I2c::PERIPH_SEL);
+        enable_peripheral_clock(syscfg, I2c::PERIPH_SEL);
 
-        let mut i2c_base = I2cCommon {
-            id: I2c::ID,
-            reg_block: I2c::PTR,
-            sys_clk,
+        let mut i2c_base = I2cBase {
+            i2c,
+            sys_clk: sysclk.into(),
         };
         if let Some(ms_cfg) = ms_cfg {
             i2c_base.cfg_master(ms_cfg);
@@ -332,32 +333,6 @@ impl I2cCommon {
         Ok(i2c_base)
     }
 
-    pub fn id(&self) -> I2cId {
-        self.id
-    }
-
-    // Returns the address and the address mode bit.
-    #[inline]
-    fn unwrap_addr(addr: I2cAddress) -> (u16, u32) {
-        match addr {
-            I2cAddress::Regular(addr) => (addr as u16, 0 << 15),
-            I2cAddress::TenBit(addr) => (addr, 1 << 15),
-        }
-    }
-
-    /// Retrieve the raw register block.
-    ///
-    /// # Safety
-    ///
-    /// Circumvents safety guarantees by the HAL.
-    pub const unsafe fn regs(&self) -> &'static I2cRegBlock {
-        self.regs_priv()
-    }
-
-    const fn regs_priv(&self) -> &'static I2cRegBlock {
-        unsafe { &*self.reg_block }
-    }
-
     fn cfg_master(&mut self, ms_cfg: &MasterConfig) {
         let (txfemd, rxfemd) = match (ms_cfg.tx_fe_mode, ms_cfg.rx_fe_mode) {
             (FifoEmptyMode::Stall, FifoEmptyMode::Stall) => (false, false),
@@ -365,17 +340,18 @@ impl I2cCommon {
             (FifoEmptyMode::EndTransaction, FifoEmptyMode::Stall) => (true, false),
             (FifoEmptyMode::EndTransaction, FifoEmptyMode::EndTransaction) => (true, true),
         };
-        let regs = self.regs_priv();
-        regs.ctrl().modify(|_, w| {
+        self.i2c.ctrl().modify(|_, w| {
             w.txfemd().bit(txfemd);
             w.rxffmd().bit(rxfemd);
             w.dlgfilter().bit(ms_cfg.dlg_filt);
             w.algfilter().bit(ms_cfg.alg_filt)
         });
         if let Some(ref tm_cfg) = ms_cfg.tm_cfg {
-            regs.tmconfig().write(|w| unsafe { w.bits(tm_cfg.reg()) });
+            self.i2c
+                .tmconfig()
+                .write(|w| unsafe { w.bits(tm_cfg.reg()) });
         }
-        regs.fifo_clr().write(|w| {
+        self.i2c.fifo_clr().write(|w| {
             w.rxfifo().set_bit();
             w.txfifo().set_bit()
         });
@@ -388,43 +364,47 @@ impl I2cCommon {
             (FifoEmptyMode::EndTransaction, FifoEmptyMode::Stall) => (true, false),
             (FifoEmptyMode::EndTransaction, FifoEmptyMode::EndTransaction) => (true, true),
         };
-        let regs = self.regs_priv();
-        regs.s0_ctrl().modify(|_, w| {
+        self.i2c.s0_ctrl().modify(|_, w| {
             w.txfemd().bit(txfemd);
             w.rxffmd().bit(rxfemd)
         });
-        regs.s0_fifo_clr().write(|w| {
+        self.i2c.s0_fifo_clr().write(|w| {
             w.rxfifo().set_bit();
             w.txfifo().set_bit()
         });
         let max_words = sl_cfg.max_words;
         if let Some(max_words) = max_words {
-            regs.s0_maxwords()
+            self.i2c
+                .s0_maxwords()
                 .write(|w| unsafe { w.bits((1 << 31) | max_words as u32) });
         }
         let (addr, addr_mode_mask) = Self::unwrap_addr(sl_cfg.addr);
         // The first bit is the read/write value. Normally, both read and write are matched
         // using the RWMASK bit of the address mask register
-        regs.s0_address()
+        self.i2c
+            .s0_address()
             .write(|w| unsafe { w.bits((addr << 1) as u32 | addr_mode_mask) });
         if let Some(addr_mask) = sl_cfg.addr_mask {
-            regs.s0_addressmask()
+            self.i2c
+                .s0_addressmask()
                 .write(|w| unsafe { w.bits((addr_mask << 1) as u32) });
         }
         if let Some(addr_b) = sl_cfg.addr_b {
             let (addr, addr_mode_mask) = Self::unwrap_addr(addr_b);
-            regs.s0_addressb()
+            self.i2c
+                .s0_addressb()
                 .write(|w| unsafe { w.bits((addr << 1) as u32 | addr_mode_mask) });
         }
         if let Some(addr_b_mask) = sl_cfg.addr_b_mask {
-            regs.s0_addressmaskb()
+            self.i2c
+                .s0_addressmaskb()
                 .write(|w| unsafe { w.bits((addr_b_mask << 1) as u32) });
         }
     }
 
     #[inline]
     pub fn filters(&mut self, digital_filt: bool, analog_filt: bool) {
-        self.regs_priv().ctrl().modify(|_, w| {
+        self.i2c.ctrl().modify(|_, w| {
             w.dlgfilter().bit(digital_filt);
             w.algfilter().bit(analog_filt)
         });
@@ -432,7 +412,7 @@ impl I2cCommon {
 
     #[inline]
     pub fn fifo_empty_mode(&mut self, rx: FifoEmptyMode, tx: FifoEmptyMode) {
-        self.regs_priv().ctrl().modify(|_, w| {
+        self.i2c.ctrl().modify(|_, w| {
             w.txfemd().bit(tx as u8 != 0);
             w.rxffmd().bit(rx as u8 != 0)
         });
@@ -455,7 +435,7 @@ impl I2cCommon {
         speed_mode: I2cSpeed,
     ) -> Result<(), ClockTooSlowForFastI2cError> {
         let clk_div = self.calc_clk_div(speed_mode)?;
-        self.regs_priv()
+        self.i2c
             .clkscale()
             .write(|w| unsafe { w.bits(((speed_mode as u32) << 31) | clk_div as u32) });
         Ok(())
@@ -463,14 +443,14 @@ impl I2cCommon {
 
     pub fn load_address(&mut self, addr: u16) {
         // Load address
-        self.regs_priv()
+        self.i2c
             .address()
             .write(|w| unsafe { w.bits((addr << 1) as u32) });
     }
 
     #[inline]
     fn stop_cmd(&mut self) {
-        self.regs_priv()
+        self.i2c
             .cmd()
             .write(|w| unsafe { w.bits(I2cCmd::Stop as u32) });
     }
@@ -480,20 +460,21 @@ impl I2cCommon {
 // I2C Master
 //==================================================================================================
 
-pub struct I2cMaster<Addr = SevenBitAddress> {
-    inner: I2cCommon,
+pub struct I2cMaster<I2c, Addr = SevenBitAddress> {
+    i2c_base: I2cBase<I2c>,
     addr: PhantomData<Addr>,
 }
 
-impl<Addr> I2cMaster<Addr> {
-    pub fn new<I2c: I2cMarker>(
-        sysclk: Hertz,
+impl<I2c: Instance, Addr> I2cMaster<I2c, Addr> {
+    pub fn new(
+        syscfg: &mut pac::Sysconfig,
+        sysclk: impl Into<Hertz>,
         i2c: I2c,
         cfg: MasterConfig,
         speed_mode: I2cSpeed,
     ) -> Result<Self, ClockTooSlowForFastI2cError> {
         Ok(I2cMaster {
-            inner: I2cCommon::new(sysclk, i2c, speed_mode, Some(&cfg), None)?,
+            i2c_base: I2cBase::new(syscfg, sysclk, i2c, speed_mode, Some(&cfg), None)?,
             addr: PhantomData,
         }
         .enable_master())
@@ -501,41 +482,32 @@ impl<Addr> I2cMaster<Addr> {
 
     #[inline]
     pub fn cancel_transfer(&self) {
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .cmd()
             .write(|w| unsafe { w.bits(I2cCmd::Cancel as u32) });
     }
 
     #[inline]
     pub fn clear_tx_fifo(&self) {
-        self.inner
-            .regs_priv()
-            .fifo_clr()
-            .write(|w| w.txfifo().set_bit());
+        self.i2c_base.i2c.fifo_clr().write(|w| w.txfifo().set_bit());
     }
 
     #[inline]
     pub fn clear_rx_fifo(&self) {
-        self.inner
-            .regs_priv()
-            .fifo_clr()
-            .write(|w| w.rxfifo().set_bit());
+        self.i2c_base.i2c.fifo_clr().write(|w| w.rxfifo().set_bit());
     }
 
     #[inline]
     pub fn enable_master(self) -> Self {
-        self.inner
-            .regs_priv()
-            .ctrl()
-            .modify(|_, w| w.enable().set_bit());
+        self.i2c_base.i2c.ctrl().modify(|_, w| w.enable().set_bit());
         self
     }
 
     #[inline]
     pub fn disable_master(self) -> Self {
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .ctrl()
             .modify(|_, w| w.enable().clear_bit());
         self
@@ -543,21 +515,21 @@ impl<Addr> I2cMaster<Addr> {
 
     #[inline(always)]
     fn load_fifo(&self, word: u8) {
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .data()
             .write(|w| unsafe { w.bits(word as u32) });
     }
 
     #[inline(always)]
     fn read_fifo(&self) -> u8 {
-        self.inner.regs_priv().data().read().bits() as u8
+        self.i2c_base.i2c.data().read().bits() as u8
     }
 
     fn error_handler_write(&mut self, init_cmd: &I2cCmd) {
         self.clear_tx_fifo();
         if *init_cmd == I2cCmd::Start {
-            self.inner.stop_cmd()
+            self.i2c_base.stop_cmd()
         }
     }
 
@@ -569,13 +541,13 @@ impl<Addr> I2cMaster<Addr> {
     ) -> Result<(), Error> {
         let mut iter = bytes.into_iter();
         // Load address
-        let (addr, addr_mode_bit) = I2cCommon::unwrap_addr(addr);
-        self.inner.regs_priv().address().write(|w| unsafe {
+        let (addr, addr_mode_bit) = I2cBase::<I2c>::unwrap_addr(addr);
+        self.i2c_base.i2c.address().write(|w| unsafe {
             w.bits(I2cDirection::Send as u32 | (addr << 1) as u32 | addr_mode_bit)
         });
 
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .cmd()
             .write(|w| unsafe { w.bits(init_cmd as u32) });
         let mut load_if_next_available = || {
@@ -584,7 +556,7 @@ impl<Addr> I2cMaster<Addr> {
             }
         };
         loop {
-            let status_reader = self.inner.regs_priv().status().read();
+            let status_reader = self.i2c_base.i2c.status().read();
             if status_reader.arblost().bit_is_set() {
                 self.error_handler_write(&init_cmd);
                 return Err(Error::ArbitrationLost);
@@ -619,8 +591,8 @@ impl<Addr> I2cMaster<Addr> {
             return Err(Error::DataTooLarge);
         }
         // Load number of words
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .words()
             .write(|w| unsafe { w.bits(len as u32) });
         let mut bytes = output.iter();
@@ -649,8 +621,8 @@ impl<Addr> I2cMaster<Addr> {
         self.clear_rx_fifo();
 
         // Load number of words
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .words()
             .write(|w| unsafe { w.bits(len as u32) });
         let (addr, addr_mode_bit) = match addr {
@@ -658,15 +630,15 @@ impl<Addr> I2cMaster<Addr> {
             I2cAddress::TenBit(addr) => (addr, 1 << 15),
         };
         // Load address
-        self.inner.regs_priv().address().write(|w| unsafe {
+        self.i2c_base.i2c.address().write(|w| unsafe {
             w.bits(I2cDirection::Read as u32 | (addr << 1) as u32 | addr_mode_bit)
         });
 
         let mut buf_iter = buffer.iter_mut();
         let mut read_bytes = 0;
         // Start receive transfer
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .cmd()
             .write(|w| unsafe { w.bits(I2cCmd::StartWithStop as u32) });
         let mut read_if_next_available = || {
@@ -675,7 +647,7 @@ impl<Addr> I2cMaster<Addr> {
             }
         };
         loop {
-            let status_reader = self.inner.regs_priv().status().read();
+            let status_reader = self.i2c_base.i2c.status().read();
             if status_reader.arblost().bit_is_set() {
                 self.clear_rx_fifo();
                 return Err(Error::ArbitrationLost);
@@ -699,11 +671,11 @@ impl<Addr> I2cMaster<Addr> {
 // Embedded HAL I2C implementations
 //======================================================================================
 
-impl embedded_hal::i2c::ErrorType for I2cMaster<SevenBitAddress> {
+impl<I2c> embedded_hal::i2c::ErrorType for I2cMaster<I2c, SevenBitAddress> {
     type Error = Error;
 }
 
-impl embedded_hal::i2c::I2c for I2cMaster<SevenBitAddress> {
+impl<I2c: Instance> embedded_hal::i2c::I2c for I2cMaster<I2c, SevenBitAddress> {
     fn transaction(
         &mut self,
         address: SevenBitAddress,
@@ -723,11 +695,11 @@ impl embedded_hal::i2c::I2c for I2cMaster<SevenBitAddress> {
     }
 }
 
-impl embedded_hal::i2c::ErrorType for I2cMaster<TenBitAddress> {
+impl<I2c> embedded_hal::i2c::ErrorType for I2cMaster<I2c, TenBitAddress> {
     type Error = Error;
 }
 
-impl embedded_hal::i2c::I2c<TenBitAddress> for I2cMaster<TenBitAddress> {
+impl<I2c: Instance> embedded_hal::i2c::I2c<TenBitAddress> for I2cMaster<I2c, TenBitAddress> {
     fn transaction(
         &mut self,
         address: TenBitAddress,
@@ -749,20 +721,21 @@ impl embedded_hal::i2c::I2c<TenBitAddress> for I2cMaster<TenBitAddress> {
 // I2C Slave
 //==================================================================================================
 
-pub struct I2cSlave<Addr = SevenBitAddress> {
-    inner: I2cCommon,
+pub struct I2cSlave<I2c, Addr = SevenBitAddress> {
+    i2c_base: I2cBase<I2c>,
     addr: PhantomData<Addr>,
 }
 
-impl<Addr> I2cSlave<Addr> {
-    fn new_generic<I2c: I2cMarker>(
-        sys_clk: Hertz,
+impl<I2c: Instance, Addr> I2cSlave<I2c, Addr> {
+    fn new_generic(
+        sys_cfg: &mut pac::Sysconfig,
+        sys_clk: impl Into<Hertz>,
         i2c: I2c,
         cfg: SlaveConfig,
         speed_mode: I2cSpeed,
     ) -> Result<Self, ClockTooSlowForFastI2cError> {
         Ok(I2cSlave {
-            inner: I2cCommon::new(sys_clk, i2c, speed_mode, None, Some(&cfg))?,
+            i2c_base: I2cBase::new(sys_cfg, sys_clk, i2c, speed_mode, None, Some(&cfg))?,
             addr: PhantomData,
         }
         .enable_slave())
@@ -770,8 +743,8 @@ impl<Addr> I2cSlave<Addr> {
 
     #[inline]
     pub fn enable_slave(self) -> Self {
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .s0_ctrl()
             .modify(|_, w| w.enable().set_bit());
         self
@@ -779,8 +752,8 @@ impl<Addr> I2cSlave<Addr> {
 
     #[inline]
     pub fn disable_slave(self) -> Self {
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .s0_ctrl()
             .modify(|_, w| w.enable().clear_bit());
         self
@@ -788,29 +761,29 @@ impl<Addr> I2cSlave<Addr> {
 
     #[inline(always)]
     fn load_fifo(&self, word: u8) {
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .s0_data()
             .write(|w| unsafe { w.bits(word as u32) });
     }
 
     #[inline(always)]
     fn read_fifo(&self) -> u8 {
-        self.inner.regs_priv().s0_data().read().bits() as u8
+        self.i2c_base.i2c.s0_data().read().bits() as u8
     }
 
     #[inline]
     fn clear_tx_fifo(&self) {
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .s0_fifo_clr()
             .write(|w| w.txfifo().set_bit());
     }
 
     #[inline]
     fn clear_rx_fifo(&self) {
-        self.inner
-            .regs_priv()
+        self.i2c_base
+            .i2c
             .s0_fifo_clr()
             .write(|w| w.rxfifo().set_bit());
     }
@@ -818,7 +791,7 @@ impl<Addr> I2cSlave<Addr> {
     /// Get the last address that was matched by the slave control and the corresponding
     /// master direction
     pub fn last_address(&self) -> (I2cDirection, u32) {
-        let bits = self.inner.regs_priv().s0_lastaddress().read().bits();
+        let bits = self.i2c_base.i2c.s0_lastaddress().read().bits();
         match bits & 0x01 {
             0 => (I2cDirection::Send, bits >> 1),
             1 => (I2cDirection::Read, bits >> 1),
@@ -845,7 +818,7 @@ impl<Addr> I2cSlave<Addr> {
             self.load_fifo(*bytes.next().unwrap());
         }
 
-        let status_reader = self.inner.regs_priv().s0_status().read();
+        let status_reader = self.i2c_base.i2c.s0_status().read();
         let mut load_if_next_available = || {
             if let Some(next_byte) = bytes.next() {
                 self.load_fifo(*next_byte);
@@ -885,7 +858,7 @@ impl<Addr> I2cSlave<Addr> {
             }
         };
         loop {
-            let status_reader = self.inner.regs_priv().s0_status().read();
+            let status_reader = self.i2c_base.i2c.s0_status().read();
             if status_reader.idle().bit_is_set() {
                 if read_bytes != len {
                     return Err(Error::InsufficientDataReceived);
@@ -899,10 +872,11 @@ impl<Addr> I2cSlave<Addr> {
     }
 }
 
-impl I2cSlave<SevenBitAddress> {
+impl<I2c: Instance> I2cSlave<I2c, SevenBitAddress> {
     /// Create a new I2C slave for seven bit addresses
-    pub fn new<I2c: I2cMarker>(
-        sys_clk: Hertz,
+    pub fn new(
+        sys_cfg: &mut pac::Sysconfig,
+        sys_clk: impl Into<Hertz>,
         i2c: I2c,
         cfg: SlaveConfig,
         speed_mode: I2cSpeed,
@@ -910,17 +884,18 @@ impl I2cSlave<SevenBitAddress> {
         if let I2cAddress::TenBit(_) = cfg.addr {
             return Err(InitError::WrongAddrMode);
         }
-        Ok(Self::new_generic(sys_clk, i2c, cfg, speed_mode)?)
+        Ok(Self::new_generic(sys_cfg, sys_clk, i2c, cfg, speed_mode)?)
     }
 }
 
-impl I2cSlave<TenBitAddress> {
-    pub fn new_ten_bit_addr<I2c: I2cMarker>(
-        sys_clk: Hertz,
+impl<I2c: Instance> I2cSlave<I2c, TenBitAddress> {
+    pub fn new_ten_bit_addr(
+        sys_cfg: &mut pac::Sysconfig,
+        sys_clk: impl Into<Hertz>,
         i2c: I2c,
         cfg: SlaveConfig,
         speed_mode: I2cSpeed,
     ) -> Result<Self, ClockTooSlowForFastI2cError> {
-        Self::new_generic(sys_clk, i2c, cfg, speed_mode)
+        Self::new_generic(sys_cfg, sys_clk, i2c, cfg, speed_mode)
     }
 }

va108xx-hal/src/lib.rs

@@ -8,23 +8,69 @@ pub use va108xx as pac;
 pub mod clock;
 pub mod gpio;
 pub mod i2c;
-pub mod pins;
 pub mod prelude;
 pub mod pwm;
 pub mod spi;
 pub mod sysconfig;
 pub mod time;
 pub mod timer;
+pub mod typelevel;
 pub mod uart;
 
-pub use vorago_shared_periphs::FunSel;
+#[derive(Debug, Eq, Copy, Clone, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum FunSel {
+    Sel0 = 0b00,
+    Sel1 = 0b01,
+    Sel2 = 0b10,
+    Sel3 = 0b11,
+}
 
-/// This is the NONE destination reigster value for the IRQSEL peripheral.
-pub const IRQ_DST_NONE: u32 = 0xffffffff;
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum PeripheralSelect {
+    PortA = 0,
+    PortB = 1,
+    Spi0 = 4,
+    Spi1 = 5,
+    Spi2 = 6,
+    Uart0 = 8,
+    Uart1 = 9,
+    I2c0 = 16,
+    I2c1 = 17,
+    Irqsel = 21,
+    Ioconfig = 22,
+    Utility = 23,
+    Gpio = 24,
+}
 
-pub use vorago_shared_periphs::{
-    disable_nvic_interrupt, enable_nvic_interrupt, InterruptConfig, PeripheralSelect,
-};
+/// Generic interrupt config which can be used to specify whether the HAL driver will
+/// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the
+/// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might want to
+/// perform those steps themselves.
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct InterruptConfig {
+    /// Interrupt target vector. Should always be set, might be required for disabling IRQs
+    pub id: pac::Interrupt,
+    /// Specfiy whether IRQ should be routed to an IRQ vector using the IRQSEL peripheral.
+    pub route: bool,
+    /// Specify whether the IRQ is unmasked in the Cortex-M NVIC. If an interrupt is used for
+    /// multiple purposes, the user can enable the interrupts themselves.
+    pub enable_in_nvic: bool,
+}
+
+impl InterruptConfig {
+    pub fn new(id: pac::Interrupt, route: bool, enable_in_nvic: bool) -> Self {
+        InterruptConfig {
+            id,
+            route,
+            enable_in_nvic,
+        }
+    }
+}
+
+pub type IrqCfg = InterruptConfig;
 
 #[derive(Debug, PartialEq, Eq, thiserror::Error)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -55,7 +101,20 @@ pub fn port_function_select(
     Ok(())
 }
 
-#[allow(dead_code)]
-pub(crate) mod sealed {
-    pub trait Sealed {}
+/// Enable a specific interrupt using the NVIC peripheral.
+///
+/// # Safety
+///
+/// This function is `unsafe` because it can break mask-based critical sections.
+#[inline]
+pub unsafe fn enable_nvic_interrupt(irq: pac::Interrupt) {
+    unsafe {
+        cortex_m::peripheral::NVIC::unmask(irq);
+    }
+}
+
+/// Disable a specific interrupt using the NVIC peripheral.
+#[inline]
+pub fn disable_nvic_interrupt(irq: pac::Interrupt) {
+    cortex_m::peripheral::NVIC::mask(irq);
 }

va108xx-hal/src/pins.rs

@@ -1,6 +0,0 @@
-//! Pin resource management singletons.
-//!
-//! This module contains the pin singletons. It allows creating those singletons
-//! to access the [Pin] structures of individual ports in a safe way with checked ownership
-//! rules.
-pub use vorago_shared_periphs::pins::*;

va108xx-hal/src/pwm.rs

@@ -8,44 +8,16 @@
 use core::convert::Infallible;
 use core::marker::PhantomData;
 
-use vorago_shared_periphs::gpio::IoPeriphPin;
-use vorago_shared_periphs::PeripheralSelect;
-
-use crate::clock::enable_peripheral_clock;
+use crate::pac;
 use crate::time::Hertz;
-use crate::timer::{TimId, TimMarker, TimPin, TimRegInterface};
+use crate::timer::{TimDynRegister, TimPin, TimRegInterface, ValidTim, ValidTimAndPin};
+use crate::{clock::enable_peripheral_clock, gpio::DynPinId};
 
 const DUTY_MAX: u16 = u16::MAX;
 
 #[derive(Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
-enum StatusSelPwm {
-    PwmA = 3,
-    PwmB = 4,
-}
-
-#[derive(Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct PwmA {}
-#[derive(Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct PwmB {}
-
-#[derive(Debug, thiserror::Error)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[error("pin tim ID {pin_tim:?} and timer tim id {tim_id:?} do not match")]
-pub struct TimMissmatchError {
-    pin_tim: TimId,
-    tim_id: TimId,
-}
-
-//==================================================================================================
-// PWM pin
-//==================================================================================================
-
-/// Reduced version where type information is deleted
-pub struct PwmPin<Mode = PwmA> {
-    tim_id: TimId,
+pub(crate) struct PwmCommon {
     sys_clk: Hertz,
     /// For PWMB, this is the upper limit
     current_duty: u16,
@@ -53,46 +25,201 @@ pub struct PwmPin<Mode = PwmA> {
     current_lower_limit: u16,
     current_period: Hertz,
     current_rst_val: u32,
+}
+
+enum StatusSelPwm {
+    PwmA = 3,
+    PwmB = 4,
+}
+
+pub struct PwmA {}
+pub struct PwmB {}
+
+//==================================================================================================
+// Strongly typed PWM pin
+//==================================================================================================
+
+pub struct PwmPin<Pin: TimPin, Tim: ValidTim, Mode = PwmA> {
+    pin_and_tim: (Pin, Tim),
+    inner: ReducedPwmPin<Mode>,
     mode: PhantomData<Mode>,
 }
 
-impl<Mode> PwmPin<Mode> {
-    /// Create a new strongly typed PWM pin
-    pub fn new<Pin: TimPin, Tim: TimMarker + TimRegInterface>(
-        sys_clk: Hertz,
+impl<Pin: TimPin, Tim: ValidTim, Mode> PwmPin<Pin, Tim, Mode>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    /// Create a new stronlgy typed PWM pin
+    pub fn new(
+        sys_cfg: &mut pac::Sysconfig,
+        sys_clk: impl Into<Hertz> + Copy,
         pin_and_tim: (Pin, Tim),
-        initial_frequency: Hertz,
-    ) -> Result<Self, TimMissmatchError> {
-        if Pin::TIM_ID != Tim::ID {
-            return Err(TimMissmatchError {
-                pin_tim: Pin::TIM_ID,
-                tim_id: Tim::ID,
-            });
-        }
-        IoPeriphPin::new(Pin::PIN_ID, Pin::FUN_SEL, None);
+        initial_period: impl Into<Hertz> + Copy,
+    ) -> Self {
         let mut pin = PwmPin {
-            tim_id: Tim::ID,
-            current_duty: 0,
-            current_lower_limit: 0,
-            current_period: initial_frequency,
-            current_rst_val: 0,
-            sys_clk,
+            pin_and_tim,
+            inner: ReducedPwmPin::<Mode>::new(
+                Tim::TIM_ID,
+                Pin::DYN,
+                PwmCommon {
+                    current_duty: 0,
+                    current_lower_limit: 0,
+                    current_period: initial_period.into(),
+                    current_rst_val: 0,
+                    sys_clk: sys_clk.into(),
+                },
+            ),
+            //unsafe { TimAndPin::new(tim_and_pin.0, tim_and_pin.1) },
             mode: PhantomData,
         };
-        enable_peripheral_clock(PeripheralSelect::Gpio);
-        enable_peripheral_clock(PeripheralSelect::Ioconfig);
-        let syscfg = unsafe { va108xx::Sysconfig::steal() };
-        syscfg
+        enable_peripheral_clock(sys_cfg, crate::clock::PeripheralClocks::Gpio);
+        enable_peripheral_clock(sys_cfg, crate::clock::PeripheralClocks::Ioconfig);
+        sys_cfg
             .tim_clk_enable()
-            .modify(|r, w| unsafe { w.bits(r.bits() | pin_and_tim.1.mask_32()) });
+            .modify(|r, w| unsafe { w.bits(r.bits() | pin.pin_and_tim.1.mask_32()) });
         pin.enable_pwm_a();
-        pin.set_period(initial_frequency);
-        Ok(pin)
+        pin.set_period(initial_period);
+        pin
+    }
+
+    pub fn downgrade(self) -> ReducedPwmPin<Mode> {
+        self.inner
+    }
+
+    pub fn release(self) -> (Pin, Tim) {
+        self.pin_and_tim
     }
 
     #[inline]
     fn enable_pwm_a(&mut self) {
-        self.tim_id
+        self.inner.enable_pwm_a();
+    }
+
+    #[inline]
+    fn enable_pwm_b(&mut self) {
+        self.inner.enable_pwm_b();
+    }
+
+    #[inline]
+    pub fn get_period(&self) -> Hertz {
+        self.inner.get_period()
+    }
+
+    #[inline]
+    pub fn set_period(&mut self, period: impl Into<Hertz>) {
+        self.inner.set_period(period);
+    }
+
+    #[inline]
+    pub fn disable(&mut self) {
+        self.inner.disable();
+    }
+
+    #[inline]
+    pub fn enable(&mut self) {
+        self.inner.enable();
+    }
+
+    #[inline]
+    pub fn period(&self) -> Hertz {
+        self.inner.period()
+    }
+
+    #[inline(always)]
+    pub fn duty(&self) -> u16 {
+        self.inner.duty()
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim, PwmA>> for PwmPin<Pin, Tim, PwmB>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    fn from(other: PwmPin<Pin, Tim, PwmA>) -> Self {
+        let mut pwmb = Self {
+            mode: PhantomData,
+            pin_and_tim: other.pin_and_tim,
+            inner: other.inner.into(),
+        };
+        pwmb.enable_pwm_b();
+        pwmb
+    }
+}
+
+impl<PIN: TimPin, TIM: ValidTim> From<PwmPin<PIN, TIM, PwmB>> for PwmPin<PIN, TIM, PwmA>
+where
+    (PIN, TIM): ValidTimAndPin<PIN, TIM>,
+{
+    fn from(other: PwmPin<PIN, TIM, PwmB>) -> Self {
+        let mut pwma = Self {
+            mode: PhantomData,
+            pin_and_tim: other.pin_and_tim,
+            inner: other.inner.into(),
+        };
+        pwma.enable_pwm_a();
+        pwma
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> PwmPin<Pin, Tim, PwmA>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    pub fn pwma(
+        sys_cfg: &mut pac::Sysconfig,
+        sys_clk: impl Into<Hertz> + Copy,
+        pin_and_tim: (Pin, Tim),
+        initial_period: impl Into<Hertz> + Copy,
+    ) -> Self {
+        let mut pin: PwmPin<Pin, Tim, PwmA> =
+            Self::new(sys_cfg, sys_clk, pin_and_tim, initial_period);
+        pin.enable_pwm_a();
+        pin
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> PwmPin<Pin, Tim, PwmB>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    pub fn pwmb(
+        sys_cfg: &mut pac::Sysconfig,
+        sys_clk: impl Into<Hertz> + Copy,
+        pin_and_tim: (Pin, Tim),
+        initial_period: impl Into<Hertz> + Copy,
+    ) -> Self {
+        let mut pin: PwmPin<Pin, Tim, PwmB> =
+            Self::new(sys_cfg, sys_clk, pin_and_tim, initial_period);
+        pin.enable_pwm_b();
+        pin
+    }
+}
+
+//==================================================================================================
+// Reduced PWM pin
+//==================================================================================================
+
+/// Reduced version where type information is deleted
+pub struct ReducedPwmPin<Mode = PwmA> {
+    dyn_reg: TimDynRegister,
+    common: PwmCommon,
+    mode: PhantomData<Mode>,
+}
+
+impl<Mode> ReducedPwmPin<Mode> {
+    pub(crate) fn new(tim_id: u8, pin_id: DynPinId, common: PwmCommon) -> Self {
+        Self {
+            dyn_reg: TimDynRegister { tim_id, pin_id },
+            common,
+            mode: PhantomData,
+        }
+    }
+}
+
+impl<Mode> ReducedPwmPin<Mode> {
+    #[inline]
+    fn enable_pwm_a(&mut self) {
+        self.dyn_reg
             .reg_block()
             .ctrl()
             .modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmA as u8) });
@@ -100,7 +227,7 @@ impl<Mode> PwmPin<Mode> {
 
     #[inline]
     fn enable_pwm_b(&mut self) {
-        self.tim_id
+        self.dyn_reg
             .reg_block()
             .ctrl()
             .modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmB as u8) });
@@ -108,26 +235,26 @@ impl<Mode> PwmPin<Mode> {
 
     #[inline]
     pub fn get_period(&self) -> Hertz {
-        self.current_period
+        self.common.current_period
     }
 
     #[inline]
     pub fn set_period(&mut self, period: impl Into<Hertz>) {
-        self.current_period = period.into();
+        self.common.current_period = period.into();
         // Avoid division by 0
-        if self.current_period.raw() == 0 {
+        if self.common.current_period.raw() == 0 {
             return;
         }
-        self.current_rst_val = self.sys_clk.raw() / self.current_period.raw();
-        self.tim_id
+        self.common.current_rst_val = self.common.sys_clk.raw() / self.common.current_period.raw();
+        self.dyn_reg
             .reg_block()
             .rst_value()
-            .write(|w| unsafe { w.bits(self.current_rst_val) });
+            .write(|w| unsafe { w.bits(self.common.current_rst_val) });
     }
 
     #[inline]
     pub fn disable(&mut self) {
-        self.tim_id
+        self.dyn_reg
             .reg_block()
             .ctrl()
             .modify(|_, w| w.enable().clear_bit());
@@ -135,7 +262,7 @@ impl<Mode> PwmPin<Mode> {
 
     #[inline]
     pub fn enable(&mut self) {
-        self.tim_id
+        self.dyn_reg
             .reg_block()
             .ctrl()
             .modify(|_, w| w.enable().set_bit());
@@ -143,41 +270,51 @@ impl<Mode> PwmPin<Mode> {
 
     #[inline]
     pub fn period(&self) -> Hertz {
-        self.current_period
+        self.common.current_period
     }
 
     #[inline(always)]
     pub fn duty(&self) -> u16 {
-        self.current_duty
+        self.common.current_duty
     }
 }
 
-impl From<PwmPin<PwmA>> for PwmPin<PwmB> {
-    fn from(other: PwmPin<PwmA>) -> Self {
+impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim, PwmA>> for ReducedPwmPin<PwmA>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    fn from(value: PwmPin<Pin, Tim, PwmA>) -> Self {
+        value.downgrade()
+    }
+}
+
+impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim, PwmB>> for ReducedPwmPin<PwmB>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    fn from(value: PwmPin<Pin, Tim, PwmB>) -> Self {
+        value.downgrade()
+    }
+}
+
+impl From<ReducedPwmPin<PwmA>> for ReducedPwmPin<PwmB> {
+    fn from(other: ReducedPwmPin<PwmA>) -> Self {
         let mut pwmb = Self {
+            dyn_reg: other.dyn_reg,
+            common: other.common,
             mode: PhantomData,
-            tim_id: other.tim_id,
-            sys_clk: other.sys_clk,
-            current_duty: other.current_duty,
-            current_lower_limit: other.current_lower_limit,
-            current_period: other.current_period,
-            current_rst_val: other.current_rst_val,
         };
         pwmb.enable_pwm_b();
         pwmb
     }
 }
 
-impl From<PwmPin<PwmB>> for PwmPin<PwmA> {
-    fn from(other: PwmPin<PwmB>) -> Self {
+impl From<ReducedPwmPin<PwmB>> for ReducedPwmPin<PwmA> {
+    fn from(other: ReducedPwmPin<PwmB>) -> Self {
         let mut pwmb = Self {
+            dyn_reg: other.dyn_reg,
+            common: other.common,
             mode: PhantomData,
-            tim_id: other.tim_id,
-            sys_clk: other.sys_clk,
-            current_duty: other.current_duty,
-            current_lower_limit: other.current_lower_limit,
-            current_period: other.current_period,
-            current_rst_val: other.current_rst_val,
         };
         pwmb.enable_pwm_a();
         pwmb
@@ -188,15 +325,48 @@ impl From<PwmPin<PwmB>> for PwmPin<PwmA> {
 // PWMB implementations
 //==================================================================================================
 
-impl PwmPin<PwmB> {
+impl<Pin: TimPin, Tim: ValidTim> PwmPin<Pin, Tim, PwmB>
+where
+    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
+{
+    pub fn pwmb_lower_limit(&self) -> u16 {
+        self.inner.pwmb_lower_limit()
+    }
+
+    pub fn pwmb_upper_limit(&self) -> u16 {
+        self.inner.pwmb_upper_limit()
+    }
+
+    /// Set the lower limit for PWMB
+    ///
+    /// The PWM signal will be 1 as long as the current RST counter is larger than
+    /// the lower limit. For example, with a lower limit of 0.5 and and an upper limit
+    /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
+    /// state
+    pub fn set_pwmb_lower_limit(&mut self, duty: u16) {
+        self.inner.set_pwmb_lower_limit(duty);
+    }
+
+    /// Set the higher limit for PWMB
+    ///
+    /// The PWM signal will be 1 as long as the current RST counter is smaller than
+    /// the higher limit. For example, with a lower limit of 0.5 and and an upper limit
+    /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
+    /// state
+    pub fn set_pwmb_upper_limit(&mut self, duty: u16) {
+        self.inner.set_pwmb_upper_limit(duty);
+    }
+}
+
+impl ReducedPwmPin<PwmB> {
     #[inline(always)]
     pub fn pwmb_lower_limit(&self) -> u16 {
-        self.current_lower_limit
+        self.common.current_lower_limit
     }
 
     #[inline(always)]
     pub fn pwmb_upper_limit(&self) -> u16 {
-        self.current_duty
+        self.common.current_duty
     }
 
     /// Set the lower limit for PWMB
@@ -207,10 +377,11 @@ impl PwmPin<PwmB> {
     /// state
     #[inline(always)]
     pub fn set_pwmb_lower_limit(&mut self, duty: u16) {
-        self.current_lower_limit = duty;
-        let pwmb_val: u64 =
-            (self.current_rst_val as u64 * self.current_lower_limit as u64) / DUTY_MAX as u64;
-        self.tim_id
+        self.common.current_lower_limit = duty;
+        let pwmb_val: u64 = (self.common.current_rst_val as u64
+            * self.common.current_lower_limit as u64)
+            / DUTY_MAX as u64;
+        self.dyn_reg
             .reg_block()
             .pwmb_value()
             .write(|w| unsafe { w.bits(pwmb_val as u32) });
@@ -223,10 +394,10 @@ impl PwmPin<PwmB> {
     /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high
     /// state
     pub fn set_pwmb_upper_limit(&mut self, duty: u16) {
-        self.current_duty = duty;
-        let pwma_val: u64 =
-            (self.current_rst_val as u64 * self.current_duty as u64) / DUTY_MAX as u64;
-        self.tim_id
+        self.common.current_duty = duty;
+        let pwma_val: u64 = (self.common.current_rst_val as u64 * self.common.current_duty as u64)
+            / DUTY_MAX as u64;
+        self.dyn_reg
             .reg_block()
             .pwma_value()
             .write(|w| unsafe { w.bits(pwma_val as u32) });
@@ -237,11 +408,15 @@ impl PwmPin<PwmB> {
 // Embedded HAL implementation: PWMA only
 //==================================================================================================
 
-impl embedded_hal::pwm::ErrorType for PwmPin {
+impl<Pin: TimPin, Tim: ValidTim> embedded_hal::pwm::ErrorType for PwmPin<Pin, Tim> {
     type Error = Infallible;
 }
 
-impl embedded_hal::pwm::SetDutyCycle for PwmPin {
+impl embedded_hal::pwm::ErrorType for ReducedPwmPin {
+    type Error = Infallible;
+}
+
+impl embedded_hal::pwm::SetDutyCycle for ReducedPwmPin {
     #[inline]
     fn max_duty_cycle(&self) -> u16 {
         DUTY_MAX
@@ -249,11 +424,11 @@ impl embedded_hal::pwm::SetDutyCycle for PwmPin {
 
     #[inline]
     fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
-        self.current_duty = duty;
-        let pwma_val: u64 = (self.current_rst_val as u64
-            * (DUTY_MAX as u64 - self.current_duty as u64))
+        self.common.current_duty = duty;
+        let pwma_val: u64 = (self.common.current_rst_val as u64
+            * (DUTY_MAX as u64 - self.common.current_duty as u64))
             / DUTY_MAX as u64;
-        self.tim_id
+        self.dyn_reg
             .reg_block()
             .pwma_value()
             .write(|w| unsafe { w.bits(pwma_val as u32) });
@@ -261,6 +436,18 @@ impl embedded_hal::pwm::SetDutyCycle for PwmPin {
     }
 }
 
+impl<Pin: TimPin, Tim: ValidTim> embedded_hal::pwm::SetDutyCycle for PwmPin<Pin, Tim> {
+    #[inline]
+    fn max_duty_cycle(&self) -> u16 {
+        DUTY_MAX
+    }
+
+    #[inline]
+    fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
+        self.inner.set_duty_cycle(duty)
+    }
+}
+
 /// Get the corresponding u16 duty cycle from a percent value ranging between 0.0 and 1.0.
 ///
 /// Please note that this might load a lot of floating point code because this processor does not

va108xx-hal/src/spi/pins.rs

@@ -1,424 +0,0 @@
-use vorago_shared_periphs::gpio::{PinId, PinIdProvider};
-use vorago_shared_periphs::FunSel;
-
-use crate::{
-    pins::{
-        Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, Pa16, Pa17, Pa18, Pa19, Pa20, Pa21, Pa22, Pa23, Pa24,
-        Pa25, Pa26, Pa27, Pa28, Pa29, Pa30, Pa31, Pb0, Pb1, Pb10, Pb11, Pb12, Pb13, Pb14, Pb15,
-        Pb16, Pb17, Pb18, Pb19, Pb2, Pb22, Pb23, Pb3, Pb4, Pb5, Pb6, Pb7, Pb8, Pb9, Pin, PinMarker,
-    },
-    sealed::Sealed,
-};
-
-use super::{HwChipSelectId, SpiId};
-
-pub trait PinSck: PinMarker {
-    const SPI_ID: SpiId;
-    const FUN_SEL: FunSel;
-}
-
-pub trait PinMosi: PinMarker {
-    const SPI_ID: SpiId;
-    const FUN_SEL: FunSel;
-}
-
-pub trait PinMiso: PinMarker {
-    const SPI_ID: SpiId;
-    const FUN_SEL: FunSel;
-}
-
-pub trait HwCsProvider {
-    const PIN_ID: PinId;
-    const SPI_ID: SpiId;
-    const FUN_SEL: FunSel;
-    const CS_ID: HwChipSelectId;
-}
-
-macro_rules! hw_cs_pins {
-    ($SpiId:path, $(($Px:ident, $FunSel:path, $HwCsIdent:path),)+) => {
-        $(
-            impl HwCsProvider for Pin<$Px> {
-                const PIN_ID: PinId = $Px::ID;
-                const SPI_ID: SpiId = $SpiId;
-                const FUN_SEL: FunSel = $FunSel;
-                const CS_ID: HwChipSelectId = $HwCsIdent;
-            }
-        )+
-    };
-}
-macro_rules! hw_cs_multi_pin {
-    (
-        // name of the newtype wrapper struct
-        $name:ident,
-        // Pb0
-        $pin_id:ident,
-        // SpiId::B
-        $spi_id:path,
-        // FunSel::Sel1
-        $fun_sel:path,
-        // HwChipSelectId::Id2
-        $cs_id:path
-    ) => {
-        #[doc = concat!(
-                                            "Newtype wrapper to use [Pin] [`", stringify!($pin_ty),
-                                            "`] as a HW CS pin for [`", stringify!($spi_id),
-                                            "`] with [`", stringify!($cs_id), "`]."
-                                        )]
-        pub struct $name(Pin<$pin_id>);
-
-        impl $name {
-            pub fn new(pin: Pin<$pin_id>) -> Self {
-                Self(pin)
-            }
-        }
-
-        impl Sealed for $name {}
-
-        impl HwCsProvider for $name {
-            const PIN_ID: PinId = <$pin_id as PinIdProvider>::ID;
-            const SPI_ID: SpiId = $spi_id;
-            const FUN_SEL: FunSel = $fun_sel;
-            const CS_ID: HwChipSelectId = $cs_id;
-        }
-    };
-}
-
-// SPIA
-
-impl PinSck for Pin<Pa31> {
-    const SPI_ID: SpiId = SpiId::A;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-impl PinMosi for Pin<Pa30> {
-    const SPI_ID: SpiId = SpiId::A;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-impl PinMiso for Pin<Pa29> {
-    const SPI_ID: SpiId = SpiId::A;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-
-pub type SpiAPortASck = Pin<Pa31>;
-pub type SpiAPortAMosi = Pin<Pa30>;
-pub type SpiAPortAMiso = Pin<Pa29>;
-
-impl PinSck for Pin<Pb9> {
-    const SPI_ID: SpiId = SpiId::A;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-impl PinMosi for Pin<Pb8> {
-    const SPI_ID: SpiId = SpiId::A;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-impl PinMiso for Pin<Pb7> {
-    const SPI_ID: SpiId = SpiId::A;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-
-pub type SpiAPortBSck = Pin<Pb9>;
-pub type SpiAPortBMosi = Pin<Pb8>;
-pub type SpiAPortBMiso = Pin<Pb7>;
-
-hw_cs_pins!(
-    SpiId::A,
-    (Pb0, FunSel::Sel2, HwChipSelectId::Id1),
-    (Pb1, FunSel::Sel2, HwChipSelectId::Id2),
-    (Pb2, FunSel::Sel2, HwChipSelectId::Id3),
-    (Pb3, FunSel::Sel2, HwChipSelectId::Id4),
-    (Pb4, FunSel::Sel2, HwChipSelectId::Id5),
-    (Pb5, FunSel::Sel2, HwChipSelectId::Id6),
-    (Pb6, FunSel::Sel2, HwChipSelectId::Id0),
-    (Pa24, FunSel::Sel1, HwChipSelectId::Id4),
-    (Pa25, FunSel::Sel1, HwChipSelectId::Id3),
-    (Pa26, FunSel::Sel1, HwChipSelectId::Id2),
-    (Pa27, FunSel::Sel1, HwChipSelectId::Id1),
-    (Pa28, FunSel::Sel1, HwChipSelectId::Id0),
-);
-
-hw_cs_multi_pin!(
-    PinPb0SpiaHwCsId1,
-    Pb0,
-    SpiId::A,
-    FunSel::Sel2,
-    HwChipSelectId::Id1
-);
-hw_cs_multi_pin!(
-    PinPb1SpiaHwCsId2,
-    Pb1,
-    SpiId::A,
-    FunSel::Sel2,
-    HwChipSelectId::Id2
-);
-hw_cs_multi_pin!(
-    PinPb2SpiaHwCsId3,
-    Pb2,
-    SpiId::A,
-    FunSel::Sel2,
-    HwChipSelectId::Id3
-);
-
-hw_cs_multi_pin!(
-    PinPa21SpiaHwCsId7,
-    Pa21,
-    SpiId::A,
-    FunSel::Sel1,
-    HwChipSelectId::Id7
-);
-hw_cs_multi_pin!(
-    PinPa22SpiaHwCsId6,
-    Pa22,
-    SpiId::A,
-    FunSel::Sel1,
-    HwChipSelectId::Id6
-);
-hw_cs_multi_pin!(
-    PinPa23SpiaHwCsId5,
-    Pa23,
-    SpiId::A,
-    FunSel::Sel1,
-    HwChipSelectId::Id5
-);
-
-// SPIB
-
-impl PinSck for Pin<Pa20> {
-    const SPI_ID: SpiId = SpiId::B;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-impl PinMosi for Pin<Pa19> {
-    const SPI_ID: SpiId = SpiId::B;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-impl PinMiso for Pin<Pa18> {
-    const SPI_ID: SpiId = SpiId::B;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-
-pub type SpiBPortASck = Pin<Pa20>;
-pub type SpiBPortAMosi = Pin<Pa19>;
-pub type SpiBPortAMiso = Pin<Pa18>;
-
-impl PinSck for Pin<Pb19> {
-    const SPI_ID: SpiId = SpiId::B;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-impl PinMosi for Pin<Pb18> {
-    const SPI_ID: SpiId = SpiId::B;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-impl PinMiso for Pin<Pb17> {
-    const SPI_ID: SpiId = SpiId::B;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-
-impl PinSck for Pin<Pb5> {
-    const SPI_ID: SpiId = SpiId::B;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-impl PinMosi for Pin<Pb4> {
-    const SPI_ID: SpiId = SpiId::B;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-impl PinMiso for Pin<Pb3> {
-    const SPI_ID: SpiId = SpiId::B;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-
-// TODO: Need to deal with these duplications..
-hw_cs_pins!(
-    SpiId::B,
-    (Pb16, FunSel::Sel1, HwChipSelectId::Id0),
-    (Pb15, FunSel::Sel1, HwChipSelectId::Id1),
-    (Pb14, FunSel::Sel1, HwChipSelectId::Id2),
-    (Pb13, FunSel::Sel1, HwChipSelectId::Id3),
-    (Pa17, FunSel::Sel2, HwChipSelectId::Id0),
-    (Pa16, FunSel::Sel2, HwChipSelectId::Id1),
-    (Pa15, FunSel::Sel2, HwChipSelectId::Id2),
-    (Pa14, FunSel::Sel2, HwChipSelectId::Id3),
-    (Pa13, FunSel::Sel2, HwChipSelectId::Id4),
-    (Pa12, FunSel::Sel2, HwChipSelectId::Id5),
-    (Pa11, FunSel::Sel2, HwChipSelectId::Id6),
-    (Pa10, FunSel::Sel2, HwChipSelectId::Id7),
-    (Pa23, FunSel::Sel2, HwChipSelectId::Id5),
-    (Pa22, FunSel::Sel2, HwChipSelectId::Id6),
-    (Pa21, FunSel::Sel2, HwChipSelectId::Id7),
-);
-
-hw_cs_multi_pin!(
-    PinPb0SpibHwCsId2,
-    Pb0,
-    SpiId::B,
-    FunSel::Sel1,
-    HwChipSelectId::Id2
-);
-hw_cs_multi_pin!(
-    PinPb1SpibHwCsId1,
-    Pb1,
-    SpiId::B,
-    FunSel::Sel1,
-    HwChipSelectId::Id1
-);
-hw_cs_multi_pin!(
-    PinPb2SpibHwCsId0,
-    Pb2,
-    SpiId::B,
-    FunSel::Sel1,
-    HwChipSelectId::Id0
-);
-
-hw_cs_multi_pin!(
-    PinPb10SpibHwCsId6,
-    Pb10,
-    SpiId::B,
-    FunSel::Sel1,
-    HwChipSelectId::Id6
-);
-hw_cs_multi_pin!(
-    PinPb11SpibHwCsId5,
-    Pb11,
-    SpiId::B,
-    FunSel::Sel1,
-    HwChipSelectId::Id5
-);
-hw_cs_multi_pin!(
-    PinPb12SpibHwCsId4,
-    Pb12,
-    SpiId::B,
-    FunSel::Sel1,
-    HwChipSelectId::Id4
-);
-
-hw_cs_multi_pin!(
-    PinPb10SpibHwCsId2,
-    Pb10,
-    SpiId::B,
-    FunSel::Sel2,
-    HwChipSelectId::Id2
-);
-hw_cs_multi_pin!(
-    PinPb11SpibHwCsId1,
-    Pb11,
-    SpiId::B,
-    FunSel::Sel2,
-    HwChipSelectId::Id1
-);
-hw_cs_multi_pin!(
-    PinPb12SpibHwCsId0,
-    Pb12,
-    SpiId::B,
-    FunSel::Sel2,
-    HwChipSelectId::Id0
-);
-
-hw_cs_multi_pin!(
-    PinPa21SpibHwCsId7,
-    Pa21,
-    SpiId::B,
-    FunSel::Sel2,
-    HwChipSelectId::Id7
-);
-hw_cs_multi_pin!(
-    PinPa22SpibHwCsId6,
-    Pa22,
-    SpiId::B,
-    FunSel::Sel2,
-    HwChipSelectId::Id6
-);
-hw_cs_multi_pin!(
-    PinPa23SpibHwCsId5,
-    Pa23,
-    SpiId::B,
-    FunSel::Sel2,
-    HwChipSelectId::Id5
-);
-
-// SPIC
-
-/*
-//  Dummy pin defintion for the ROM SCK.
-pub struct RomSck;
-//  Dummy pin defintion for the ROM MOSI.
-pub struct RomMosi;
-//  Dummy pin defintion for the ROM MISO.
-pub struct RomMiso;
-//  Dummy pin defintion for the ROM chip select.
-pub struct RomCs;
-
-impl Sealed for RomSck {}
-impl PinSck for RomSck {
-    const SPI_ID: SpiId = SpiId::C;
-    /// Function select does not make sense here, just select default value.
-    const FUN_SEL: FunSel = FunSel::Sel0;
-}
-impl Sealed for RomMosi {}
-impl PinMosi for RomMosi {
-    const SPI_ID: SpiId = SpiId::C;
-    /// Function select does not make sense here, just select default value.
-    const FUN_SEL: FunSel = FunSel::Sel0;
-}
-impl Sealed for RomMiso {}
-impl PinMiso for RomMiso {
-    const SPI_ID: SpiId = SpiId::C;
-    /// Function select does not make sense here, just select default value.
-    const FUN_SEL: FunSel = FunSel::Sel0;
-}
-impl Sealed for RomCs {}
-*/
-
-hw_cs_pins!(
-    SpiId::C,
-    (Pb9, FunSel::Sel3, HwChipSelectId::Id1),
-    (Pb8, FunSel::Sel3, HwChipSelectId::Id2),
-    (Pb7, FunSel::Sel3, HwChipSelectId::Id3),
-    (Pb23, FunSel::Sel3, HwChipSelectId::Id2),
-    (Pb22, FunSel::Sel3, HwChipSelectId::Id1),
-    (Pa20, FunSel::Sel1, HwChipSelectId::Id1),
-    (Pa19, FunSel::Sel1, HwChipSelectId::Id2),
-    (Pb18, FunSel::Sel1, HwChipSelectId::Id3),
-);
-
-hw_cs_multi_pin!(
-    PinPa21SpicHwCsId3,
-    Pa21,
-    SpiId::C,
-    FunSel::Sel3,
-    HwChipSelectId::Id3
-);
-hw_cs_multi_pin!(
-    PinPa22SpicHwCsId2,
-    Pa22,
-    SpiId::C,
-    FunSel::Sel3,
-    HwChipSelectId::Id2
-);
-hw_cs_multi_pin!(
-    PinPa23SpicHwCsId1,
-    Pa23,
-    SpiId::C,
-    FunSel::Sel3,
-    HwChipSelectId::Id1
-);
-
-hw_cs_multi_pin!(
-    PinPa20SpicHwCsId1,
-    Pa20,
-    SpiId::C,
-    FunSel::Sel1,
-    HwChipSelectId::Id1
-);
-hw_cs_multi_pin!(
-    PinPa20SpicHwCsId4,
-    Pa20,
-    SpiId::C,
-    FunSel::Sel3,
-    HwChipSelectId::Id4
-);
-
-/*
-impl HwCsProvider for RomCs {
-    const CS_ID: HwChipSelectId = HwChipSelectId::Id0;
-    const SPI_ID: SpiId = SpiId::C;
-    /// Function select does not make sense here, just select default value.
-    const FUN_SEL: FunSel = FunSel::Sel0;
-}
-*/

va108xx-hal/src/sysconfig.rs

@@ -1,3 +1,5 @@
+use crate::{pac, PeripheralSelect};
+
 #[derive(PartialEq, Eq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct InvalidCounterResetVal(pub(crate) ());
@@ -6,8 +8,10 @@ pub struct InvalidCounterResetVal(pub(crate) ());
 ///
 /// Returns [InvalidCounterResetVal] if the scrub rate is 0
 /// (equivalent to disabling) or larger than 24 bits
-pub fn enable_rom_scrubbing(scrub_rate: u32) -> Result<(), InvalidCounterResetVal> {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
+pub fn enable_rom_scrubbing(
+    syscfg: &mut pac::Sysconfig,
+    scrub_rate: u32,
+) -> Result<(), InvalidCounterResetVal> {
     if scrub_rate == 0 || scrub_rate > u32::pow(2, 24) {
         return Err(InvalidCounterResetVal(()));
     }
@@ -15,8 +19,7 @@ pub fn enable_rom_scrubbing(scrub_rate: u32) -> Result<(), InvalidCounterResetVa
     Ok(())
 }
 
-pub fn disable_rom_scrubbing() {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
+pub fn disable_rom_scrubbing(syscfg: &mut pac::Sysconfig) {
     syscfg.rom_scrub().write(|w| unsafe { w.bits(0) });
 }
 
@@ -24,8 +27,10 @@ pub fn disable_rom_scrubbing() {
 ///
 /// Returns [InvalidCounterResetVal] if the scrub rate is 0
 /// (equivalent to disabling) or larger than 24 bits
-pub fn enable_ram_scrubbing(scrub_rate: u32) -> Result<(), InvalidCounterResetVal> {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
+pub fn enable_ram_scrubbing(
+    syscfg: &mut pac::Sysconfig,
+    scrub_rate: u32,
+) -> Result<(), InvalidCounterResetVal> {
     if scrub_rate == 0 || scrub_rate > u32::pow(2, 24) {
         return Err(InvalidCounterResetVal(()));
     }
@@ -33,11 +38,20 @@ pub fn enable_ram_scrubbing(scrub_rate: u32) -> Result<(), InvalidCounterResetVa
     Ok(())
 }
 
-pub fn disable_ram_scrubbing() {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
+pub fn disable_ram_scrubbing(syscfg: &mut pac::Sysconfig) {
     syscfg.ram_scrub().write(|w| unsafe { w.bits(0) });
 }
 
-pub use vorago_shared_periphs::sysconfig::{
-    assert_peripheral_reset, disable_peripheral_clock, enable_peripheral_clock,
-};
+/// Clear the reset bit. This register is active low, so doing this will hold the peripheral
+/// in a reset state
+pub fn clear_reset_bit(syscfg: &mut pac::Sysconfig, periph_sel: PeripheralSelect) {
+    syscfg
+        .peripheral_reset()
+        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << periph_sel as u8)) });
+}
+
+pub fn set_reset_bit(syscfg: &mut pac::Sysconfig, periph_sel: PeripheralSelect) {
+    syscfg
+        .peripheral_reset()
+        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
+}

va108xx-hal/src/time.rs

@@ -1,2 +1,26 @@
 //! Time units
-pub use vorago_shared_periphs::time::*;
+
+// Frequency based
+
+/// Hertz
+pub type Hertz = fugit::HertzU32;
+
+/// KiloHertz
+pub type KiloHertz = fugit::KilohertzU32;
+
+/// MegaHertz
+pub type MegaHertz = fugit::MegahertzU32;
+
+// Period based
+
+/// Seconds
+pub type Seconds = fugit::SecsDurationU32;
+
+/// Milliseconds
+pub type Milliseconds = fugit::MillisDurationU32;
+
+/// Microseconds
+pub type Microseconds = fugit::MicrosDurationU32;
+
+/// Nanoseconds
+pub type Nanoseconds = fugit::NanosDurationU32;

va108xx-hal/src/timer.rs

@@ -6,24 +6,25 @@
 //! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/cascade.rs)
 pub use crate::InterruptConfig;
 use crate::{
+    clock::{enable_peripheral_clock, PeripheralClocks},
     enable_nvic_interrupt,
-    pac::{self, tim0},
-    pins::{
-        Pa0, Pa1, Pa10, Pa11, Pa12, Pa13, Pa14, Pa15, Pa2, Pa24, Pa25, Pa26, Pa27, Pa28, Pa29, Pa3,
-        Pa30, Pa31, Pa4, Pa5, Pa6, Pa7, Pa8, Pa9, Pb0, Pb1, Pb10, Pb11, Pb12, Pb13, Pb14, Pb15,
-        Pb16, Pb17, Pb18, Pb19, Pb2, Pb20, Pb21, Pb22, Pb23, Pb3, Pb4, Pb5, Pb6,
+    gpio::{
+        AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14,
+        PA15, PA2, PA24, PA25, PA26, PA27, PA28, PA29, PA3, PA30, PA31, PA4, PA5, PA6, PA7, PA8,
+        PA9, PB0, PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB16, PB17, PB18, PB19, PB2, PB20, PB21,
+        PB22, PB23, PB3, PB4, PB5, PB6,
     },
-    sealed::Sealed,
+    pac::{self, tim0},
     time::Hertz,
+    timer,
+    typelevel::Sealed,
 };
+use core::cell::Cell;
+use critical_section::Mutex;
 use fugit::RateExtU32;
-use vorago_shared_periphs::{
-    gpio::{Pin, PinId, PinIdProvider},
-    ioconfig::regs::FunSel,
-    pins::PinMarker,
-    sysconfig::enable_peripheral_clock,
-    PeripheralSelect,
-};
+
+const IRQ_DST_NONE: u32 = 0xffffffff;
+pub static MS_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
 
 /// Get the peripheral block of a TIM peripheral given the index.
 ///
@@ -161,30 +162,20 @@ impl CascadeSource {
 // Valid TIM and PIN combinations
 //==================================================================================================
 
-pub trait TimPin: PinMarker {
-    const PIN_ID: PinId;
-    const FUN_SEL: FunSel;
-    const TIM_ID: TimId;
+pub trait TimPin {
+    const DYN: DynPinId;
 }
 
-pub trait TimMarker: Sealed {
+pub trait ValidTim {
     // TIM ID ranging from 0 to 23 for 24 TIM peripherals
-    const ID: TimId;
+    const TIM_ID: u8;
 }
 
 macro_rules! tim_marker {
     ($TIMX:path, $ID:expr) => {
-        impl TimMarker for $TIMX {
-            const ID: TimId = TimId($ID);
+        impl ValidTim for $TIMX {
+            const TIM_ID: u8 = $ID;
         }
-
-        unsafe impl TimRegInterface for $TIMX {
-            fn raw_id(&self) -> u8 {
-                Self::ID.0
-            }
-        }
-
-        impl Sealed for $TIMX {}
     };
 }
 
@@ -213,69 +204,76 @@ tim_marker!(pac::Tim21, 21);
 tim_marker!(pac::Tim22, 22);
 tim_marker!(pac::Tim23, 23);
 
-pub trait ValidTimAndPin<Pin: TimPin, Tim: TimMarker>: Sealed {}
+pub trait ValidTimAndPin<PIN: TimPin, TIM: ValidTim>: Sealed {}
 
 macro_rules! pin_and_tim {
-    ($Px:ident, $FunSel:path, $ID:expr) => {
-        impl TimPin for Pin<$Px>
+    ($PAX:ident, $ALTFUNC:ident, $ID:expr, $TIMX:path) => {
+        impl TimPin for Pin<$PAX, $ALTFUNC>
         where
-            $Px: PinIdProvider,
+            $PAX: PinId,
         {
-            const PIN_ID: PinId = $Px::ID;
-            const FUN_SEL: FunSel = $FunSel;
-            const TIM_ID: TimId = TimId($ID);
+            const DYN: DynPinId = $PAX::DYN;
         }
+
+        impl<PIN: TimPin, TIM: ValidTim> ValidTimAndPin<PIN, TIM> for (Pin<$PAX, $ALTFUNC>, $TIMX)
+        where
+            Pin<$PAX, $ALTFUNC>: TimPin,
+            $PAX: PinId,
+        {
+        }
+
+        impl Sealed for (Pin<$PAX, $ALTFUNC>, $TIMX) {}
     };
 }
 
-pin_and_tim!(Pa0, FunSel::Sel1, 0);
-pin_and_tim!(Pa1, FunSel::Sel1, 1);
-pin_and_tim!(Pa2, FunSel::Sel1, 2);
-pin_and_tim!(Pa3, FunSel::Sel1, 3);
-pin_and_tim!(Pa4, FunSel::Sel1, 4);
-pin_and_tim!(Pa5, FunSel::Sel1, 5);
-pin_and_tim!(Pa6, FunSel::Sel1, 6);
-pin_and_tim!(Pa7, FunSel::Sel1, 7);
-pin_and_tim!(Pa8, FunSel::Sel1, 8);
-pin_and_tim!(Pa9, FunSel::Sel1, 9);
-pin_and_tim!(Pa10, FunSel::Sel1, 10);
-pin_and_tim!(Pa11, FunSel::Sel1, 11);
-pin_and_tim!(Pa12, FunSel::Sel1, 12);
-pin_and_tim!(Pa13, FunSel::Sel1, 13);
-pin_and_tim!(Pa14, FunSel::Sel1, 14);
-pin_and_tim!(Pa15, FunSel::Sel1, 15);
+pin_and_tim!(PA31, AltFunc2, 23, pac::Tim23);
+pin_and_tim!(PA30, AltFunc2, 22, pac::Tim22);
+pin_and_tim!(PA29, AltFunc2, 21, pac::Tim21);
+pin_and_tim!(PA28, AltFunc2, 20, pac::Tim20);
+pin_and_tim!(PA27, AltFunc2, 19, pac::Tim19);
+pin_and_tim!(PA26, AltFunc2, 18, pac::Tim18);
+pin_and_tim!(PA25, AltFunc2, 17, pac::Tim17);
+pin_and_tim!(PA24, AltFunc2, 16, pac::Tim16);
 
-pin_and_tim!(Pa24, FunSel::Sel2, 16);
-pin_and_tim!(Pa25, FunSel::Sel2, 17);
-pin_and_tim!(Pa26, FunSel::Sel2, 18);
-pin_and_tim!(Pa27, FunSel::Sel2, 19);
-pin_and_tim!(Pa28, FunSel::Sel2, 20);
-pin_and_tim!(Pa29, FunSel::Sel2, 21);
-pin_and_tim!(Pa30, FunSel::Sel2, 22);
-pin_and_tim!(Pa31, FunSel::Sel2, 23);
+pin_and_tim!(PA15, AltFunc1, 15, pac::Tim15);
+pin_and_tim!(PA14, AltFunc1, 14, pac::Tim14);
+pin_and_tim!(PA13, AltFunc1, 13, pac::Tim13);
+pin_and_tim!(PA12, AltFunc1, 12, pac::Tim12);
+pin_and_tim!(PA11, AltFunc1, 11, pac::Tim11);
+pin_and_tim!(PA10, AltFunc1, 10, pac::Tim10);
+pin_and_tim!(PA9, AltFunc1, 9, pac::Tim9);
+pin_and_tim!(PA8, AltFunc1, 8, pac::Tim8);
+pin_and_tim!(PA7, AltFunc1, 7, pac::Tim7);
+pin_and_tim!(PA6, AltFunc1, 6, pac::Tim6);
+pin_and_tim!(PA5, AltFunc1, 5, pac::Tim5);
+pin_and_tim!(PA4, AltFunc1, 4, pac::Tim4);
+pin_and_tim!(PA3, AltFunc1, 3, pac::Tim3);
+pin_and_tim!(PA2, AltFunc1, 2, pac::Tim2);
+pin_and_tim!(PA1, AltFunc1, 1, pac::Tim1);
+pin_and_tim!(PA0, AltFunc1, 0, pac::Tim0);
 
-pin_and_tim!(Pb0, FunSel::Sel3, 0);
-pin_and_tim!(Pb1, FunSel::Sel3, 1);
-pin_and_tim!(Pb2, FunSel::Sel3, 2);
-pin_and_tim!(Pb3, FunSel::Sel3, 3);
-pin_and_tim!(Pb4, FunSel::Sel3, 4);
-pin_and_tim!(Pb5, FunSel::Sel3, 5);
-pin_and_tim!(Pb6, FunSel::Sel3, 6);
+pin_and_tim!(PB23, AltFunc3, 23, pac::Tim23);
+pin_and_tim!(PB22, AltFunc3, 22, pac::Tim22);
+pin_and_tim!(PB21, AltFunc3, 21, pac::Tim21);
+pin_and_tim!(PB20, AltFunc3, 20, pac::Tim20);
+pin_and_tim!(PB19, AltFunc3, 19, pac::Tim19);
+pin_and_tim!(PB18, AltFunc3, 18, pac::Tim18);
+pin_and_tim!(PB17, AltFunc3, 17, pac::Tim17);
+pin_and_tim!(PB16, AltFunc3, 16, pac::Tim16);
+pin_and_tim!(PB15, AltFunc3, 15, pac::Tim15);
+pin_and_tim!(PB14, AltFunc3, 14, pac::Tim14);
+pin_and_tim!(PB13, AltFunc3, 13, pac::Tim13);
+pin_and_tim!(PB12, AltFunc3, 12, pac::Tim12);
+pin_and_tim!(PB11, AltFunc3, 11, pac::Tim11);
+pin_and_tim!(PB10, AltFunc3, 10, pac::Tim10);
 
-pin_and_tim!(Pb10, FunSel::Sel3, 10);
-pin_and_tim!(Pb11, FunSel::Sel3, 11);
-pin_and_tim!(Pb12, FunSel::Sel3, 12);
-pin_and_tim!(Pb13, FunSel::Sel3, 13);
-pin_and_tim!(Pb14, FunSel::Sel3, 14);
-pin_and_tim!(Pb15, FunSel::Sel3, 15);
-pin_and_tim!(Pb16, FunSel::Sel3, 16);
-pin_and_tim!(Pb17, FunSel::Sel3, 17);
-pin_and_tim!(Pb18, FunSel::Sel3, 18);
-pin_and_tim!(Pb19, FunSel::Sel3, 19);
-pin_and_tim!(Pb20, FunSel::Sel3, 20);
-pin_and_tim!(Pb21, FunSel::Sel3, 21);
-pin_and_tim!(Pb22, FunSel::Sel3, 22);
-pin_and_tim!(Pb23, FunSel::Sel3, 23);
+pin_and_tim!(PB6, AltFunc3, 6, pac::Tim6);
+pin_and_tim!(PB5, AltFunc3, 5, pac::Tim5);
+pin_and_tim!(PB4, AltFunc3, 4, pac::Tim4);
+pin_and_tim!(PB3, AltFunc3, 3, pac::Tim3);
+pin_and_tim!(PB2, AltFunc3, 2, pac::Tim2);
+pin_and_tim!(PB1, AltFunc3, 1, pac::Tim1);
+pin_and_tim!(PB0, AltFunc3, 0, pac::Tim0);
 
 //==================================================================================================
 // Register Interface for TIM registers and TIM pins
@@ -290,12 +288,12 @@ pub type TimRegBlock = tim0::RegisterBlock;
 ///
 /// # Safety
 ///
-/// Users should only implement the [Self::raw_id] function. No default function
+/// Users should only implement the [Self::tim_id] function. No default function
 /// implementations should be overridden. The implementing type must also have
 /// "control" over the corresponding pin ID, i.e. it must guarantee that a each
 /// pin ID is a singleton.
 pub unsafe trait TimRegInterface {
-    fn raw_id(&self) -> u8;
+    fn tim_id(&self) -> u8;
 
     const PORT_BASE: *const tim0::RegisterBlock = pac::Tim0::ptr() as *const _;
 
@@ -303,12 +301,12 @@ pub unsafe trait TimRegInterface {
     /// memory mapped peripheral depending on the TIM ID.
     #[inline(always)]
     fn reg_block(&self) -> &TimRegBlock {
-        unsafe { &*Self::PORT_BASE.offset(self.raw_id() as isize) }
+        unsafe { &*Self::PORT_BASE.offset(self.tim_id() as isize) }
     }
 
     #[inline(always)]
     fn mask_32(&self) -> u32 {
-        1 << self.raw_id()
+        1 << self.tim_id()
     }
 
     /// Clear the reset bit of the TIM, holding it in reset
@@ -317,7 +315,8 @@ pub unsafe trait TimRegInterface {
     ///
     /// Only the bit related to the corresponding TIM peripheral is modified
     #[inline]
-    fn assert_tim_reset(&self) {
+    #[allow(dead_code)]
+    fn clear_tim_reset_bit(&self) {
         unsafe {
             va108xx::Peripherals::steal()
                 .sysconfig
@@ -327,7 +326,8 @@ pub unsafe trait TimRegInterface {
     }
 
     #[inline]
-    fn deassert_tim_reset(&self) {
+    #[allow(dead_code)]
+    fn set_tim_reset_bit(&self) {
         unsafe {
             va108xx::Peripherals::steal()
                 .sysconfig
@@ -335,21 +335,24 @@ pub unsafe trait TimRegInterface {
                 .modify(|r, w| w.bits(r.bits() | self.mask_32()));
         }
     }
+}
 
-    fn assert_tim_reset_for_cycles(&self, cycles: u32) {
-        self.assert_tim_reset();
-        cortex_m::asm::delay(cycles);
-        self.deassert_tim_reset();
+unsafe impl<Tim: ValidTim> TimRegInterface for Tim {
+    fn tim_id(&self) -> u8 {
+        Tim::TIM_ID
     }
 }
 
-#[derive(Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct TimId(u8);
+pub(crate) struct TimDynRegister {
+    pub(crate) tim_id: u8,
+    #[allow(dead_code)]
+    pub(crate) pin_id: DynPinId,
+}
 
-unsafe impl TimRegInterface for TimId {
-    fn raw_id(&self) -> u8 {
-        self.0
+unsafe impl TimRegInterface for TimDynRegister {
+    #[inline(always)]
+    fn tim_id(&self) -> u8 {
+        self.tim_id
     }
 }
 
@@ -358,80 +361,128 @@ unsafe impl TimRegInterface for TimId {
 //==================================================================================================
 
 /// Hardware timers
-pub struct CountdownTimer {
-    tim: TimId,
+pub struct CountdownTimer<Tim: ValidTim> {
+    tim: Tim,
     curr_freq: Hertz,
+    irq_cfg: Option<InterruptConfig>,
     sys_clk: Hertz,
     rst_val: u32,
     last_cnt: u32,
+    listening: bool,
 }
 
-unsafe impl TimRegInterface for CountdownTimer {
-    fn raw_id(&self) -> u8 {
-        self.tim.0
+#[inline(always)]
+pub fn enable_tim_clk(syscfg: &mut pac::Sysconfig, idx: u8) {
+    syscfg
+        .tim_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << idx)) });
+}
+
+#[inline(always)]
+pub fn disable_tim_clk(syscfg: &mut pac::Sysconfig, idx: u8) {
+    syscfg
+        .tim_clk_enable()
+        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << idx)) });
+}
+
+unsafe impl<TIM: ValidTim> TimRegInterface for CountdownTimer<TIM> {
+    fn tim_id(&self) -> u8 {
+        TIM::TIM_ID
     }
 }
 
-impl CountdownTimer {
-    /// Create a countdown timer structure for a given TIM peripheral.
-    ///
-    /// This does not enable the timer. You can use the [Self::load], [Self::start],
-    /// [Self::enable_interrupt] and [Self::enable] API to set up and configure the countdown
-    /// timer.
-    pub fn new<Tim: TimMarker + TimRegInterface>(sys_clk: Hertz, tim: Tim) -> Self {
-        enable_tim_clk(Tim::ID.raw_id());
-        tim.assert_tim_reset_for_cycles(2);
-        CountdownTimer {
-            tim: Tim::ID,
-            sys_clk,
+impl<Tim: ValidTim> CountdownTimer<Tim> {
+    /// Configures a TIM peripheral as a periodic count down timer
+    pub fn new(syscfg: &mut pac::Sysconfig, sys_clk: impl Into<Hertz>, tim: Tim) -> Self {
+        enable_tim_clk(syscfg, Tim::TIM_ID);
+        let cd_timer = CountdownTimer {
+            tim,
+            sys_clk: sys_clk.into(),
+            irq_cfg: None,
             rst_val: 0,
             curr_freq: 0.Hz(),
+            listening: false,
             last_cnt: 0,
+        };
+        cd_timer
+            .tim
+            .reg_block()
+            .ctrl()
+            .modify(|_, w| w.enable().set_bit());
+        cd_timer
+    }
+
+    /// Listen for events. Depending on the IRQ configuration, this also activates the IRQ in the
+    /// IRQSEL peripheral for the provided interrupt and unmasks the interrupt
+    pub fn listen(
+        &mut self,
+        event: Event,
+        irq_cfg: InterruptConfig,
+        irq_sel: Option<&mut pac::Irqsel>,
+        sys_cfg: Option<&mut pac::Sysconfig>,
+    ) {
+        match event {
+            Event::TimeOut => {
+                cortex_m::peripheral::NVIC::mask(irq_cfg.id);
+                self.irq_cfg = Some(irq_cfg);
+                if irq_cfg.route {
+                    if let Some(sys_cfg) = sys_cfg {
+                        enable_peripheral_clock(sys_cfg, PeripheralClocks::Irqsel);
+                    }
+                    if let Some(irq_sel) = irq_sel {
+                        irq_sel
+                            .tim0(Tim::TIM_ID as usize)
+                            .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
+                    }
+                }
+                self.listening = true;
+            }
+        }
+    }
+
+    pub fn unlisten(
+        &mut self,
+        event: Event,
+        syscfg: &mut pac::Sysconfig,
+        irqsel: &mut pac::Irqsel,
+    ) {
+        match event {
+            Event::TimeOut => {
+                enable_peripheral_clock(syscfg, PeripheralClocks::Irqsel);
+                irqsel
+                    .tim0(Tim::TIM_ID as usize)
+                    .write(|w| unsafe { w.bits(IRQ_DST_NONE) });
+                self.disable_interrupt();
+                self.listening = false;
+            }
         }
     }
 
     #[inline(always)]
-    pub fn enable(&mut self) {
-        self.tim
-            .reg_block()
-            .enable()
-            .write(|w| unsafe { w.bits(1) });
-    }
-
-    pub fn enable_interrupt(&mut self, irq_cfg: InterruptConfig) {
-        if irq_cfg.route {
-            let irqsel = unsafe { pac::Irqsel::steal() };
-            enable_peripheral_clock(PeripheralSelect::Irqsel);
-            irqsel
-                .tim0(self.raw_id() as usize)
-                .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
-        }
-        if irq_cfg.enable_in_nvic {
-            unsafe { enable_nvic_interrupt(irq_cfg.id) };
-        }
+    pub fn enable_interrupt(&mut self) {
         self.tim
             .reg_block()
             .ctrl()
             .modify(|_, w| w.irq_enb().set_bit());
     }
 
-    /// Calls [Self::load] to configure the specified frequency and then calls [Self::enable].
-    pub fn start(&mut self, frequency: impl Into<Hertz>) {
-        self.load(frequency);
-        self.enable();
+    #[inline(always)]
+    pub fn disable_interrupt(&mut self) {
+        self.tim
+            .reg_block()
+            .ctrl()
+            .modify(|_, w| w.irq_enb().clear_bit());
     }
 
-    /// Return `Ok` if the timer has wrapped. Peripheral will automatically clear the
-    /// flag and restart the time if configured correctly
-    pub fn wait(&mut self) -> nb::Result<(), void::Void> {
-        let cnt = self.tim.reg_block().cnt_value().read().bits();
-        if (cnt > self.last_cnt) || cnt == 0 {
-            self.last_cnt = self.rst_val;
-            Ok(())
-        } else {
-            self.last_cnt = cnt;
-            Err(nb::Error::WouldBlock)
-        }
+    pub fn release(self, syscfg: &mut pac::Sysconfig) -> Tim {
+        self.tim
+            .reg_block()
+            .ctrl()
+            .write(|w| w.enable().clear_bit());
+        syscfg
+            .tim_clk_enable()
+            .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << Tim::TIM_ID)) });
+        self.tim
     }
 
     /// Load the count down timer with a timeout but do not start it.
@@ -467,6 +518,20 @@ impl CountdownTimer {
         self.tim.reg_block().cnt_value().read().bits()
     }
 
+    #[inline(always)]
+    pub fn enable(&mut self) {
+        if let Some(irq_cfg) = self.irq_cfg {
+            self.enable_interrupt();
+            if irq_cfg.enable_in_nvic {
+                unsafe { enable_nvic_interrupt(irq_cfg.id) };
+            }
+        }
+        self.tim
+            .reg_block()
+            .enable()
+            .write(|w| unsafe { w.bits(1) });
+    }
+
     #[inline(always)]
     pub fn disable(&mut self) {
         self.tim
@@ -557,38 +622,49 @@ impl CountdownTimer {
         self.curr_freq
     }
 
-    /// This function only clears the interrupt enable bit.
-    ///
-    /// It does not mask the interrupt in the NVIC or un-route the IRQ.
-    #[inline(always)]
-    pub fn disable_interrupt(&mut self) {
-        self.tim
-            .reg_block()
-            .ctrl()
-            .modify(|_, w| w.irq_enb().clear_bit());
-    }
-
-    /// Disables the TIM and the dedicated TIM clock.
-    pub fn stop_with_clock_disable(self) {
-        self.tim
-            .reg_block()
-            .ctrl()
-            .write(|w| w.enable().clear_bit());
-        let syscfg = unsafe { va108xx::Sysconfig::steal() };
-        syscfg
-            .tim_clk_enable()
-            .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.raw_id())) });
+    pub fn listening(&self) -> bool {
+        self.listening
     }
 }
 
 /// CountDown implementation for TIMx
-impl CountdownTimer {}
+impl<TIM: ValidTim> CountdownTimer<TIM> {
+    #[inline]
+    pub fn start<T>(&mut self, timeout: T)
+    where
+        T: Into<Hertz>,
+    {
+        self.load(timeout);
+        self.enable();
+    }
 
-//==================================================================================================
-// Delay implementations
-//==================================================================================================
-//
-impl embedded_hal::delay::DelayNs for CountdownTimer {
+    /// Return `Ok` if the timer has wrapped. Peripheral will automatically clear the
+    /// flag and restart the time if configured correctly
+    pub fn wait(&mut self) -> nb::Result<(), void::Void> {
+        let cnt = self.tim.reg_block().cnt_value().read().bits();
+        if (cnt > self.last_cnt) || cnt == 0 {
+            self.last_cnt = self.rst_val;
+            Ok(())
+        } else {
+            self.last_cnt = cnt;
+            Err(nb::Error::WouldBlock)
+        }
+    }
+
+    /// Returns [false] if the timer was not active, and true otherwise.
+    pub fn cancel(&mut self) -> bool {
+        if !self.tim.reg_block().ctrl().read().enable().bit_is_set() {
+            return false;
+        }
+        self.tim
+            .reg_block()
+            .ctrl()
+            .write(|w| w.enable().clear_bit());
+        true
+    }
+}
+
+impl<TIM: ValidTim> embedded_hal::delay::DelayNs for CountdownTimer<TIM> {
     fn delay_ns(&mut self, ns: u32) {
         let ticks = (u64::from(ns)) * (u64::from(self.sys_clk.raw())) / 1_000_000_000;
 
@@ -642,18 +718,72 @@ impl embedded_hal::delay::DelayNs for CountdownTimer {
     }
 }
 
-#[inline(always)]
-pub fn enable_tim_clk(idx: u8) {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
-    syscfg
-        .tim_clk_enable()
-        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << idx)) });
+// Set up a millisecond timer on TIM0. Please note that the user still has to provide an IRQ handler
+// which should call [default_ms_irq_handler].
+pub fn set_up_ms_tick<TIM: ValidTim>(
+    irq_cfg: InterruptConfig,
+    sys_cfg: &mut pac::Sysconfig,
+    irq_sel: Option<&mut pac::Irqsel>,
+    sys_clk: impl Into<Hertz>,
+    tim0: TIM,
+) -> CountdownTimer<TIM> {
+    let mut ms_timer = CountdownTimer::new(sys_cfg, sys_clk, tim0);
+    ms_timer.listen(timer::Event::TimeOut, irq_cfg, irq_sel, Some(sys_cfg));
+    ms_timer.start(1000.Hz());
+    ms_timer
 }
 
-#[inline(always)]
-pub fn disable_tim_clk(idx: u8) {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
-    syscfg
-        .tim_clk_enable()
-        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << idx)) });
+pub fn set_up_ms_delay_provider<TIM: ValidTim>(
+    sys_cfg: &mut pac::Sysconfig,
+    sys_clk: impl Into<Hertz>,
+    tim: TIM,
+) -> CountdownTimer<TIM> {
+    let mut provider = CountdownTimer::new(sys_cfg, sys_clk, tim);
+    provider.start(1000.Hz());
+    provider
+}
+
+/// This function can be called in a specified interrupt handler to increment
+/// the MS counter
+pub fn default_ms_irq_handler() {
+    critical_section::with(|cs| {
+        let mut ms = MS_COUNTER.borrow(cs).get();
+        ms += 1;
+        MS_COUNTER.borrow(cs).set(ms);
+    });
+}
+
+/// Get the current MS tick count
+pub fn get_ms_ticks() -> u32 {
+    critical_section::with(|cs| MS_COUNTER.borrow(cs).get())
+}
+
+//==================================================================================================
+// Delay implementations
+//==================================================================================================
+
+pub struct DelayMs(CountdownTimer<pac::Tim0>);
+
+impl DelayMs {
+    pub fn new(timer: CountdownTimer<pac::Tim0>) -> Option<Self> {
+        if timer.curr_freq() != Hertz::from_raw(1000) || !timer.listening() {
+            return None;
+        }
+        Some(Self(timer))
+    }
+}
+
+/// This assumes that the user has already set up a MS tick timer in TIM0 as a system tick
+/// with [`set_up_ms_delay_provider`]
+impl embedded_hal::delay::DelayNs for DelayMs {
+    fn delay_ns(&mut self, ns: u32) {
+        let ns_as_ms = ns / 1_000_000;
+        if self.0.curr_freq() != Hertz::from_raw(1000) || !self.0.listening() {
+            return;
+        }
+        let start_time = get_ms_ticks();
+        while get_ms_ticks() - start_time < ns_as_ms {
+            cortex_m::asm::nop();
+        }
+    }
 }

va108xx-hal/src/typelevel.rs

@@ -0,0 +1,155 @@
+//! Module supporting type-level programming
+//!
+//! This module is identical to the
+//! [atsamd typelevel](https://docs.rs/atsamd-hal/latest/atsamd_hal/typelevel/index.html).
+
+use core::ops::{Add, Sub};
+
+use typenum::{Add1, Bit, Sub1, UInt, Unsigned, B1, U0};
+
+mod private {
+    /// Super trait used to mark traits with an exhaustive set of
+    /// implementations
+    pub trait Sealed {}
+
+    impl Sealed for u8 {}
+    impl Sealed for i8 {}
+    impl Sealed for u16 {}
+    impl Sealed for i16 {}
+    impl Sealed for u32 {}
+    impl Sealed for i32 {}
+    impl Sealed for f32 {}
+
+    /// Mapping from an instance of a countable type to its successor
+    pub trait Increment {
+        /// Successor type of `Self`
+        type Inc;
+        /// Consume an instance of `Self` and return its successor
+        fn inc(self) -> Self::Inc;
+    }
+
+    /// Mapping from an instance of a countable type to its predecessor
+    pub trait Decrement {
+        /// Predecessor type of `Self`
+        type Dec;
+        /// Consume an instance of `Self` and return its predecessor
+        fn dec(self) -> Self::Dec;
+    }
+}
+
+pub(crate) use private::Decrement as PrivateDecrement;
+pub(crate) use private::Increment as PrivateIncrement;
+pub(crate) use private::Sealed;
+
+/// Type-level version of the [`None`] variant
+#[derive(Default)]
+pub struct NoneT;
+
+impl Sealed for NoneT {}
+
+//==============================================================================
+// Is
+//==============================================================================
+
+/// Marker trait for type identity
+///
+/// This trait is used as part of the [`AnyKind`] trait pattern. It represents
+/// the concept of type identity, because all implementors have
+/// `<Self as Is>::Type == Self`. When used as a trait bound with a specific
+/// type, it guarantees that the corresponding type parameter is exactly the
+/// specific type. Stated differently, it guarantees that `T == Specific` in
+/// the following example.
+///
+/// ```ignore
+/// where T: Is<Type = Specific>
+/// ```
+///
+/// Moreover, the super traits guarantee that any instance of or reference to a
+/// type `T` can be converted into the `Specific` type.
+///
+/// ```ignore
+/// fn example<T>(mut any: T)
+/// where
+///     T: Is<Type = Specific>,
+/// {
+///     let specific_mut: &mut Specific = any.as_mut();
+///     let specific_ref: &Specific = any.as_ref();
+///     let specific: Specific = any.into();
+/// }
+/// ```
+///
+/// [`AnyKind`]: #anykind-trait-pattern
+pub trait Is
+where
+    Self: Sealed,
+    Self: From<IsType<Self>>,
+    Self: Into<IsType<Self>>,
+    Self: AsRef<IsType<Self>>,
+    Self: AsMut<IsType<Self>>,
+{
+    type Type;
+}
+
+/// Type alias for [`Is::Type`]
+pub type IsType<T> = <T as Is>::Type;
+
+impl<T> Is for T
+where
+    T: Sealed + AsRef<T> + AsMut<T>,
+{
+    type Type = T;
+}
+
+//==============================================================================
+// Counting
+//==============================================================================
+
+/// Implement `Sealed` for [`U0`]
+impl Sealed for U0 {}
+
+/// Implement `Sealed` for all type-level, [`Unsigned`] integers *except* [`U0`]
+impl<U: Unsigned, B: Bit> Sealed for UInt<U, B> {}
+
+/// Trait mapping each countable type to its successor
+///
+/// This trait maps each countable type to its corresponding successor type. The
+/// actual implementation of this trait is contained within `PrivateIncrement`.
+/// Access to `PrivateIncrement` is restricted, so that safe HAL APIs can be
+/// built with it.
+pub trait Increment: PrivateIncrement {}
+
+impl<T: PrivateIncrement> Increment for T {}
+
+/// Trait mapping each countable type to its predecessor
+///
+/// This trait maps each countable type to its corresponding predecessor type.
+/// The actual implementation of this trait is contained within
+/// `PrivateDecrement`. Access to `PrivateDecrement` is restricted, so that safe
+/// HAL APIs can be built with it.
+pub trait Decrement: PrivateDecrement {}
+
+impl<T: PrivateDecrement> Decrement for T {}
+
+impl<N> PrivateIncrement for N
+where
+    N: Unsigned + Add<B1>,
+    Add1<N>: Unsigned,
+{
+    type Inc = Add1<N>;
+    #[inline]
+    fn inc(self) -> Self::Inc {
+        Self::Inc::default()
+    }
+}
+
+impl<N> PrivateDecrement for N
+where
+    N: Unsigned + Sub<B1>,
+    Sub1<N>: Unsigned,
+{
+    type Dec = Sub1<N>;
+    #[inline]
+    fn dec(self) -> Self::Dec {
+        Self::Dec::default()
+    }
+}

va108xx-hal/src/uart/rx_asynch.rs

@@ -26,7 +26,7 @@ use embedded_io::ErrorType;
 use portable_atomic::AtomicBool;
 use va108xx::uarta as uart_base;
 
-use super::{Rx, UartErrors, UartId};
+use super::{Bank, Instance, Rx, UartErrors};
 
 static UART_RX_WAKERS: [AtomicWaker; 2] = [const { AtomicWaker::new() }; 2];
 static RX_READ_ACTIVE: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2];
@@ -37,10 +37,10 @@ struct RxFuture {
 }
 
 impl RxFuture {
-    pub fn new(rx: &mut Rx) -> Self {
-        RX_READ_ACTIVE[rx.0 as usize].store(true, Ordering::Relaxed);
+    pub fn new<Uart: Instance>(_rx: &mut Rx<Uart>) -> Self {
+        RX_READ_ACTIVE[Uart::IDX as usize].store(true, Ordering::Relaxed);
         Self {
-            uart_idx: rx.0 as usize,
+            uart_idx: Uart::IDX as usize,
         }
     }
 }
@@ -92,12 +92,12 @@ fn on_interrupt_handle_rx_errors(uart: &'static uart_base::RegisterBlock) -> Opt
 }
 
 fn on_interrupt_rx_common_post_processing(
-    id: UartId,
+    bank: Bank,
     rx_enabled: bool,
     read_some_data: bool,
     irq_end: u32,
 ) -> Option<UartErrors> {
-    let idx = id as usize;
+    let idx = bank as usize;
     if read_some_data {
         RX_HAS_DATA[idx].store(true, Ordering::Relaxed);
         if RX_READ_ACTIVE[idx].load(Ordering::Relaxed) {
@@ -106,7 +106,7 @@ fn on_interrupt_rx_common_post_processing(
     }
 
     let mut errors = None;
-    let uart_regs = unsafe { id.reg_block() };
+    let uart_regs = unsafe { bank.reg_block() };
     // Check for RX errors
     if rx_enabled {
         errors = on_interrupt_handle_rx_errors(uart_regs);
@@ -123,7 +123,7 @@ fn on_interrupt_rx_common_post_processing(
 /// asynchronous reception. This variant will overwrite old data in the ring buffer in case
 /// the ring buffer is full.
 pub fn on_interrupt_rx_overwriting<const N: usize>(
-    bank: UartId,
+    bank: Bank,
     prod: &mut heapless::spsc::Producer<u8, N>,
     shared_consumer: &Mutex<RefCell<Option<heapless::spsc::Consumer<'static, u8, N>>>>,
 ) -> Result<(), AsyncUartErrors> {
@@ -131,7 +131,7 @@ pub fn on_interrupt_rx_overwriting<const N: usize>(
 }
 
 pub fn on_interrupt_rx_async_heapless_queue_overwriting<const N: usize>(
-    bank: UartId,
+    bank: Bank,
     prod: &mut heapless::spsc::Producer<u8, N>,
     shared_consumer: &Mutex<RefCell<Option<heapless::spsc::Consumer<'static, u8, N>>>>,
 ) -> Result<(), AsyncUartErrors> {
@@ -194,14 +194,14 @@ pub fn on_interrupt_rx_async_heapless_queue_overwriting<const N: usize>(
 ///
 /// Should be called in the user interrupt handler to enable asynchronous reception.
 pub fn on_interrupt_rx<const N: usize>(
-    bank: UartId,
+    bank: Bank,
     prod: &mut heapless::spsc::Producer<'_, u8, N>,
 ) -> Result<(), AsyncUartErrors> {
     on_interrupt_rx_async_heapless_queue(bank, prod)
 }
 
 pub fn on_interrupt_rx_async_heapless_queue<const N: usize>(
-    bank: UartId,
+    bank: Bank,
     prod: &mut heapless::spsc::Producer<'_, u8, N>,
 ) -> Result<(), AsyncUartErrors> {
     let uart = unsafe { bank.reg_block() };
@@ -259,33 +259,33 @@ impl Drop for ActiveReadGuard {
     }
 }
 
-struct RxAsyncInner<const N: usize> {
-    rx: Rx,
+struct RxAsyncInner<Uart: Instance, const N: usize> {
+    rx: Rx<Uart>,
     pub queue: heapless::spsc::Consumer<'static, u8, N>,
 }
 
 /// Core data structure to allow asynchronous UART reception.
 ///
 /// If the ring buffer becomes full, data will be lost.
-pub struct RxAsync<const N: usize>(Option<RxAsyncInner<N>>);
+pub struct RxAsync<Uart: Instance, const N: usize>(Option<RxAsyncInner<Uart, N>>);
 
-impl<const N: usize> ErrorType for RxAsync<N> {
+impl<Uart: Instance, const N: usize> ErrorType for RxAsync<Uart, N> {
     /// Error reporting is done using the result of the interrupt functions.
     type Error = Infallible;
 }
 
-fn stop_async_rx(rx: &mut Rx) {
+fn stop_async_rx<Uart: Instance>(rx: &mut Rx<Uart>) {
     rx.disable_interrupts();
     rx.disable();
     rx.clear_fifo();
 }
 
-impl<const N: usize> RxAsync<N> {
+impl<Uart: Instance, const N: usize> RxAsync<Uart, N> {
     /// Create a new asynchronous receiver.
     ///
     /// The passed [heapless::spsc::Consumer] will be used to asynchronously receive data which
     /// is filled by the interrupt handler [on_interrupt_rx].
-    pub fn new(mut rx: Rx, queue: heapless::spsc::Consumer<'static, u8, N>) -> Self {
+    pub fn new(mut rx: Rx<Uart>, queue: heapless::spsc::Consumer<'static, u8, N>) -> Self {
         rx.disable_interrupts();
         rx.disable();
         rx.clear_fifo();
@@ -301,28 +301,27 @@ impl<const N: usize> RxAsync<N> {
         stop_async_rx(&mut self.0.as_mut().unwrap().rx);
     }
 
-    pub fn release(mut self) -> (Rx, heapless::spsc::Consumer<'static, u8, N>) {
+    pub fn release(mut self) -> (Rx<Uart>, heapless::spsc::Consumer<'static, u8, N>) {
         self.stop();
         let inner = self.0.take().unwrap();
         (inner.rx, inner.queue)
     }
 }
 
-impl<const N: usize> Drop for RxAsync<N> {
+impl<Uart: Instance, const N: usize> Drop for RxAsync<Uart, N> {
     fn drop(&mut self) {
         self.stop();
     }
 }
 
-impl<const N: usize> embedded_io_async::Read for RxAsync<N> {
+impl<Uart: Instance, const N: usize> embedded_io_async::Read for RxAsync<Uart, N> {
     async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
-        let inner = self.0.as_ref().unwrap();
         // Need to wait for the IRQ to read data and set this flag. If the queue is not
         // empty, we can read data immediately.
-        if inner.queue.len() == 0 {
-            RX_HAS_DATA[inner.rx.0 as usize].store(false, Ordering::Relaxed);
+        if self.0.as_ref().unwrap().queue.len() == 0 {
+            RX_HAS_DATA[Uart::IDX as usize].store(false, Ordering::Relaxed);
         }
-        let _guard = ActiveReadGuard(inner.rx.0 as usize);
+        let _guard = ActiveReadGuard(Uart::IDX as usize);
         let mut handle_data_in_queue = |consumer: &mut heapless::spsc::Consumer<'static, u8, N>| {
             let data_to_read = consumer.len().min(buf.len());
             for byte in buf.iter_mut().take(data_to_read) {
@@ -344,8 +343,8 @@ impl<const N: usize> embedded_io_async::Read for RxAsync<N> {
     }
 }
 
-struct RxAsyncOverwritingInner<const N: usize> {
-    rx: Rx,
+struct RxAsyncOverwritingInner<Uart: Instance, const N: usize> {
+    rx: Rx<Uart>,
     pub shared_consumer: &'static Mutex<RefCell<Option<heapless::spsc::Consumer<'static, u8, N>>>>,
 }
 
@@ -353,21 +352,23 @@ struct RxAsyncOverwritingInner<const N: usize> {
 ///
 /// If the ring buffer becomes full, the oldest data will be overwritten when using the
 /// [on_interrupt_rx_overwriting] interrupt handlers.
-pub struct RxAsyncOverwriting<const N: usize>(Option<RxAsyncOverwritingInner<N>>);
+pub struct RxAsyncOverwriting<Uart: Instance, const N: usize>(
+    Option<RxAsyncOverwritingInner<Uart, N>>,
+);
 
-impl<const N: usize> ErrorType for RxAsyncOverwriting<N> {
+impl<Uart: Instance, const N: usize> ErrorType for RxAsyncOverwriting<Uart, N> {
     /// Error reporting is done using the result of the interrupt functions.
     type Error = Infallible;
 }
 
-impl<const N: usize> RxAsyncOverwriting<N> {
+impl<Uart: Instance, const N: usize> RxAsyncOverwriting<Uart, N> {
     /// Create a new asynchronous receiver.
     ///
     /// The passed shared [heapless::spsc::Consumer] will be used to asynchronously receive data
     /// which is filled by the interrupt handler. The shared property allows using it in the
     /// interrupt handler to overwrite old data.
     pub fn new(
-        mut rx: Rx,
+        mut rx: Rx<Uart>,
         shared_consumer: &'static Mutex<RefCell<Option<heapless::spsc::Consumer<'static, u8, N>>>>,
     ) -> Self {
         rx.disable_interrupts();
@@ -388,34 +389,32 @@ impl<const N: usize> RxAsyncOverwriting<N> {
         stop_async_rx(&mut self.0.as_mut().unwrap().rx);
     }
 
-    pub fn release(mut self) -> Rx {
+    pub fn release(mut self) -> Rx<Uart> {
         self.stop();
         let inner = self.0.take().unwrap();
         inner.rx
     }
 }
 
-impl<const N: usize> Drop for RxAsyncOverwriting<N> {
+impl<Uart: Instance, const N: usize> Drop for RxAsyncOverwriting<Uart, N> {
     fn drop(&mut self) {
         self.stop();
     }
 }
 
-impl<const N: usize> embedded_io_async::Read for RxAsyncOverwriting<N> {
+impl<Uart: Instance, const N: usize> embedded_io_async::Read for RxAsyncOverwriting<Uart, N> {
     async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
-        let inner = self.0.as_ref().unwrap();
-        let id = inner.rx.0 as usize;
         // Need to wait for the IRQ to read data and set this flag. If the queue is not
         // empty, we can read data immediately.
 
         critical_section::with(|cs| {
-            let queue = inner.shared_consumer.borrow(cs);
+            let queue = self.0.as_ref().unwrap().shared_consumer.borrow(cs);
             if queue.borrow().as_ref().unwrap().len() == 0 {
-                RX_HAS_DATA[id].store(false, Ordering::Relaxed);
+                RX_HAS_DATA[Uart::IDX as usize].store(false, Ordering::Relaxed);
             }
         });
-        let _guard = ActiveReadGuard(id);
-        let mut handle_data_in_queue = |inner: &mut RxAsyncOverwritingInner<N>| {
+        let _guard = ActiveReadGuard(Uart::IDX as usize);
+        let mut handle_data_in_queue = |inner: &mut RxAsyncOverwritingInner<Uart, N>| {
             critical_section::with(|cs| {
                 let mut consumer_ref = inner.shared_consumer.borrow(cs).borrow_mut();
                 let consumer = consumer_ref.as_mut().unwrap();

va108xx-hal/src/uart/tx_asynch.rs

@@ -32,7 +32,7 @@ static TX_DONE: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2];
 ///
 /// The user has to call this once in the interrupt handler responsible for the TX interrupts on
 /// the given UART bank.
-pub fn on_interrupt_tx(bank: UartId) {
+pub fn on_interrupt_tx(bank: Bank) {
     let uart = unsafe { bank.reg_block() };
     let idx = bank as usize;
     let irq_enb = uart.irq_enb().read();
@@ -153,20 +153,20 @@ impl TxFuture {
     ///
     /// This function stores the raw pointer of the passed data slice. The user MUST ensure
     /// that the slice outlives the data structure.
-    pub unsafe fn new(tx: &mut Tx, data: &[u8]) -> Self {
-        TX_DONE[tx.0 as usize].store(false, core::sync::atomic::Ordering::Relaxed);
+    pub unsafe fn new<Uart: Instance>(tx: &mut Tx<Uart>, data: &[u8]) -> Self {
+        TX_DONE[Uart::IDX as usize].store(false, core::sync::atomic::Ordering::Relaxed);
         tx.disable_interrupts();
         tx.disable();
         tx.clear_fifo();
 
-        let uart_tx = tx.regs_priv();
+        let uart_tx = unsafe { tx.uart() };
         let init_fill_count = core::cmp::min(data.len(), 16);
         // We fill the FIFO.
         for data in data.iter().take(init_fill_count) {
             uart_tx.data().write(|w| unsafe { w.bits(*data as u32) });
         }
         critical_section::with(|cs| {
-            let context_ref = TX_CONTEXTS[tx.0 as usize].borrow(cs);
+            let context_ref = TX_CONTEXTS[Uart::IDX as usize].borrow(cs);
             let mut context = context_ref.borrow_mut();
             context.slice.set(data);
             context.progress = init_fill_count;
@@ -177,7 +177,7 @@ impl TxFuture {
             tx.enable();
         });
         Self {
-            uart_idx: tx.0 as usize,
+            uart_idx: Uart::IDX as usize,
         }
     }
 }
@@ -213,15 +213,17 @@ impl Drop for TxFuture {
     }
 }
 
-pub struct TxAsync(Tx);
+pub struct TxAsync<Uart: Instance> {
+    tx: Tx<Uart>,
+}
 
-impl TxAsync {
-    pub fn new(tx: Tx) -> Self {
-        Self(tx)
+impl<Uart: Instance> TxAsync<Uart> {
+    pub fn new(tx: Tx<Uart>) -> Self {
+        Self { tx }
     }
 
-    pub fn release(self) -> Tx {
-        self.0
+    pub fn release(self) -> Tx<Uart> {
+        self.tx
     }
 }
 
@@ -236,17 +238,17 @@ impl embedded_io_async::Error for TxOverrunError {
     }
 }
 
-impl embedded_io::ErrorType for TxAsync {
+impl<Uart: Instance> embedded_io::ErrorType for TxAsync<Uart> {
     type Error = TxOverrunError;
 }
 
-impl Write for TxAsync {
+impl<Uart: Instance> Write for TxAsync<Uart> {
     /// Write a buffer asynchronously.
     ///
     /// This implementation is not side effect free, and a started future might have already
     /// written part of the passed buffer.
     async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
-        let fut = unsafe { TxFuture::new(&mut self.0, buf) };
+        let fut = unsafe { TxFuture::new(&mut self.tx, buf) };
         fut.await
     }
 }

vorago-reb1/Cargo.toml

@@ -15,11 +15,10 @@ cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7"
 embedded-hal = "1"
 nb = "1"
-bitbybit = "1.3"
-arbitrary-int = "1.3"
+bitfield = ">=0.17, <=0.19"
 max116xx-10bit = "0.3"
 
-va108xx-hal = { version = ">=0.10, <=0.11", path = "../va108xx-hal", features = ["rt"] }
+va108xx-hal = { version = ">=0.10, <=0.11", features = ["rt"] }
 
 [features]
 rt = ["va108xx-hal/rt"]

vorago-reb1/examples/adt75-temp-sensor.rs

@@ -4,17 +4,17 @@ use cortex_m_rt::entry;
 use embedded_hal::delay::DelayNs;
 use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
-use va108xx_hal::{pac, prelude::*, timer::CountdownTimer};
+use va108xx_hal::{pac, prelude::*, timer::set_up_ms_delay_provider};
 use vorago_reb1::temp_sensor::Adt75TempSensor;
 
 #[entry]
 fn main() -> ! {
     rtt_init_print!();
     rprintln!("-- Vorago Temperature Sensor and I2C Example --");
-    let dp = pac::Peripherals::take().unwrap();
-    let mut delay = CountdownTimer::new(50.MHz(), dp.tim0);
-    let mut temp_sensor =
-        Adt75TempSensor::new(50.MHz(), dp.i2ca).expect("Creating temperature sensor struct failed");
+    let mut dp = pac::Peripherals::take().unwrap();
+    let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
+    let mut temp_sensor = Adt75TempSensor::new(&mut dp.sysconfig, 50.MHz(), dp.i2ca)
+        .expect("Creating temperature sensor struct failed");
     loop {
         let temp = temp_sensor
             .read_temperature()

vorago-reb1/examples/adxl343-accelerometer.rs

@@ -9,14 +9,13 @@ use embedded_hal::delay::DelayNs;
 use embedded_hal::spi::{SpiBus, MODE_3};
 use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
-use va108xx_hal::gpio::{Output, PinState};
-use va108xx_hal::pins::PinsA;
-use va108xx_hal::spi::{configure_pin_as_hw_cs_pin, SpiClkConfig};
-use va108xx_hal::timer::CountdownTimer;
+use va108xx_hal::spi::SpiClkConfig;
 use va108xx_hal::{
+    gpio::PinsA,
     pac,
     prelude::*,
     spi::{Spi, SpiConfig},
+    timer::set_up_ms_delay_provider,
 };
 
 const READ_MASK: u8 = 1 << 7;
@@ -30,15 +29,19 @@ const PWR_MEASUREMENT_MODE_MASK: u8 = 1 << 3;
 fn main() -> ! {
     rtt_init_print!();
     rprintln!("-- Vorago Accelerometer Example --");
-    let dp = pac::Peripherals::take().unwrap();
-    let pinsa = PinsA::new(dp.porta);
-    let mut delay = CountdownTimer::new(50.MHz(), dp.tim0);
-    let (sck, mosi, miso) = (pinsa.pa20, pinsa.pa19, pinsa.pa18);
-    let cs_pin = pinsa.pa16;
-    let hw_cs_id = configure_pin_as_hw_cs_pin(cs_pin);
+    let mut dp = pac::Peripherals::take().unwrap();
+    let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
+    let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let (sck, mosi, miso) = (
+        pinsa.pa20.into_funsel_2(),
+        pinsa.pa19.into_funsel_2(),
+        pinsa.pa18.into_funsel_2(),
+    );
+    let cs_pin = pinsa.pa16.into_funsel_2();
 
     // Need to set the ADC chip select low
-    Output::new(pinsa.pa17, PinState::Low);
+    let mut adc_cs = pinsa.pa17.into_push_pull_output();
+    adc_cs.set_high();
 
     let spi_cfg = SpiConfig::default()
         .clk_cfg(
@@ -46,8 +49,14 @@ fn main() -> ! {
         )
         .mode(MODE_3)
         .slave_output_disable(true);
-    let mut spi = Spi::new(50.MHz(), dp.spib, (sck, miso, mosi), spi_cfg).unwrap();
-    spi.cfg_hw_cs(hw_cs_id);
+    let mut spi = Spi::new(
+        &mut dp.sysconfig,
+        50.MHz(),
+        dp.spib,
+        (sck, miso, mosi),
+        spi_cfg,
+    );
+    spi.cfg_hw_cs_with_pin(&cs_pin);
 
     let mut tx_rx_buf: [u8; 3] = [0; 3];
     tx_rx_buf[0] = READ_MASK | DEVID_REG;

vorago-reb1/examples/blinky-button-irq.rs

@@ -10,10 +10,10 @@ use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{
     clock::{set_clk_div_register, FilterClkSel},
-    gpio::{FilterType, InterruptEdge},
+    gpio::{FilterType, InterruptEdge, PinsA},
     pac::{self, interrupt},
-    pins::PinsA,
-    timer::InterruptConfig,
+    prelude::*,
+    timer::{default_ms_irq_handler, set_up_ms_tick, InterruptConfig},
 };
 use vorago_reb1::button::Button;
 use vorago_reb1::leds::Leds;
@@ -35,18 +35,18 @@ fn main() -> ! {
     rtt_init_print!();
     rprintln!("-- Vorago Button IRQ Example --");
     let mut dp = pac::Peripherals::take().unwrap();
-    let pinsa = PinsA::new(dp.porta);
+    let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
     let edge_irq = match PRESS_MODE {
         PressMode::Toggle => InterruptEdge::HighToLow,
         PressMode::Keep => InterruptEdge::BothEdges,
     };
 
     // Configure an edge interrupt on the button and route it to interrupt vector 15
-    let mut button = Button::new(pinsa.pa11);
+    let mut button = Button::new(pinsa.pa11.into_floating_input());
 
     if PRESS_MODE == PressMode::Toggle {
         // This filter debounces the switch for edge based interrupts
-        button.configure_filter_type(FilterType::FilterFourCycles, FilterClkSel::Clk1);
+        button.configure_filter_type(FilterType::FilterFourClockCycles, FilterClkSel::Clk1);
         set_clk_div_register(&mut dp.sysconfig, FilterClkSel::Clk1, 50_000);
     }
     button.configure_and_enable_edge_interrupt(
@@ -54,7 +54,18 @@ fn main() -> ! {
         InterruptConfig::new(pac::interrupt::OC15, true, true),
     );
 
-    let mut leds = Leds::new(pinsa.pa10, pinsa.pa7, pinsa.pa6);
+    set_up_ms_tick(
+        InterruptConfig::new(pac::Interrupt::OC0, true, true),
+        &mut dp.sysconfig,
+        Some(&mut dp.irqsel),
+        50.MHz(),
+        dp.tim0,
+    );
+    let mut leds = Leds::new(
+        pinsa.pa10.into_push_pull_output(),
+        pinsa.pa7.into_push_pull_output(),
+        pinsa.pa6.into_push_pull_output(),
+    );
     for led in leds.iter_mut() {
         led.off();
     }
@@ -68,6 +79,11 @@ fn main() -> ! {
     }
 }
 
+#[interrupt]
+fn OC0() {
+    default_ms_irq_handler();
+}
+
 #[interrupt]
 fn OC15() {
     cortex_m::interrupt::free(|cs| {

vorago-reb1/examples/blinky-leds.rs

@@ -9,13 +9,7 @@
 use cortex_m_rt::entry;
 use embedded_hal::delay::DelayNs;
 use panic_halt as _;
-use va108xx_hal::{
-    gpio::{Output, PinState},
-    pac,
-    pins::PinsA,
-    prelude::*,
-    timer::CountdownTimer,
-};
+use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::set_up_ms_delay_provider};
 use vorago_reb1::leds::Leds;
 
 // REB LED pin definitions. All on port A
@@ -32,7 +26,7 @@ enum LibType {
 
 #[entry]
 fn main() -> ! {
-    let dp = pac::Peripherals::take().unwrap();
+    let mut dp = pac::Peripherals::take().unwrap();
 
     let lib_type = LibType::Bsp;
 
@@ -66,11 +60,11 @@ fn main() -> ! {
             }
         }
         LibType::Hal => {
-            let pins = PinsA::new(dp.porta);
-            let mut led1 = Output::new(pins.pa10, PinState::Low);
-            let mut led2 = Output::new(pins.pa7, PinState::Low);
-            let mut led3 = Output::new(pins.pa6, PinState::Low);
-            let mut delay = CountdownTimer::new(50.MHz(), dp.tim0);
+            let pins = PinsA::new(&mut dp.sysconfig, dp.porta);
+            let mut led1 = pins.pa10.into_readable_push_pull_output();
+            let mut led2 = pins.pa7.into_readable_push_pull_output();
+            let mut led3 = pins.pa6.into_readable_push_pull_output();
+            let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
             for _ in 0..10 {
                 led1.set_low();
                 led2.set_low();
@@ -89,9 +83,13 @@ fn main() -> ! {
             }
         }
         LibType::Bsp => {
-            let pinsa = PinsA::new(dp.porta);
-            let mut leds = Leds::new(pinsa.pa10, pinsa.pa7, pinsa.pa6);
-            let mut delay = CountdownTimer::new(50.MHz(), dp.tim0);
+            let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
+            let mut leds = Leds::new(
+                pinsa.pa10.into_push_pull_output(),
+                pinsa.pa7.into_push_pull_output(),
+                pinsa.pa6.into_push_pull_output(),
+            );
+            let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
             for _ in 0..10 {
                 // Blink all LEDs quickly
                 for led in leds.iter_mut() {

vorago-reb1/examples/max11619-adc.rs

@@ -14,19 +14,20 @@ use max116xx_10bit::VoltageRefMode;
 use max116xx_10bit::{AveragingConversions, AveragingResults};
 use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
-use va108xx_hal::gpio::{Input, Output, PinState, Port};
-use va108xx_hal::pins::PinsA;
-use va108xx_hal::spi::{configure_pin_as_hw_cs_pin, SpiClkConfig};
+use va108xx_hal::gpio::Port;
+use va108xx_hal::spi::{OptionalHwCs, SpiClkConfig};
 use va108xx_hal::timer::CountdownTimer;
 use va108xx_hal::{
-    pac,
+    gpio::PinsA,
+    pac::{self, interrupt},
     prelude::*,
-    spi::{HwChipSelectId, Spi, SpiConfig},
+    spi::{Spi, SpiBase, SpiConfig},
+    timer::{default_ms_irq_handler, set_up_ms_tick, DelayMs, InterruptConfig},
 };
 use va108xx_hal::{port_function_select, FunSel};
 use vorago_reb1::max11619::{
     max11619_externally_clocked_no_wakeup, max11619_externally_clocked_with_wakeup,
-    max11619_internally_clocked, AN2_CHANNEL, POTENTIOMETER_CHANNEL,
+    max11619_internally_clocked, EocPin, AN2_CHANNEL, POTENTIOMETER_CHANNEL,
 };
 
 #[derive(Debug, PartialEq, Copy, Clone)]
@@ -56,34 +57,34 @@ const MUX_MODE: MuxMode = MuxMode::None;
 
 // This is probably more or less a re-implementation of https://docs.rs/embedded-hal-bus/latest/embedded_hal_bus/spi/struct.ExclusiveDevice.html.
 // Users should look at the embedded-hal-bus crate for sharing the bus.
-pub struct SpiWithHwCs<Delay> {
-    inner: Spi<u8>,
+pub struct SpiWithHwCs<Delay, HwCs> {
+    inner: SpiBase<pac::Spib, u8>,
     delay_provider: Delay,
-    hw_cs_id: HwChipSelectId,
+    hw_cs: HwCs,
 }
 
-impl<Delay: DelayNs> SpiWithHwCs<Delay> {
-    pub fn new(spi: Spi<u8>, hw_cs_id: HwChipSelectId, delay_provider: Delay) -> Self {
+impl<Delay: DelayNs, HwCs: OptionalHwCs<pac::Spib>> SpiWithHwCs<Delay, HwCs> {
+    pub fn new(spi: SpiBase<pac::Spib, u8>, hw_cs: HwCs, delay_provider: Delay) -> Self {
         Self {
             inner: spi,
-            hw_cs_id,
+            hw_cs,
             delay_provider,
         }
     }
 }
 
-impl<Delay> embedded_hal::spi::ErrorType for SpiWithHwCs<Delay> {
+impl<Delay, HwCs> embedded_hal::spi::ErrorType for SpiWithHwCs<Delay, HwCs> {
     type Error = Infallible;
 }
 
-impl<Delay: DelayNs> SpiDevice for SpiWithHwCs<Delay> {
+impl<Delay: DelayNs, HwCs: OptionalHwCs<pac::Spib>> SpiDevice for SpiWithHwCs<Delay, HwCs> {
     fn transaction(
         &mut self,
         operations: &mut [spi::Operation<'_, u8>],
     ) -> Result<(), Self::Error> {
         // Only the HW CS is configured here. This is not really necessary, but showcases
         // that we could scale this multiple SPI devices.
-        self.inner.cfg_hw_cs(self.hw_cs_id);
+        self.inner.cfg_hw_cs_with_pin(&self.hw_cs);
         for operation in operations {
             match operation {
                 spi::Operation::Read(buf) => self.inner.read(buf).ok().unwrap(),
@@ -110,17 +111,28 @@ fn main() -> ! {
     rprintln!("-- Vorago ADC Example --");
 
     let mut dp = pac::Peripherals::take().unwrap();
-    let mut delay = CountdownTimer::new(SYS_CLK, dp.tim0);
+    let tim0 = set_up_ms_tick(
+        InterruptConfig::new(pac::Interrupt::OC0, true, true),
+        &mut dp.sysconfig,
+        Some(&mut dp.irqsel),
+        SYS_CLK,
+        dp.tim0,
+    );
+    let delay = DelayMs::new(tim0).unwrap();
     unsafe {
         cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0);
     }
 
-    let pinsa = PinsA::new(dp.porta);
+    let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
     let spi_cfg = SpiConfig::default()
         .clk_cfg(SpiClkConfig::from_clk(SYS_CLK, 3.MHz()).unwrap())
         .mode(MODE_0)
         .blockmode(true);
-    let (sck, mosi, miso) = (pinsa.pa20, pinsa.pa19, pinsa.pa18);
+    let (sck, mosi, miso) = (
+        pinsa.pa20.into_funsel_2(),
+        pinsa.pa19.into_funsel_2(),
+        pinsa.pa18.into_funsel_2(),
+    );
 
     if MUX_MODE == MuxMode::PortB19to17 {
         port_function_select(&mut dp.ioconfig, Port::B, 19, FunSel::Sel1).ok();
@@ -129,30 +141,39 @@ fn main() -> ! {
         port_function_select(&mut dp.ioconfig, Port::B, 16, FunSel::Sel1).ok();
     }
     // Set the accelerometer chip select low in case the board slot is populated
-    Output::new(pinsa.pa16, PinState::Low);
+    let mut accel_cs = pinsa.pa16.into_push_pull_output();
+    accel_cs.set_high();
 
-    let hw_cs_id = configure_pin_as_hw_cs_pin(pinsa.pa17);
-    let spi = Spi::new(50.MHz(), dp.spib, (sck, miso, mosi), spi_cfg).unwrap();
-
-    let delay_spi = CountdownTimer::new(SYS_CLK, dp.tim1);
-    let spi_with_hwcs = SpiWithHwCs::new(spi, hw_cs_id, delay_spi);
+    let spi = Spi::new(
+        &mut dp.sysconfig,
+        50.MHz(),
+        dp.spib,
+        (sck, miso, mosi),
+        spi_cfg,
+    )
+    .downgrade();
+    let delay_provider = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim1);
+    let spi_with_hwcs = SpiWithHwCs::new(spi, pinsa.pa17.into_funsel_2(), delay_provider);
     match EXAMPLE_MODE {
-        ExampleMode::NotUsingEoc => spi_example_externally_clocked(spi_with_hwcs, &mut delay),
+        ExampleMode::NotUsingEoc => spi_example_externally_clocked(spi_with_hwcs, delay),
         ExampleMode::UsingEoc => {
-            spi_example_internally_clocked(
-                spi_with_hwcs,
-                &mut delay,
-                Input::new_floating(pinsa.pa14),
-            );
+            spi_example_internally_clocked(spi_with_hwcs, delay, pinsa.pa14.into_floating_input());
         }
         ExampleMode::NotUsingEocWithDelay => {
-            spi_example_externally_clocked_with_delay(spi_with_hwcs, &mut delay);
+            let delay_us = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim2);
+            spi_example_externally_clocked_with_delay(spi_with_hwcs, delay, delay_us);
         }
     }
 }
 
+#[interrupt]
+#[allow(non_snake_case)]
+fn OC0() {
+    default_ms_irq_handler();
+}
+
 /// Use the SPI clock as the conversion clock
-fn spi_example_externally_clocked(spi: impl SpiDevice, delay: &mut impl DelayNs) -> ! {
+fn spi_example_externally_clocked(spi: impl SpiDevice, mut delay: DelayMs) -> ! {
     let mut adc = max11619_externally_clocked_no_wakeup(spi)
         .expect("Creating externally clocked MAX11619 device failed");
     if READ_MODE == ReadMode::AverageN {
@@ -207,7 +228,11 @@ fn spi_example_externally_clocked(spi: impl SpiDevice, delay: &mut impl DelayNs)
     }
 }
 
-fn spi_example_externally_clocked_with_delay(spi: impl SpiDevice, delay: &mut impl DelayNs) -> ! {
+fn spi_example_externally_clocked_with_delay(
+    spi: impl SpiDevice,
+    mut delay: DelayMs,
+    mut delay_us: impl DelayNs,
+) -> ! {
     let mut adc =
         max11619_externally_clocked_with_wakeup(spi).expect("Creating MAX116xx device failed");
     let mut cmd_buf: [u8; 32] = [0; 32];
@@ -219,7 +244,7 @@ fn spi_example_externally_clocked_with_delay(spi: impl SpiDevice, delay: &mut im
             ReadMode::Single => {
                 rprintln!("Reading single potentiometer channel");
                 let pot_val = adc
-                    .read_single_channel(&mut cmd_buf, POTENTIOMETER_CHANNEL, delay)
+                    .read_single_channel(&mut cmd_buf, POTENTIOMETER_CHANNEL, &mut delay_us)
                     .expect("Creating externally clocked MAX11619 ADC failed");
                 rprintln!("Single channel read:");
                 rprintln!("\tPotentiometer value: {}", pot_val);
@@ -230,7 +255,7 @@ fn spi_example_externally_clocked_with_delay(spi: impl SpiDevice, delay: &mut im
                     &mut cmd_buf,
                     &mut res_buf.iter_mut(),
                     POTENTIOMETER_CHANNEL,
-                    delay,
+                    &mut delay_us,
                 )
                 .expect("Multi-Channel read failed");
                 print_res_buf(&res_buf);
@@ -241,7 +266,7 @@ fn spi_example_externally_clocked_with_delay(spi: impl SpiDevice, delay: &mut im
                     &mut cmd_buf,
                     &mut res_buf.iter_mut(),
                     AN2_CHANNEL,
-                    delay,
+                    &mut delay_us,
                 )
                 .expect("Multi-Channel read failed");
                 rprintln!("Multi channel read from 2 to 3:");
@@ -258,11 +283,7 @@ fn spi_example_externally_clocked_with_delay(spi: impl SpiDevice, delay: &mut im
 }
 
 /// This function uses the EOC pin to determine whether the conversion finished
-fn spi_example_internally_clocked(
-    spi: impl SpiDevice,
-    delay: &mut impl DelayNs,
-    eoc_pin: Input,
-) -> ! {
+fn spi_example_internally_clocked(spi: impl SpiDevice, mut delay: DelayMs, eoc_pin: EocPin) -> ! {
     let mut adc = max11619_internally_clocked(
         spi,
         eoc_pin,

vorago-reb1/examples/nvm.rs

@@ -15,12 +15,12 @@ fn main() -> ! {
     rtt_init_print!();
     rprintln!("-- VA108XX REB1 NVM example --");
 
-    let dp = pac::Peripherals::take().unwrap();
+    let mut dp = pac::Peripherals::take().unwrap();
 
-    let mut timer = CountdownTimer::new(CLOCK_FREQ, dp.tim0);
-    let mut nvm = M95M01::new(CLOCK_FREQ, dp.spic);
+    let mut timer = CountdownTimer::new(&mut dp.sysconfig, CLOCK_FREQ, dp.tim0);
+    let mut nvm = M95M01::new(&mut dp.sysconfig, CLOCK_FREQ, dp.spic);
     let status_reg = nvm.read_status_reg().expect("reading status reg failed");
-    if status_reg.zero_segment().value() == 0b111 {
+    if status_reg.zero_segment() == 0b111 {
         panic!("status register unexpected values");
     }
 

vorago-reb1/src/button.rs

@@ -5,18 +5,16 @@
 //! - [Button Blinky with IRQs](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-irq.rs)
 //! - [Button Blinky with IRQs and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-rtic.rs)
 use va108xx_hal::{
-    clock::FilterClkSel,
-    gpio::{FilterType, Input, InterruptEdge, InterruptLevel, Pin},
-    pins::Pa11,
+    gpio::{FilterClkSel, FilterType, InputFloating, InterruptEdge, InterruptLevel, Pin, PA11},
     InterruptConfig,
 };
 
 #[derive(Debug)]
-pub struct Button(pub Input);
+pub struct Button(pub Pin<PA11, InputFloating>);
 
 impl Button {
-    pub fn new(pin: Pin<Pa11>) -> Button {
-        Button(Input::new_floating(pin))
+    pub fn new(pin: Pin<PA11, InputFloating>) -> Button {
+        Button(pin)
     }
 
     #[inline]

vorago-reb1/src/leds.rs

@@ -6,20 +6,20 @@
 //! - [Button Blinky using IRQs](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-irq.rs)
 //! - [Button Blinky using IRQs and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-rtic.rs)
 use va108xx_hal::{
-    gpio::{Output, PinState},
-    pins::{Pa10, Pa6, Pa7, Pin},
+    gpio::dynpin::DynPin,
+    gpio::pin::{Pin, PushPullOutput, PA10, PA6, PA7},
 };
 
+pub type LD2 = Pin<PA10, PushPullOutput>;
+pub type LD3 = Pin<PA7, PushPullOutput>;
+pub type LD4 = Pin<PA6, PushPullOutput>;
+
 #[derive(Debug)]
 pub struct Leds(pub [Led; 3]);
 
 impl Leds {
-    pub fn new(led_pin1: Pin<Pa10>, led_pin2: Pin<Pa7>, led_pin3: Pin<Pa6>) -> Leds {
-        Leds([
-            Led(Output::new(led_pin1, PinState::Low)),
-            Led(Output::new(led_pin2, PinState::Low)),
-            Led(Output::new(led_pin3, PinState::Low)),
-        ])
+    pub fn new(led_pin1: LD2, led_pin2: LD3, led_pin3: LD4) -> Leds {
+        Leds([led_pin1.into(), led_pin2.into(), led_pin3.into()])
     }
 }
 
@@ -52,24 +52,38 @@ impl core::ops::IndexMut<usize> for Leds {
 }
 
 #[derive(Debug)]
-pub struct Led(Output);
+pub struct Led(pub DynPin);
+
+macro_rules! ctor {
+	($($ldx:ident),+) => {
+		$(
+			impl From<$ldx> for Led {
+				fn from(led: $ldx) -> Self {
+					Led(led.into())
+				}
+			}
+		)+
+	}
+}
+
+ctor!(LD2, LD3, LD4);
 
 impl Led {
     /// Turns the LED off. Setting the pin high actually turns the LED off
     #[inline]
     pub fn off(&mut self) {
-        self.0.set_high();
+        self.0.set_high().ok();
     }
 
     /// Turns the LED on. Setting the pin low actually turns the LED on
     #[inline]
     pub fn on(&mut self) {
-        self.0.set_low();
+        self.0.set_low().ok();
     }
 
     /// Toggles the LED
     #[inline]
     pub fn toggle(&mut self) {
-        self.0.toggle();
+        self.0.toggle().ok();
     }
 }

vorago-reb1/src/m95m01.rs

@@ -7,25 +7,20 @@
 //! # Example
 //!
 //! - [REB1 EEPROM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/nvm.rs)
-use arbitrary_int::{u2, u3};
 use core::convert::Infallible;
 use embedded_hal::spi::SpiBus;
 
 pub const PAGE_SIZE: usize = 256;
 
-#[bitbybit::bitfield(u8)]
-#[derive(Debug)]
-pub struct StatusReg {
-    #[bit(7, r)]
-    status_register_write_protect: bool,
-    #[bits(4..=6, r)]
-    zero_segment: u3,
-    #[bits(2..=3, rw)]
-    block_protection_bits: u2,
-    #[bit(1, r)]
-    write_enable_latch: bool,
-    #[bit(0, r)]
-    write_in_progress: bool,
+bitfield::bitfield! {
+    pub struct StatusReg(u8);
+    impl Debug;
+    u8;
+    pub status_register_write_protect, _: 7;
+    pub zero_segment, _: 6, 4;
+    pub block_protection_bits, set_block_protection_bits: 3, 2;
+    pub write_enable_latch, _: 1;
+    pub write_in_progress, _: 0;
 }
 
 // Registers.
@@ -48,10 +43,10 @@ use regs::*;
 use va108xx_hal::{
     pac,
     prelude::*,
-    spi::{Spi, SpiClkConfig, SpiConfig, SpiLowLevel, BMSTART_BMSTOP_MASK},
+    spi::{RomMiso, RomMosi, RomSck, Spi, SpiClkConfig, SpiConfig, BMSTART_BMSTOP_MASK},
 };
 
-pub type RomSpi = Spi<u8>;
+pub type RomSpi = Spi<pac::Spic, (RomSck, RomMiso, RomMosi), u8>;
 
 /// Driver for the ST device M95M01 EEPROM memory.
 ///
@@ -64,13 +59,14 @@ pub struct M95M01 {
 pub struct PageBoundaryExceededError;
 
 impl M95M01 {
-    pub fn new(sys_clk: Hertz, spi: pac::Spic) -> Self {
-        let spi = RomSpi::new_for_rom(
+    pub fn new(syscfg: &mut pac::Sysconfig, sys_clk: impl Into<Hertz>, spi: pac::Spic) -> Self {
+        let spi = RomSpi::new(
+            syscfg,
             sys_clk,
             spi,
+            (RomSck, RomMiso, RomMosi),
             SpiConfig::default().clk_cfg(SpiClkConfig::new(2, 4)),
-        )
-        .unwrap();
+        );
         let mut spi_dev = Self { spi };
         spi_dev.clear_block_protection().unwrap();
         spi_dev
@@ -78,7 +74,7 @@ impl M95M01 {
 
     pub fn release(mut self) -> pac::Spic {
         self.set_block_protection().unwrap();
-        unsafe { pac::Spic::steal() }
+        self.spi.release().0
     }
 
     // Wait until the write-in-progress state is cleared. This exposes a [nb] API, so this function
@@ -94,7 +90,7 @@ impl M95M01 {
     pub fn read_status_reg(&mut self) -> Result<StatusReg, Infallible> {
         let mut write_read: [u8; 2] = [regs::RDSR, 0x00];
         self.spi.transfer_in_place(&mut write_read)?;
-        Ok(StatusReg::new_with_raw_value(write_read[1]))
+        Ok(StatusReg(write_read[1]))
     }
 
     pub fn write_enable(&mut self) -> Result<(), Infallible> {
@@ -108,10 +104,10 @@ impl M95M01 {
     }
 
     pub fn set_block_protection(&mut self) -> Result<(), Infallible> {
-        let mut reg = StatusReg::new_with_raw_value(0);
-        reg.set_block_protection_bits(u2::new(0b11));
+        let mut reg = StatusReg(0);
+        reg.set_block_protection_bits(0b11);
         self.write_enable()?;
-        self.spi.write(&[WRSR, reg.raw_value()])
+        self.spi.write(&[WRSR, reg.0])
     }
 
     fn common_init_write_and_read(&mut self, address: usize, reg: u8) -> Result<(), Infallible> {

vorago-reb1/src/max11619.rs

@@ -9,7 +9,7 @@ use max116xx_10bit::{
     Error, ExternallyClocked, InternallyClockedInternallyTimedSerialInterface, Max116xx10Bit,
     Max116xx10BitEocExt, VoltageRefMode, WithWakeupDelay, WithoutWakeupDelay,
 };
-use va108xx_hal::gpio::Input;
+use va108xx_hal::gpio::{Floating, Input, Pin, PA14};
 
 pub type Max11619ExternallyClockedNoWakeup<Spi> =
     Max116xx10Bit<Spi, ExternallyClocked, WithoutWakeupDelay>;
@@ -17,6 +17,7 @@ pub type Max11619ExternallyClockedWithWakeup<Spi> =
     Max116xx10Bit<Spi, ExternallyClocked, WithWakeupDelay>;
 pub type Max11619InternallyClocked<Spi, Eoc> =
     Max116xx10BitEocExt<Spi, Eoc, InternallyClockedInternallyTimedSerialInterface>;
+pub type EocPin = Pin<PA14, Input<Floating>>;
 
 pub const AN0_CHANNEL: u8 = 0;
 pub const AN1_CHANNEL: u8 = 1;
@@ -43,9 +44,9 @@ pub fn max11619_externally_clocked_with_wakeup<Spi: SpiDevice>(
 
 pub fn max11619_internally_clocked<Spi: SpiDevice>(
     spi: Spi,
-    eoc: Input,
+    eoc: EocPin,
     v_ref: VoltageRefMode,
-) -> Result<Max11619InternallyClocked<Spi, Input>, Error<Spi::Error, Infallible>> {
+) -> Result<Max11619InternallyClocked<Spi, EocPin>, Error<Spi::Error, Infallible>> {
     let mut adc = Max116xx10Bit::max11619(spi)?
         .into_int_clkd_int_timed_through_ser_if_without_wakeup(v_ref, eoc)?;
     adc.reset(false)?;

vorago-reb1/src/temp_sensor.rs

@@ -15,7 +15,7 @@ use va108xx_hal::{
 const ADT75_I2C_ADDR: u8 = 0b1001000;
 
 pub struct Adt75TempSensor {
-    sensor_if: I2cMaster<SevenBitAddress>,
+    sensor_if: I2cMaster<pac::I2ca, SevenBitAddress>,
     cmd_buf: [u8; 1],
     current_reg: RegAddresses,
 }
@@ -48,10 +48,15 @@ impl From<Error> for AdtInitError {
 }
 
 impl Adt75TempSensor {
-    pub fn new(sys_clk: Hertz, i2ca: pac::I2ca) -> Result<Self, Error> {
+    pub fn new(
+        sys_cfg: &mut pac::Sysconfig,
+        sys_clk: impl Into<Hertz> + Copy,
+        i2ca: pac::I2ca,
+    ) -> Result<Self, Error> {
         let mut sensor = Adt75TempSensor {
             // The master construction can not fail for regular I2C speed.
             sensor_if: I2cMaster::new(
+                sys_cfg,
                 sys_clk,
                 i2ca,
                 MasterConfig::default(),

vorago-shared-periphs/Cargo.toml

@@ -1,39 +0,0 @@
-[package]
-name = "vorago-shared-periphs"
-version = "0.1.0"
-description = "Peripheral drivers shared between Vorago families"
-edition = "2024"
-
-[dependencies]
-cortex-m = { version = "0.7" }
-cfg-if = "1"
-derive-mmio = { path = "../../../ROMEO/derive-mmio" }
-bitbybit = "1.3"
-arbitrary-int = "1.3"
-static_assertions = "1.1"
-nb = "1"
-heapless = "0.8"
-critical-section = "1"
-embedded-hal = { version = "1.0" }
-embedded-hal-async = "1"
-embedded-hal-nb = "1"
-embedded-io = "0.6"
-embedded-io-async = "0.6"
-raw-slicee = "0.1"
-thiserror = { version = "2", default-features = false }
-paste = "1"
-fugit = "0.3"
-embassy-sync = "0.6"
-defmt = { version = "1", optional = true }
-va108xx = { version = "0.5", default-features = false, optional = true }
-
-[target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
-portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
-[target.'cfg(not(all(target_arch = "arm", target_os = "none")))'.dependencies]
-portable-atomic = "1"
-
-[features]
-vor1x = ["_family-selected", "va108xx"]
-vor4x = ["_family-selected"]
-
-_family-selected = []

vorago-shared-periphs/src/gpio/asynch.rs

@@ -1,231 +0,0 @@
-//! # Async GPIO functionality for the Vorago GPIO peripherals.
-//!
-//! This module provides the [InputPinAsync] which implements
-//! the [embedded_hal_async::digital::Wait] trait. These types allow for asynchronous waiting
-//! on GPIO pins. Please note that this module does not specify/declare the interrupt handlers
-//! which must be provided for async support to work. However, it provides the
-//! [on_interrupt_for_async_gpio_for_port] generic interrupt handler. This should be called in all
-//! IRQ functions which handle any GPIO interrupts with the corresponding [Port] argument.
-use core::future::Future;
-
-use embassy_sync::waitqueue::AtomicWaker;
-use embedded_hal_async::digital::Wait;
-use portable_atomic::AtomicBool;
-
-use crate::{InterruptConfig, NUM_PORT_A, NUM_PORT_B};
-
-pub use super::ll::InterruptEdge;
-use super::{
-    Input, Port,
-    ll::{LowLevelGpio, PinId},
-};
-
-static WAKERS_FOR_PORT_A: [AtomicWaker; NUM_PORT_A] = [const { AtomicWaker::new() }; NUM_PORT_A];
-static WAKERS_FOR_PORT_B: [AtomicWaker; NUM_PORT_B] = [const { AtomicWaker::new() }; NUM_PORT_B];
-static EDGE_DETECTION_PORT_A: [AtomicBool; NUM_PORT_A] =
-    [const { AtomicBool::new(false) }; NUM_PORT_A];
-static EDGE_DETECTION_PORT_B: [AtomicBool; NUM_PORT_B] =
-    [const { AtomicBool::new(false) }; NUM_PORT_B];
-
-/// Generic interrupt handler for GPIO interrupts on a specific port to support async functionalities
-///
-/// This function should be called in all interrupt handlers which handle any GPIO interrupts
-/// matching the [Port] argument.
-/// The handler will wake the corresponding wakers for the pins that triggered an interrupts
-/// as well as update the static edge detection structures. This allows the pin future tocomplete
-/// complete async operations.
-pub fn on_interrupt_for_async_gpio_for_port(port: Port) {
-    let gpio = unsafe { port.steal_gpio() };
-
-    let irq_enb = gpio.read_irq_enable();
-    let edge_status = gpio.read_edge_status();
-    let (wakers, edge_detection) = match port {
-        Port::A => (WAKERS_FOR_PORT_A.as_ref(), EDGE_DETECTION_PORT_A.as_ref()),
-        Port::B => (WAKERS_FOR_PORT_B.as_ref(), EDGE_DETECTION_PORT_B.as_ref()),
-    };
-
-    on_interrupt_for_port(irq_enb, edge_status, wakers, edge_detection);
-}
-
-#[inline]
-fn on_interrupt_for_port(
-    mut irq_enb: u32,
-    edge_status: u32,
-    wakers: &'static [AtomicWaker],
-    edge_detection: &'static [AtomicBool],
-) {
-    while irq_enb != 0 {
-        let bit_pos = irq_enb.trailing_zeros() as usize;
-        let bit_mask = 1 << bit_pos;
-
-        wakers[bit_pos].wake();
-
-        if edge_status & bit_mask != 0 {
-            edge_detection[bit_pos].store(true, core::sync::atomic::Ordering::Relaxed);
-
-            // Clear the processed bit
-            irq_enb &= !bit_mask;
-        }
-    }
-}
-
-/// Input pin future which implements the [Future] trait.
-///
-/// Generally, you want to use the [InputPinAsync] types instead of this
-/// which also implements the [embedded_hal_async::digital::Wait] trait. However, access to this
-/// struture is granted  to allow writing custom async structures.
-pub struct InputPinFuture {
-    id: PinId,
-    waker_group: &'static [AtomicWaker],
-    edge_detection_group: &'static [AtomicBool],
-}
-
-impl InputPinFuture {
-    #[inline]
-    pub fn pin_group_to_waker_and_edge_detection_group(
-        group: Port,
-    ) -> (&'static [AtomicWaker], &'static [AtomicBool]) {
-        match group {
-            Port::A => (WAKERS_FOR_PORT_A.as_ref(), EDGE_DETECTION_PORT_A.as_ref()),
-            Port::B => (WAKERS_FOR_PORT_B.as_ref(), EDGE_DETECTION_PORT_B.as_ref()),
-        }
-    }
-
-    pub fn new_with_input_pin(
-        pin: &mut Input,
-        irq: va108xx::Interrupt,
-        edge: InterruptEdge,
-    ) -> Self {
-        let (waker_group, edge_detection_group) =
-            Self::pin_group_to_waker_and_edge_detection_group(pin.id().port());
-        edge_detection_group[pin.id().offset()].store(false, core::sync::atomic::Ordering::Relaxed);
-        pin.configure_edge_interrupt(edge);
-        #[cfg(feature = "vor1x")]
-        pin.enable_interrupt(InterruptConfig::new(irq, true, true));
-        Self {
-            id: pin.id(),
-            waker_group,
-            edge_detection_group,
-        }
-    }
-}
-
-impl Drop for InputPinFuture {
-    fn drop(&mut self) {
-        let mut ll = LowLevelGpio::new(self.id);
-        ll.disable_interrupt(false);
-    }
-}
-
-impl Future for InputPinFuture {
-    type Output = ();
-    fn poll(
-        self: core::pin::Pin<&mut Self>,
-        cx: &mut core::task::Context<'_>,
-    ) -> core::task::Poll<Self::Output> {
-        let idx = self.id.offset();
-        self.waker_group[idx].register(cx.waker());
-        if self.edge_detection_group[idx].swap(false, core::sync::atomic::Ordering::Relaxed) {
-            return core::task::Poll::Ready(());
-        }
-        core::task::Poll::Pending
-    }
-}
-
-pub struct InputPinAsync {
-    pin: Input,
-    #[cfg(feature = "vor1x")]
-    irq: va108xx::Interrupt,
-}
-
-impl InputPinAsync {
-    /// Create a new asynchronous input pin from an [Input] pin. The interrupt ID to be used must be
-    /// passed as well and is used to route and enable the interrupt.
-    ///
-    /// Please note that the interrupt handler itself must be provided by the user and the
-    /// generic [on_interrupt_for_async_gpio_for_port] function must be called inside that function
-    /// for the asynchronous functionality to work.
-    #[cfg(feature = "vor1x")]
-    pub fn new(pin: Input, irq: va108xx::Interrupt) -> Self {
-        Self { pin, irq }
-    }
-
-    /// Asynchronously wait until the pin is high.
-    ///
-    /// This returns immediately if the pin is already high.
-    pub async fn wait_for_high(&mut self) {
-        // Unwrap okay, checked pin in constructor.
-        let fut =
-            InputPinFuture::new_with_input_pin(&mut self.pin, self.irq, InterruptEdge::LowToHigh);
-        if self.pin.is_high() {
-            return;
-        }
-        fut.await;
-    }
-
-    /// Asynchronously wait until the pin is low.
-    ///
-    /// This returns immediately if the pin is already high.
-    pub async fn wait_for_low(&mut self) {
-        // Unwrap okay, checked pin in constructor.
-        let fut =
-            InputPinFuture::new_with_input_pin(&mut self.pin, self.irq, InterruptEdge::HighToLow);
-        if self.pin.is_low() {
-            return;
-        }
-        fut.await;
-    }
-
-    /// Asynchronously wait until the pin sees a falling edge.
-    pub async fn wait_for_falling_edge(&mut self) {
-        // Unwrap okay, checked pin in constructor.
-        InputPinFuture::new_with_input_pin(&mut self.pin, self.irq, InterruptEdge::HighToLow).await;
-    }
-
-    /// Asynchronously wait until the pin sees a rising edge.
-    pub async fn wait_for_rising_edge(&mut self) {
-        // Unwrap okay, checked pin in constructor.
-        InputPinFuture::new_with_input_pin(&mut self.pin, self.irq, InterruptEdge::LowToHigh).await;
-    }
-
-    /// Asynchronously wait until the pin sees any edge (either rising or falling).
-    pub async fn wait_for_any_edge(&mut self) {
-        // Unwrap okay, checked pin in constructor.
-        InputPinFuture::new_with_input_pin(&mut self.pin, self.irq, InterruptEdge::BothEdges).await;
-    }
-
-    pub fn release(self) -> Input {
-        self.pin
-    }
-}
-
-impl embedded_hal::digital::ErrorType for InputPinAsync {
-    type Error = core::convert::Infallible;
-}
-
-impl Wait for InputPinAsync {
-    async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_high().await;
-        Ok(())
-    }
-
-    async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_low().await;
-        Ok(())
-    }
-
-    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_rising_edge().await;
-        Ok(())
-    }
-
-    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_falling_edge().await;
-        Ok(())
-    }
-
-    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_any_edge().await;
-        Ok(())
-    }
-}

vorago-shared-periphs/src/gpio/ll.rs

@@ -1,424 +0,0 @@
-pub use embedded_hal::digital::PinState;
-
-use crate::ioconfig::FilterClkSel;
-use crate::ioconfig::FilterType;
-#[cfg(feature = "vor1x")]
-use crate::{PeripheralSelect, sysconfig::enable_peripheral_clock};
-
-pub use crate::InvalidOffsetError;
-pub use crate::Port;
-pub use crate::ioconfig::regs::Pull;
-use crate::ioconfig::regs::{FunSel, IoConfig, MmioIoConfig};
-
-use super::Pin;
-use super::PinIdProvider;
-
-#[derive(Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum InterruptEdge {
-    HighToLow,
-    LowToHigh,
-    BothEdges,
-}
-
-#[derive(Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum InterruptLevel {
-    Low = 0,
-    High = 1,
-}
-
-/// Pin identifier for all physical pins exposed by Vorago MCUs.
-#[derive(Debug, PartialEq, Eq, Clone, Copy)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct PinId {
-    port: Port,
-    /// Offset within the port.
-    offset: u8,
-}
-
-impl PinId {
-    /// Unchecked constructor which panics on invalid offsets.
-    pub const fn new_unchecked(port: Port, offset: usize) -> Self {
-        if offset >= port.max_offset() {
-            panic!("Pin ID construction: offset is out of range");
-        }
-        PinId {
-            port,
-            offset: offset as u8,
-        }
-    }
-
-    pub const fn new(port: Port, offset: usize) -> Result<Self, InvalidOffsetError> {
-        if offset >= port.max_offset() {
-            return Err(InvalidOffsetError { offset, port });
-        }
-        Ok(PinId {
-            port,
-            offset: offset as u8,
-        })
-    }
-
-    pub const fn port(&self) -> Port {
-        self.port
-    }
-
-    pub const fn offset(&self) -> usize {
-        self.offset as usize
-    }
-}
-
-/// Low-level driver structure for GPIO pins.
-pub struct LowLevelGpio {
-    gpio: super::regs::MmioGpio<'static>,
-    ioconfig: MmioIoConfig<'static>,
-    id: PinId,
-}
-
-impl core::fmt::Debug for LowLevelGpio {
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        f.debug_struct("LowLevelGpio")
-            .field("gpio", &self.gpio.port())
-            .field("id", &self.id)
-            .finish()
-    }
-}
-
-impl LowLevelGpio {
-    /// Create a new low-level GPIO pin instance from a given [Pin].
-    ///
-    /// Can be used for performing resource management of the [Pin]s.
-    pub fn new_with_pin<I: PinIdProvider>(_pin: Pin<I>) -> Self {
-        Self::new(I::ID)
-    }
-
-    /// Create a new low-level GPIO pin instance using only the [PinId].
-    pub fn new(id: PinId) -> Self {
-        LowLevelGpio {
-            gpio: super::regs::Gpio::new_mmio(id.port),
-            ioconfig: IoConfig::new_mmio(),
-            id,
-        }
-    }
-
-    #[inline]
-    pub fn id(&self) -> PinId {
-        self.id
-    }
-
-    #[inline]
-    pub fn port(&self) -> Port {
-        self.id.port()
-    }
-
-    #[inline]
-    pub fn offset(&self) -> usize {
-        self.id.offset()
-    }
-
-    pub fn configure_as_input_floating(&mut self) {
-        self.ioconfig.modify_pin_config(self.id, |mut config| {
-            config.set_funsel(FunSel::Sel0);
-            config.set_io_disable(false);
-            config.set_invert_input(false);
-            config.set_open_drain(false);
-            config.set_pull_enable(false);
-            config.set_pull_when_output_active(false);
-            config.set_invert_output(false);
-            config.set_input_enable_when_output(false);
-            config
-        });
-        self.gpio.modify_dir(|mut dir| {
-            dir &= !(1 << self.id.offset());
-            dir
-        });
-    }
-
-    pub fn configure_as_input_with_pull(&mut self, pull: Pull) {
-        self.ioconfig.modify_pin_config(self.id, |mut config| {
-            config.set_funsel(FunSel::Sel0);
-            config.set_io_disable(false);
-            config.set_invert_input(false);
-            config.set_open_drain(false);
-            config.set_pull_enable(true);
-            config.set_pull_dir(pull);
-            config.set_pull_when_output_active(false);
-            config.set_invert_output(false);
-            config.set_input_enable_when_output(false);
-            config
-        });
-        self.gpio.modify_dir(|mut dir| {
-            dir &= !(1 << self.id.offset());
-            dir
-        });
-    }
-
-    pub fn configure_as_output_push_pull(&mut self, init_level: PinState) {
-        self.ioconfig.modify_pin_config(self.id, |mut config| {
-            config.set_funsel(FunSel::Sel0);
-            config.set_io_disable(false);
-            config.set_invert_input(false);
-            config.set_open_drain(false);
-            config.set_pull_enable(false);
-            config.set_pull_when_output_active(false);
-            config.set_invert_output(false);
-            config.set_input_enable_when_output(true);
-            config
-        });
-        match init_level {
-            PinState::Low => self.gpio.write_clr_out(self.mask_32()),
-            PinState::High => self.gpio.write_set_out(self.mask_32()),
-        }
-        self.gpio.modify_dir(|mut dir| {
-            dir |= 1 << self.id.offset();
-            dir
-        });
-    }
-
-    pub fn configure_as_output_open_drain(&mut self, init_level: PinState) {
-        self.ioconfig.modify_pin_config(self.id, |mut config| {
-            config.set_funsel(FunSel::Sel0);
-            config.set_io_disable(false);
-            config.set_invert_input(false);
-            config.set_open_drain(true);
-            config.set_pull_enable(true);
-            config.set_pull_dir(Pull::Up);
-            config.set_pull_when_output_active(false);
-            config.set_invert_output(false);
-            config.set_input_enable_when_output(true);
-            config
-        });
-        let mask32 = self.mask_32();
-        match init_level {
-            PinState::Low => self.gpio.write_clr_out(mask32),
-            PinState::High => self.gpio.write_set_out(mask32),
-        }
-        self.gpio.modify_dir(|mut dir| {
-            dir |= mask32;
-            dir
-        });
-    }
-
-    pub fn configure_as_peripheral_pin(&mut self, fun_sel: FunSel, pull: Option<Pull>) {
-        self.ioconfig.modify_pin_config(self.id, |mut config| {
-            config.set_funsel(fun_sel);
-            config.set_io_disable(false);
-            config.set_invert_input(false);
-            config.set_open_drain(false);
-            config.set_pull_enable(pull.is_some());
-            config.set_pull_dir(pull.unwrap_or(Pull::Up));
-            config.set_invert_output(false);
-            config
-        });
-    }
-
-    #[inline]
-    pub fn is_high(&self) -> bool {
-        (self.gpio.read_data_in() >> self.offset()) & 1 == 1
-    }
-
-    #[inline]
-    pub fn is_low(&self) -> bool {
-        !self.is_high()
-    }
-
-    #[inline]
-    pub fn set_high(&mut self) {
-        self.gpio.write_set_out(self.mask_32());
-    }
-
-    #[inline]
-    pub fn set_low(&mut self) {
-        self.gpio.write_clr_out(self.mask_32());
-    }
-
-    #[inline]
-    pub fn is_set_high(&self) -> bool {
-        (self.gpio.read_data_out() >> self.offset()) & 1 == 1
-    }
-
-    #[inline]
-    pub fn is_set_low(&self) -> bool {
-        !self.is_set_high()
-    }
-
-    #[inline]
-    pub fn toggle(&mut self) {
-        self.gpio.write_tog_out(self.mask_32());
-    }
-
-    #[cfg(feature = "vor1x")]
-    pub fn enable_interrupt(&mut self, irq_cfg: crate::InterruptConfig) {
-        if irq_cfg.route {
-            self.configure_irqsel(irq_cfg.id);
-        }
-        if irq_cfg.enable_in_nvic {
-            unsafe { crate::enable_nvic_interrupt(irq_cfg.id) };
-        }
-        self.gpio.modify_irq_enable(|mut value| {
-            value |= 1 << self.id.offset;
-            value
-        });
-    }
-
-    #[cfg(feature = "vor1x")]
-    pub fn disable_interrupt(&mut self, reset_irqsel: bool) {
-        if reset_irqsel {
-            self.reset_irqsel();
-        }
-        // We only manipulate our own bit.
-        self.gpio.modify_irq_enable(|mut value| {
-            value &= !(1 << self.id.offset);
-            value
-        });
-    }
-
-    /// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure
-    /// When using edge mode, it is possible to generate interrupts on both edges as well
-    #[inline]
-    pub fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) {
-        let mask32 = self.mask_32();
-        self.gpio.modify_irq_sen(|mut value| {
-            value &= !mask32;
-            value
-        });
-        match edge_type {
-            InterruptEdge::HighToLow => {
-                self.gpio.modify_irq_evt(|mut value| {
-                    value &= !mask32;
-                    value
-                });
-            }
-            InterruptEdge::LowToHigh => {
-                self.gpio.modify_irq_evt(|mut value| {
-                    value |= mask32;
-                    value
-                });
-            }
-            InterruptEdge::BothEdges => {
-                self.gpio.modify_irq_edge(|mut value| {
-                    value |= mask32;
-                    value
-                });
-            }
-        }
-    }
-
-    /// Configure which edge or level type triggers an interrupt
-    #[inline]
-    pub fn configure_level_interrupt(&mut self, level: InterruptLevel) {
-        let mask32 = self.mask_32();
-        self.gpio.modify_irq_sen(|mut value| {
-            value |= mask32;
-            value
-        });
-        if level == InterruptLevel::Low {
-            self.gpio.modify_irq_evt(|mut value| {
-                value &= !mask32;
-                value
-            });
-        } else {
-            self.gpio.modify_irq_evt(|mut value| {
-                value |= mask32;
-                value
-            });
-        }
-    }
-
-    /// Only useful for input pins
-    #[inline]
-    pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
-        self.ioconfig.modify_pin_config(self.id, |mut config| {
-            config.set_filter_type(filter);
-            config.set_filter_clk_sel(clksel);
-            config
-        });
-    }
-
-    /// Only useful for output pins.
-    #[inline]
-    pub fn configure_pulse_mode(&mut self, enable: bool, default_state: PinState) {
-        self.gpio.modify_pulse(|mut value| {
-            if enable {
-                value |= 1 << self.id.offset;
-            } else {
-                value &= !(1 << self.id.offset);
-            }
-            value
-        });
-        self.gpio.modify_pulsebase(|mut value| {
-            if default_state == PinState::High {
-                value |= 1 << self.id.offset;
-            } else {
-                value &= !(1 << self.id.offset);
-            }
-            value
-        });
-    }
-
-    /// Only useful for output pins
-    #[inline]
-    pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool) {
-        self.gpio.modify_delay1(|mut value| {
-            if delay_1 {
-                value |= 1 << self.id.offset;
-            } else {
-                value &= !(1 << self.id.offset);
-            }
-            value
-        });
-        self.gpio.modify_delay2(|mut value| {
-            if delay_2 {
-                value |= 1 << self.id.offset;
-            } else {
-                value &= !(1 << self.id.offset);
-            }
-            value
-        });
-    }
-
-    #[cfg(feature = "vor1x")]
-    /// Configure the IRQSEL peripheral for this particular pin with the given interrupt ID.
-    pub fn configure_irqsel(&mut self, id: va108xx::Interrupt) {
-        let irqsel = unsafe { va108xx::Irqsel::steal() };
-        enable_peripheral_clock(PeripheralSelect::Irqsel);
-        match self.id().port() {
-            // Set the correct interrupt number in the IRQSEL register
-            super::Port::A => {
-                irqsel
-                    .porta0(self.id().offset())
-                    .write(|w| unsafe { w.bits(id as u32) });
-            }
-            super::Port::B => {
-                irqsel
-                    .portb0(self.id().offset())
-                    .write(|w| unsafe { w.bits(id as u32) });
-            }
-        }
-    }
-
-    #[cfg(feature = "vor1x")]
-    /// Reset the IRQSEL peripheral value for this particular pin.
-    pub fn reset_irqsel(&mut self) {
-        let irqsel = unsafe { va108xx::Irqsel::steal() };
-        enable_peripheral_clock(PeripheralSelect::Irqsel);
-        match self.id().port() {
-            // Set the correct interrupt number in the IRQSEL register
-            super::Port::A => {
-                irqsel
-                    .porta0(self.id().offset())
-                    .write(|w| unsafe { w.bits(u32::MAX) });
-            }
-            super::Port::B => {
-                irqsel
-                    .portb0(self.id().offset())
-                    .write(|w| unsafe { w.bits(u32::MAX) });
-            }
-        }
-    }
-
-    #[inline(always)]
-    pub const fn mask_32(&self) -> u32 {
-        1 << self.id.offset()
-    }
-}

vorago-shared-periphs/src/gpio/mod.rs

@@ -1,374 +0,0 @@
-//! GPIO support module.
-use core::convert::Infallible;
-
-pub use crate::ioconfig::{FilterClkSel, FilterType, regs::FunSel};
-pub use embedded_hal::digital::PinState;
-pub use ll::{InterruptEdge, InterruptLevel, PinId, Port, Pull};
-
-pub mod asynch;
-pub mod ll;
-pub mod regs;
-
-/// Trait implemented by data structures assocaited with pin identifiacation.
-pub trait PinIdProvider {
-    const ID: ll::PinId;
-}
-
-/// Primary Pin structure for the physical pins exposed by Vorago MCUs.
-///
-/// This pin structure is only used for resource management and does not do anything on its
-/// own.
-pub struct Pin<I: PinIdProvider> {
-    phantom: core::marker::PhantomData<I>,
-}
-
-impl<I: PinIdProvider> Pin<I> {
-    #[allow(clippy::new_without_default)]
-    #[doc(hidden)]
-    pub const fn __new() -> Self {
-        Self {
-            phantom: core::marker::PhantomData,
-        }
-    }
-
-    /// Create a new pin instance.
-    ///
-    /// # Safety
-    ///
-    /// This circumvents ownership rules of the HAL and allows creating multiple instances
-    /// of the same pin.
-    pub const unsafe fn steal() -> Self {
-        Self::__new()
-    }
-}
-
-/// Push-Pull output pin.
-#[derive(Debug)]
-pub struct Output(ll::LowLevelGpio);
-
-impl Output {
-    pub fn new<I: PinIdProvider>(_pin: Pin<I>, init_level: PinState) -> Self {
-        let mut ll = ll::LowLevelGpio::new(I::ID);
-        ll.configure_as_output_push_pull(init_level);
-        Output(ll)
-    }
-
-    #[inline]
-    pub fn port(&self) -> Port {
-        self.0.port()
-    }
-
-    #[inline]
-    pub fn offset(&self) -> usize {
-        self.0.offset()
-    }
-
-    #[inline]
-    pub fn set_high(&mut self) {
-        self.0.set_high();
-    }
-
-    #[inline]
-    pub fn set_low(&mut self) {
-        self.0.set_low();
-    }
-
-    #[inline]
-    pub fn is_set_high(&self) -> bool {
-        self.0.is_set_high()
-    }
-
-    #[inline]
-    pub fn is_set_low(&self) -> bool {
-        self.0.is_set_low()
-    }
-
-    /// Toggle pin output with dedicated HW feature.
-    #[inline]
-    pub fn toggle(&mut self) {
-        self.0.toggle();
-    }
-}
-
-impl embedded_hal::digital::ErrorType for Output {
-    type Error = Infallible;
-}
-
-impl embedded_hal::digital::OutputPin for Output {
-    fn set_low(&mut self) -> Result<(), Self::Error> {
-        self.0.set_low();
-        Ok(())
-    }
-
-    fn set_high(&mut self) -> Result<(), Self::Error> {
-        self.0.set_high();
-        Ok(())
-    }
-}
-
-impl embedded_hal::digital::StatefulOutputPin for Output {
-    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
-        Ok(self.0.is_set_high())
-    }
-
-    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
-        Ok(self.0.is_set_low())
-    }
-
-    /// Toggle pin output with dedicated HW feature.
-    fn toggle(&mut self) -> Result<(), Self::Error> {
-        self.0.toggle();
-        Ok(())
-    }
-}
-
-/// Input pin.
-///
-/// Can be created as a floating input pin or as an input pin with pull-up or pull-down.
-#[derive(Debug)]
-pub struct Input(ll::LowLevelGpio);
-
-impl Input {
-    pub fn new_floating<I: PinIdProvider>(_pin: Pin<I>) -> Self {
-        let mut ll = ll::LowLevelGpio::new(I::ID);
-        ll.configure_as_input_floating();
-        Input(ll)
-    }
-
-    pub fn new_with_pull<I: PinIdProvider>(_pin: Pin<I>, pull: Pull) -> Self {
-        let mut ll = ll::LowLevelGpio::new(I::ID);
-        ll.configure_as_input_with_pull(pull);
-        Input(ll)
-    }
-
-    #[inline]
-    pub fn id(&self) -> PinId {
-        self.0.id()
-    }
-
-    #[cfg(feature = "vor1x")]
-    #[inline]
-    pub fn enable_interrupt(&mut self, irq_cfg: crate::InterruptConfig) {
-        self.0.enable_interrupt(irq_cfg);
-    }
-
-    #[inline]
-    pub fn configure_edge_interrupt(&mut self, edge: InterruptEdge) {
-        self.0.configure_edge_interrupt(edge);
-    }
-
-    #[inline]
-    pub fn configure_level_interrupt(&mut self, edge: InterruptLevel) {
-        self.0.configure_level_interrupt(edge);
-    }
-
-    #[inline]
-    pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool) {
-        self.0.configure_delay(delay_1, delay_2);
-    }
-
-    #[inline]
-    pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
-        self.0.configure_filter_type(filter, clksel);
-    }
-
-    #[inline]
-    pub fn is_low(&self) -> bool {
-        self.0.is_low()
-    }
-
-    #[inline]
-    pub fn is_high(&self) -> bool {
-        self.0.is_high()
-    }
-}
-
-impl embedded_hal::digital::ErrorType for Input {
-    type Error = Infallible;
-}
-
-impl embedded_hal::digital::InputPin for Input {
-    fn is_low(&mut self) -> Result<bool, Self::Error> {
-        Ok(self.0.is_low())
-    }
-
-    fn is_high(&mut self) -> Result<bool, Self::Error> {
-        Ok(self.0.is_high())
-    }
-}
-
-#[derive(Debug)]
-pub enum PinMode {
-    InputFloating,
-    InputWithPull(Pull),
-    OutputPushPull,
-    OutputOpenDrain,
-}
-
-impl PinMode {
-    pub fn is_input(&self) -> bool {
-        matches!(self, PinMode::InputFloating | PinMode::InputWithPull(_))
-    }
-
-    pub fn is_output(&self) -> bool {
-        !self.is_input()
-    }
-}
-
-/// Flex pin abstraction which can be dynamically re-configured.
-///
-/// The following functions can be configured at run-time:
-///
-///  - Input Floating
-///  - Input with Pull-Up
-///  - Output Push-Pull
-///  - Output Open-Drain.
-///
-/// Flex pins are always floating input pins after construction.
-#[derive(Debug)]
-pub struct Flex {
-    ll: ll::LowLevelGpio,
-    mode: PinMode,
-}
-
-impl Flex {
-    pub fn new<I: PinIdProvider>(_pin: Pin<I>) -> Self {
-        let mut ll = ll::LowLevelGpio::new(I::ID);
-        ll.configure_as_input_floating();
-        Flex {
-            ll,
-            mode: PinMode::InputFloating,
-        }
-    }
-
-    #[inline]
-    pub fn port(&self) -> Port {
-        self.ll.port()
-    }
-
-    #[inline]
-    pub fn offset(&self) -> usize {
-        self.ll.offset()
-    }
-
-    /// Reads the input state of the pin, regardless of configured mode.
-    #[inline]
-    pub fn is_low(&self) -> bool {
-        self.ll.is_low()
-    }
-
-    /// Reads the input state of the pin, regardless of configured mode.
-    #[inline]
-    pub fn is_high(&self) -> bool {
-        self.ll.is_high()
-    }
-
-    /// If the pin is configured as an input pin, this function does nothing.
-    #[inline]
-    pub fn set_low(&mut self) {
-        if !self.mode.is_input() {
-            return;
-        }
-        self.ll.set_low();
-    }
-
-    /// If the pin is configured as an input pin, this function does nothing.
-    #[inline]
-    pub fn set_high(&mut self) {
-        if !self.mode.is_input() {
-            return;
-        }
-        self.ll.set_high();
-    }
-}
-
-impl embedded_hal::digital::ErrorType for Flex {
-    type Error = Infallible;
-}
-
-impl embedded_hal::digital::InputPin for Flex {
-    /// Reads the input state of the pin, regardless of configured mode.
-    fn is_low(&mut self) -> Result<bool, Self::Error> {
-        Ok(self.ll.is_low())
-    }
-
-    /// Reads the input state of the pin, regardless of configured mode.
-    fn is_high(&mut self) -> Result<bool, Self::Error> {
-        Ok(self.ll.is_high())
-    }
-}
-
-impl embedded_hal::digital::OutputPin for Flex {
-    /// If the pin is configured as an input pin, this function does nothing.
-    fn set_low(&mut self) -> Result<(), Self::Error> {
-        self.set_low();
-        Ok(())
-    }
-
-    /// If the pin is configured as an input pin, this function does nothing.
-    fn set_high(&mut self) -> Result<(), Self::Error> {
-        self.set_high();
-        Ok(())
-    }
-}
-
-impl embedded_hal::digital::StatefulOutputPin for Flex {
-    /// If the pin is not configured as a stateful output pin like Output Push-Pull, the result
-    /// of this function is undefined.
-    fn is_set_high(&mut self) -> Result<bool, Self::Error> {
-        Ok(self.ll.is_set_high())
-    }
-
-    /// If the pin is not configured as a stateful output pin like Output Push-Pull, the result
-    /// of this function is undefined.
-    fn is_set_low(&mut self) -> Result<bool, Self::Error> {
-        Ok(self.ll.is_set_low())
-    }
-
-    /// Toggle pin output.
-    ///
-    /// If the pin is not configured as a stateful output pin like Output Push-Pull, the result
-    /// of this function is undefined.
-    fn toggle(&mut self) -> Result<(), Self::Error> {
-        self.ll.toggle();
-        Ok(())
-    }
-}
-
-/// IO peripheral pin structure.
-///
-/// Can be used to configure pins as IO peripheral pins.
-pub struct IoPeriphPin {
-    ll: ll::LowLevelGpio,
-    fun_sel: FunSel,
-}
-
-impl IoPeriphPin {
-    pub fn new_with_pin<I: PinIdProvider>(
-        _pin: Pin<I>,
-        fun_sel: FunSel,
-        pull: Option<Pull>,
-    ) -> Self {
-        let mut ll = ll::LowLevelGpio::new(I::ID);
-        ll.configure_as_peripheral_pin(fun_sel, pull);
-        IoPeriphPin { ll, fun_sel }
-    }
-
-    pub fn new(pin_id: PinId, fun_sel: FunSel, pull: Option<Pull>) -> Self {
-        let mut ll = ll::LowLevelGpio::new(pin_id);
-        ll.configure_as_peripheral_pin(fun_sel, pull);
-        IoPeriphPin { ll, fun_sel }
-    }
-
-    pub fn port(&self) -> Port {
-        self.ll.port()
-    }
-
-    pub fn offset(&self) -> usize {
-        self.ll.offset()
-    }
-
-    pub fn fun_sel(&self) -> FunSel {
-        self.fun_sel
-    }
-}

vorago-shared-periphs/src/gpio/regs.rs

@@ -1,126 +0,0 @@
-use crate::Port;
-
-cfg_if::cfg_if! {
-    if #[cfg(feature = "vor1x")] {
-        /// PORT A base address.
-        pub const GPIO_0_BASE: usize = 0x5000_0000;
-        /// PORT B base address.
-        pub const GPIO_1_BASE: usize = 0x5000_1000;
-    } else if #[cfg(feature = "vor4x")] {
-        /// PORT A base address.
-        pub const GPIO_0_BASE: usize = 0x4001_2000;
-        /// PORT B base address.
-        pub const GPIO_1_BASE: usize = 0x4001_2400;
-        /// PORT C base address.
-        pub const GPIO_2_BASE: usize = 0x4001_2800;
-        /// PORT D base address.
-        pub const GPIO_3_BASE: usize = 0x4001_2C00;
-        /// PORT E base address.
-        pub const GPIO_4_BASE: usize = 0x4001_3000;
-        /// PORT F base address.
-        pub const GPIO_5_BASE: usize = 0x4001_3400;
-        /// PORT G base address.
-        pub const GPIO_6_BASE: usize = 0x4001_3800;
-    }
-}
-
-#[derive(derive_mmio::Mmio)]
-#[mmio(no_ctors)]
-#[repr(C)]
-pub struct Gpio {
-    #[mmio(PureRead)]
-    data_in: u32,
-    #[mmio(PureRead)]
-    data_in_raw: u32,
-    data_out: u32,
-    data_out_raw: u32,
-    #[mmio(Write)]
-    set_out: u32,
-    #[mmio(Write)]
-    clr_out: u32,
-    #[mmio(Write)]
-    tog_out: u32,
-    data_mask: u32,
-    /// Direction bits. 1 for output, 0 for input.
-    dir: u32,
-    pulse: u32,
-    pulsebase: u32,
-    delay1: u32,
-    delay2: u32,
-    irq_sen: u32,
-    irq_edge: u32,
-    irq_evt: u32,
-    irq_enable: u32,
-    /// Raw interrupt status. This register is not latched and may not indicated edge sensitive
-    /// events.
-    #[mmio(PureRead)]
-    irq_raw: u32,
-    /// Read-only register which shows enabled and active interrupts. Called IRQ_end by Vorago.
-    #[mmio(PureRead)]
-    irq_status: u32,
-    #[mmio(PureRead)]
-    edge_status: u32,
-
-    #[cfg(feature = "vor1x")]
-    _reserved: [u32; 0x3eb],
-    #[cfg(feature = "vor4x")]
-    _reserved: [u32; 0xeb],
-
-    /// Peripheral ID. Vorago 1x reset value: 0x0040_07e1. Vorago 4x reset value: 0x0210_07E9.
-    perid: u32,
-}
-
-cfg_if::cfg_if! {
-    if #[cfg(feature = "vor1x")] {
-        static_assertions::const_assert_eq!(core::mem::size_of::<Gpio>(), 0x1000);
-    } else if #[cfg(feature = "vor4x")] {
-        static_assertions::const_assert_eq!(core::mem::size_of::<Gpio>(), 0x400);
-    }
-}
-
-impl Gpio {
-    const fn new_mmio_at(base: usize) -> MmioGpio<'static> {
-        MmioGpio {
-            ptr: base as *mut _,
-            phantom: core::marker::PhantomData,
-        }
-    }
-
-    pub const fn new_mmio(port: Port) -> MmioGpio<'static> {
-        match port {
-            Port::A => Self::new_mmio_at(GPIO_0_BASE),
-            Port::B => Self::new_mmio_at(GPIO_1_BASE),
-            #[cfg(feature = "vor4x")]
-            Port::C => Self::new_mmio_at(GPIO_2_BASE),
-            #[cfg(feature = "vor4x")]
-            Port::D => Self::new_mmio_at(GPIO_3_BASE),
-            #[cfg(feature = "vor4x")]
-            Port::E => Self::new_mmio_at(GPIO_4_BASE),
-            #[cfg(feature = "vor4x")]
-            Port::F => Self::new_mmio_at(GPIO_5_BASE),
-            #[cfg(feature = "vor4x")]
-            Port::G => Self::new_mmio_at(GPIO_6_BASE),
-        }
-    }
-}
-
-impl MmioGpio<'_> {
-    pub fn port(&self) -> Port {
-        match unsafe { self.ptr() } as usize {
-            GPIO_0_BASE => Port::A,
-            GPIO_1_BASE => Port::B,
-            #[cfg(feature = "vor4x")]
-            GPIO_2_BASE => Port::C,
-            #[cfg(feature = "vor4x")]
-            GPIO_3_BASE => Port::D,
-            #[cfg(feature = "vor4x")]
-            GPIO_4_BASE => Port::E,
-            #[cfg(feature = "vor4x")]
-            GPIO_5_BASE => Port::F,
-            #[cfg(feature = "vor4x")]
-            GPIO_6_BASE => Port::G,
-            // Constructors were disabled, so this should really not happen.
-            _ => panic!("unexpected base address of GPIO register block"),
-        }
-    }
-}

vorago-shared-periphs/src/ioconfig/mod.rs

@@ -1,3 +0,0 @@
-pub use regs::{FilterClkSel, FilterType};
-
-pub mod regs;

vorago-shared-periphs/src/ioconfig/regs.rs

@@ -1,177 +0,0 @@
-use core::marker::PhantomData;
-
-use crate::{NUM_PORT_A, NUM_PORT_B, gpio::PinId};
-#[cfg(feature = "vor4x")]
-use crate::{NUM_PORT_DEFAULT, NUM_PORT_G};
-
-#[cfg(feature = "vor1x")]
-pub const BASE_ADDR: usize = 0x4000_2000;
-#[cfg(feature = "vor4x")]
-pub const BASE_ADDR: usize = 0x4001_1000;
-
-#[bitbybit::bitenum(u3)]
-pub enum FilterType {
-    SysClk = 0,
-    DirectInput = 1,
-    FilterOneCycle = 2,
-    FilterTwoCycles = 3,
-    FilterThreeCycles = 4,
-    FilterFourCycles = 5,
-}
-
-#[derive(Debug, PartialEq, Eq)]
-#[bitbybit::bitenum(u3, exhaustive = true)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum FilterClkSel {
-    SysClk = 0,
-    Clk1 = 1,
-    Clk2 = 2,
-    Clk3 = 3,
-    Clk4 = 4,
-    Clk5 = 5,
-    Clk6 = 6,
-    Clk7 = 7,
-}
-
-#[derive(Debug, PartialEq, Eq)]
-#[bitbybit::bitenum(u1, exhaustive = true)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Pull {
-    Up = 0,
-    Down = 1,
-}
-
-#[derive(Debug, Eq, PartialEq)]
-#[bitbybit::bitenum(u2, exhaustive = true)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum FunSel {
-    Sel0 = 0b00,
-    Sel1 = 0b01,
-    Sel2 = 0b10,
-    Sel3 = 0b11,
-}
-
-#[bitbybit::bitfield(u32)]
-pub struct Config {
-    #[bit(16, rw)]
-    io_disable: bool,
-    #[bits(13..=14, rw)]
-    funsel: FunSel,
-    #[bit(12, rw)]
-    pull_when_output_active: bool,
-    #[bit(11, rw)]
-    pull_enable: bool,
-    #[bit(10, rw)]
-    pull_dir: Pull,
-    #[bit(9, rw)]
-    invert_output: bool,
-    #[bit(8, rw)]
-    open_drain: bool,
-    /// IEWO bit. Allows monitoring of output values.
-    #[bit(7, rw)]
-    input_enable_when_output: bool,
-    #[bit(6, rw)]
-    invert_input: bool,
-    #[bits(3..=5, rw)]
-    filter_clk_sel: FilterClkSel,
-    #[bits(0..=2, rw)]
-    filter_type: Option<FilterType>,
-}
-
-#[derive(derive_mmio::Mmio)]
-#[mmio(no_ctors)]
-#[repr(C)]
-pub struct IoConfig {
-    port_a: [Config; NUM_PORT_A],
-    port_b: [Config; NUM_PORT_B],
-    #[cfg(feature = "vor4x")]
-    port_c: [Config; NUM_PORT_DEFAULT],
-    #[cfg(feature = "vor4x")]
-    port_d: [Config; NUM_PORT_DEFAULT],
-    #[cfg(feature = "vor4x")]
-    port_e: [Config; NUM_PORT_DEFAULT],
-    #[cfg(feature = "vor4x")]
-    port_f: [Config; NUM_PORT_DEFAULT],
-    #[cfg(feature = "vor4x")]
-    port_g: [Config; NUM_PORT_G],
-    #[cfg(feature = "vor4x")]
-    _reserved0: [u32; 0x8],
-    #[cfg(feature = "vor4x")]
-    #[mmio(PureRead)]
-    clk_div_0: u32,
-    #[cfg(feature = "vor4x")]
-    clk_div_1: u32,
-    #[cfg(feature = "vor4x")]
-    clk_div_2: u32,
-    #[cfg(feature = "vor4x")]
-    clk_div_3: u32,
-    #[cfg(feature = "vor4x")]
-    clk_div_4: u32,
-    #[cfg(feature = "vor4x")]
-    clk_div_5: u32,
-    #[cfg(feature = "vor4x")]
-    clk_div_6: u32,
-    #[cfg(feature = "vor4x")]
-    clk_div_7: u32,
-    #[cfg(feature = "vor4x")]
-    _reserved1: [u32; 0x387],
-    #[cfg(feature = "vor1x")]
-    _reserved1: [u32; 0x3c7],
-    #[mmio(PureRead)]
-    /// Reset value: 0x0282_07E9 for Vorago 4x, and 0x0182_07E1 for Vorago 1x
-    perid: u32,
-}
-
-static_assertions::const_assert_eq!(core::mem::size_of::<IoConfig>(), 0x1000);
-
-impl IoConfig {
-    pub const fn new_mmio() -> MmioIoConfig<'static> {
-        MmioIoConfig {
-            ptr: BASE_ADDR as *mut _,
-            phantom: PhantomData,
-        }
-    }
-}
-
-impl MmioIoConfig<'_> {
-    pub fn read_pin_config(&self, id: PinId) -> Config {
-        let offset = id.offset();
-        match id.port() {
-            crate::Port::A => unsafe { self.read_port_a_unchecked(offset) },
-            crate::Port::B => unsafe { self.read_port_b_unchecked(offset) },
-            #[cfg(feature = "vor4x")]
-            crate::Port::C => unsafe { self.read_port_c_unchecked(offset) },
-            #[cfg(feature = "vor4x")]
-            crate::Port::D => unsafe { self.read_port_d_unchecked(offset) },
-            #[cfg(feature = "vor4x")]
-            crate::Port::E => unsafe { self.read_port_e_unchecked(offset) },
-            #[cfg(feature = "vor4x")]
-            crate::Port::F => unsafe { self.read_port_f_unchecked(offset) },
-            #[cfg(feature = "vor4x")]
-            crate::Port::G => unsafe { self.read_port_g_unchecked(offset) },
-        }
-    }
-
-    pub fn modify_pin_config<F: FnOnce(Config) -> Config>(&mut self, id: PinId, f: F) {
-        let config = self.read_pin_config(id);
-        self.write_pin_config(id, f(config))
-    }
-
-    pub fn write_pin_config(&mut self, id: PinId, config: Config) {
-        let offset = id.offset();
-        match id.port() {
-            crate::Port::A => unsafe { self.write_port_a_unchecked(offset, config) },
-            crate::Port::B => unsafe { self.write_port_b_unchecked(offset, config) },
-            #[cfg(feature = "vor4x")]
-            crate::Port::C => unsafe { self.write_port_c_unchecked(offset, config) },
-            #[cfg(feature = "vor4x")]
-            crate::Port::D => unsafe { self.write_port_d_unchecked(offset, config) },
-            #[cfg(feature = "vor4x")]
-            crate::Port::E => unsafe { self.write_port_e_unchecked(offset, config) },
-            #[cfg(feature = "vor4x")]
-            crate::Port::F => unsafe { self.write_port_f_unchecked(offset, config) },
-            #[cfg(feature = "vor4x")]
-            crate::Port::G => unsafe { self.write_port_g_unchecked(offset, config) },
-        }
-    }
-}

vorago-shared-periphs/src/lib.rs

@@ -1,152 +0,0 @@
-#![no_std]
-pub mod gpio;
-pub mod ioconfig;
-pub mod pins;
-pub mod sysconfig;
-pub mod time;
-pub mod uart;
-
-pub use sysconfig::{disable_peripheral_clock, enable_peripheral_clock};
-
-#[cfg(not(feature = "_family-selected"))]
-compile_error!("no Vorago CPU family was select. Choices: vor1x or vor4x");
-
-pub use ioconfig::regs::FunSel;
-
-#[cfg(feature = "vor1x")]
-#[derive(Debug, Copy, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum PeripheralSelect {
-    PortA = 0,
-    PortB = 1,
-    Spi0 = 4,
-    Spi1 = 5,
-    Spi2 = 6,
-    Uart0 = 8,
-    Uart1 = 9,
-    I2c0 = 16,
-    I2c1 = 17,
-    Irqsel = 21,
-    Ioconfig = 22,
-    Utility = 23,
-    Gpio = 24,
-}
-
-cfg_if::cfg_if! {
-    if #[cfg(feature = "vor1x")] {
-        /// Number of GPIO ports and IOCONFIG registers for PORT A
-        pub const NUM_PORT_A: usize = 32;
-        /// Number of GPIO ports and IOCONFIG registers for PORT B
-        pub const NUM_PORT_B: usize = 24;
-    } else if #[cfg(feature = "vor4x")] {
-        /// Number of GPIO ports and IOCONFIG registers for PORT C to Port F
-        pub const NUM_PORT_DEFAULT: usize = 16;
-        /// Number of GPIO ports and IOCONFIG registers for PORT A
-        pub const NUM_PORT_A: usize = NUM_PORT_DEFAULT;
-        /// Number of GPIO ports and IOCONFIG registers for PORT B
-        pub const NUM_PORT_B: usize = NUM_PORT_DEFAULT;
-        /// Number of GPIO ports and IOCONFIG registers for PORT G
-        pub const NUM_PORT_G: usize = 8;
-    }
-}
-
-/// GPIO port enumeration.
-#[derive(Debug, Clone, Copy, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Port {
-    A = 0,
-    B = 1,
-    #[cfg(feature = "vor4x")]
-    C = 2,
-    #[cfg(feature = "vor4x")]
-    D = 3,
-    #[cfg(feature = "vor4x")]
-    E = 4,
-    #[cfg(feature = "vor4x")]
-    F = 5,
-    #[cfg(feature = "vor4x")]
-    G = 6,
-}
-
-impl Port {
-    pub const fn max_offset(&self) -> usize {
-        match self {
-            Port::A => NUM_PORT_A,
-            Port::B => NUM_PORT_B,
-            #[cfg(feature = "vor4x")]
-            Port::C | Port::D | Port::E | Port::F => NUM_PORT_DEFAULT,
-            #[cfg(feature = "vor4x")]
-            Port::G => NUM_PORT_G,
-        }
-    }
-
-    /// Unsafely steal the GPIO peripheral block for the given port.
-    ///
-    /// # Safety
-    ///
-    /// Circumvents ownership and safety guarantees by the HAL.
-    pub unsafe fn steal_gpio(&self) -> gpio::regs::MmioGpio<'static> {
-        gpio::regs::Gpio::new_mmio(*self)
-    }
-}
-
-#[derive(Debug, thiserror::Error)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[error("invalid GPIO offset {offset} for port {port:?}")]
-pub struct InvalidOffsetError {
-    offset: usize,
-    port: Port,
-}
-
-/// Generic interrupt config which can be used to specify whether the HAL driver will
-/// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the
-/// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might want to
-/// perform those steps themselves.
-#[cfg(feature = "vor1x")]
-#[derive(Debug, PartialEq, Eq, Clone, Copy)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct InterruptConfig {
-    /// Interrupt target vector. Should always be set, might be required for disabling IRQs
-    pub id: va108xx::Interrupt,
-    /// Specfiy whether IRQ should be routed to an IRQ vector using the IRQSEL peripheral.
-    pub route: bool,
-    /// Specify whether the IRQ is unmasked in the Cortex-M NVIC. If an interrupt is used for
-    /// multiple purposes, the user can enable the interrupts themselves.
-    pub enable_in_nvic: bool,
-}
-
-#[cfg(feature = "vor1x")]
-impl InterruptConfig {
-    pub fn new(id: va108xx::Interrupt, route: bool, enable_in_nvic: bool) -> Self {
-        InterruptConfig {
-            id,
-            route,
-            enable_in_nvic,
-        }
-    }
-}
-
-/// Enable a specific interrupt using the NVIC peripheral.
-///
-/// # Safety
-///
-/// This function is `unsafe` because it can break mask-based critical sections.
-#[cfg(feature = "vor1x")]
-#[inline]
-pub unsafe fn enable_nvic_interrupt(irq: va108xx::Interrupt) {
-    unsafe {
-        cortex_m::peripheral::NVIC::unmask(irq);
-    }
-}
-
-/// Disable a specific interrupt using the NVIC peripheral.
-#[cfg(feature = "vor1x")]
-#[inline]
-pub fn disable_nvic_interrupt(irq: va108xx::Interrupt) {
-    cortex_m::peripheral::NVIC::mask(irq);
-}
-
-#[allow(dead_code)]
-pub(crate) mod sealed {
-    pub trait Sealed {}
-}

vorago-shared-periphs/src/pins.rs

@@ -1,236 +0,0 @@
-use crate::sysconfig::reset_peripheral_for_cycles;
-
-pub use crate::gpio::{Pin, PinId, PinIdProvider, Port};
-
-use crate::PeripheralSelect;
-use crate::sealed::Sealed;
-
-pub trait PinMarker: Sealed {
-    const ID: PinId;
-}
-
-macro_rules! pin_id {
-    ($Id:ident, $Port:path, $num:literal) => {
-        // Need paste macro to use ident in doc attribute
-        paste::paste! {
-            #[doc = "Pin ID representing pin " $Id]
-            #[derive(Debug)]
-            pub enum $Id {}
-
-            impl $crate::sealed::Sealed for $Id {}
-            impl PinIdProvider for $Id {
-                const ID: PinId = PinId::new_unchecked($Port, $num);
-            }
-
-            impl PinMarker for Pin<$Id> {
-                const ID: PinId = $Id::ID;
-            }
-        }
-    };
-}
-
-impl<I: PinIdProvider + Sealed> Sealed for Pin<I> {}
-
-pin_id!(Pa0, Port::A, 0);
-pin_id!(Pa1, Port::A, 1);
-pin_id!(Pa2, Port::A, 2);
-pin_id!(Pa3, Port::A, 3);
-pin_id!(Pa4, Port::A, 4);
-pin_id!(Pa5, Port::A, 5);
-pin_id!(Pa6, Port::A, 6);
-pin_id!(Pa7, Port::A, 7);
-pin_id!(Pa8, Port::A, 8);
-pin_id!(Pa9, Port::A, 9);
-pin_id!(Pa10, Port::A, 10);
-pin_id!(Pa11, Port::A, 11);
-pin_id!(Pa12, Port::A, 12);
-pin_id!(Pa13, Port::A, 13);
-pin_id!(Pa14, Port::A, 14);
-pin_id!(Pa15, Port::A, 15);
-pin_id!(Pa16, Port::A, 16);
-pin_id!(Pa17, Port::A, 17);
-pin_id!(Pa18, Port::A, 18);
-pin_id!(Pa19, Port::A, 19);
-pin_id!(Pa20, Port::A, 20);
-pin_id!(Pa21, Port::A, 21);
-pin_id!(Pa22, Port::A, 22);
-pin_id!(Pa23, Port::A, 23);
-pin_id!(Pa24, Port::A, 24);
-pin_id!(Pa25, Port::A, 25);
-pin_id!(Pa26, Port::A, 26);
-pin_id!(Pa27, Port::A, 27);
-pin_id!(Pa28, Port::A, 28);
-pin_id!(Pa29, Port::A, 29);
-pin_id!(Pa30, Port::A, 30);
-pin_id!(Pa31, Port::A, 31);
-
-pin_id!(Pb0, Port::B, 0);
-pin_id!(Pb1, Port::B, 1);
-pin_id!(Pb2, Port::B, 2);
-pin_id!(Pb3, Port::B, 3);
-pin_id!(Pb4, Port::B, 4);
-pin_id!(Pb5, Port::B, 5);
-pin_id!(Pb6, Port::B, 6);
-pin_id!(Pb7, Port::B, 7);
-pin_id!(Pb8, Port::B, 8);
-pin_id!(Pb9, Port::B, 9);
-pin_id!(Pb10, Port::B, 10);
-pin_id!(Pb11, Port::B, 11);
-pin_id!(Pb12, Port::B, 12);
-pin_id!(Pb13, Port::B, 13);
-pin_id!(Pb14, Port::B, 14);
-pin_id!(Pb15, Port::B, 15);
-pin_id!(Pb16, Port::B, 16);
-pin_id!(Pb17, Port::B, 17);
-pin_id!(Pb18, Port::B, 18);
-pin_id!(Pb19, Port::B, 19);
-pin_id!(Pb20, Port::B, 20);
-pin_id!(Pb21, Port::B, 21);
-pin_id!(Pb22, Port::B, 22);
-pin_id!(Pb23, Port::B, 23);
-
-pub struct PinsA {
-    pub pa0: Pin<Pa0>,
-    pub pa1: Pin<Pa1>,
-    pub pa2: Pin<Pa2>,
-    pub pa3: Pin<Pa3>,
-    pub pa4: Pin<Pa4>,
-    pub pa5: Pin<Pa5>,
-    pub pa6: Pin<Pa6>,
-    pub pa7: Pin<Pa7>,
-    pub pa8: Pin<Pa8>,
-    pub pa9: Pin<Pa9>,
-    pub pa10: Pin<Pa10>,
-    pub pa11: Pin<Pa11>,
-    pub pa12: Pin<Pa12>,
-    pub pa13: Pin<Pa13>,
-    pub pa14: Pin<Pa14>,
-    pub pa15: Pin<Pa15>,
-    pub pa16: Pin<Pa16>,
-    pub pa17: Pin<Pa17>,
-    pub pa18: Pin<Pa18>,
-    pub pa19: Pin<Pa19>,
-    pub pa20: Pin<Pa20>,
-    pub pa21: Pin<Pa21>,
-    pub pa22: Pin<Pa22>,
-    pub pa23: Pin<Pa23>,
-    pub pa24: Pin<Pa24>,
-    pub pa25: Pin<Pa25>,
-    pub pa26: Pin<Pa26>,
-    pub pa27: Pin<Pa27>,
-    pub pa28: Pin<Pa28>,
-    pub pa29: Pin<Pa29>,
-    pub pa30: Pin<Pa30>,
-    pub pa31: Pin<Pa31>,
-}
-
-impl PinsA {
-    pub fn new(_port_a: va108xx::Porta) -> Self {
-        let syscfg = unsafe { va108xx::Sysconfig::steal() };
-        reset_peripheral_for_cycles(PeripheralSelect::PortA, 2);
-        syscfg.peripheral_clk_enable().modify(|_, w| {
-            w.porta().set_bit();
-            w.gpio().set_bit();
-            w.ioconfig().set_bit()
-        });
-        Self {
-            pa0: Pin::__new(),
-            pa1: Pin::__new(),
-            pa2: Pin::__new(),
-            pa3: Pin::__new(),
-            pa4: Pin::__new(),
-            pa5: Pin::__new(),
-            pa6: Pin::__new(),
-            pa7: Pin::__new(),
-            pa8: Pin::__new(),
-            pa9: Pin::__new(),
-            pa10: Pin::__new(),
-            pa11: Pin::__new(),
-            pa12: Pin::__new(),
-            pa13: Pin::__new(),
-            pa14: Pin::__new(),
-            pa15: Pin::__new(),
-            pa16: Pin::__new(),
-            pa17: Pin::__new(),
-            pa18: Pin::__new(),
-            pa19: Pin::__new(),
-            pa20: Pin::__new(),
-            pa21: Pin::__new(),
-            pa22: Pin::__new(),
-            pa23: Pin::__new(),
-            pa24: Pin::__new(),
-            pa25: Pin::__new(),
-            pa26: Pin::__new(),
-            pa27: Pin::__new(),
-            pa28: Pin::__new(),
-            pa29: Pin::__new(),
-            pa30: Pin::__new(),
-            pa31: Pin::__new(),
-        }
-    }
-}
-
-pub struct PinsB {
-    pub pb0: Pin<Pb0>,
-    pub pb1: Pin<Pb1>,
-    pub pb2: Pin<Pb2>,
-    pub pb3: Pin<Pb3>,
-    pub pb4: Pin<Pb4>,
-    pub pb5: Pin<Pb5>,
-    pub pb6: Pin<Pb6>,
-    pub pb7: Pin<Pb7>,
-    pub pb8: Pin<Pb8>,
-    pub pb9: Pin<Pb9>,
-    pub pb10: Pin<Pb10>,
-    pub pb11: Pin<Pb11>,
-    pub pb12: Pin<Pb12>,
-    pub pb13: Pin<Pb13>,
-    pub pb14: Pin<Pb14>,
-    pub pb15: Pin<Pb15>,
-    pub pb16: Pin<Pb16>,
-    pub pb17: Pin<Pb17>,
-    pub pb18: Pin<Pb18>,
-    pub pb19: Pin<Pb19>,
-    pub pb20: Pin<Pb20>,
-    pub pb21: Pin<Pb21>,
-    pub pb22: Pin<Pb22>,
-    pub pb23: Pin<Pb23>,
-}
-
-impl PinsB {
-    pub fn new(_port_b: va108xx::Portb) -> Self {
-        let syscfg = unsafe { va108xx::Sysconfig::steal() };
-        reset_peripheral_for_cycles(PeripheralSelect::PortB, 2);
-        syscfg.peripheral_clk_enable().modify(|_, w| {
-            w.portb().set_bit();
-            w.gpio().set_bit();
-            w.ioconfig().set_bit()
-        });
-        Self {
-            pb0: Pin::__new(),
-            pb1: Pin::__new(),
-            pb2: Pin::__new(),
-            pb3: Pin::__new(),
-            pb4: Pin::__new(),
-            pb5: Pin::__new(),
-            pb6: Pin::__new(),
-            pb7: Pin::__new(),
-            pb8: Pin::__new(),
-            pb9: Pin::__new(),
-            pb10: Pin::__new(),
-            pb11: Pin::__new(),
-            pb12: Pin::__new(),
-            pb13: Pin::__new(),
-            pb14: Pin::__new(),
-            pb15: Pin::__new(),
-            pb16: Pin::__new(),
-            pb17: Pin::__new(),
-            pb18: Pin::__new(),
-            pb19: Pin::__new(),
-            pb20: Pin::__new(),
-            pb21: Pin::__new(),
-            pb22: Pin::__new(),
-            pb23: Pin::__new(),
-        }
-    }
-}

vorago-shared-periphs/src/sysconfig.rs

@@ -1,43 +0,0 @@
-#[cfg(feature = "vor1x")]
-#[inline]
-pub fn enable_peripheral_clock(clock: crate::PeripheralSelect) {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
-    syscfg
-        .peripheral_clk_enable()
-        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
-}
-
-#[cfg(feature = "vor1x")]
-#[inline]
-pub fn disable_peripheral_clock(clock: crate::PeripheralSelect) {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
-    syscfg
-        .peripheral_clk_enable()
-        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) });
-}
-
-#[cfg(feature = "vor1x")]
-#[inline]
-pub fn assert_peripheral_reset(periph_sel: crate::PeripheralSelect) {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
-    syscfg
-        .peripheral_reset()
-        .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << periph_sel as u8)) });
-}
-
-#[cfg(feature = "vor1x")]
-#[inline]
-pub fn deassert_peripheral_reset(periph_sel: crate::PeripheralSelect) {
-    let syscfg = unsafe { va108xx::Sysconfig::steal() };
-    syscfg
-        .peripheral_reset()
-        .modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
-}
-
-#[cfg(feature = "vor1x")]
-#[inline]
-pub fn reset_peripheral_for_cycles(periph_sel: crate::PeripheralSelect, cycles: u32) {
-    assert_peripheral_reset(periph_sel);
-    cortex_m::asm::delay(cycles);
-    deassert_peripheral_reset(periph_sel);
-}

vorago-shared-periphs/src/time.rs

@@ -1,26 +0,0 @@
-//! Time units
-
-// Frequency based
-
-/// Hertz
-pub type Hertz = fugit::HertzU32;
-
-/// KiloHertz
-pub type KiloHertz = fugit::KilohertzU32;
-
-/// MegaHertz
-pub type MegaHertz = fugit::MegahertzU32;
-
-// Period based
-
-/// Seconds
-pub type Seconds = fugit::SecsDurationU32;
-
-/// Milliseconds
-pub type Milliseconds = fugit::MillisDurationU32;
-
-/// Microseconds
-pub type Microseconds = fugit::MicrosDurationU32;
-
-/// Nanoseconds
-pub type Nanoseconds = fugit::NanosDurationU32;

vorago-shared-periphs/src/uart/pins_vor1x.rs

@@ -1,112 +0,0 @@
-// UART A pins
-
-use crate::{
-    FunSel,
-    pins::{
-        Pa2, Pa3, Pa8, Pa9, Pa16, Pa17, Pa18, Pa19, Pa26, Pa27, Pa30, Pa31, Pb6, Pb7, Pb8, Pb9,
-        Pb18, Pb19, Pb20, Pb21, Pb22, Pb23, Pin,
-    },
-};
-
-use super::{Bank, RxPin, TxPin};
-
-impl TxPin for Pin<Pa9> {
-    const BANK: Bank = Bank::Uart0;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-impl RxPin for Pin<Pa8> {
-    const BANK: Bank = Bank::Uart0;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-
-impl TxPin for Pin<Pa17> {
-    const BANK: Bank = Bank::Uart0;
-    const FUN_SEL: FunSel = FunSel::Sel3;
-}
-impl RxPin for Pin<Pa16> {
-    const BANK: Bank = Bank::Uart0;
-    const FUN_SEL: FunSel = FunSel::Sel3;
-}
-
-impl TxPin for Pin<Pa31> {
-    const BANK: Bank = Bank::Uart0;
-    const FUN_SEL: FunSel = FunSel::Sel3;
-}
-impl RxPin for Pin<Pa30> {
-    const BANK: Bank = Bank::Uart0;
-    const FUN_SEL: FunSel = FunSel::Sel3;
-}
-
-impl TxPin for Pin<Pb9> {
-    const BANK: Bank = Bank::Uart0;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-impl RxPin for Pin<Pb8> {
-    const BANK: Bank = Bank::Uart0;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-
-impl TxPin for Pin<Pb23> {
-    const BANK: Bank = Bank::Uart0;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-impl RxPin for Pin<Pb22> {
-    const BANK: Bank = Bank::Uart0;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-
-// UART B pins
-
-impl TxPin for Pin<Pa3> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-impl RxPin for Pin<Pa2> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-
-impl TxPin for Pin<Pa19> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel3;
-}
-impl RxPin for Pin<Pa18> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel3;
-}
-
-impl TxPin for Pin<Pa27> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel3;
-}
-impl RxPin for Pin<Pa26> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel3;
-}
-
-impl TxPin for Pin<Pb7> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-impl RxPin for Pin<Pb6> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-
-impl TxPin for Pin<Pb19> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-impl RxPin for Pin<Pb18> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel2;
-}
-
-impl TxPin for Pin<Pb21> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}
-impl RxPin for Pin<Pb20> {
-    const BANK: Bank = Bank::Uart1;
-    const FUN_SEL: FunSel = FunSel::Sel1;
-}

vorago-shared-periphs/src/uart/regs.rs

@@ -1,303 +0,0 @@
-use core::marker::PhantomData;
-
-use arbitrary_int::{u5, u6, u18};
-
-#[derive(Debug, PartialEq, Eq, Clone, Copy)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Bank {
-    Uart0 = 0,
-    Uart1 = 1,
-    #[cfg(feature = "vor4x")]
-    Uart2 = 2,
-}
-
-impl Bank {
-    /// Unsafely steal the GPIO peripheral block for the given port.
-    ///
-    /// # Safety
-    ///
-    /// Circumvents ownership and safety guarantees by the HAL.
-    pub unsafe fn steal_regs(&self) -> MmioUart<'static> {
-        Uart::new_mmio(*self)
-    }
-}
-cfg_if::cfg_if! {
-    if #[cfg(feature = "vor1x")] {
-        /// UART A base address
-        const BASE_ADDR_0: usize = 0x4004_0000;
-        /// UART B base address
-        const BASE_ADDR_1: usize = 0x4004_1000;
-    } else if #[cfg(feature = "vor4x")] {
-        /// UART 0 base address
-        const BASE_ADDR_0: usize = 0x4002_4000;
-        /// UART 1 base address
-        const BASE_ADDR_1: usize = 0x4002_5000;
-        /// UART 2 base address
-        const BASE_ADDR_2: usize = 0x4001_7000;
-    }
-}
-
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
-pub struct Data {
-    #[bit(15, rw)]
-    dparity: bool,
-    #[bits(0..=7, rw)]
-    value: u8,
-}
-
-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
-pub struct Enable {
-    #[bit(1, rw)]
-    tx: bool,
-    #[bit(0, rw)]
-    rx: bool,
-}
-
-#[bitbybit::bitenum(u1, exhaustive = true)]
-#[derive(Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Stopbits {
-    One = 0,
-    Two = 1,
-}
-
-#[bitbybit::bitenum(u2, exhaustive = true)]
-#[derive(Debug, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum WordSize {
-    Five = 0b00,
-    Six = 0b01,
-    Seven = 0b10,
-    Eight = 0b11,
-}
-
-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
-pub struct Control {
-    #[bit(11, rw)]
-    baud8: bool,
-    #[bit(10, rw)]
-    auto_rts: bool,
-    #[bit(9, rw)]
-    def_rts: bool,
-    #[bit(8, rw)]
-    auto_cts: bool,
-    #[bit(7, rw)]
-    loopback_block: bool,
-    #[bit(6, rw)]
-    loopback: bool,
-    #[bits(4..=5, rw)]
-    wordsize: WordSize,
-    #[bit(3, rw)]
-    stopbits: Stopbits,
-    #[bit(2, rw)]
-    parity_manual: bool,
-    #[bit(1, rw)]
-    parity_even: bool,
-    #[bit(0, rw)]
-    parity_enable: bool,
-}
-
-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
-pub struct ClkScale {
-    #[bits(6..=23, rw)]
-    int: u18,
-    #[bits(0..=5, rw)]
-    frac: u6,
-}
-
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
-pub struct RxStatus {
-    #[bit(15, r)]
-    rx_rtsn: bool,
-    #[bit(9, r)]
-    rx_addr9: bool,
-    #[bit(8, r)]
-    busy_break: bool,
-    #[bit(7, r)]
-    break_error: bool,
-    #[bit(6, r)]
-    parity_error: bool,
-    #[bit(5, r)]
-    framing_error: bool,
-    #[bit(4, r)]
-    overrun_error: bool,
-    #[bit(3, r)]
-    timeout: bool,
-    #[bit(2, r)]
-    busy: bool,
-    #[bit(1, r)]
-    not_full: bool,
-    #[bit(0, r)]
-    data_available: bool,
-}
-
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
-pub struct TxStatus {
-    #[bit(15, r)]
-    tx_ctsn: bool,
-    #[bit(3, r)]
-    wr_lost: bool,
-    #[bit(2, r)]
-    tx_busy: bool,
-    #[bit(1, r)]
-    write_busy: bool,
-    /// There is space in the FIFO to write data.
-    #[bit(0, r)]
-    ready: bool,
-}
-
-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
-pub struct FifoClear {
-    #[bit(1, w)]
-    tx: bool,
-    #[bit(0, w)]
-    rx: bool,
-}
-
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
-pub struct InterruptControl {
-    /// Generate an interrrupt when the RX FIFO is at least half-full (FIFO count >= trigger level)
-    #[bit(0, rw)]
-    rx: bool,
-    /// Interrupts for status conditions (overrun, framing, parity and break)
-    #[bit(1, rw)]
-    rx_status: bool,
-    /// Interrupt on timeout conditions.
-    #[bit(2, rw)]
-    rx_timeout: bool,
-
-    /// Generates an interrupt when the TX FIFO is at least half-empty (FIFO count < trigger level)
-    #[bit(4, rw)]
-    tx: bool,
-    /// Generates an interrupt on TX FIFO overflow.
-    #[bit(5, rw)]
-    tx_status: bool,
-    /// Generates an interrupt when the transmit FIFO is empty and TXBUSY is 0.
-    #[bit(6, rw)]
-    tx_empty: bool,
-    #[bit(7, rw)]
-    tx_cts: bool,
-}
-
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
-pub struct InterruptStatus {
-    /// Generate an interrrupt when the RX FIFO is at least half-full (FIFO count >= trigger level)
-    #[bit(0, r)]
-    rx: bool,
-    /// Interrupts for status conditions (overrun, framing, parity and break)
-    #[bit(1, r)]
-    rx_status: bool,
-    /// Interrupt on timeout conditions.
-    #[bit(2, r)]
-    rx_timeout: bool,
-
-    /// Generates an interrupt when the TX FIFO is at least half-empty (FIFO count < trigger level)
-    #[bit(4, r)]
-    tx: bool,
-    /// Generates an interrupt on TX FIFO overflow.
-    #[bit(5, r)]
-    tx_status: bool,
-    /// Generates an interrupt when the transmit FIFO is empty and TXBUSY is 0.
-    #[bit(6, r)]
-    tx_empty: bool,
-    #[bit(7, r)]
-    tx_cts: bool,
-}
-
-/// As specified in the VA416x0 Programmers Guide, only the RX overflow bit can be cleared.
-#[bitbybit::bitfield(u32, default = 0x0)]
-#[derive(Debug)]
-pub struct InterruptClear {
-    #[bit(1, w)]
-    rx_overrun: bool,
-    /// Not sure if this does anything, the programmer guides are not consistent on this..
-    #[bit(5, w)]
-    tx_overrun: bool,
-}
-
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
-pub struct FifoTrigger {
-    #[bits(0..=4, rw)]
-    level: u5,
-}
-
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
-pub struct State {
-    #[bits(0..=7, r)]
-    rx_state: u8,
-    /// Data count.
-    #[bits(8..=12, r)]
-    rx_fifo: u5,
-    #[bits(16..=23, r)]
-    tx_state: u8,
-    /// Data count.
-    #[bits(24..=28, r)]
-    tx_fifo: u5,
-}
-
-#[derive(derive_mmio::Mmio)]
-#[mmio(no_ctors)]
-#[repr(C)]
-pub struct Uart {
-    data: Data,
-    enable: Enable,
-    ctrl: Control,
-    clkscale: ClkScale,
-    #[mmio(PureRead)]
-    rx_status: RxStatus,
-    #[mmio(PureRead)]
-    tx_status: TxStatus,
-    #[mmio(Write)]
-    fifo_clr: FifoClear,
-    #[mmio(Write)]
-    txbreak: u32,
-    addr9: u32,
-    addr9mask: u32,
-    irq_enabled: InterruptControl,
-    #[mmio(PureRead)]
-    irq_raw: InterruptStatus,
-    #[mmio(PureRead)]
-    irq_status: InterruptStatus,
-    #[mmio(Write)]
-    irq_clr: InterruptClear,
-    rx_fifo_trigger: FifoTrigger,
-    tx_fifo_trigger: FifoTrigger,
-    rx_fifo_rts_trigger: u32,
-    #[mmio(PureRead)]
-    state: State,
-    _reserved: [u32; 0x3ED],
-    /// Vorago 1x value: 0x0112_07E1. Vorago 4x value: 0x0212_07E9
-    #[mmio(PureRead)]
-    perid: u32,
-}
-
-static_assertions::const_assert_eq!(core::mem::size_of::<Uart>(), 0x1000);
-
-impl Uart {
-    fn new_mmio_at(base: usize) -> MmioUart<'static> {
-        MmioUart {
-            ptr: base as *mut _,
-            phantom: PhantomData,
-        }
-    }
-
-    pub fn new_mmio(bank: Bank) -> MmioUart<'static> {
-        match bank {
-            Bank::Uart0 => Self::new_mmio_at(BASE_ADDR_0),
-            Bank::Uart1 => Self::new_mmio_at(BASE_ADDR_1),
-            #[cfg(feature = "vor4x")]
-            Bank::Uart2 => Self::new_mmio_at(BASE_ADDR_2),
-        }
-    }
-}

vorago-shared-periphs/src/uart/rx_asynch.rs

@@ -1,437 +0,0 @@
-//! # Async UART reception functionality for the VA416xx family.
-//!
-//! This module provides the [RxAsync] and [RxAsyncOverwriting] struct which both implement the
-//! [embedded_io_async::Read] trait.
-//! This trait allows for asynchronous reception of data streams. Please note that this module does
-//! not specify/declare the interrupt handlers which must be provided for async support to work.
-//! However, it provides two interrupt handlers:
-//!
-//! - [on_interrupt_rx]
-//! - [on_interrupt_rx_overwriting]
-//!
-//! The first two are used for the [RxAsync] struct, while the latter two are used with the
-//! [RxAsyncOverwriting] struct. The later two will overwrite old values in the used ring buffer.
-//!
-//! Error handling is performed in the user interrupt handler by checking the [AsyncUartErrors]
-//! structure returned by the interrupt handlers.
-use core::{cell::RefCell, convert::Infallible, future::Future, sync::atomic::Ordering};
-
-use arbitrary_int::Number;
-use critical_section::Mutex;
-use embassy_sync::waitqueue::AtomicWaker;
-use embedded_io::ErrorType;
-use portable_atomic::AtomicBool;
-
-use super::{
-    Bank, Rx, UartErrors,
-    regs::{InterruptClear, MmioUart},
-};
-
-static UART_RX_WAKERS: [AtomicWaker; 2] = [const { AtomicWaker::new() }; 2];
-static RX_READ_ACTIVE: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2];
-static RX_HAS_DATA: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2];
-
-struct RxFuture {
-    id: Bank,
-}
-
-impl RxFuture {
-    pub fn new(rx: &mut Rx) -> Self {
-        RX_READ_ACTIVE[rx.id as usize].store(true, Ordering::Relaxed);
-        Self { id: rx.id }
-    }
-}
-
-impl Future for RxFuture {
-    type Output = Result<(), Infallible>;
-
-    fn poll(
-        self: core::pin::Pin<&mut Self>,
-        cx: &mut core::task::Context<'_>,
-    ) -> core::task::Poll<Self::Output> {
-        UART_RX_WAKERS[self.id as usize].register(cx.waker());
-        if RX_HAS_DATA[self.id as usize].load(Ordering::Relaxed) {
-            return core::task::Poll::Ready(Ok(()));
-        }
-        core::task::Poll::Pending
-    }
-}
-
-#[derive(Debug, Clone, Copy)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct AsyncUartErrors {
-    /// Queue has overflowed, data might have been lost.
-    pub queue_overflow: bool,
-    /// UART errors.
-    pub uart_errors: UartErrors,
-}
-
-fn on_interrupt_handle_rx_errors(uart: &mut MmioUart<'static>) -> Option<UartErrors> {
-    let rx_status = uart.read_rx_status();
-    if rx_status.overrun_error() || rx_status.framing_error() || rx_status.parity_error() {
-        let mut errors_val = UartErrors::default();
-
-        if rx_status.overrun_error() {
-            errors_val.overflow = true;
-        }
-        if rx_status.framing_error() {
-            errors_val.framing = true;
-        }
-        if rx_status.parity_error() {
-            errors_val.parity = true;
-        }
-        return Some(errors_val);
-    }
-    None
-}
-
-fn on_interrupt_rx_common_post_processing(
-    id: Bank,
-    rx_enabled: bool,
-    read_some_data: bool,
-) -> Option<UartErrors> {
-    let idx = id as usize;
-    if read_some_data {
-        RX_HAS_DATA[idx].store(true, Ordering::Relaxed);
-        if RX_READ_ACTIVE[idx].load(Ordering::Relaxed) {
-            UART_RX_WAKERS[idx].wake();
-        }
-    }
-
-    let mut errors = None;
-    let mut uart_regs = unsafe { id.steal_regs() };
-    // Check for RX errors
-    if rx_enabled {
-        errors = on_interrupt_handle_rx_errors(&mut uart_regs);
-    }
-
-    // Clear the interrupt status bits
-    uart_regs.write_irq_clr(
-        InterruptClear::builder()
-            .with_rx_overrun(true)
-            .with_tx_overrun(false)
-            .build(),
-    );
-    errors
-}
-
-/// Interrupt handler with overwriting behaviour when the ring buffer is full.
-///
-/// Should be called in the user interrupt handler to enable
-/// asynchronous reception. This variant will overwrite old data in the ring buffer in case
-/// the ring buffer is full.
-pub fn on_interrupt_rx_overwriting<const N: usize>(
-    bank: Bank,
-    prod: &mut heapless::spsc::Producer<u8, N>,
-    shared_consumer: &Mutex<RefCell<Option<heapless::spsc::Consumer<'static, u8, N>>>>,
-) -> Result<(), AsyncUartErrors> {
-    on_interrupt_rx_async_heapless_queue_overwriting(bank, prod, shared_consumer)
-}
-
-pub fn on_interrupt_rx_async_heapless_queue_overwriting<const N: usize>(
-    bank: Bank,
-    prod: &mut heapless::spsc::Producer<u8, N>,
-    shared_consumer: &Mutex<RefCell<Option<heapless::spsc::Consumer<'static, u8, N>>>>,
-) -> Result<(), AsyncUartErrors> {
-    let uart_regs = unsafe { bank.steal_regs() };
-    let irq_status = uart_regs.read_irq_status();
-    let irq_enabled = uart_regs.read_irq_enabled();
-    let rx_enabled = irq_enabled.rx();
-    let mut read_some_data = false;
-    let mut queue_overflow = false;
-
-    // Half-Full interrupt. We have a guaranteed amount of data we can read.
-    if irq_status.rx() {
-        let available_bytes = uart_regs.read_rx_fifo_trigger().level().as_usize();
-
-        // If this interrupt bit is set, the trigger level is available at the very least.
-        // Read everything as fast as possible
-        for _ in 0..available_bytes {
-            let byte = uart_regs.read_data().value();
-            if !prod.ready() {
-                queue_overflow = true;
-                critical_section::with(|cs| {
-                    let mut cons_ref = shared_consumer.borrow(cs).borrow_mut();
-                    cons_ref.as_mut().unwrap().dequeue();
-                });
-            }
-            prod.enqueue(byte).ok();
-        }
-        read_some_data = true;
-    }
-
-    // Timeout, empty the FIFO completely.
-    if irq_status.rx_timeout() {
-        while uart_regs.read_rx_status().data_available() {
-            // While there is data in the FIFO, write it into the reception buffer
-            let byte = uart_regs.read_data().value();
-            if !prod.ready() {
-                queue_overflow = true;
-                critical_section::with(|cs| {
-                    let mut cons_ref = shared_consumer.borrow(cs).borrow_mut();
-                    cons_ref.as_mut().unwrap().dequeue();
-                });
-            }
-            prod.enqueue(byte).ok();
-        }
-        read_some_data = true;
-    }
-
-    let uart_errors = on_interrupt_rx_common_post_processing(bank, rx_enabled, read_some_data);
-    if uart_errors.is_some() || queue_overflow {
-        return Err(AsyncUartErrors {
-            queue_overflow,
-            uart_errors: uart_errors.unwrap_or_default(),
-        });
-    }
-    Ok(())
-}
-
-/// Interrupt handler for asynchronous RX operations.
-///
-/// Should be called in the user interrupt handler to enable asynchronous reception.
-pub fn on_interrupt_rx<const N: usize>(
-    bank: Bank,
-    prod: &mut heapless::spsc::Producer<'_, u8, N>,
-) -> Result<(), AsyncUartErrors> {
-    on_interrupt_rx_async_heapless_queue(bank, prod)
-}
-
-pub fn on_interrupt_rx_async_heapless_queue<const N: usize>(
-    bank: Bank,
-    prod: &mut heapless::spsc::Producer<'_, u8, N>,
-) -> Result<(), AsyncUartErrors> {
-    let uart_regs = unsafe { bank.steal_regs() };
-    let irq_status = uart_regs.read_irq_status();
-    let irq_enabled = uart_regs.read_irq_enabled();
-    let rx_enabled = irq_enabled.rx();
-    let mut read_some_data = false;
-    let mut queue_overflow = false;
-
-    // Half-Full interrupt. We have a guaranteed amount of data we can read.
-    if irq_status.rx() {
-        let available_bytes = uart_regs.read_rx_fifo_trigger().level().as_usize();
-
-        // If this interrupt bit is set, the trigger level is available at the very least.
-        // Read everything as fast as possible
-        for _ in 0..available_bytes {
-            let byte = uart_regs.read_data().value();
-            if !prod.ready() {
-                queue_overflow = true;
-            }
-            prod.enqueue(byte).ok();
-        }
-        read_some_data = true;
-    }
-
-    // Timeout, empty the FIFO completely.
-    if irq_status.rx_timeout() {
-        while uart_regs.read_rx_status().data_available() {
-            // While there is data in the FIFO, write it into the reception buffer
-            let byte = uart_regs.read_data().value();
-            if !prod.ready() {
-                queue_overflow = true;
-            }
-            prod.enqueue(byte).ok();
-        }
-        read_some_data = true;
-    }
-
-    let uart_errors = on_interrupt_rx_common_post_processing(bank, rx_enabled, read_some_data);
-    if uart_errors.is_some() || queue_overflow {
-        return Err(AsyncUartErrors {
-            queue_overflow,
-            uart_errors: uart_errors.unwrap_or_default(),
-        });
-    }
-    Ok(())
-}
-
-struct ActiveReadGuard(usize);
-
-impl Drop for ActiveReadGuard {
-    fn drop(&mut self) {
-        RX_READ_ACTIVE[self.0].store(false, Ordering::Relaxed);
-    }
-}
-
-struct RxAsyncInner<const N: usize> {
-    rx: Rx,
-    pub queue: heapless::spsc::Consumer<'static, u8, N>,
-}
-
-/// Core data structure to allow asynchronous UART reception.
-///
-/// If the ring buffer becomes full, data will be lost.
-pub struct RxAsync<const N: usize>(Option<RxAsyncInner<N>>);
-
-impl<const N: usize> ErrorType for RxAsync<N> {
-    /// Error reporting is done using the result of the interrupt functions.
-    type Error = Infallible;
-}
-
-fn stop_async_rx(rx: &mut Rx) {
-    rx.disable_interrupts();
-    rx.disable();
-    rx.clear_fifo();
-}
-
-impl<const N: usize> RxAsync<N> {
-    /// Create a new asynchronous receiver.
-    ///
-    /// The passed [heapless::spsc::Consumer] will be used to asynchronously receive data which
-    /// is filled by the interrupt handler [on_interrupt_rx].
-    pub fn new(mut rx: Rx, queue: heapless::spsc::Consumer<'static, u8, N>) -> Self {
-        rx.disable_interrupts();
-        rx.disable();
-        rx.clear_fifo();
-        // Enable those together.
-        critical_section::with(|_| {
-            rx.enable_interrupts(true);
-            rx.enable();
-        });
-        Self(Some(RxAsyncInner { rx, queue }))
-    }
-
-    pub fn stop(&mut self) {
-        stop_async_rx(&mut self.0.as_mut().unwrap().rx);
-    }
-
-    pub fn release(mut self) -> (Rx, heapless::spsc::Consumer<'static, u8, N>) {
-        self.stop();
-        let inner = self.0.take().unwrap();
-        (inner.rx, inner.queue)
-    }
-}
-
-impl<const N: usize> Drop for RxAsync<N> {
-    fn drop(&mut self) {
-        self.stop();
-    }
-}
-
-impl<const N: usize> embedded_io_async::Read for RxAsync<N> {
-    async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
-        let inner = self.0.as_ref().unwrap();
-        // Need to wait for the IRQ to read data and set this flag. If the queue is not
-        // empty, we can read data immediately.
-        if inner.queue.len() == 0 {
-            RX_HAS_DATA[inner.rx.id as usize].store(false, Ordering::Relaxed);
-        }
-        let _guard = ActiveReadGuard(inner.rx.id as usize);
-        let mut handle_data_in_queue = |consumer: &mut heapless::spsc::Consumer<'static, u8, N>| {
-            let data_to_read = consumer.len().min(buf.len());
-            for byte in buf.iter_mut().take(data_to_read) {
-                // We own the consumer and we checked that the amount of data is guaranteed to be available.
-                *byte = unsafe { consumer.dequeue_unchecked() };
-            }
-            data_to_read
-        };
-        let mut_ref = self.0.as_mut().unwrap();
-        let fut = RxFuture::new(&mut mut_ref.rx);
-        // Data is available, so read that data immediately.
-        let read_data = handle_data_in_queue(&mut mut_ref.queue);
-        if read_data > 0 {
-            return Ok(read_data);
-        }
-        // Await data.
-        let _ = fut.await;
-        Ok(handle_data_in_queue(&mut mut_ref.queue))
-    }
-}
-
-struct RxAsyncOverwritingInner<const N: usize> {
-    rx: Rx,
-    pub shared_consumer: &'static Mutex<RefCell<Option<heapless::spsc::Consumer<'static, u8, N>>>>,
-}
-
-/// Core data structure to allow asynchronous UART reception.
-///
-/// If the ring buffer becomes full, the oldest data will be overwritten when using the
-/// [on_interrupt_rx_overwriting] interrupt handlers.
-pub struct RxAsyncOverwriting<const N: usize>(Option<RxAsyncOverwritingInner<N>>);
-
-impl<const N: usize> ErrorType for RxAsyncOverwriting<N> {
-    /// Error reporting is done using the result of the interrupt functions.
-    type Error = Infallible;
-}
-
-impl<const N: usize> RxAsyncOverwriting<N> {
-    /// Create a new asynchronous receiver.
-    ///
-    /// The passed shared [heapless::spsc::Consumer] will be used to asynchronously receive data
-    /// which is filled by the interrupt handler. The shared property allows using it in the
-    /// interrupt handler to overwrite old data.
-    pub fn new(
-        mut rx: Rx,
-        shared_consumer: &'static Mutex<RefCell<Option<heapless::spsc::Consumer<'static, u8, N>>>>,
-    ) -> Self {
-        rx.disable_interrupts();
-        rx.disable();
-        rx.clear_fifo();
-        // Enable those together.
-        critical_section::with(|_| {
-            rx.enable_interrupts(true);
-            rx.enable();
-        });
-        Self(Some(RxAsyncOverwritingInner {
-            rx,
-            shared_consumer,
-        }))
-    }
-
-    pub fn stop(&mut self) {
-        stop_async_rx(&mut self.0.as_mut().unwrap().rx);
-    }
-
-    pub fn release(mut self) -> Rx {
-        self.stop();
-        let inner = self.0.take().unwrap();
-        inner.rx
-    }
-}
-
-impl<const N: usize> Drop for RxAsyncOverwriting<N> {
-    fn drop(&mut self) {
-        self.stop();
-    }
-}
-
-impl<const N: usize> embedded_io_async::Read for RxAsyncOverwriting<N> {
-    async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
-        let inner = self.0.as_ref().unwrap();
-        let id = inner.rx.id as usize;
-        // Need to wait for the IRQ to read data and set this flag. If the queue is not
-        // empty, we can read data immediately.
-
-        critical_section::with(|cs| {
-            let queue = inner.shared_consumer.borrow(cs);
-            if queue.borrow().as_ref().unwrap().len() == 0 {
-                RX_HAS_DATA[id].store(false, Ordering::Relaxed);
-            }
-        });
-        let _guard = ActiveReadGuard(id);
-        let mut handle_data_in_queue = |inner: &mut RxAsyncOverwritingInner<N>| {
-            critical_section::with(|cs| {
-                let mut consumer_ref = inner.shared_consumer.borrow(cs).borrow_mut();
-                let consumer = consumer_ref.as_mut().unwrap();
-                let data_to_read = consumer.len().min(buf.len());
-                for byte in buf.iter_mut().take(data_to_read) {
-                    // We own the consumer and we checked that the amount of data is guaranteed to be available.
-                    *byte = unsafe { consumer.dequeue_unchecked() };
-                }
-                data_to_read
-            })
-        };
-        let fut = RxFuture::new(&mut self.0.as_mut().unwrap().rx);
-        // Data is available, so read that data immediately.
-        let read_data = handle_data_in_queue(self.0.as_mut().unwrap());
-        if read_data > 0 {
-            return Ok(read_data);
-        }
-        // Await data.
-        let _ = fut.await;
-        let read_data = handle_data_in_queue(self.0.as_mut().unwrap());
-        Ok(read_data)
-    }
-}

vorago-shared-periphs/src/uart/tx_asynch.rs

@@ -1,205 +0,0 @@
-//! # Async UART transmission functionality for the VA108xx family.
-//!
-//! This module provides the [TxAsync] struct which implements the [embedded_io_async::Write] trait.
-//! This trait allows for asynchronous sending of data streams. Please note that this module does
-//! not specify/declare the interrupt handlers which must be provided for async support to work.
-//! However, it the [on_interrupt_tx] interrupt handler.
-//!
-//! This handler should be called in ALL user interrupt handlers which handle UART TX interrupts
-//! for a given UART bank.
-use core::{cell::RefCell, future::Future};
-
-use critical_section::Mutex;
-use embassy_sync::waitqueue::AtomicWaker;
-use embedded_io_async::Write;
-use portable_atomic::AtomicBool;
-use raw_slice::RawBufSlice;
-
-use super::*;
-
-static UART_TX_WAKERS: [AtomicWaker; 2] = [const { AtomicWaker::new() }; 2];
-static TX_CONTEXTS: [Mutex<RefCell<TxContext>>; 2] =
-    [const { Mutex::new(RefCell::new(TxContext::new())) }; 2];
-// Completion flag. Kept outside of the context structure as an atomic to avoid
-// critical section.
-static TX_DONE: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2];
-
-/// This is a generic interrupt handler to handle asynchronous UART TX operations for a given
-/// UART bank.
-///
-/// The user has to call this once in the interrupt handler responsible for the TX interrupts on
-/// the given UART bank.
-pub fn on_interrupt_tx(bank: Bank) {
-    let mut uart = unsafe { bank.steal_regs() };
-    let idx = bank as usize;
-    let irq_enabled = uart.read_irq_enabled();
-    // IRQ is not related to TX.
-    if !irq_enabled.tx() && !irq_enabled.tx_empty() {
-        return;
-    }
-
-    let tx_status = uart.read_tx_status();
-    let unexpected_overrun = tx_status.wr_lost();
-    let mut context = critical_section::with(|cs| {
-        let context_ref = TX_CONTEXTS[idx].borrow(cs);
-        *context_ref.borrow()
-    });
-    context.tx_overrun = unexpected_overrun;
-    // Safety: We documented that the user provided slice must outlive the future, so we convert
-    // the raw pointer back to the slice here.
-    let slice = unsafe { context.slice.get().unwrap() };
-    if context.progress >= slice.len() && !tx_status.tx_busy() {
-        uart.modify_irq_enabled(|mut value| {
-            value.set_tx(false);
-            value.set_tx_empty(false);
-            value.set_tx_status(false);
-            value
-        });
-        uart.modify_enable(|mut value| {
-            value.set_tx(false);
-            value
-        });
-        // Write back updated context structure.
-        critical_section::with(|cs| {
-            let context_ref = TX_CONTEXTS[idx].borrow(cs);
-            *context_ref.borrow_mut() = context;
-        });
-        // Transfer is done.
-        TX_DONE[idx].store(true, core::sync::atomic::Ordering::Relaxed);
-        UART_TX_WAKERS[idx].wake();
-        return;
-    }
-    while context.progress < slice.len() {
-        if !uart.read_tx_status().ready() {
-            break;
-        }
-        // Safety: TX structure is owned by the future which does not write into the the data
-        // register, so we can assume we are the only one writing to the data register.
-        uart.write_data(Data::new_with_raw_value(slice[context.progress] as u32));
-        context.progress += 1;
-    }
-
-    // Write back updated context structure.
-    critical_section::with(|cs| {
-        let context_ref = TX_CONTEXTS[idx].borrow(cs);
-        *context_ref.borrow_mut() = context;
-    });
-}
-
-#[derive(Debug, Copy, Clone)]
-pub struct TxContext {
-    progress: usize,
-    tx_overrun: bool,
-    slice: RawBufSlice,
-}
-
-#[allow(clippy::new_without_default)]
-impl TxContext {
-    pub const fn new() -> Self {
-        Self {
-            progress: 0,
-            tx_overrun: false,
-            slice: RawBufSlice::new_nulled(),
-        }
-    }
-}
-
-pub struct TxFuture {
-    id: Bank,
-}
-
-impl TxFuture {
-    /// # Safety
-    ///
-    /// This function stores the raw pointer of the passed data slice. The user MUST ensure
-    /// that the slice outlives the data structure.
-    pub unsafe fn new(tx: &mut Tx, data: &[u8]) -> Self {
-        TX_DONE[tx.id as usize].store(false, core::sync::atomic::Ordering::Relaxed);
-        tx.disable_interrupts();
-        tx.disable();
-        tx.clear_fifo();
-
-        let init_fill_count = core::cmp::min(data.len(), 16);
-        // We fill the FIFO.
-        for data in data.iter().take(init_fill_count) {
-            tx.regs.write_data(Data::new_with_raw_value(*data as u32));
-        }
-        critical_section::with(|cs| {
-            let context_ref = TX_CONTEXTS[tx.id as usize].borrow(cs);
-            let mut context = context_ref.borrow_mut();
-            unsafe { context.slice.set(data) };
-            context.progress = init_fill_count;
-
-            // Ensure those are enabled inside a critical section at the same time. Can lead to
-            // weird glitches otherwise.
-            tx.enable_interrupts();
-            tx.enable();
-        });
-        Self { id: tx.id }
-    }
-}
-
-impl Future for TxFuture {
-    type Output = Result<usize, TxOverrunError>;
-
-    fn poll(
-        self: core::pin::Pin<&mut Self>,
-        cx: &mut core::task::Context<'_>,
-    ) -> core::task::Poll<Self::Output> {
-        UART_TX_WAKERS[self.id as usize].register(cx.waker());
-        if TX_DONE[self.id as usize].swap(false, core::sync::atomic::Ordering::Relaxed) {
-            let progress = critical_section::with(|cs| {
-                TX_CONTEXTS[self.id as usize].borrow(cs).borrow().progress
-            });
-            return core::task::Poll::Ready(Ok(progress));
-        }
-        core::task::Poll::Pending
-    }
-}
-
-impl Drop for TxFuture {
-    fn drop(&mut self) {
-        let mut reg_block = unsafe { self.id.steal_regs() };
-
-        disable_tx_interrupts(&mut reg_block);
-        disable_tx(&mut reg_block);
-    }
-}
-
-pub struct TxAsync(Tx);
-
-impl TxAsync {
-    pub fn new(tx: Tx) -> Self {
-        Self(tx)
-    }
-
-    pub fn release(self) -> Tx {
-        self.0
-    }
-}
-
-#[derive(Debug, thiserror::Error)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[error("TX overrun error")]
-pub struct TxOverrunError;
-
-impl embedded_io_async::Error for TxOverrunError {
-    fn kind(&self) -> embedded_io_async::ErrorKind {
-        embedded_io_async::ErrorKind::Other
-    }
-}
-
-impl embedded_io::ErrorType for TxAsync {
-    type Error = TxOverrunError;
-}
-
-impl Write for TxAsync {
-    /// Write a buffer asynchronously.
-    ///
-    /// This implementation is not side effect free, and a started future might have already
-    /// written part of the passed buffer.
-    async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
-        let fut = unsafe { TxFuture::new(&mut self.0, buf) };
-        fut.await
-    }
-}

vscode/launch.json

@@ -15,10 +15,6 @@
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
             "preLaunchTask": "rust: cargo build led blinky",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/blinky-leds",
             "interface": "jtag",
             "runToEntryPoint": "main",
@@ -43,10 +39,6 @@
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
             "preLaunchTask": "rust: cargo build hal tests",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/board-tests",
             "interface": "jtag",
             "runToEntryPoint": "main",
@@ -62,6 +54,30 @@
                 ]
             }
         },
+        {
+            "type": "cortex-debug",
+            "request": "launch",
+            "name": "Debug RTT",
+            "servertype": "jlink",
+            "cwd": "${workspaceRoot}",
+            "device": "Cortex-M0",
+            "svdFile": "./va108xx/svd/va108xx.svd.patched",
+            "preLaunchTask": "rust: cargo build rtt",
+            "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/rtt-log",
+            "interface": "jtag",
+            "runToEntryPoint": "main",
+            "rttConfig": {
+                "enabled": true,
+                "address": "auto",
+                "decoders": [
+                    {
+                        "port": 0,
+                        "timestamp": true,
+                        "type": "console"
+                    }
+                ]
+            }
+        },
         {
             "type": "cortex-debug",
             "request": "launch",
@@ -71,10 +87,6 @@
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
             "preLaunchTask": "rust: cargo build button blinky",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/blinky-button-irq",
             "interface": "jtag",
             "runToEntryPoint": "main",
@@ -101,10 +113,6 @@
             "preLaunchTask": "rust: cargo build systick",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/timer-ticks",
             "interface": "jtag",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "runToEntryPoint": "main",
             "rttConfig": {
                 "enabled": true,
@@ -125,11 +133,7 @@
             "servertype": "jlink",
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
-            "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
+            "svdFile": "./va108xx/svd/va108xx-base.svd.patched",
             "preLaunchTask": "rust: cargo build uart",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/uart",
             "interface": "jtag",
@@ -154,10 +158,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "rust: cargo build spi",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/spi",
             "interface": "jtag",
@@ -182,10 +182,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx-base.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "rust: cargo build temp sensor",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/adt75-temp-sensor",
             "interface": "jtag",
@@ -210,10 +206,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx-base.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "rust: cargo build button blinky rtic",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/blinky-button-rtic",
             "interface": "jtag",
@@ -238,10 +230,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx-base.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "uart-echo-rtic-example",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/uart-echo-rtic",
             "interface": "jtag",
@@ -266,10 +254,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "rust: cargo build pwm",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/pwm",
             "interface": "jtag",
@@ -294,10 +278,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "rust: cargo build cascade",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/cascade",
             "interface": "jtag",
@@ -322,10 +302,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "rust: cargo build accelerometer",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/adxl343-accelerometer",
             "interface": "jtag",
@@ -342,6 +318,19 @@
                 ]
             }
         },
+        {
+            "type": "cortex-debug",
+            "request": "launch",
+            "name": "Blinky HAL",
+            "servertype": "jlink",
+            "cwd": "${workspaceRoot}",
+            "device": "Cortex-M0",
+            "svdFile": "./va108xx/svd/va108xx.svd.patched",
+            "preLaunchTask": "blinky-hal",
+            "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/blinky",
+            "interface": "jtag",
+            "runToEntryPoint": "main",
+        },
         {
             "type": "cortex-debug",
             "request": "launch",
@@ -350,10 +339,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "rust: cargo build adc",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/max11619-adc",
             "interface": "jtag",
@@ -378,10 +363,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "uart-echo-rtic-example",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/uart-echo-rtic",
             "interface": "jtag",
@@ -406,10 +387,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "reb1-nvm",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/examples/nvm",
             "interface": "jtag",
@@ -434,10 +411,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "rtic-example",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/rtic-example",
             "interface": "jtag",
@@ -462,10 +435,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "embassy-example",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/embassy-example",
             "interface": "jtag",
@@ -490,10 +459,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "bootloader",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/release/bootloader",
             "interface": "jtag",
@@ -518,10 +483,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "flashloader",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/release/flashloader",
             "interface": "jtag",
@@ -546,10 +507,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "async-gpio",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/async-gpio",
             "interface": "jtag",
@@ -574,10 +531,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "async-uart-tx",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/async-uart-tx",
             "interface": "jtag",
@@ -602,10 +555,6 @@
             "cwd": "${workspaceRoot}",
             "device": "Cortex-M0",
             "svdFile": "./va108xx/svd/va108xx.svd.patched",
-            "serverArgs": [
-                "-jtagconf",
-                "-1,-1"
-            ],
             "preLaunchTask": "async-uart-rx",
             "executable": "${workspaceFolder}/target/thumbv6m-none-eabi/debug/async-uart-rx",
             "interface": "jtag",
@@ -623,4 +572,4 @@
             }
         },
     ]
-}
+}

vscode/tasks.json

@@ -31,6 +31,20 @@
         "isDefault": true
       }
     },
+    {
+      "label": "rust: cargo build rtt",
+      "type": "shell",
+      "command": "~/.cargo/bin/cargo", // note: full path to the cargo
+      "args": [
+        "build",
+        "--example",
+        "rtt-log"
+      ],
+      "group": {
+        "kind": "build",
+        "isDefault": true
+      }
+    },
     {
       "label": "rust: cargo build systick",
       "type": "shell",
@@ -305,4 +319,4 @@
       ]
     }
   ]
-}
+}