19 Commits

Author SHA1 Message Date
6402b9f014 small docs update 2025-02-10 11:44:49 +01:00
2fe92c76c6 va108xx v0.4.0: Regnerate PAC 2025-02-09 13:26:36 +01:00
b2d17e10ed Merge pull request 'bootloader tweak' (#26) from bootloader-tweak into main
Reviewed-on: #26
2025-01-14 10:30:08 +01:00
1412e1b7d1 bootloader tweak 2025-01-14 01:21:20 +01:00
88ee85a4cd Merge pull request 'new update for ringbuf' (#25) from update-for-ringbuf into main
Reviewed-on: #25
2025-01-11 11:39:59 +01:00
4b318ecc76 new update for ringbuf 2025-01-11 11:38:04 +01:00
badeea8071 Merge pull request 'fix memory x file' (#24) from fix-memory-x-file into main
Reviewed-on: #24
2025-01-10 17:49:45 +01:00
c95558ff55 Merge branch 'main' into fix-memory-x-file 2025-01-10 17:49:38 +01:00
cd222fd1e1 Merge pull request 'some clippy fixes' (#23) from some-clippy-fixes into main
Reviewed-on: #23
2025-01-10 17:49:20 +01:00
f438e7e40f some clippy fixes 2025-01-10 17:19:28 +01:00
9e547668c2 fix memory x file 2025-01-10 16:38:17 +01:00
cf55fe1504 Merge pull request 'bootloader and flashloader update' (#22) from bootloader-flashloader-update into main
Reviewed-on: #22
2025-01-10 16:31:39 +01:00
74eebdcc03 bootloader and flashloader update 2025-01-10 16:31:15 +01:00
35527f092a Merge pull request 'update probe-rs files' (#21) from probe-rs-update into main
Reviewed-on: #21
2024-11-26 10:23:37 +01:00
c6314f48d7 update probe-rs files 2024-11-26 10:23:27 +01:00
7189cb246b Merge pull request 'delete some more re-exports' (#20) from delete-some-re-exports into main
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Reviewed-on: #20
2024-10-07 09:48:13 +02:00
39b8633065 delete some more re-exports
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2024-10-07 09:47:24 +02:00
df0760da98 Merge pull request 'prepare BSP release' (#19) from prep-bsp-release into main
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Reviewed-on: #19
2024-09-30 12:12:20 +02:00
8ed26db6a7 prepare BSP release
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2024-09-30 12:10:03 +02:00
161 changed files with 909 additions and 1056 deletions

2
.gitignore vendored
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@@ -16,3 +16,5 @@ Cargo.lock
# JetBrains IDEs # JetBrains IDEs
/.idea /.idea
*.iml *.iml
/Embed.toml

12
Embed.toml.sample Normal file
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@@ -0,0 +1,12 @@
[default.probe]
protocol = "Jtag"
[default.general]
chip = "VA108xx_RAM"
[default.rtt]
enabled = true
[default.gdb]
# Whether or not a GDB server should be opened after flashing.
enabled = false

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@@ -11,6 +11,7 @@ panic-rtt-target = { version = "0.1.3" }
panic-halt = { version = "0.2" } panic-halt = { version = "0.2" }
rtt-target = { version = "0.5" } rtt-target = { version = "0.5" }
crc = "3" crc = "3"
num_enum = { version = "0.7", default-features = false }
static_assertions = "1" static_assertions = "1"
[dependencies.va108xx-hal] [dependencies.va108xx-hal]

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@@ -9,14 +9,15 @@ The bootloader uses the following memory map:
| Address | Notes | Size | | Address | Notes | Size |
| ------ | ---- | ---- | | ------ | ---- | ---- |
| 0x0 | Bootloader start | code up to 0x3FFC bytes | | 0x0 | Bootloader start | code up to 0x2FFE bytes |
| 0x2FFE | Bootloader CRC | word | | 0x2FFE | Bootloader CRC | half-word |
| 0x3000 | App image A start | code up to 0xE7F8 (~58K) bytes | | 0x3000 | App image A start | code up to 0xE7F4 (~59K) bytes |
| 0x117F8 | App image A CRC check length | word | | 0x117F8 | App image A CRC check length | word |
| 0x117FC | App image A CRC check value | word | | 0x117FC | App image A CRC check value | word |
| 0x11800 | App image B start | code up to 0xE7F8 (~58K) bytes | | 0x117FC | App image B start | code up to 0xE7F4 (~59K) bytes |
| 0x1FFF8 | App image B CRC check length | word | | 0x1FFF0 | App image B CRC check length | word |
| 0x1FFFC | App image B CRC check value | word | | 0x1FFF4 | App image B CRC check value | word |
| 0x1FFF8 | Reserved section, contains boot select parameter | 8 bytes |
| 0x20000 | End of NVM | end | | 0x20000 | End of NVM | end |
## Additional Information ## Additional Information
@@ -35,13 +36,15 @@ The bootloader performs the following steps:
1. The application will calculate the checksum of itself if the bootloader CRC is blank (all zeroes 1. The application will calculate the checksum of itself if the bootloader CRC is blank (all zeroes
or all ones). If the CRC is not blank and the checksum check fails, it will immediately boot or all ones). If the CRC is not blank and the checksum check fails, it will immediately boot
application image A. Otherwise, it proceeds to the next step. application image A. Otherwise, it proceeds to the next step.
2. Check the checksum of App A. If that checksum is valid, it will boot App A. If not, it will 2. Read the boot slot from a reserved section at the end of the EEPROM. If no valid value is read,
proceed to the next step. select boot slot A.
3. Check the checksum of App B. If that checksum is valid, it will boot App B. If not, it will 3. Check the checksum of the boot slot. If that checksum is valid, it will boot that slot. If not,
boot App A as the fallback image. it will proceed to the next step.
4. Check the checksum of the other slot . If that checksum is valid, it will boot that slot. If
not, it will boot App A as the fallback image.
You could adapt and combine this bootloader with a non-volatile memory to select a prefered app In your actual production application, a command to update the preferred boot slot could be exposed
image, which would be a first step towards an updatable flight software. to allow performing software updates in a safe way.
Please note that you *MUST* compile the application at slot A and slot B with an appropriate Please note that you *MUST* compile the application at slot A and slot B with an appropriate
`memory.x` file where the base address of the `FLASH` was adapted according to the base address `memory.x` file where the base address of the `FLASH` was adapted according to the base address

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@@ -5,6 +5,7 @@ use bootloader::NvmInterface;
use cortex_m_rt::entry; use cortex_m_rt::entry;
use crc::{Crc, CRC_16_IBM_3740}; use crc::{Crc, CRC_16_IBM_3740};
use embedded_hal::delay::DelayNs; use embedded_hal::delay::DelayNs;
use num_enum::TryFromPrimitive;
#[cfg(not(feature = "rtt-panic"))] #[cfg(not(feature = "rtt-panic"))]
use panic_halt as _; use panic_halt as _;
#[cfg(feature = "rtt-panic")] #[cfg(feature = "rtt-panic")]
@@ -59,8 +60,9 @@ const APP_B_SIZE_ADDR: u32 = APP_B_END_ADDR - 8;
// Four bytes reserved, even when only 2 byte CRC is used. Leaves flexibility to switch to CRC32. // Four bytes reserved, even when only 2 byte CRC is used. Leaves flexibility to switch to CRC32.
// 0x1FFFC // 0x1FFFC
const APP_B_CRC_ADDR: u32 = APP_B_END_ADDR - 4; const APP_B_CRC_ADDR: u32 = APP_B_END_ADDR - 4;
// 0x20000 // 0x20000. 8 bytes at end of EEPROM reserved for preferred image parameter. This reserved
pub const APP_B_END_ADDR: u32 = NVM_SIZE; // size should be a multiple of 8 due to alignment requirements.
pub const APP_B_END_ADDR: u32 = NVM_SIZE - 8;
pub const APP_IMG_SZ: u32 = (APP_B_END_ADDR - APP_A_START_ADDR) / 2; pub const APP_IMG_SZ: u32 = (APP_B_END_ADDR - APP_A_START_ADDR) / 2;
static_assertions::const_assert!((APP_B_END_ADDR - BOOTLOADER_END_ADDR) % 2 == 0); static_assertions::const_assert!((APP_B_END_ADDR - BOOTLOADER_END_ADDR) % 2 == 0);
@@ -68,13 +70,15 @@ static_assertions::const_assert!((APP_B_END_ADDR - BOOTLOADER_END_ADDR) % 2 == 0
pub const VECTOR_TABLE_OFFSET: u32 = 0x0; pub const VECTOR_TABLE_OFFSET: u32 = 0x0;
pub const VECTOR_TABLE_LEN: u32 = 0xC0; pub const VECTOR_TABLE_LEN: u32 = 0xC0;
pub const RESET_VECTOR_OFFSET: u32 = 0x4; pub const RESET_VECTOR_OFFSET: u32 = 0x4;
pub const PREFERRED_SLOT_OFFSET: u32 = 0x20000 - 1;
const CRC_ALGO: Crc<u16> = Crc::<u16>::new(&CRC_16_IBM_3740); const CRC_ALGO: Crc<u16> = Crc::<u16>::new(&CRC_16_IBM_3740);
#[derive(Debug, Copy, Clone, PartialEq, Eq)] #[derive(Debug, Copy, Clone, PartialEq, Eq, TryFromPrimitive)]
#[repr(u8)]
enum AppSel { enum AppSel {
A, A = 0,
B, B = 1,
} }
pub struct NvmWrapper(pub M95M01); pub struct NvmWrapper(pub M95M01);
@@ -154,10 +158,20 @@ fn main() -> ! {
// Check bootloader's CRC (and write it if blank) // Check bootloader's CRC (and write it if blank)
check_own_crc(&dp.sysconfig, &cp, &mut nvm, &mut timer); check_own_crc(&dp.sysconfig, &cp, &mut nvm, &mut timer);
if check_app_crc(AppSel::A) { let mut preferred_app_raw = [0; 1];
boot_app(&dp.sysconfig, &cp, AppSel::A, &mut timer) nvm.read(PREFERRED_SLOT_OFFSET as usize, &mut preferred_app_raw)
} else if check_app_crc(AppSel::B) { .expect("reading preferred slot failed");
boot_app(&dp.sysconfig, &cp, AppSel::B, &mut timer) let preferred_app = AppSel::try_from(preferred_app_raw[0]).unwrap_or(AppSel::A);
let other_app = if preferred_app == AppSel::A {
AppSel::B
} else {
AppSel::A
};
if check_app_crc(preferred_app) {
boot_app(&dp.sysconfig, &cp, preferred_app, &mut timer)
} else if check_app_crc(other_app) {
boot_app(&dp.sysconfig, &cp, other_app, &mut timer)
} else { } else {
if DEBUG_PRINTOUTS && RTT_PRINTOUT { if DEBUG_PRINTOUTS && RTT_PRINTOUT {
rprintln!("both images corrupt! booting image A"); rprintln!("both images corrupt! booting image A");

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@@ -38,7 +38,7 @@ default-features = false
features = ["portable-atomic"] features = ["portable-atomic"]
[dependencies.va108xx-hal] [dependencies.va108xx-hal]
path = "../../va108xx-hal" version = "0.8"
[dependencies.vorago-reb1] [dependencies.vorago-reb1]
path = "../../vorago-reb1" path = "../../vorago-reb1"

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@@ -5,25 +5,17 @@
#![no_main] #![no_main]
#![no_std] #![no_std]
use once_cell::sync::Lazy;
use ringbuf::StaticRb; use ringbuf::StaticRb;
// Larger buffer for TC to be able to hold the possibly large memory write packets. // Larger buffer for TC to be able to hold the possibly large memory write packets.
const RX_RING_BUF_SIZE: usize = 1024; const RX_RING_BUF_SIZE: usize = 1024;
// Ring buffers to handling variable sized telemetry
static mut RINGBUF: Lazy<StaticRb<u8, RX_RING_BUF_SIZE>> =
Lazy::new(StaticRb::<u8, RX_RING_BUF_SIZE>::default);
#[rtic::app(device = pac, dispatchers = [OC4])] #[rtic::app(device = pac, dispatchers = [OC4])]
mod app { mod app {
use super::*; use super::*;
use embedded_io::Write; use embedded_io::Write;
use panic_rtt_target as _; use panic_rtt_target as _;
use ringbuf::{ use ringbuf::traits::{Consumer, Observer, Producer};
traits::{Consumer, Observer, Producer, SplitRef},
CachingCons, StaticProd,
};
use rtic_example::SYSCLK_FREQ; use rtic_example::SYSCLK_FREQ;
use rtic_monotonics::Monotonic; use rtic_monotonics::Monotonic;
use rtt_target::{rprintln, rtt_init_print}; use rtt_target::{rprintln, rtt_init_print};
@@ -36,14 +28,14 @@ mod app {
#[local] #[local]
struct Local { struct Local {
data_producer: StaticProd<'static, u8, RX_RING_BUF_SIZE>,
data_consumer: CachingCons<&'static StaticRb<u8, RX_RING_BUF_SIZE>>,
rx: RxWithIrq<pac::Uarta>, rx: RxWithIrq<pac::Uarta>,
tx: Tx<pac::Uarta>, tx: Tx<pac::Uarta>,
} }
#[shared] #[shared]
struct Shared {} struct Shared {
rb: StaticRb<u8, RX_RING_BUF_SIZE>,
}
rtic_monotonics::systick_monotonic!(Mono, 1_000); rtic_monotonics::systick_monotonic!(Mono, 1_000);
@@ -71,13 +63,12 @@ mod app {
rx.start(); rx.start();
let (data_producer, data_consumer) = unsafe { RINGBUF.split_ref() };
echo_handler::spawn().unwrap(); echo_handler::spawn().unwrap();
( (
Shared {}, Shared {
rb: StaticRb::default(),
},
Local { Local {
data_producer,
data_consumer,
rx, rx,
tx, tx,
}, },
@@ -94,24 +85,23 @@ mod app {
#[task( #[task(
binds = OC3, binds = OC3,
shared = [], shared = [rb],
local = [ local = [
rx, rx,
data_producer
], ],
)] )]
fn reception_task(cx: reception_task::Context) { fn reception_task(mut cx: reception_task::Context) {
let mut buf: [u8; 16] = [0; 16]; let mut buf: [u8; 16] = [0; 16];
let mut ringbuf_full = false; let mut ringbuf_full = false;
let result = cx.local.rx.irq_handler(&mut buf); let result = cx.local.rx.irq_handler(&mut buf);
if result.bytes_read > 0 && result.errors.is_none() { if result.bytes_read > 0 && result.errors.is_none() {
if cx.local.data_producer.vacant_len() < result.bytes_read { cx.shared.rb.lock(|rb| {
if rb.vacant_len() < result.bytes_read {
ringbuf_full = true; ringbuf_full = true;
} else { } else {
cx.local rb.push_slice(&buf[0..result.bytes_read]);
.data_producer
.push_slice(&buf[0..result.bytes_read]);
} }
});
} }
if ringbuf_full { if ringbuf_full {
// Could also drop oldest data, but that would require the consumer to be shared. // Could also drop oldest data, but that would require the consumer to be shared.
@@ -119,24 +109,23 @@ mod app {
} }
} }
#[task(shared = [], local = [ #[task(shared = [rb], local = [
buf: [u8; RX_RING_BUF_SIZE] = [0; RX_RING_BUF_SIZE], buf: [u8; RX_RING_BUF_SIZE] = [0; RX_RING_BUF_SIZE],
data_consumer,
tx tx
], priority=1)] ], priority=1)]
async fn echo_handler(cx: echo_handler::Context) { async fn echo_handler(mut cx: echo_handler::Context) {
loop { loop {
let bytes_to_read = cx.local.data_consumer.occupied_len(); cx.shared.rb.lock(|rb| {
let bytes_to_read = rb.occupied_len();
if bytes_to_read > 0 { if bytes_to_read > 0 {
let actual_read_bytes = cx let actual_read_bytes = rb.pop_slice(&mut cx.local.buf[0..bytes_to_read]);
.local
.data_consumer
.pop_slice(&mut cx.local.buf[0..bytes_to_read]);
cx.local cx.local
.tx .tx
.write_all(&cx.local.buf[0..actual_read_bytes]) .write_all(&cx.local.buf[0..actual_read_bytes])
.expect("Failed to write to TX"); .expect("Failed to write to TX");
} }
});
Mono::delay(50.millis()).await; Mono::delay(50.millis()).await;
} }
} }

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@@ -16,7 +16,7 @@ embedded-io = "0.6"
cortex-m-semihosting = "0.5.0" cortex-m-semihosting = "0.5.0"
[dependencies.va108xx-hal] [dependencies.va108xx-hal]
path = "../../va108xx-hal" version = "0.8"
features = ["rt", "defmt"] features = ["rt", "defmt"]
[dependencies.vorago-reb1] [dependencies.vorago-reb1]

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@@ -11,6 +11,7 @@ embedded-hal-nb = "1"
embedded-io = "0.6" embedded-io = "0.6"
panic-rtt-target = { version = "0.1.3" } panic-rtt-target = { version = "0.1.3" }
rtt-target = { version = "0.5" } rtt-target = { version = "0.5" }
num_enum = { version = "0.7", default-features = false }
log = "0.4" log = "0.4"
crc = "3" crc = "3"

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@@ -59,6 +59,15 @@ to write it to slot A.
You can use You can use
```sh
./image-loader.py -s a
```
to select the Slot A as a boot slot. The boot slot is stored in a reserved section in EEPROM
and will be read and used by the bootloader to determine which slot to boot.
You can use
```sh ```sh
./image-loader.py -c -t a ./image-loader.py -c -t a
``` ```

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@@ -30,20 +30,21 @@ BOOTLOADER_CRC_ADDR = BOOTLOADER_END_ADDR - 2
BOOTLOADER_MAX_SIZE = BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 2 BOOTLOADER_MAX_SIZE = BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 2
APP_A_START_ADDR = 0x3000 APP_A_START_ADDR = 0x3000
APP_A_END_ADDR = 0x11800 APP_B_END_ADDR = 0x20000 - 8
IMG_SLOT_SIZE = (APP_B_END_ADDR - APP_A_START_ADDR) // 2
APP_A_END_ADDR = APP_A_START_ADDR + IMG_SLOT_SIZE
# The actual size of the image which is relevant for CRC calculation. # The actual size of the image which is relevant for CRC calculation.
APP_A_SIZE_ADDR = APP_A_END_ADDR - 8 APP_A_SIZE_ADDR = APP_A_END_ADDR - 8
APP_A_CRC_ADDR = APP_A_END_ADDR - 4 APP_A_CRC_ADDR = APP_A_END_ADDR - 4
APP_A_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8 APP_A_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8
APP_B_START_ADDR = APP_A_END_ADDR APP_B_START_ADDR = APP_A_END_ADDR
APP_B_END_ADDR = 0x20000
# The actual size of the image which is relevant for CRC calculation. # The actual size of the image which is relevant for CRC calculation.
APP_B_SIZE_ADDR = APP_B_END_ADDR - 8 APP_B_SIZE_ADDR = APP_B_END_ADDR - 8
APP_B_CRC_ADDR = APP_B_END_ADDR - 4 APP_B_CRC_ADDR = APP_B_END_ADDR - 4
APP_B_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8 APP_B_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8
APP_IMG_SZ = (APP_B_END_ADDR - APP_A_START_ADDR) // 2
CHUNK_SIZE = 400 CHUNK_SIZE = 400
@@ -58,6 +59,7 @@ PING_PAYLOAD_SIZE = 0
class ActionId(enum.IntEnum): class ActionId(enum.IntEnum):
CORRUPT_APP_A = 128 CORRUPT_APP_A = 128
CORRUPT_APP_B = 129 CORRUPT_APP_B = 129
SET_BOOT_SLOT = 130
_LOGGER = logging.getLogger(__name__) _LOGGER = logging.getLogger(__name__)
@@ -78,11 +80,37 @@ class Target(enum.Enum):
APP_B = 2 APP_B = 2
class AppSel(enum.IntEnum):
APP_A = 0
APP_B = 1
class ImageLoader: class ImageLoader:
def __init__(self, com_if: ComInterface, verificator: PusVerificator) -> None: def __init__(self, com_if: ComInterface, verificator: PusVerificator) -> None:
self.com_if = com_if self.com_if = com_if
self.verificator = verificator self.verificator = verificator
def handle_boot_sel_cmd(self, target: AppSel):
_LOGGER.info("Sending ping command")
action_tc = PusTc(
apid=0x00,
service=PusService.S8_FUNC_CMD,
subservice=ActionId.SET_BOOT_SLOT,
seq_count=SEQ_PROVIDER.get_and_increment(),
app_data=bytes([target]),
)
self.verificator.add_tc(action_tc)
self.com_if.send(bytes(action_tc.pack()))
data_available = self.com_if.data_available(0.4)
if not data_available:
_LOGGER.warning("no reply received for boot image selection command")
for reply in self.com_if.receive():
result = self.verificator.add_tm(
Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0))
)
if result is not None and result.completed:
_LOGGER.info("received boot image selection command confirmation")
def handle_ping_cmd(self): def handle_ping_cmd(self):
_LOGGER.info("Sending ping command") _LOGGER.info("Sending ping command")
ping_tc = PusTc( ping_tc = PusTc(
@@ -106,7 +134,6 @@ class ImageLoader:
_LOGGER.info("received ping completion reply") _LOGGER.info("received ping completion reply")
def handle_corruption_cmd(self, target: Target): def handle_corruption_cmd(self, target: Target):
if target == Target.BOOTLOADER: if target == Target.BOOTLOADER:
_LOGGER.error("can not corrupt bootloader") _LOGGER.error("can not corrupt bootloader")
if target == Target.APP_A: if target == Target.APP_A:
@@ -131,7 +158,8 @@ class ImageLoader:
_LOGGER.info("Parsing ELF file for loadable sections") _LOGGER.info("Parsing ELF file for loadable sections")
total_size = 0 total_size = 0
loadable_segments, total_size = create_loadable_segments(target, file_path) loadable_segments, total_size = create_loadable_segments(target, file_path)
segments_info_str(target, loadable_segments, total_size, file_path) check_segments(target, total_size)
print_segments_info(target, loadable_segments, total_size, file_path)
result = self._perform_flashing_algorithm(loadable_segments) result = self._perform_flashing_algorithm(loadable_segments)
if result != 0: if result != 0:
return result return result
@@ -251,6 +279,9 @@ def main() -> int:
prog="image-loader", description="Python VA416XX Image Loader Application" prog="image-loader", description="Python VA416XX Image Loader Application"
) )
parser.add_argument("-p", "--ping", action="store_true", help="Send ping command") parser.add_argument("-p", "--ping", action="store_true", help="Send ping command")
parser.add_argument(
"-s", "--sel", choices=["a", "b"], help="Set boot slot (Slot A or B)"
)
parser.add_argument("-c", "--corrupt", action="store_true", help="Corrupt a target") parser.add_argument("-c", "--corrupt", action="store_true", help="Corrupt a target")
parser.add_argument( parser.add_argument(
"-t", "-t",
@@ -286,6 +317,14 @@ def main() -> int:
target = Target.APP_A target = Target.APP_A
elif args.target == "b": elif args.target == "b":
target = Target.APP_B target = Target.APP_B
boot_sel = None
if args.sel:
if args.sel == "a":
boot_sel = AppSel.APP_A
elif args.sel == "b":
boot_sel = AppSel.APP_B
image_loader = ImageLoader(com_if, verificator) image_loader = ImageLoader(com_if, verificator)
file_path = None file_path = None
result = -1 result = -1
@@ -293,6 +332,8 @@ def main() -> int:
image_loader.handle_ping_cmd() image_loader.handle_ping_cmd()
com_if.close() com_if.close()
return 0 return 0
if args.sel and boot_sel is not None:
image_loader.handle_boot_sel_cmd(boot_sel)
if target: if target:
if not args.corrupt: if not args.corrupt:
if not args.path: if not args.path:
@@ -307,7 +348,7 @@ def main() -> int:
return -1 return -1
image_loader.handle_corruption_cmd(target) image_loader.handle_corruption_cmd(target)
else: else:
assert file_path is not None if file_path is not None:
assert target is not None assert target is not None
result = image_loader.handle_flash_cmd(target, file_path) result = image_loader.handle_flash_cmd(target, file_path)
@@ -377,7 +418,22 @@ def create_loadable_segments(
return loadable_segments, total_size return loadable_segments, total_size
def segments_info_str( def check_segments(
target: Target,
total_size: int,
):
# Set context string and perform basic sanity checks.
if target == Target.BOOTLOADER and total_size > BOOTLOADER_MAX_SIZE:
raise ValueError(
f"provided bootloader app larger than allowed {total_size} bytes"
)
elif target == Target.APP_A and total_size > APP_A_MAX_SIZE:
raise ValueError(f"provided App A larger than allowed {total_size} bytes")
elif target == Target.APP_B and total_size > APP_B_MAX_SIZE:
raise ValueError(f"provided App B larger than allowed {total_size} bytes")
def print_segments_info(
target: Target, target: Target,
loadable_segments: List[LoadableSegment], loadable_segments: List[LoadableSegment],
total_size: int, total_size: int,
@@ -385,21 +441,10 @@ def segments_info_str(
): ):
# Set context string and perform basic sanity checks. # Set context string and perform basic sanity checks.
if target == Target.BOOTLOADER: if target == Target.BOOTLOADER:
if total_size > BOOTLOADER_MAX_SIZE:
_LOGGER.error(
f"provided bootloader app larger than allowed {total_size} bytes"
)
return -1
context_str = "Bootloader" context_str = "Bootloader"
elif target == Target.APP_A: elif target == Target.APP_A:
if total_size > APP_A_MAX_SIZE:
_LOGGER.error(f"provided App A larger than allowed {total_size} bytes")
return -1
context_str = "App Slot A" context_str = "App Slot A"
elif target == Target.APP_B: elif target == Target.APP_B:
if total_size > APP_B_MAX_SIZE:
_LOGGER.error(f"provided App B larger than allowed {total_size} bytes")
return -1
context_str = "App Slot B" context_str = "App Slot B"
_LOGGER.info(f"Flashing {context_str} with image {file_path} (size {total_size})") _LOGGER.info(f"Flashing {context_str} with image {file_path} (size {total_size})")
for idx, segment in enumerate(loadable_segments): for idx, segment in enumerate(loadable_segments):

View File

@@ -1,7 +1,7 @@
/* Special linker script for application slot A with an offset at address 0x3000 */ /* Special linker script for application slot A with an offset at address 0x3000 */
MEMORY MEMORY
{ {
FLASH : ORIGIN = 0x00003000, LENGTH = 0xE800 FLASH : ORIGIN = 0x00003000, LENGTH = 0xE7FC
RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */
} }

View File

@@ -1,7 +1,7 @@
/* Special linker script for application slot B with an offset at address 0x11800 */ /* Special linker script for application slot B */
MEMORY MEMORY
{ {
FLASH : ORIGIN = 0x00011800, LENGTH = 0xE800 FLASH : ORIGIN = 0x000117FC, LENGTH = 0xE7FC
RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */ RAM : ORIGIN = 0x10000000, LENGTH = 0x08000 /* 32K */
} }

View File

@@ -3,11 +3,11 @@
#![no_main] #![no_main]
#![no_std] #![no_std]
use once_cell::sync::Lazy; use num_enum::TryFromPrimitive;
use panic_rtt_target as _; use panic_rtt_target as _;
use ringbuf::{ use ringbuf::{
traits::{Consumer, Observer, Producer, SplitRef}, traits::{Consumer, Observer, Producer},
CachingCons, StaticProd, StaticRb, StaticRb,
}; };
use va108xx_hal::prelude::*; use va108xx_hal::prelude::*;
@@ -26,6 +26,14 @@ const RX_DEBUGGING: bool = false;
pub enum ActionId { pub enum ActionId {
CorruptImageA = 128, CorruptImageA = 128,
CorruptImageB = 129, CorruptImageB = 129,
SetBootSlot = 130,
}
#[derive(Debug, Copy, Clone, PartialEq, Eq, TryFromPrimitive)]
#[repr(u8)]
enum AppSel {
A = 0,
B = 1,
} }
// Larger buffer for TC to be able to hold the possibly large memory write packets. // Larger buffer for TC to be able to hold the possibly large memory write packets.
@@ -35,33 +43,18 @@ const SIZES_RB_SIZE_TC: usize = 16;
const BUF_RB_SIZE_TM: usize = 256; const BUF_RB_SIZE_TM: usize = 256;
const SIZES_RB_SIZE_TM: usize = 16; const SIZES_RB_SIZE_TM: usize = 16;
// Ring buffers to handling variable sized telemetry pub struct RingBufWrapper<const BUF_SIZE: usize, const SIZES_LEN: usize> {
static mut BUF_RB_TM: Lazy<StaticRb<u8, BUF_RB_SIZE_TM>> = pub buf: StaticRb<u8, BUF_SIZE>,
Lazy::new(StaticRb::<u8, BUF_RB_SIZE_TM>::default); pub sizes: StaticRb<usize, SIZES_LEN>,
static mut SIZES_RB_TM: Lazy<StaticRb<usize, SIZES_RB_SIZE_TM>> =
Lazy::new(StaticRb::<usize, SIZES_RB_SIZE_TM>::default);
// Ring buffers to handling variable sized telecommands
static mut BUF_RB_TC: Lazy<StaticRb<u8, BUF_RB_SIZE_TC>> =
Lazy::new(StaticRb::<u8, BUF_RB_SIZE_TC>::default);
static mut SIZES_RB_TC: Lazy<StaticRb<usize, SIZES_RB_SIZE_TC>> =
Lazy::new(StaticRb::<usize, SIZES_RB_SIZE_TC>::default);
pub struct DataProducer<const BUF_SIZE: usize, const SIZES_LEN: usize> {
pub buf_prod: StaticProd<'static, u8, BUF_SIZE>,
pub sizes_prod: StaticProd<'static, usize, SIZES_LEN>,
}
pub struct DataConsumer<const BUF_SIZE: usize, const SIZES_LEN: usize> {
pub buf_cons: CachingCons<&'static StaticRb<u8, BUF_SIZE>>,
pub sizes_cons: CachingCons<&'static StaticRb<usize, SIZES_LEN>>,
} }
pub const APP_A_START_ADDR: u32 = 0x3000; pub const APP_A_START_ADDR: u32 = 0x3000;
pub const APP_A_END_ADDR: u32 = 0x11800; pub const APP_A_END_ADDR: u32 = 0x117FC;
pub const APP_B_START_ADDR: u32 = APP_A_END_ADDR; pub const APP_B_START_ADDR: u32 = APP_A_END_ADDR;
pub const APP_B_END_ADDR: u32 = 0x20000; pub const APP_B_END_ADDR: u32 = 0x20000;
pub const PREFERRED_SLOT_OFFSET: u32 = 0x20000 - 1;
#[rtic::app(device = pac, dispatchers = [OC20, OC21, OC22])] #[rtic::app(device = pac, dispatchers = [OC20, OC21, OC22])]
mod app { mod app {
use super::*; use super::*;
@@ -94,12 +87,6 @@ mod app {
uart_rx: uart::RxWithIrq<pac::Uarta>, uart_rx: uart::RxWithIrq<pac::Uarta>,
uart_tx: uart::Tx<pac::Uarta>, uart_tx: uart::Tx<pac::Uarta>,
rx_context: IrqContextTimeoutOrMaxSize, rx_context: IrqContextTimeoutOrMaxSize,
// We handle all TM in one task.
tm_cons: DataConsumer<BUF_RB_SIZE_TM, SIZES_RB_SIZE_TM>,
// We consume all TC in one task.
tc_cons: DataConsumer<BUF_RB_SIZE_TC, SIZES_RB_SIZE_TC>,
// We produce all TC in one task.
tc_prod: DataProducer<BUF_RB_SIZE_TC, SIZES_RB_SIZE_TC>,
verif_reporter: VerificationReportCreator, verif_reporter: VerificationReportCreator,
nvm: M95M01, nvm: M95M01,
} }
@@ -107,7 +94,8 @@ mod app {
#[shared] #[shared]
struct Shared { struct Shared {
// Having this shared allows multiple tasks to generate telemetry. // Having this shared allows multiple tasks to generate telemetry.
tm_prod: DataProducer<BUF_RB_SIZE_TM, SIZES_RB_SIZE_TM>, tm_rb: RingBufWrapper<BUF_RB_SIZE_TM, SIZES_RB_SIZE_TM>,
tc_rb: RingBufWrapper<BUF_RB_SIZE_TC, SIZES_RB_SIZE_TC>,
} }
rtic_monotonics::systick_monotonic!(Mono, 1000); rtic_monotonics::systick_monotonic!(Mono, 1000);
@@ -138,12 +126,6 @@ mod app {
let verif_reporter = VerificationReportCreator::new(0).unwrap(); let verif_reporter = VerificationReportCreator::new(0).unwrap();
let (buf_prod_tm, buf_cons_tm) = unsafe { BUF_RB_TM.split_ref() };
let (sizes_prod_tm, sizes_cons_tm) = unsafe { SIZES_RB_TM.split_ref() };
let (buf_prod_tc, buf_cons_tc) = unsafe { BUF_RB_TC.split_ref() };
let (sizes_prod_tc, sizes_cons_tc) = unsafe { SIZES_RB_TC.split_ref() };
let mut rx_context = IrqContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE); let mut rx_context = IrqContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE);
rx.read_fixed_len_or_timeout_based_using_irq(&mut rx_context) rx.read_fixed_len_or_timeout_based_using_irq(&mut rx_context)
.expect("initiating UART RX failed"); .expect("initiating UART RX failed");
@@ -151,27 +133,19 @@ mod app {
pus_tm_tx_handler::spawn().unwrap(); pus_tm_tx_handler::spawn().unwrap();
( (
Shared { Shared {
tm_prod: DataProducer { tc_rb: RingBufWrapper {
buf_prod: buf_prod_tm, buf: StaticRb::default(),
sizes_prod: sizes_prod_tm, sizes: StaticRb::default(),
},
tm_rb: RingBufWrapper {
buf: StaticRb::default(),
sizes: StaticRb::default(),
}, },
}, },
Local { Local {
uart_rx: rx, uart_rx: rx,
uart_tx: tx, uart_tx: tx,
rx_context, rx_context,
tm_cons: DataConsumer {
buf_cons: buf_cons_tm,
sizes_cons: sizes_cons_tm,
},
tc_cons: DataConsumer {
buf_cons: buf_cons_tc,
sizes_cons: sizes_cons_tc,
},
tc_prod: DataProducer {
buf_prod: buf_prod_tc,
sizes_prod: sizes_prod_tc,
},
verif_reporter, verif_reporter,
nvm, nvm,
}, },
@@ -194,10 +168,10 @@ mod app {
rx_buf: [u8; MAX_TC_FRAME_SIZE] = [0; MAX_TC_FRAME_SIZE], rx_buf: [u8; MAX_TC_FRAME_SIZE] = [0; MAX_TC_FRAME_SIZE],
rx_context, rx_context,
uart_rx, uart_rx,
tc_prod
], ],
shared = [tc_rb]
)] )]
fn uart_rx_irq(cx: uart_rx_irq::Context) { fn uart_rx_irq(mut cx: uart_rx_irq::Context) {
match cx match cx
.local .local
.uart_rx .uart_rx
@@ -220,16 +194,17 @@ mod app {
log::warn!("COBS decoding failed"); log::warn!("COBS decoding failed");
} else { } else {
let decoded_size = decoded_size.unwrap(); let decoded_size = decoded_size.unwrap();
if cx.local.tc_prod.sizes_prod.vacant_len() >= 1 let mut tc_rb_full = false;
&& cx.local.tc_prod.buf_prod.vacant_len() >= decoded_size cx.shared.tc_rb.lock(|rb| {
if rb.sizes.vacant_len() >= 1 && rb.buf.vacant_len() >= decoded_size
{ {
// Should never fail, we checked there is enough space. rb.sizes.try_push(decoded_size).unwrap();
cx.local.tc_prod.sizes_prod.try_push(decoded_size).unwrap(); rb.buf.push_slice(&cx.local.rx_buf[1..1 + decoded_size]);
cx.local
.tc_prod
.buf_prod
.push_slice(&cx.local.rx_buf[1..1 + decoded_size]);
} else { } else {
tc_rb_full = true;
}
});
if tc_rb_full {
log::warn!("COBS TC queue full"); log::warn!("COBS TC queue full");
} }
} }
@@ -260,16 +235,15 @@ mod app {
readback_buf: [u8; MAX_TC_SIZE] = [0; MAX_TC_SIZE], readback_buf: [u8; MAX_TC_SIZE] = [0; MAX_TC_SIZE],
src_data_buf: [u8; 16] = [0; 16], src_data_buf: [u8; 16] = [0; 16],
verif_buf: [u8; 32] = [0; 32], verif_buf: [u8; 32] = [0; 32],
tc_cons,
nvm, nvm,
verif_reporter verif_reporter
], ],
shared=[tm_prod] shared=[tm_rb, tc_rb]
)] )]
async fn pus_tc_handler(mut cx: pus_tc_handler::Context) { async fn pus_tc_handler(mut cx: pus_tc_handler::Context) {
loop { loop {
// Try to read a TC from the ring buffer. // Try to read a TC from the ring buffer.
let packet_len = cx.local.tc_cons.sizes_cons.try_pop(); let packet_len = cx.shared.tc_rb.lock(|rb| rb.sizes.try_pop());
if packet_len.is_none() { if packet_len.is_none() {
// Small delay, TCs might arrive very quickly. // Small delay, TCs might arrive very quickly.
Mono::delay(20.millis()).await; Mono::delay(20.millis()).await;
@@ -277,13 +251,11 @@ mod app {
} }
let packet_len = packet_len.unwrap(); let packet_len = packet_len.unwrap();
log::info!(target: "TC Handler", "received packet with length {}", packet_len); log::info!(target: "TC Handler", "received packet with length {}", packet_len);
assert_eq!( let popped_packet_len = cx.shared.tc_rb.lock(|rb| {
cx.local rb.buf
.tc_cons .pop_slice(&mut cx.local.tc_buf[0..packet_len])
.buf_cons });
.pop_slice(&mut cx.local.tc_buf[0..packet_len]), assert_eq!(popped_packet_len, packet_len);
packet_len
);
// Read a telecommand, now handle it. // Read a telecommand, now handle it.
handle_valid_pus_tc(&mut cx); handle_valid_pus_tc(&mut cx);
} }
@@ -298,9 +270,9 @@ mod app {
let (pus_tc, _) = pus_tc.unwrap(); let (pus_tc, _) = pus_tc.unwrap();
let mut write_and_send = |tm: &PusTmCreator| { let mut write_and_send = |tm: &PusTmCreator| {
let written_size = tm.write_to_bytes(cx.local.verif_buf).unwrap(); let written_size = tm.write_to_bytes(cx.local.verif_buf).unwrap();
cx.shared.tm_prod.lock(|prod| { cx.shared.tm_rb.lock(|prod| {
prod.sizes_prod.try_push(tm.len_written()).unwrap(); prod.sizes.try_push(tm.len_written()).unwrap();
prod.buf_prod prod.buf
.push_slice(&cx.local.verif_buf[0..written_size]); .push_slice(&cx.local.verif_buf[0..written_size]);
}); });
}; };
@@ -346,6 +318,26 @@ mod app {
rprintln!("corrupting App Image B"); rprintln!("corrupting App Image B");
corrupt_image(APP_B_START_ADDR); corrupt_image(APP_B_START_ADDR);
} }
if pus_tc.subservice() == ActionId::SetBootSlot as u8 {
if pus_tc.app_data().is_empty() {
log::warn!(target: "TC Handler", "App data for preferred image command too short");
}
let app_sel_result = AppSel::try_from(pus_tc.app_data()[0]);
if app_sel_result.is_err() {
log::warn!("Invalid app selection value: {}", pus_tc.app_data()[0]);
}
log::info!(target: "TC Handler", "received boot selection command with app select: {:?}", app_sel_result.unwrap());
cx.local
.nvm
.write(PREFERRED_SLOT_OFFSET as usize, &[pus_tc.app_data()[0]])
.expect("writing to NVM failed");
let tm = cx
.local
.verif_reporter
.completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
.expect("completion success failed");
write_and_send(&tm);
}
} }
if pus_tc.service() == PusServiceId::Test as u8 && pus_tc.subservice() == 1 { if pus_tc.service() == PusServiceId::Test as u8 && pus_tc.subservice() == 1 {
log::info!(target: "TC Handler", "received ping TC"); log::info!(target: "TC Handler", "received ping TC");
@@ -444,18 +436,18 @@ mod app {
read_buf: [u8;MAX_TM_SIZE] = [0; MAX_TM_SIZE], read_buf: [u8;MAX_TM_SIZE] = [0; MAX_TM_SIZE],
encoded_buf: [u8;MAX_TM_FRAME_SIZE] = [0; MAX_TM_FRAME_SIZE], encoded_buf: [u8;MAX_TM_FRAME_SIZE] = [0; MAX_TM_FRAME_SIZE],
uart_tx, uart_tx,
tm_cons
], ],
shared=[] shared=[tm_rb]
)] )]
async fn pus_tm_tx_handler(cx: pus_tm_tx_handler::Context) { async fn pus_tm_tx_handler(mut cx: pus_tm_tx_handler::Context) {
loop { loop {
while cx.local.tm_cons.sizes_cons.occupied_len() > 0 { let mut occupied_len = cx.shared.tm_rb.lock(|rb| rb.sizes.occupied_len());
let next_size = cx.local.tm_cons.sizes_cons.try_pop().unwrap(); while occupied_len > 0 {
cx.local let next_size = cx.shared.tm_rb.lock(|rb| {
.tm_cons let next_size = rb.sizes.try_pop().unwrap();
.buf_cons rb.buf.pop_slice(&mut cx.local.read_buf[0..next_size]);
.pop_slice(&mut cx.local.read_buf[0..next_size]); next_size
});
cx.local.encoded_buf[0] = 0; cx.local.encoded_buf[0] = 0;
let send_size = cobs::encode( let send_size = cobs::encode(
&cx.local.read_buf[0..next_size], &cx.local.read_buf[0..next_size],
@@ -466,6 +458,7 @@ mod app {
.uart_tx .uart_tx
.write(&cx.local.encoded_buf[0..send_size + 2]) .write(&cx.local.encoded_buf[0..send_size + 2])
.unwrap(); .unwrap();
occupied_len -= 1;
Mono::delay(2.millis()).await; Mono::delay(2.millis()).await;
} }
Mono::delay(50.millis()).await; Mono::delay(50.millis()).await;

View File

@@ -1,3 +1,3 @@
#!/bin/bash #!/bin/bash
JLinkGDBServer -select USB -device Cortex-M0 -endian little -if JTAG-speed auto \ JLinkGDBServer -select USB -device Cortex-M0 -endian little -if JTAG -speed auto \
-LocalhostOnly -LocalhostOnly

View File

@@ -9,6 +9,7 @@ variants:
core_access_options: !Arm core_access_options: !Arm
ap: 0 ap: 0
psel: 0x0 psel: 0x0
jtag_tap: 1
memory_map: memory_map:
- !Ram - !Ram
name: DRAM name: DRAM
@@ -22,9 +23,11 @@ variants:
range: range:
start: 0x0 start: 0x0
end: 0x20000 end: 0x20000
is_boot_memory: true
cores: cores:
- main - main
access:
write: false
boot: true
flash_algorithms: flash_algorithms:
- va108xx_fm25v20a_fram_128kb_prog - va108xx_fm25v20a_fram_128kb_prog
- va108xx_m95m01_128kb_prog - va108xx_m95m01_128kb_prog
@@ -37,6 +40,7 @@ variants:
core_access_options: !Arm core_access_options: !Arm
ap: 0 ap: 0
psel: 0x0 psel: 0x0
jtag_tap: 1
memory_map: memory_map:
- !Ram - !Ram
name: DRAM name: DRAM
@@ -50,9 +54,11 @@ variants:
range: range:
start: 0x0 start: 0x0
end: 0x20000 end: 0x20000
is_boot_memory: true
cores: cores:
- main - main
access:
write: false
boot: true
flash_algorithms: flash_algorithms:
- name: va108xx_fm25v20a_fram_128kb_prog - name: va108xx_fm25v20a_fram_128kb_prog
description: VA108_FM25V20A_FRAM_128KB description: VA108_FM25V20A_FRAM_128KB

View File

@@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased] ## [unreleased]
## [v0.9.0] 2024-10-07
- Deleted some HAL re-exports in the PWM module
## [v0.8.0] 2024-09-30 ## [v0.8.0] 2024-09-30
## Changed ## Changed

View File

@@ -320,7 +320,6 @@ macro_rules! pin_id {
//================================================================================================== //==================================================================================================
/// A type-level GPIO pin, parameterized by [PinId] and [PinMode] types /// A type-level GPIO pin, parameterized by [PinId] and [PinMode] types
pub struct Pin<I: PinId, M: PinMode> { pub struct Pin<I: PinId, M: PinMode> {
pub(in crate::gpio) regs: Registers<I>, pub(in crate::gpio) regs: Registers<I>,
mode: PhantomData<M>, mode: PhantomData<M>,

View File

@@ -9,11 +9,11 @@ use core::convert::Infallible;
use core::marker::PhantomData; use core::marker::PhantomData;
use crate::pac; use crate::pac;
use crate::time::Hertz;
use crate::timer::{ use crate::timer::{
TimAndPinRegister, TimDynRegister, TimPin, TimRegInterface, ValidTim, ValidTimAndPin, TimAndPinRegister, TimDynRegister, TimPin, TimRegInterface, ValidTim, ValidTimAndPin,
}; };
use crate::{clock::enable_peripheral_clock, gpio::DynPinId}; use crate::{clock::enable_peripheral_clock, gpio::DynPinId};
pub use crate::{gpio::PinId, time::Hertz};
const DUTY_MAX: u16 = u16::MAX; const DUTY_MAX: u16 = u16::MAX;

View File

@@ -284,17 +284,17 @@ impl IrqResultMaxSizeOrTimeout {
#[inline] #[inline]
pub fn overflow_error(&self) -> bool { pub fn overflow_error(&self) -> bool {
self.errors.map_or(false, |e| e.overflow) self.errors.is_some_and(|e| e.overflow)
} }
#[inline] #[inline]
pub fn framing_error(&self) -> bool { pub fn framing_error(&self) -> bool {
self.errors.map_or(false, |e| e.framing) self.errors.is_some_and(|e| e.framing)
} }
#[inline] #[inline]
pub fn parity_error(&self) -> bool { pub fn parity_error(&self) -> bool {
self.errors.map_or(false, |e| e.parity) self.errors.is_some_and(|e| e.parity)
} }
#[inline] #[inline]

View File

@@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased] ## [unreleased]
## [v0.4.0]
- Re-generated PAC with `svd2rust` v0.35.0
## [v0.3.0] 2024-06-16 ## [v0.3.0] 2024-06-16
- Re-generated PAC with `svd2rust` v0.33.3 - Re-generated PAC with `svd2rust` v0.33.3

View File

@@ -1,6 +1,6 @@
[package] [package]
name = "va108xx" name = "va108xx"
version = "0.3.0" version = "0.4.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"] authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021" edition = "2021"
description = "PAC for the Vorago VA108xx family of microcontrollers" description = "PAC for the Vorago VA108xx family of microcontrollers"

View File

@@ -24,7 +24,7 @@ features = ["rt"]
The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`. The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`.
For full details on the autgenerated API, please see the For full details on the autgenerated API, please see the
[svd2rust documentation](https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api). [svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/#peripheral-api).
## Regenerating the PAC ## Regenerating the PAC

View File

@@ -1,4 +1,4 @@
#!/bin/sh #!/bin/bash
# Use installed tool by default # Use installed tool by default
svd2rust_bin="svd2rust" svd2rust_bin="svd2rust"

View File

@@ -82,169 +82,6 @@ pub trait Resettable: RegisterSpec {
Self::RESET_VALUE Self::RESET_VALUE
} }
} }
#[doc = " This structure provides volatile access to registers."]
#[repr(transparent)]
pub struct Reg<REG: RegisterSpec> {
register: vcell::VolatileCell<REG::Ux>,
_marker: marker::PhantomData<REG>,
}
unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
impl<REG: RegisterSpec> Reg<REG> {
#[doc = " Returns the underlying memory address of register."]
#[doc = ""]
#[doc = " ```ignore"]
#[doc = " let reg_ptr = periph.reg.as_ptr();"]
#[doc = " ```"]
#[inline(always)]
pub fn as_ptr(&self) -> *mut REG::Ux {
self.register.as_ptr()
}
}
impl<REG: Readable> Reg<REG> {
#[doc = " Reads the contents of a `Readable` register."]
#[doc = ""]
#[doc = " You can read the raw contents of a register by using `bits`:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.read().bits();"]
#[doc = " ```"]
#[doc = " or get the content of a particular field of a register:"]
#[doc = " ```ignore"]
#[doc = " let reader = periph.reg.read();"]
#[doc = " let bits = reader.field1().bits();"]
#[doc = " let flag = reader.field2().bit_is_set();"]
#[doc = " ```"]
#[inline(always)]
pub fn read(&self) -> R<REG> {
R {
bits: self.register.get(),
_reg: marker::PhantomData,
}
}
}
impl<REG: Resettable + Writable> Reg<REG> {
#[doc = " Writes the reset value to `Writable` register."]
#[doc = ""]
#[doc = " Resets the register to its initial state."]
#[inline(always)]
pub fn reset(&self) {
self.register.set(REG::RESET_VALUE)
}
#[doc = " Writes bits to a `Writable` register."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[inline(always)]
pub fn write<F>(&self, f: F)
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
self.register.set(
f(&mut W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
})
.bits,
);
}
}
impl<REG: Writable> Reg<REG> {
#[doc = " Writes 0 to a `Writable` register."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline(always)]
pub unsafe fn write_with_zero<F>(&self, f: F)
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
self.register.set(
f(&mut W {
bits: REG::Ux::default(),
_reg: marker::PhantomData,
})
.bits,
);
}
}
impl<REG: Readable + Writable> Reg<REG> {
#[doc = " Modifies the contents of the register by reading and then writing it."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
#[doc = " r.bits() | 3"]
#[doc = " ) });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline(always)]
pub fn modify<F>(&self, f: F)
where
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
{
let bits = self.register.get();
self.register.set(
f(
&R {
bits,
_reg: marker::PhantomData,
},
&mut W {
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
},
)
.bits,
);
}
}
impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
where
R<REG>: core::fmt::Debug,
{
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}
#[doc(hidden)] #[doc(hidden)]
pub mod raw; pub mod raw;
#[doc = " Register reader."] #[doc = " Register reader."]
@@ -369,7 +206,7 @@ pub struct RangeTo<const MAX: u64>;
#[doc = " Write field Proxy"] #[doc = " Write field Proxy"]
pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> = pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
raw::FieldWriter<'a, REG, WI, FI, Safety>; raw::FieldWriter<'a, REG, WI, FI, Safety>;
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
where where
REG: Writable + RegisterSpec, REG: Writable + RegisterSpec,
FI: FieldSpec, FI: FieldSpec,
@@ -616,3 +453,278 @@ where
self.w self.w
} }
} }
#[doc = " This structure provides volatile access to registers."]
#[repr(transparent)]
pub struct Reg<REG: RegisterSpec> {
register: vcell::VolatileCell<REG::Ux>,
_marker: marker::PhantomData<REG>,
}
unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
impl<REG: RegisterSpec> Reg<REG> {
#[doc = " Returns the underlying memory address of register."]
#[doc = ""]
#[doc = " ```ignore"]
#[doc = " let reg_ptr = periph.reg.as_ptr();"]
#[doc = " ```"]
#[inline(always)]
pub fn as_ptr(&self) -> *mut REG::Ux {
self.register.as_ptr()
}
}
impl<REG: Readable> Reg<REG> {
#[doc = " Reads the contents of a `Readable` register."]
#[doc = ""]
#[doc = " You can read the raw contents of a register by using `bits`:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.read().bits();"]
#[doc = " ```"]
#[doc = " or get the content of a particular field of a register:"]
#[doc = " ```ignore"]
#[doc = " let reader = periph.reg.read();"]
#[doc = " let bits = reader.field1().bits();"]
#[doc = " let flag = reader.field2().bit_is_set();"]
#[doc = " ```"]
#[inline(always)]
pub fn read(&self) -> R<REG> {
R {
bits: self.register.get(),
_reg: marker::PhantomData,
}
}
}
impl<REG: Resettable + Writable> Reg<REG> {
#[doc = " Writes the reset value to `Writable` register."]
#[doc = ""]
#[doc = " Resets the register to its initial state."]
#[inline(always)]
pub fn reset(&self) {
self.register.set(REG::RESET_VALUE)
}
#[doc = " Writes bits to a `Writable` register."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write(|w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[inline(always)]
pub fn write<F>(&self, f: F) -> REG::Ux
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let value = f(&mut W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
})
.bits;
self.register.set(value);
value
}
#[doc = " Writes bits to a `Writable` register and produce a value."]
#[doc = ""]
#[doc = " You can write raw bits into a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
#[doc = " ```"]
#[doc = " or write only the fields you need:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| {"]
#[doc = " w.field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.write_and(|w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " In the latter case, other fields will be set to their reset value."]
#[doc = ""]
#[doc = " Values can be returned from the closure:"]
#[doc = " ```ignore"]
#[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
#[doc = " ```"]
#[inline(always)]
pub fn from_write<F, T>(&self, f: F) -> T
where
F: FnOnce(&mut W<REG>) -> T,
{
let mut writer = W {
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
};
let result = f(&mut writer);
self.register.set(writer.bits);
result
}
}
impl<REG: Writable> Reg<REG> {
#[doc = " Writes 0 to a `Writable` register."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline(always)]
pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
where
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
{
let value = f(&mut W {
bits: REG::Ux::default(),
_reg: marker::PhantomData,
})
.bits;
self.register.set(value);
value
}
#[doc = " Writes 0 to a `Writable` register and produces a value."]
#[doc = ""]
#[doc = " Similar to `write`, but unused bits will contain 0."]
#[doc = ""]
#[doc = " # Safety"]
#[doc = ""]
#[doc = " Unsafe to use with registers which don't allow to write 0."]
#[inline(always)]
pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
where
F: FnOnce(&mut W<REG>) -> T,
{
let mut writer = W {
bits: REG::Ux::default(),
_reg: marker::PhantomData,
};
let result = f(&mut writer);
self.register.set(writer.bits);
result
}
}
impl<REG: Readable + Writable> Reg<REG> {
#[doc = " Modifies the contents of the register by reading and then writing it."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
#[doc = " r.bits() | 3"]
#[doc = " ) });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| w"]
#[doc = " .field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT)"]
#[doc = " );"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT)"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline(always)]
pub fn modify<F>(&self, f: F) -> REG::Ux
where
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
{
let bits = self.register.get();
let value = f(
&R {
bits,
_reg: marker::PhantomData,
},
&mut W {
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
},
)
.bits;
self.register.set(value);
value
}
#[doc = " Modifies the contents of the register by reading and then writing it"]
#[doc = " and produces a value."]
#[doc = ""]
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
#[doc = " ```ignore"]
#[doc = " let bits = periph.reg.modify(|r, w| {"]
#[doc = " let new_bits = r.bits() | 3;"]
#[doc = " unsafe {"]
#[doc = " w.bits(new_bits);"]
#[doc = " }"]
#[doc = ""]
#[doc = " new_bits"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits)"]
#[doc = " .field2().set_bit()"]
#[doc = " .field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " or an alternative way of saying the same:"]
#[doc = " ```ignore"]
#[doc = " periph.reg.modify(|_, w| {"]
#[doc = " w.field1().bits(newfield1bits);"]
#[doc = " w.field2().set_bit();"]
#[doc = " w.field3().variant(VARIANT);"]
#[doc = " });"]
#[doc = " ```"]
#[doc = " Other fields will have the value they had before the call to `modify`."]
#[inline(always)]
pub fn from_modify<F, T>(&self, f: F) -> T
where
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
{
let bits = self.register.get();
let mut writer = W {
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
_reg: marker::PhantomData,
};
let result = f(
&R {
bits,
_reg: marker::PhantomData,
},
&mut writer,
);
self.register.set(writer.bits);
result
}
}
impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
where
R<REG>: core::fmt::Debug,
{
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
core::fmt::Debug::fmt(&self.read(), f)
}
}

View File

@@ -41,6 +41,7 @@ impl<FI> BitReader<FI> {
} }
} }
} }
#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
where where
REG: Writable + RegisterSpec, REG: Writable + RegisterSpec,
@@ -66,6 +67,7 @@ where
} }
} }
} }
#[must_use = "after creating `BitWriter` you need to call bit setting method"]
pub struct BitWriter<'a, REG, FI = bool, M = BitM> pub struct BitWriter<'a, REG, FI = bool, M = BitM>
where where
REG: Writable + RegisterSpec, REG: Writable + RegisterSpec,

View File

@@ -240,67 +240,67 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] #[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
module"] module"]
#[doc(alias = "CTRL")] #[doc(alias = "CTRL")]
pub type Ctrl = crate::Reg<ctrl::CtrlSpec>; pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
#[doc = "Control Register"] #[doc = "Control Register"]
pub mod ctrl; pub mod ctrl;
#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] #[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
module"] module"]
#[doc(alias = "CLKSCALE")] #[doc(alias = "CLKSCALE")]
pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>; pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
#[doc = "Clock Scale divide value"] #[doc = "Clock Scale divide value"]
pub mod clkscale; pub mod clkscale;
#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`] #[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
module"] module"]
#[doc(alias = "WORDS")] #[doc(alias = "WORDS")]
pub type Words = crate::Reg<words::WordsSpec>; pub type Words = crate::Reg<words::WordsSpec>;
#[doc = "Word Count value"] #[doc = "Word Count value"]
pub mod words; pub mod words;
#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`] #[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
module"] module"]
#[doc(alias = "ADDRESS")] #[doc(alias = "ADDRESS")]
pub type Address = crate::Reg<address::AddressSpec>; pub type Address = crate::Reg<address::AddressSpec>;
#[doc = "I2C Address value"] #[doc = "I2C Address value"]
pub mod address; pub mod address;
#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] #[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"] module"]
#[doc(alias = "DATA")] #[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>; pub type Data = crate::Reg<data::DataSpec>;
#[doc = "Data Input/Output"] #[doc = "Data Input/Output"]
pub mod data; pub mod data;
#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] #[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
module"] module"]
#[doc(alias = "CMD")] #[doc(alias = "CMD")]
pub type Cmd = crate::Reg<cmd::CmdSpec>; pub type Cmd = crate::Reg<cmd::CmdSpec>;
#[doc = "Command Register"] #[doc = "Command Register"]
pub mod cmd; pub mod cmd;
#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] #[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"] module"]
#[doc(alias = "STATUS")] #[doc(alias = "STATUS")]
pub type Status = crate::Reg<status::StatusSpec>; pub type Status = crate::Reg<status::StatusSpec>;
#[doc = "I2C Controller Status Register"] #[doc = "I2C Controller Status Register"]
pub mod status; pub mod status;
#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] #[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
module"] module"]
#[doc(alias = "STATE")] #[doc(alias = "STATE")]
pub type State = crate::Reg<state::StateSpec>; pub type State = crate::Reg<state::StateSpec>;
#[doc = "Internal STATE of I2C Master Controller"] #[doc = "Internal STATE of I2C Master Controller"]
pub mod state; pub mod state;
#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`] #[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
module"] module"]
#[doc(alias = "TXCOUNT")] #[doc(alias = "TXCOUNT")]
pub type Txcount = crate::Reg<txcount::TxcountSpec>; pub type Txcount = crate::Reg<txcount::TxcountSpec>;
#[doc = "TX Count Register"] #[doc = "TX Count Register"]
pub mod txcount; pub mod txcount;
#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`] #[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
module"] module"]
#[doc(alias = "RXCOUNT")] #[doc(alias = "RXCOUNT")]
pub type Rxcount = crate::Reg<rxcount::RxcountSpec>; pub type Rxcount = crate::Reg<rxcount::RxcountSpec>;
#[doc = "RX Count Register"] #[doc = "RX Count Register"]
pub mod rxcount; pub mod rxcount;
#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] #[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"] module"]
#[doc(alias = "IRQ_ENB")] #[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>; pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
@@ -312,97 +312,97 @@ pub use irq_enb as irq_clr;
pub use IrqEnb as IrqRaw; pub use IrqEnb as IrqRaw;
pub use IrqEnb as IrqEnd; pub use IrqEnb as IrqEnd;
pub use IrqEnb as IrqClr; pub use IrqEnb as IrqClr;
#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] #[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
module"] module"]
#[doc(alias = "RXFIFOIRQTRG")] #[doc(alias = "RXFIFOIRQTRG")]
pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>; pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
#[doc = "Rx FIFO IRQ Trigger Level"] #[doc = "Rx FIFO IRQ Trigger Level"]
pub mod rxfifoirqtrg; pub mod rxfifoirqtrg;
#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] #[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
module"] module"]
#[doc(alias = "TXFIFOIRQTRG")] #[doc(alias = "TXFIFOIRQTRG")]
pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>; pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
#[doc = "Tx FIFO IRQ Trigger Level"] #[doc = "Tx FIFO IRQ Trigger Level"]
pub mod txfifoirqtrg; pub mod txfifoirqtrg;
#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] #[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
module"] module"]
#[doc(alias = "FIFO_CLR")] #[doc(alias = "FIFO_CLR")]
pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>; pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
#[doc = "Clear FIFO Register"] #[doc = "Clear FIFO Register"]
pub mod fifo_clr; pub mod fifo_clr;
#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`] #[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
module"] module"]
#[doc(alias = "TMCONFIG")] #[doc(alias = "TMCONFIG")]
pub type Tmconfig = crate::Reg<tmconfig::TmconfigSpec>; pub type Tmconfig = crate::Reg<tmconfig::TmconfigSpec>;
#[doc = "Timing Config Register"] #[doc = "Timing Config Register"]
pub mod tmconfig; pub mod tmconfig;
#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`] #[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
module"] module"]
#[doc(alias = "CLKTOLIMIT")] #[doc(alias = "CLKTOLIMIT")]
pub type Clktolimit = crate::Reg<clktolimit::ClktolimitSpec>; pub type Clktolimit = crate::Reg<clktolimit::ClktolimitSpec>;
#[doc = "Clock Low Timeout Limit Register"] #[doc = "Clock Low Timeout Limit Register"]
pub mod clktolimit; pub mod clktolimit;
#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`] #[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
module"] module"]
#[doc(alias = "S0_CTRL")] #[doc(alias = "S0_CTRL")]
pub type S0Ctrl = crate::Reg<s0_ctrl::S0CtrlSpec>; pub type S0Ctrl = crate::Reg<s0_ctrl::S0CtrlSpec>;
#[doc = "Slave Control Register"] #[doc = "Slave Control Register"]
pub mod s0_ctrl; pub mod s0_ctrl;
#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`] #[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
module"] module"]
#[doc(alias = "S0_MAXWORDS")] #[doc(alias = "S0_MAXWORDS")]
pub type S0Maxwords = crate::Reg<s0_maxwords::S0MaxwordsSpec>; pub type S0Maxwords = crate::Reg<s0_maxwords::S0MaxwordsSpec>;
#[doc = "Slave MaxWords Register"] #[doc = "Slave MaxWords Register"]
pub mod s0_maxwords; pub mod s0_maxwords;
#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`] #[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
module"] module"]
#[doc(alias = "S0_ADDRESS")] #[doc(alias = "S0_ADDRESS")]
pub type S0Address = crate::Reg<s0_address::S0AddressSpec>; pub type S0Address = crate::Reg<s0_address::S0AddressSpec>;
#[doc = "Slave I2C Address Value"] #[doc = "Slave I2C Address Value"]
pub mod s0_address; pub mod s0_address;
#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`] #[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
module"] module"]
#[doc(alias = "S0_ADDRESSMASK")] #[doc(alias = "S0_ADDRESSMASK")]
pub type S0Addressmask = crate::Reg<s0_addressmask::S0AddressmaskSpec>; pub type S0Addressmask = crate::Reg<s0_addressmask::S0AddressmaskSpec>;
#[doc = "Slave I2C Address Mask value"] #[doc = "Slave I2C Address Mask value"]
pub mod s0_addressmask; pub mod s0_addressmask;
#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`] #[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
module"] module"]
#[doc(alias = "S0_DATA")] #[doc(alias = "S0_DATA")]
pub type S0Data = crate::Reg<s0_data::S0DataSpec>; pub type S0Data = crate::Reg<s0_data::S0DataSpec>;
#[doc = "Slave Data Input/Output"] #[doc = "Slave Data Input/Output"]
pub mod s0_data; pub mod s0_data;
#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`] #[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
module"] module"]
#[doc(alias = "S0_LASTADDRESS")] #[doc(alias = "S0_LASTADDRESS")]
pub type S0Lastaddress = crate::Reg<s0_lastaddress::S0LastaddressSpec>; pub type S0Lastaddress = crate::Reg<s0_lastaddress::S0LastaddressSpec>;
#[doc = "Slave I2C Last Address value"] #[doc = "Slave I2C Last Address value"]
pub mod s0_lastaddress; pub mod s0_lastaddress;
#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`] #[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
module"] module"]
#[doc(alias = "S0_STATUS")] #[doc(alias = "S0_STATUS")]
pub type S0Status = crate::Reg<s0_status::S0StatusSpec>; pub type S0Status = crate::Reg<s0_status::S0StatusSpec>;
#[doc = "Slave I2C Controller Status Register"] #[doc = "Slave I2C Controller Status Register"]
pub mod s0_status; pub mod s0_status;
#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`] #[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
module"] module"]
#[doc(alias = "S0_STATE")] #[doc(alias = "S0_STATE")]
pub type S0State = crate::Reg<s0_state::S0StateSpec>; pub type S0State = crate::Reg<s0_state::S0StateSpec>;
#[doc = "Internal STATE of I2C Slave Controller"] #[doc = "Internal STATE of I2C Slave Controller"]
pub mod s0_state; pub mod s0_state;
#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`] #[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
module"] module"]
#[doc(alias = "S0_TXCOUNT")] #[doc(alias = "S0_TXCOUNT")]
pub type S0Txcount = crate::Reg<s0_txcount::S0TxcountSpec>; pub type S0Txcount = crate::Reg<s0_txcount::S0TxcountSpec>;
#[doc = "Slave TX Count Register"] #[doc = "Slave TX Count Register"]
pub mod s0_txcount; pub mod s0_txcount;
#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`] #[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
module"] module"]
#[doc(alias = "S0_RXCOUNT")] #[doc(alias = "S0_RXCOUNT")]
pub type S0Rxcount = crate::Reg<s0_rxcount::S0RxcountSpec>; pub type S0Rxcount = crate::Reg<s0_rxcount::S0RxcountSpec>;
#[doc = "Slave RX Count Register"] #[doc = "Slave RX Count Register"]
pub mod s0_rxcount; pub mod s0_rxcount;
#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`] #[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
module"] module"]
#[doc(alias = "S0_IRQ_ENB")] #[doc(alias = "S0_IRQ_ENB")]
pub type S0IrqEnb = crate::Reg<s0_irq_enb::S0IrqEnbSpec>; pub type S0IrqEnb = crate::Reg<s0_irq_enb::S0IrqEnbSpec>;
@@ -414,37 +414,37 @@ pub use s0_irq_enb as s0_irq_clr;
pub use S0IrqEnb as S0IrqRaw; pub use S0IrqEnb as S0IrqRaw;
pub use S0IrqEnb as S0IrqEnd; pub use S0IrqEnb as S0IrqEnd;
pub use S0IrqEnb as S0IrqClr; pub use S0IrqEnb as S0IrqClr;
#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`] #[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
module"] module"]
#[doc(alias = "S0_RXFIFOIRQTRG")] #[doc(alias = "S0_RXFIFOIRQTRG")]
pub type S0Rxfifoirqtrg = crate::Reg<s0_rxfifoirqtrg::S0RxfifoirqtrgSpec>; pub type S0Rxfifoirqtrg = crate::Reg<s0_rxfifoirqtrg::S0RxfifoirqtrgSpec>;
#[doc = "Slave Rx FIFO IRQ Trigger Level"] #[doc = "Slave Rx FIFO IRQ Trigger Level"]
pub mod s0_rxfifoirqtrg; pub mod s0_rxfifoirqtrg;
#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`] #[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
module"] module"]
#[doc(alias = "S0_TXFIFOIRQTRG")] #[doc(alias = "S0_TXFIFOIRQTRG")]
pub type S0Txfifoirqtrg = crate::Reg<s0_txfifoirqtrg::S0TxfifoirqtrgSpec>; pub type S0Txfifoirqtrg = crate::Reg<s0_txfifoirqtrg::S0TxfifoirqtrgSpec>;
#[doc = "Slave Tx FIFO IRQ Trigger Level"] #[doc = "Slave Tx FIFO IRQ Trigger Level"]
pub mod s0_txfifoirqtrg; pub mod s0_txfifoirqtrg;
#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`] #[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
module"] module"]
#[doc(alias = "S0_FIFO_CLR")] #[doc(alias = "S0_FIFO_CLR")]
pub type S0FifoClr = crate::Reg<s0_fifo_clr::S0FifoClrSpec>; pub type S0FifoClr = crate::Reg<s0_fifo_clr::S0FifoClrSpec>;
#[doc = "Slave Clear FIFO Register"] #[doc = "Slave Clear FIFO Register"]
pub mod s0_fifo_clr; pub mod s0_fifo_clr;
#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`] #[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
module"] module"]
#[doc(alias = "S0_ADDRESSB")] #[doc(alias = "S0_ADDRESSB")]
pub type S0Addressb = crate::Reg<s0_addressb::S0AddressbSpec>; pub type S0Addressb = crate::Reg<s0_addressb::S0AddressbSpec>;
#[doc = "Slave I2C Address B Value"] #[doc = "Slave I2C Address B Value"]
pub mod s0_addressb; pub mod s0_addressb;
#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`] #[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
module"] module"]
#[doc(alias = "S0_ADDRESSMASKB")] #[doc(alias = "S0_ADDRESSMASKB")]
pub type S0Addressmaskb = crate::Reg<s0_addressmaskb::S0AddressmaskbSpec>; pub type S0Addressmaskb = crate::Reg<s0_addressmaskb::S0AddressmaskbSpec>;
#[doc = "Slave I2C Address B Mask value"] #[doc = "Slave I2C Address B Mask value"]
pub mod s0_addressmaskb; pub mod s0_addressmaskb;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"] module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;

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@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AddressSpec; pub struct AddressSpec;
impl crate::RegisterSpec for AddressSpec { impl crate::RegisterSpec for AddressSpec {
type Ux = u32; type Ux = u32;

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@@ -25,18 +25,16 @@ impl R {
impl W { impl W {
#[doc = "Bits 0:30 - Enable FastMode"] #[doc = "Bits 0:30 - Enable FastMode"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn value(&mut self) -> ValueW<ClkscaleSpec> { pub fn value(&mut self) -> ValueW<ClkscaleSpec> {
ValueW::new(self, 0) ValueW::new(self, 0)
} }
#[doc = "Bit 31 - Enable FastMode"] #[doc = "Bit 31 - Enable FastMode"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn fastmode(&mut self) -> FastmodeW<ClkscaleSpec> { pub fn fastmode(&mut self) -> FastmodeW<ClkscaleSpec> {
FastmodeW::new(self, 31) FastmodeW::new(self, 31)
} }
} }
#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClkscaleSpec; pub struct ClkscaleSpec;
impl crate::RegisterSpec for ClkscaleSpec { impl crate::RegisterSpec for ClkscaleSpec {
type Ux = u32; type Ux = u32;

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@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClktolimitSpec; pub struct ClktolimitSpec;
impl crate::RegisterSpec for ClktolimitSpec { impl crate::RegisterSpec for ClktolimitSpec {
type Ux = u32; type Ux = u32;

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@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmdSpec; pub struct CmdSpec;
impl crate::RegisterSpec for CmdSpec { impl crate::RegisterSpec for CmdSpec {
type Ux = u32; type Ux = u32;

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@@ -88,60 +88,51 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - I2C CLK Enabled"] #[doc = "Bit 0 - I2C CLK Enabled"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn clkenabled(&mut self) -> ClkenabledW<CtrlSpec> { pub fn clkenabled(&mut self) -> ClkenabledW<CtrlSpec> {
ClkenabledW::new(self, 0) ClkenabledW::new(self, 0)
} }
#[doc = "Bit 1 - I2C Activated"] #[doc = "Bit 1 - I2C Activated"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn enabled(&mut self) -> EnabledW<CtrlSpec> { pub fn enabled(&mut self) -> EnabledW<CtrlSpec> {
EnabledW::new(self, 1) EnabledW::new(self, 1)
} }
#[doc = "Bit 2 - I2C Active"] #[doc = "Bit 2 - I2C Active"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn enable(&mut self) -> EnableW<CtrlSpec> { pub fn enable(&mut self) -> EnableW<CtrlSpec> {
EnableW::new(self, 2) EnableW::new(self, 2)
} }
#[doc = "Bit 3 - TX FIFIO Empty Mode"] #[doc = "Bit 3 - TX FIFIO Empty Mode"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txfemd(&mut self) -> TxfemdW<CtrlSpec> { pub fn txfemd(&mut self) -> TxfemdW<CtrlSpec> {
TxfemdW::new(self, 3) TxfemdW::new(self, 3)
} }
#[doc = "Bit 4 - RX FIFO Full Mode"] #[doc = "Bit 4 - RX FIFO Full Mode"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxffmd(&mut self) -> RxffmdW<CtrlSpec> { pub fn rxffmd(&mut self) -> RxffmdW<CtrlSpec> {
RxffmdW::new(self, 4) RxffmdW::new(self, 4)
} }
#[doc = "Bit 5 - Enable Input Analog Glitch Filter"] #[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn algfilter(&mut self) -> AlgfilterW<CtrlSpec> { pub fn algfilter(&mut self) -> AlgfilterW<CtrlSpec> {
AlgfilterW::new(self, 5) AlgfilterW::new(self, 5)
} }
#[doc = "Bit 6 - Enable Input Digital Glitch Filter"] #[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn dlgfilter(&mut self) -> DlgfilterW<CtrlSpec> { pub fn dlgfilter(&mut self) -> DlgfilterW<CtrlSpec> {
DlgfilterW::new(self, 6) DlgfilterW::new(self, 6)
} }
#[doc = "Bit 8 - Enable LoopBack Mode"] #[doc = "Bit 8 - Enable LoopBack Mode"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> { pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
LoopbackW::new(self, 8) LoopbackW::new(self, 8)
} }
#[doc = "Bit 9 - Enable Timing Config Register"] #[doc = "Bit 9 - Enable Timing Config Register"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn tmconfigenb(&mut self) -> TmconfigenbW<CtrlSpec> { pub fn tmconfigenb(&mut self) -> TmconfigenbW<CtrlSpec> {
TmconfigenbW::new(self, 9) TmconfigenbW::new(self, 9)
} }
} }
#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec; pub struct CtrlSpec;
impl crate::RegisterSpec for CtrlSpec { impl crate::RegisterSpec for CtrlSpec {
type Ux = u32; type Ux = u32;

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@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec; pub struct DataSpec;
impl crate::RegisterSpec for DataSpec { impl crate::RegisterSpec for DataSpec {
type Ux = u32; type Ux = u32;

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@@ -7,18 +7,16 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W { impl W {
#[doc = "Bit 0 - Clear Rx FIFO"] #[doc = "Bit 0 - Clear Rx FIFO"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> { pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
RxfifoW::new(self, 0) RxfifoW::new(self, 0)
} }
#[doc = "Bit 1 - Clear Tx FIFO"] #[doc = "Bit 1 - Clear Tx FIFO"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> { pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
TxfifoW::new(self, 1) TxfifoW::new(self, 1)
} }
} }
#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoClrSpec; pub struct FifoClrSpec;
impl crate::RegisterSpec for FifoClrSpec { impl crate::RegisterSpec for FifoClrSpec {
type Ux = u32; type Ux = u32;

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@@ -133,90 +133,76 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - I2C Bus is Idle"] #[doc = "Bit 0 - I2C Bus is Idle"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn i2cidle(&mut self) -> I2cidleW<IrqEnbSpec> { pub fn i2cidle(&mut self) -> I2cidleW<IrqEnbSpec> {
I2cidleW::new(self, 0) I2cidleW::new(self, 0)
} }
#[doc = "Bit 1 - Controller is Idle"] #[doc = "Bit 1 - Controller is Idle"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn idle(&mut self) -> IdleW<IrqEnbSpec> { pub fn idle(&mut self) -> IdleW<IrqEnbSpec> {
IdleW::new(self, 1) IdleW::new(self, 1)
} }
#[doc = "Bit 2 - Controller is Waiting"] #[doc = "Bit 2 - Controller is Waiting"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn waiting(&mut self) -> WaitingW<IrqEnbSpec> { pub fn waiting(&mut self) -> WaitingW<IrqEnbSpec> {
WaitingW::new(self, 2) WaitingW::new(self, 2)
} }
#[doc = "Bit 3 - Controller is Stalled"] #[doc = "Bit 3 - Controller is Stalled"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn stalled(&mut self) -> StalledW<IrqEnbSpec> { pub fn stalled(&mut self) -> StalledW<IrqEnbSpec> {
StalledW::new(self, 3) StalledW::new(self, 3)
} }
#[doc = "Bit 4 - I2C Arbitration was lost"] #[doc = "Bit 4 - I2C Arbitration was lost"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn arblost(&mut self) -> ArblostW<IrqEnbSpec> { pub fn arblost(&mut self) -> ArblostW<IrqEnbSpec> {
ArblostW::new(self, 4) ArblostW::new(self, 4)
} }
#[doc = "Bit 5 - I2C Address was not Acknowledged"] #[doc = "Bit 5 - I2C Address was not Acknowledged"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn nackaddr(&mut self) -> NackaddrW<IrqEnbSpec> { pub fn nackaddr(&mut self) -> NackaddrW<IrqEnbSpec> {
NackaddrW::new(self, 5) NackaddrW::new(self, 5)
} }
#[doc = "Bit 6 - I2C Data was not Acknowledged"] #[doc = "Bit 6 - I2C Data was not Acknowledged"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn nackdata(&mut self) -> NackdataW<IrqEnbSpec> { pub fn nackdata(&mut self) -> NackdataW<IrqEnbSpec> {
NackdataW::new(self, 6) NackdataW::new(self, 6)
} }
#[doc = "Bit 7 - I2C Clock Low Timeout"] #[doc = "Bit 7 - I2C Clock Low Timeout"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn clkloto(&mut self) -> ClklotoW<IrqEnbSpec> { pub fn clkloto(&mut self) -> ClklotoW<IrqEnbSpec> {
ClklotoW::new(self, 7) ClklotoW::new(self, 7)
} }
#[doc = "Bit 10 - TX FIFO Overflowed"] #[doc = "Bit 10 - TX FIFO Overflowed"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txoverflow(&mut self) -> TxoverflowW<IrqEnbSpec> { pub fn txoverflow(&mut self) -> TxoverflowW<IrqEnbSpec> {
TxoverflowW::new(self, 10) TxoverflowW::new(self, 10)
} }
#[doc = "Bit 11 - TX FIFO Overflowed"] #[doc = "Bit 11 - TX FIFO Overflowed"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxoverflow(&mut self) -> RxoverflowW<IrqEnbSpec> { pub fn rxoverflow(&mut self) -> RxoverflowW<IrqEnbSpec> {
RxoverflowW::new(self, 11) RxoverflowW::new(self, 11)
} }
#[doc = "Bit 12 - TX FIFO Ready"] #[doc = "Bit 12 - TX FIFO Ready"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txready(&mut self) -> TxreadyW<IrqEnbSpec> { pub fn txready(&mut self) -> TxreadyW<IrqEnbSpec> {
TxreadyW::new(self, 12) TxreadyW::new(self, 12)
} }
#[doc = "Bit 13 - RX FIFO Ready"] #[doc = "Bit 13 - RX FIFO Ready"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxready(&mut self) -> RxreadyW<IrqEnbSpec> { pub fn rxready(&mut self) -> RxreadyW<IrqEnbSpec> {
RxreadyW::new(self, 13) RxreadyW::new(self, 13)
} }
#[doc = "Bit 14 - TX FIFO Empty"] #[doc = "Bit 14 - TX FIFO Empty"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txempty(&mut self) -> TxemptyW<IrqEnbSpec> { pub fn txempty(&mut self) -> TxemptyW<IrqEnbSpec> {
TxemptyW::new(self, 14) TxemptyW::new(self, 14)
} }
#[doc = "Bit 15 - RX FIFO Full"] #[doc = "Bit 15 - RX FIFO Full"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxfull(&mut self) -> RxfullW<IrqEnbSpec> { pub fn rxfull(&mut self) -> RxfullW<IrqEnbSpec> {
RxfullW::new(self, 15) RxfullW::new(self, 15)
} }
} }
#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec; pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec { impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32; type Ux = u32;

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@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec; pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec { impl crate::RegisterSpec for PeridSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxcountSpec; pub struct RxcountSpec;
impl crate::RegisterSpec for RxcountSpec { impl crate::RegisterSpec for RxcountSpec {
type Ux = u32; type Ux = u32;

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@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxfifoirqtrgSpec; pub struct RxfifoirqtrgSpec;
impl crate::RegisterSpec for RxfifoirqtrgSpec { impl crate::RegisterSpec for RxfifoirqtrgSpec {
type Ux = u32; type Ux = u32;

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@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0AddressSpec; pub struct S0AddressSpec;
impl crate::RegisterSpec for S0AddressSpec { impl crate::RegisterSpec for S0AddressSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0AddressbSpec; pub struct S0AddressbSpec;
impl crate::RegisterSpec for S0AddressbSpec { impl crate::RegisterSpec for S0AddressbSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0AddressmaskSpec; pub struct S0AddressmaskSpec;
impl crate::RegisterSpec for S0AddressmaskSpec { impl crate::RegisterSpec for S0AddressmaskSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0AddressmaskbSpec; pub struct S0AddressmaskbSpec;
impl crate::RegisterSpec for S0AddressmaskbSpec { impl crate::RegisterSpec for S0AddressmaskbSpec {
type Ux = u32; type Ux = u32;

View File

@@ -52,36 +52,31 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - I2C Enabled"] #[doc = "Bit 0 - I2C Enabled"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn clkenabled(&mut self) -> ClkenabledW<S0CtrlSpec> { pub fn clkenabled(&mut self) -> ClkenabledW<S0CtrlSpec> {
ClkenabledW::new(self, 0) ClkenabledW::new(self, 0)
} }
#[doc = "Bit 1 - I2C Activated"] #[doc = "Bit 1 - I2C Activated"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn enabled(&mut self) -> EnabledW<S0CtrlSpec> { pub fn enabled(&mut self) -> EnabledW<S0CtrlSpec> {
EnabledW::new(self, 1) EnabledW::new(self, 1)
} }
#[doc = "Bit 2 - I2C Active"] #[doc = "Bit 2 - I2C Active"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn enable(&mut self) -> EnableW<S0CtrlSpec> { pub fn enable(&mut self) -> EnableW<S0CtrlSpec> {
EnableW::new(self, 2) EnableW::new(self, 2)
} }
#[doc = "Bit 3 - TX FIFIO Empty Mode"] #[doc = "Bit 3 - TX FIFIO Empty Mode"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txfemd(&mut self) -> TxfemdW<S0CtrlSpec> { pub fn txfemd(&mut self) -> TxfemdW<S0CtrlSpec> {
TxfemdW::new(self, 3) TxfemdW::new(self, 3)
} }
#[doc = "Bit 4 - RX FIFO Full Mode"] #[doc = "Bit 4 - RX FIFO Full Mode"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxffmd(&mut self) -> RxffmdW<S0CtrlSpec> { pub fn rxffmd(&mut self) -> RxffmdW<S0CtrlSpec> {
RxffmdW::new(self, 4) RxffmdW::new(self, 4)
} }
} }
#[doc = "Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0CtrlSpec; pub struct S0CtrlSpec;
impl crate::RegisterSpec for S0CtrlSpec { impl crate::RegisterSpec for S0CtrlSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0DataSpec; pub struct S0DataSpec;
impl crate::RegisterSpec for S0DataSpec { impl crate::RegisterSpec for S0DataSpec {
type Ux = u32; type Ux = u32;

View File

@@ -7,18 +7,16 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W { impl W {
#[doc = "Bit 0 - Clear Rx FIFO"] #[doc = "Bit 0 - Clear Rx FIFO"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxfifo(&mut self) -> RxfifoW<S0FifoClrSpec> { pub fn rxfifo(&mut self) -> RxfifoW<S0FifoClrSpec> {
RxfifoW::new(self, 0) RxfifoW::new(self, 0)
} }
#[doc = "Bit 1 - Clear Tx FIFO"] #[doc = "Bit 1 - Clear Tx FIFO"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txfifo(&mut self) -> TxfifoW<S0FifoClrSpec> { pub fn txfifo(&mut self) -> TxfifoW<S0FifoClrSpec> {
TxfifoW::new(self, 1) TxfifoW::new(self, 1)
} }
} }
#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0FifoClrSpec; pub struct S0FifoClrSpec;
impl crate::RegisterSpec for S0FifoClrSpec { impl crate::RegisterSpec for S0FifoClrSpec {
type Ux = u32; type Ux = u32;

View File

@@ -151,102 +151,86 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - Controller Complted a Transaction"] #[doc = "Bit 0 - Controller Complted a Transaction"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> { pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> {
CompletedW::new(self, 0) CompletedW::new(self, 0)
} }
#[doc = "Bit 1 - Controller is Idle"] #[doc = "Bit 1 - Controller is Idle"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> { pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> {
IdleW::new(self, 1) IdleW::new(self, 1)
} }
#[doc = "Bit 2 - Controller is Waiting"] #[doc = "Bit 2 - Controller is Waiting"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> { pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> {
WaitingW::new(self, 2) WaitingW::new(self, 2)
} }
#[doc = "Bit 3 - Controller is Tx Stalled"] #[doc = "Bit 3 - Controller is Tx Stalled"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> { pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> {
TxstalledW::new(self, 3) TxstalledW::new(self, 3)
} }
#[doc = "Bit 4 - Controller is Rx Stalled"] #[doc = "Bit 4 - Controller is Rx Stalled"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> { pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> {
RxstalledW::new(self, 4) RxstalledW::new(self, 4)
} }
#[doc = "Bit 5 - I2C Address Match"] #[doc = "Bit 5 - I2C Address Match"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> { pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> {
AddressmatchW::new(self, 5) AddressmatchW::new(self, 5)
} }
#[doc = "Bit 6 - I2C Data was not Acknowledged"] #[doc = "Bit 6 - I2C Data was not Acknowledged"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> { pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> {
NackdataW::new(self, 6) NackdataW::new(self, 6)
} }
#[doc = "Bit 7 - Pending Data is first Byte following Address"] #[doc = "Bit 7 - Pending Data is first Byte following Address"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> { pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> {
RxdatafirstW::new(self, 7) RxdatafirstW::new(self, 7)
} }
#[doc = "Bit 8 - I2C Start Condition"] #[doc = "Bit 8 - I2C Start Condition"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> { pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> {
I2cStartW::new(self, 8) I2cStartW::new(self, 8)
} }
#[doc = "Bit 9 - I2C Stop Condition"] #[doc = "Bit 9 - I2C Stop Condition"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> { pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> {
I2cStopW::new(self, 9) I2cStopW::new(self, 9)
} }
#[doc = "Bit 10 - TX FIFO Underflowed"] #[doc = "Bit 10 - TX FIFO Underflowed"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> { pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> {
TxunderflowW::new(self, 10) TxunderflowW::new(self, 10)
} }
#[doc = "Bit 11 - TX FIFO Overflowed"] #[doc = "Bit 11 - TX FIFO Overflowed"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> { pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> {
RxoverflowW::new(self, 11) RxoverflowW::new(self, 11)
} }
#[doc = "Bit 12 - TX FIFO Ready"] #[doc = "Bit 12 - TX FIFO Ready"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> { pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> {
TxreadyW::new(self, 12) TxreadyW::new(self, 12)
} }
#[doc = "Bit 13 - RX FIFO Ready"] #[doc = "Bit 13 - RX FIFO Ready"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> { pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> {
RxreadyW::new(self, 13) RxreadyW::new(self, 13)
} }
#[doc = "Bit 14 - TX FIFO Empty"] #[doc = "Bit 14 - TX FIFO Empty"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> { pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> {
TxemptyW::new(self, 14) TxemptyW::new(self, 14)
} }
#[doc = "Bit 15 - RX FIFO Full"] #[doc = "Bit 15 - RX FIFO Full"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> { pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> {
RxfullW::new(self, 15) RxfullW::new(self, 15)
} }
} }
#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0IrqEnbSpec; pub struct S0IrqEnbSpec;
impl crate::RegisterSpec for S0IrqEnbSpec { impl crate::RegisterSpec for S0IrqEnbSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0LastaddressSpec; pub struct S0LastaddressSpec;
impl crate::RegisterSpec for S0LastaddressSpec { impl crate::RegisterSpec for S0LastaddressSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0MaxwordsSpec; pub struct S0MaxwordsSpec;
impl crate::RegisterSpec for S0MaxwordsSpec { impl crate::RegisterSpec for S0MaxwordsSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0RxcountSpec; pub struct S0RxcountSpec;
impl crate::RegisterSpec for S0RxcountSpec { impl crate::RegisterSpec for S0RxcountSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0RxfifoirqtrgSpec; pub struct S0RxfifoirqtrgSpec;
impl crate::RegisterSpec for S0RxfifoirqtrgSpec { impl crate::RegisterSpec for S0RxfifoirqtrgSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0StateSpec; pub struct S0StateSpec;
impl crate::RegisterSpec for S0StateSpec { impl crate::RegisterSpec for S0StateSpec {
type Ux = u32; type Ux = u32;

View File

@@ -121,7 +121,7 @@ impl R {
RawSclR::new(((self.bits >> 31) & 1) != 0) RawSclR::new(((self.bits >> 31) & 1) != 0)
} }
} }
#[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0StatusSpec; pub struct S0StatusSpec;
impl crate::RegisterSpec for S0StatusSpec { impl crate::RegisterSpec for S0StatusSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0TxcountSpec; pub struct S0TxcountSpec;
impl crate::RegisterSpec for S0TxcountSpec { impl crate::RegisterSpec for S0TxcountSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0TxfifoirqtrgSpec; pub struct S0TxfifoirqtrgSpec;
impl crate::RegisterSpec for S0TxfifoirqtrgSpec { impl crate::RegisterSpec for S0TxfifoirqtrgSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StateSpec; pub struct StateSpec;
impl crate::RegisterSpec for StateSpec { impl crate::RegisterSpec for StateSpec {
type Ux = u32; type Ux = u32;

View File

@@ -107,7 +107,7 @@ impl R {
RawSclR::new(((self.bits >> 31) & 1) != 0) RawSclR::new(((self.bits >> 31) & 1) != 0)
} }
} }
#[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatusSpec; pub struct StatusSpec;
impl crate::RegisterSpec for StatusSpec { impl crate::RegisterSpec for StatusSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TmconfigSpec; pub struct TmconfigSpec;
impl crate::RegisterSpec for TmconfigSpec { impl crate::RegisterSpec for TmconfigSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxcountSpec; pub struct TxcountSpec;
impl crate::RegisterSpec for TxcountSpec { impl crate::RegisterSpec for TxcountSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxfifoirqtrgSpec; pub struct TxfifoirqtrgSpec;
impl crate::RegisterSpec for TxfifoirqtrgSpec { impl crate::RegisterSpec for TxfifoirqtrgSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WordsSpec; pub struct WordsSpec;
impl crate::RegisterSpec for WordsSpec { impl crate::RegisterSpec for WordsSpec {
type Ux = u32; type Ux = u32;

View File

@@ -2,8 +2,8 @@
#[doc = "Register block"] #[doc = "Register block"]
pub struct RegisterBlock { pub struct RegisterBlock {
porta: [Porta; 32], porta: [Porta; 32],
portb0: [Portb; 32], portbs: Portbs,
_reserved2: [u8; 0x0efc], _reserved2: [u8; 0x0f78],
perid: Perid, perid: Perid,
} }
impl RegisterBlock { impl RegisterBlock {
@@ -18,16 +18,10 @@ impl RegisterBlock {
pub fn porta_iter(&self) -> impl Iterator<Item = &Porta> { pub fn porta_iter(&self) -> impl Iterator<Item = &Porta> {
self.porta.iter() self.porta.iter()
} }
#[doc = "0x80..0x100 - PORTB Pin Configuration Register"] #[doc = "0x80 - PORTB Pin Configuration Register"]
#[inline(always)] #[inline(always)]
pub const fn portb0(&self, n: usize) -> &Portb { pub const fn portbs(&self) -> &Portbs {
&self.portb0[n] &self.portbs
}
#[doc = "Iterator for array of:"]
#[doc = "0x80..0x100 - PORTB Pin Configuration Register"]
#[inline(always)]
pub fn portb0_iter(&self) -> impl Iterator<Item = &Portb> {
self.portb0.iter()
} }
#[doc = "0xffc - Peripheral ID Register"] #[doc = "0xffc - Peripheral ID Register"]
#[inline(always)] #[inline(always)]
@@ -35,15 +29,15 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`] #[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`]
module"] module"]
#[doc(alias = "PORTA")] #[doc(alias = "PORTA")]
pub type Porta = crate::Reg<porta::PortaSpec>; pub type Porta = crate::Reg<porta::PortaSpec>;
#[doc = "PORTA Pin Configuration Register"] #[doc = "PORTA Pin Configuration Register"]
pub mod porta; pub mod porta;
pub use porta as portb; pub use porta as portbs;
pub use Porta as Portb; pub use Porta as Portbs;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"] module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec; pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec { impl crate::RegisterSpec for PeridSpec {
type Ux = u32; type Ux = u32;

View File

@@ -214,72 +214,61 @@ impl R {
impl W { impl W {
#[doc = "Bits 0:2 - Input Filter Selectoin"] #[doc = "Bits 0:2 - Input Filter Selectoin"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn flttype(&mut self) -> FlttypeW<PortaSpec> { pub fn flttype(&mut self) -> FlttypeW<PortaSpec> {
FlttypeW::new(self, 0) FlttypeW::new(self, 0)
} }
#[doc = "Bits 3:5 - Input Filter Clock Selection"] #[doc = "Bits 3:5 - Input Filter Clock Selection"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn fltclk(&mut self) -> FltclkW<PortaSpec> { pub fn fltclk(&mut self) -> FltclkW<PortaSpec> {
FltclkW::new(self, 3) FltclkW::new(self, 3)
} }
#[doc = "Bit 6 - Input Invert Selection"] #[doc = "Bit 6 - Input Invert Selection"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn invinp(&mut self) -> InvinpW<PortaSpec> { pub fn invinp(&mut self) -> InvinpW<PortaSpec> {
InvinpW::new(self, 6) InvinpW::new(self, 6)
} }
#[doc = "Bit 7 - Input Enable While Output enabled"] #[doc = "Bit 7 - Input Enable While Output enabled"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn iewo(&mut self) -> IewoW<PortaSpec> { pub fn iewo(&mut self) -> IewoW<PortaSpec> {
IewoW::new(self, 7) IewoW::new(self, 7)
} }
#[doc = "Bit 8 - Output Open Drain Mode"] #[doc = "Bit 8 - Output Open Drain Mode"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn opendrn(&mut self) -> OpendrnW<PortaSpec> { pub fn opendrn(&mut self) -> OpendrnW<PortaSpec> {
OpendrnW::new(self, 8) OpendrnW::new(self, 8)
} }
#[doc = "Bit 9 - Output Invert Selection"] #[doc = "Bit 9 - Output Invert Selection"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn invout(&mut self) -> InvoutW<PortaSpec> { pub fn invout(&mut self) -> InvoutW<PortaSpec> {
InvoutW::new(self, 9) InvoutW::new(self, 9)
} }
#[doc = "Bit 10 - Internal Pull up/down level"] #[doc = "Bit 10 - Internal Pull up/down level"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn plevel(&mut self) -> PlevelW<PortaSpec> { pub fn plevel(&mut self) -> PlevelW<PortaSpec> {
PlevelW::new(self, 10) PlevelW::new(self, 10)
} }
#[doc = "Bit 11 - Enable Internal Pull up/down"] #[doc = "Bit 11 - Enable Internal Pull up/down"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn pen(&mut self) -> PenW<PortaSpec> { pub fn pen(&mut self) -> PenW<PortaSpec> {
PenW::new(self, 11) PenW::new(self, 11)
} }
#[doc = "Bit 12 - Enable Pull when output active"] #[doc = "Bit 12 - Enable Pull when output active"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn pwoa(&mut self) -> PwoaW<PortaSpec> { pub fn pwoa(&mut self) -> PwoaW<PortaSpec> {
PwoaW::new(self, 12) PwoaW::new(self, 12)
} }
#[doc = "Bits 13:15 - Pin Function Selection"] #[doc = "Bits 13:15 - Pin Function Selection"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn funsel(&mut self) -> FunselW<PortaSpec> { pub fn funsel(&mut self) -> FunselW<PortaSpec> {
FunselW::new(self, 13) FunselW::new(self, 13)
} }
#[doc = "Bit 16 - IO Pin Disable"] #[doc = "Bit 16 - IO Pin Disable"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn iodis(&mut self) -> IodisW<PortaSpec> { pub fn iodis(&mut self) -> IodisW<PortaSpec> {
IodisW::new(self, 16) IodisW::new(self, 16)
} }
} }
#[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PortaSpec; pub struct PortaSpec;
impl crate::RegisterSpec for PortaSpec { impl crate::RegisterSpec for PortaSpec {
type Ux = u32; type Ux = u32;

View File

@@ -169,7 +169,7 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`] #[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`]
module"] module"]
#[doc(alias = "INT_RAM_SBE")] #[doc(alias = "INT_RAM_SBE")]
pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>; pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>;
@@ -197,7 +197,7 @@ pub use IntRamSbe as IntRamMbe;
pub use IntRamSbe as IntRomSbe; pub use IntRamSbe as IntRomSbe;
pub use IntRamSbe as IntRomMbe; pub use IntRamSbe as IntRomMbe;
pub use IntRamSbe as Txev; pub use IntRamSbe as Txev;
#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`] #[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`]
module"] module"]
#[doc(alias = "NMI")] #[doc(alias = "NMI")]
pub type Nmi = crate::Reg<nmi::NmiSpec>; pub type Nmi = crate::Reg<nmi::NmiSpec>;
@@ -213,7 +213,7 @@ pub use Nmi as Watchdog;
pub use Nmi as Mereset; pub use Nmi as Mereset;
pub use Nmi as Edbgrq; pub use Nmi as Edbgrq;
pub use Nmi as Irqs; pub use Nmi as Irqs;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"] module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ram_sbe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ram_sbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntRamSbeSpec; pub struct IntRamSbeSpec;
impl crate::RegisterSpec for IntRamSbeSpec { impl crate::RegisterSpec for IntRamSbeSpec {
type Ux = u32; type Ux = u32;

View File

@@ -9,7 +9,7 @@ impl R {
ActiveR::new((self.bits & 1) != 0) ActiveR::new((self.bits & 1) != 0)
} }
} }
#[doc = "NMI Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NmiSpec; pub struct NmiSpec;
impl crate::RegisterSpec for NmiSpec { impl crate::RegisterSpec for NmiSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec; pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec { impl crate::RegisterSpec for PeridSpec {
type Ux = u32; type Ux = u32;

View File

@@ -1,10 +1,8 @@
#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] #![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.35.0 (dac8766 2025-02-08))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.35.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)] #![allow(non_camel_case_types)]
#![allow(non_snake_case)] #![allow(non_snake_case)]
#![no_std] #![no_std]
// Manually inserted.
#![cfg_attr(docsrs, feature(doc_auto_cfg))]
use core::marker::PhantomData; use core::marker::PhantomData;
use core::ops::Deref; use core::ops::Deref;
#[doc = r"Number available in the NVIC for configuring priority"] #[doc = r"Number available in the NVIC for configuring priority"]
@@ -1974,117 +1972,43 @@ impl Peripherals {
pub unsafe fn steal() -> Self { pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true; DEVICE_PERIPHERALS = true;
Peripherals { Peripherals {
sysconfig: Sysconfig { sysconfig: Sysconfig::steal(),
_marker: PhantomData, irqsel: Irqsel::steal(),
}, ioconfig: Ioconfig::steal(),
irqsel: Irqsel { utility: Utility::steal(),
_marker: PhantomData, porta: Porta::steal(),
}, portb: Portb::steal(),
ioconfig: Ioconfig { tim0: Tim0::steal(),
_marker: PhantomData, tim1: Tim1::steal(),
}, tim2: Tim2::steal(),
utility: Utility { tim3: Tim3::steal(),
_marker: PhantomData, tim4: Tim4::steal(),
}, tim5: Tim5::steal(),
porta: Porta { tim6: Tim6::steal(),
_marker: PhantomData, tim7: Tim7::steal(),
}, tim8: Tim8::steal(),
portb: Portb { tim9: Tim9::steal(),
_marker: PhantomData, tim10: Tim10::steal(),
}, tim11: Tim11::steal(),
tim0: Tim0 { tim12: Tim12::steal(),
_marker: PhantomData, tim13: Tim13::steal(),
}, tim14: Tim14::steal(),
tim1: Tim1 { tim15: Tim15::steal(),
_marker: PhantomData, tim16: Tim16::steal(),
}, tim17: Tim17::steal(),
tim2: Tim2 { tim18: Tim18::steal(),
_marker: PhantomData, tim19: Tim19::steal(),
}, tim20: Tim20::steal(),
tim3: Tim3 { tim21: Tim21::steal(),
_marker: PhantomData, tim22: Tim22::steal(),
}, tim23: Tim23::steal(),
tim4: Tim4 { uarta: Uarta::steal(),
_marker: PhantomData, uartb: Uartb::steal(),
}, spia: Spia::steal(),
tim5: Tim5 { spib: Spib::steal(),
_marker: PhantomData, spic: Spic::steal(),
}, i2ca: I2ca::steal(),
tim6: Tim6 { i2cb: I2cb::steal(),
_marker: PhantomData,
},
tim7: Tim7 {
_marker: PhantomData,
},
tim8: Tim8 {
_marker: PhantomData,
},
tim9: Tim9 {
_marker: PhantomData,
},
tim10: Tim10 {
_marker: PhantomData,
},
tim11: Tim11 {
_marker: PhantomData,
},
tim12: Tim12 {
_marker: PhantomData,
},
tim13: Tim13 {
_marker: PhantomData,
},
tim14: Tim14 {
_marker: PhantomData,
},
tim15: Tim15 {
_marker: PhantomData,
},
tim16: Tim16 {
_marker: PhantomData,
},
tim17: Tim17 {
_marker: PhantomData,
},
tim18: Tim18 {
_marker: PhantomData,
},
tim19: Tim19 {
_marker: PhantomData,
},
tim20: Tim20 {
_marker: PhantomData,
},
tim21: Tim21 {
_marker: PhantomData,
},
tim22: Tim22 {
_marker: PhantomData,
},
tim23: Tim23 {
_marker: PhantomData,
},
uarta: Uarta {
_marker: PhantomData,
},
uartb: Uartb {
_marker: PhantomData,
},
spia: Spia {
_marker: PhantomData,
},
spib: Spib {
_marker: PhantomData,
},
spic: Spic {
_marker: PhantomData,
},
i2ca: I2ca {
_marker: PhantomData,
},
i2cb: I2cb {
_marker: PhantomData,
},
} }
} }
} }

View File

@@ -1,6 +1,3 @@
// Manually inserted.
#![allow(clippy::identity_op)]
#[repr(C)] #[repr(C)]
#[doc = "Register block"] #[doc = "Register block"]
pub struct RegisterBlock { pub struct RegisterBlock {
@@ -33,247 +30,156 @@ impl RegisterBlock {
pub const fn datainbyte(&self, n: usize) -> &Datainbyte { pub const fn datainbyte(&self, n: usize) -> &Datainbyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(0).add(1 * n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(n).cast() }
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x00 - Data In Register by Byte"] #[doc = "0x00 - Data In Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn datainbyte_iter(&self) -> impl Iterator<Item = &Datainbyte> { pub fn datainbyte_iter(&self) -> impl Iterator<Item = &Datainbyte> {
(0..4) (0..4).map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(n).cast() })
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(0).add(1 * n).cast() })
} }
#[doc = "0x00 - Data In Register"] #[doc = "0x00 - Data In Register"]
#[inline(always)] #[inline(always)]
pub const fn datain(&self) -> &Datain { pub const fn datain(&self) -> &Datain {
unsafe { &*(self as *const Self).cast::<u8>().add(0).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().cast() }
} }
#[doc = "0x04 - Data In Raw Register by Byte"] #[doc = "0x04 - Data In Raw Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn datainrawbyte0(&self, n: usize) -> &Datainrawbyte { pub const fn datainrawbytes(&self) -> &Datainrawbytes {
#[allow(clippy::no_effect)] unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).cast() }
[(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(4).add(1 * n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x04 - Data In Raw Register by Byte"]
#[inline(always)]
pub fn datainrawbyte0_iter(&self) -> impl Iterator<Item = &Datainrawbyte> {
(0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(4).add(1 * n).cast() })
} }
#[doc = "0x04 - Data In Raw Register"] #[doc = "0x04 - Data In Raw Register"]
#[inline(always)] #[inline(always)]
pub const fn datainraw(&self) -> &Datainraw { pub const fn datainraw(&self) -> &Datainraw {
unsafe { &*(self as *const Self).cast::<u8>().add(4).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).cast() }
} }
#[doc = "0x08 - Data Out Register by Byte"] #[doc = "0x08 - Data Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn dataoutbyte(&self, n: usize) -> &Dataoutbyte { pub const fn dataoutbyte(&self, n: usize) -> &Dataoutbyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(8).add(1 * n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).add(n).cast() }
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x08 - Data Out Register by Byte"] #[doc = "0x08 - Data Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn dataoutbyte_iter(&self) -> impl Iterator<Item = &Dataoutbyte> { pub fn dataoutbyte_iter(&self) -> impl Iterator<Item = &Dataoutbyte> {
(0..4) (0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(8).add(1 * n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).add(n).cast() })
} }
#[doc = "0x08 - Data Out Register"] #[doc = "0x08 - Data Out Register"]
#[inline(always)] #[inline(always)]
pub const fn dataout(&self) -> &Dataout { pub const fn dataout(&self) -> &Dataout {
unsafe { &*(self as *const Self).cast::<u8>().add(8).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).cast() }
} }
#[doc = "0x0c - Data Out Register by Byte"] #[doc = "0x0c - Data Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn dataoutrawbyte0(&self, n: usize) -> &Dataoutrawbyte { pub const fn dataoutrawbytes(&self) -> &Dataoutrawbytes {
#[allow(clippy::no_effect)] unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
[(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(12).add(1 * n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x0c - Data Out Register by Byte"]
#[inline(always)]
pub fn dataoutrawbyte0_iter(&self) -> impl Iterator<Item = &Dataoutrawbyte> {
(0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(12).add(1 * n).cast() })
} }
#[doc = "0x0c - Data Out Register"] #[doc = "0x0c - Data Out Register"]
#[inline(always)] #[inline(always)]
pub const fn dataoutraw(&self) -> &Dataoutraw { pub const fn dataoutraw(&self) -> &Dataoutraw {
unsafe { &*(self as *const Self).cast::<u8>().add(12).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
} }
#[doc = "0x10 - Set Out Register by Byte"] #[doc = "0x10 - Set Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn setoutbyte0(&self, n: usize) -> &Setoutbyte { pub const fn setoutbytes(&self) -> &Setoutbytes {
#[allow(clippy::no_effect)] unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).cast() }
[(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(16).add(1 * n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x10 - Set Out Register by Byte"]
#[inline(always)]
pub fn setoutbyte0_iter(&self) -> impl Iterator<Item = &Setoutbyte> {
(0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(16).add(1 * n).cast() })
} }
#[doc = "0x10 - Set Out Register"] #[doc = "0x10 - Set Out Register"]
#[inline(always)] #[inline(always)]
pub const fn setout(&self) -> &Setout { pub const fn setout(&self) -> &Setout {
unsafe { &*(self as *const Self).cast::<u8>().add(16).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).cast() }
} }
#[doc = "0x14 - Clear Out Register by Byte"] #[doc = "0x14 - Clear Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn clroutbyte0(&self, n: usize) -> &Clroutbyte { pub const fn clroutbytes(&self) -> &Clroutbytes {
#[allow(clippy::no_effect)] unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).cast() }
[(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(20).add(1 * n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x14 - Clear Out Register by Byte"]
#[inline(always)]
pub fn clroutbyte0_iter(&self) -> impl Iterator<Item = &Clroutbyte> {
(0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(20).add(1 * n).cast() })
} }
#[doc = "0x14 - Clear Out Register"] #[doc = "0x14 - Clear Out Register"]
#[inline(always)] #[inline(always)]
pub const fn clrout(&self) -> &Clrout { pub const fn clrout(&self) -> &Clrout {
unsafe { &*(self as *const Self).cast::<u8>().add(20).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).cast() }
} }
#[doc = "0x18 - Toggle Out Register by Byte"] #[doc = "0x18 - Toggle Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn togoutbyte0(&self, n: usize) -> &Togoutbyte { pub const fn togoutbytes(&self) -> &Togoutbytes {
#[allow(clippy::no_effect)] unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
[(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(24).add(1 * n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x18 - Toggle Out Register by Byte"]
#[inline(always)]
pub fn togoutbyte0_iter(&self) -> impl Iterator<Item = &Togoutbyte> {
(0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(24).add(1 * n).cast() })
} }
#[doc = "0x18 - Toggle Out Register"] #[doc = "0x18 - Toggle Out Register"]
#[inline(always)] #[inline(always)]
pub const fn togout(&self) -> &Togout { pub const fn togout(&self) -> &Togout {
unsafe { &*(self as *const Self).cast::<u8>().add(24).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
} }
#[doc = "0x1c - Data Out Register by Byte"] #[doc = "0x1c - Data Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn datamaskbyte(&self, n: usize) -> &Datamaskbyte { pub const fn datamaskbyte(&self, n: usize) -> &Datamaskbyte {
#[allow(clippy::no_effect)] #[allow(clippy::no_effect)]
[(); 4][n]; [(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(28).add(1 * n).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).add(n).cast() }
} }
#[doc = "Iterator for array of:"] #[doc = "Iterator for array of:"]
#[doc = "0x1c - Data Out Register by Byte"] #[doc = "0x1c - Data Out Register by Byte"]
#[inline(always)] #[inline(always)]
pub fn datamaskbyte_iter(&self) -> impl Iterator<Item = &Datamaskbyte> { pub fn datamaskbyte_iter(&self) -> impl Iterator<Item = &Datamaskbyte> {
(0..4) (0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(28).add(1 * n).cast() }) .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).add(n).cast() })
} }
#[doc = "0x1c - Data mask Register"] #[doc = "0x1c - Data mask Register"]
#[inline(always)] #[inline(always)]
pub const fn datamask(&self) -> &Datamask { pub const fn datamask(&self) -> &Datamask {
unsafe { &*(self as *const Self).cast::<u8>().add(28).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
} }
#[doc = "0x20 - Direction Register by Byte"] #[doc = "0x20 - Direction Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn dirbyte0(&self, n: usize) -> &Dirbyte { pub const fn dirbytes(&self) -> &Dirbytes {
#[allow(clippy::no_effect)] unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
[(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(32).add(1 * n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x20 - Direction Register by Byte"]
#[inline(always)]
pub fn dirbyte0_iter(&self) -> impl Iterator<Item = &Dirbyte> {
(0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(32).add(1 * n).cast() })
} }
#[doc = "0x20 - Direction Register (1:Output, 0:Input)"] #[doc = "0x20 - Direction Register (1:Output, 0:Input)"]
#[inline(always)] #[inline(always)]
pub const fn dir(&self) -> &Dir { pub const fn dir(&self) -> &Dir {
unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
} }
#[doc = "0x24 - Pulse Mode Register by Byte"] #[doc = "0x24 - Pulse Mode Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn pulsebyte0(&self, n: usize) -> &Pulsebyte { pub const fn pulsebytes(&self) -> &Pulsebytes {
#[allow(clippy::no_effect)] unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).cast() }
[(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(36).add(1 * n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x24 - Pulse Mode Register by Byte"]
#[inline(always)]
pub fn pulsebyte0_iter(&self) -> impl Iterator<Item = &Pulsebyte> {
(0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(36).add(1 * n).cast() })
} }
#[doc = "0x24 - Pulse Mode Register"] #[doc = "0x24 - Pulse Mode Register"]
#[inline(always)] #[inline(always)]
pub const fn pulse(&self) -> &Pulse { pub const fn pulse(&self) -> &Pulse {
unsafe { &*(self as *const Self).cast::<u8>().add(36).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).cast() }
} }
#[doc = "0x28 - Pulse Base Mode Register by Byte"] #[doc = "0x28 - Pulse Base Mode Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn pulsebasebyte0(&self, n: usize) -> &Pulsebasebyte { pub const fn pulsebasebytes(&self) -> &Pulsebasebytes {
#[allow(clippy::no_effect)] unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
[(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(40).add(1 * n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x28 - Pulse Base Mode Register by Byte"]
#[inline(always)]
pub fn pulsebasebyte0_iter(&self) -> impl Iterator<Item = &Pulsebasebyte> {
(0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(40).add(1 * n).cast() })
} }
#[doc = "0x28 - Pulse Base Value Register"] #[doc = "0x28 - Pulse Base Value Register"]
#[inline(always)] #[inline(always)]
pub const fn pulsebase(&self) -> &Pulsebase { pub const fn pulsebase(&self) -> &Pulsebase {
unsafe { &*(self as *const Self).cast::<u8>().add(40).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
} }
#[doc = "0x2c - Delay1 Register by Byte"] #[doc = "0x2c - Delay1 Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn delay1byte0(&self, n: usize) -> &Delay1byte { pub const fn delay1bytes(&self) -> &Delay1bytes {
#[allow(clippy::no_effect)] unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).cast() }
[(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(44).add(1 * n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x2c - Delay1 Register by Byte"]
#[inline(always)]
pub fn delay1byte0_iter(&self) -> impl Iterator<Item = &Delay1byte> {
(0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(44).add(1 * n).cast() })
} }
#[doc = "0x2c - Delay1 Register"] #[doc = "0x2c - Delay1 Register"]
#[inline(always)] #[inline(always)]
pub const fn delay1(&self) -> &Delay1 { pub const fn delay1(&self) -> &Delay1 {
unsafe { &*(self as *const Self).cast::<u8>().add(44).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).cast() }
} }
#[doc = "0x30 - Delay2 Register by Byte"] #[doc = "0x30 - Delay2 Register by Byte"]
#[inline(always)] #[inline(always)]
pub const fn delay2byte0(&self, n: usize) -> &Delay2byte { pub const fn delay2bytes(&self) -> &Delay2bytes {
#[allow(clippy::no_effect)] unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).cast() }
[(); 4][n];
unsafe { &*(self as *const Self).cast::<u8>().add(48).add(1 * n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x30 - Delay2 Register by Byte"]
#[inline(always)]
pub fn delay2byte0_iter(&self) -> impl Iterator<Item = &Delay2byte> {
(0..4)
.map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(48).add(1 * n).cast() })
} }
#[doc = "0x30 - Delay2 Register"] #[doc = "0x30 - Delay2 Register"]
#[inline(always)] #[inline(always)]
pub const fn delay2(&self) -> &Delay2 { pub const fn delay2(&self) -> &Delay2 {
unsafe { &*(self as *const Self).cast::<u8>().add(48).cast() } unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).cast() }
} }
#[doc = "0x34 - Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] #[doc = "0x34 - Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
#[inline(always)] #[inline(always)]
@@ -316,29 +222,29 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`] #[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`]
module"] module"]
#[doc(alias = "DATAIN")] #[doc(alias = "DATAIN")]
pub type Datain = crate::Reg<datain::DatainSpec>; pub type Datain = crate::Reg<datain::DatainSpec>;
#[doc = "Data In Register"] #[doc = "Data In Register"]
pub mod datain; pub mod datain;
#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`] #[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`]
module"] module"]
#[doc(alias = "DATAINBYTE")] #[doc(alias = "DATAINBYTE")]
pub type Datainbyte = crate::Reg<datainbyte::DatainbyteSpec>; pub type Datainbyte = crate::Reg<datainbyte::DatainbyteSpec>;
#[doc = "Data In Register by Byte"] #[doc = "Data In Register by Byte"]
pub mod datainbyte; pub mod datainbyte;
pub use datain as datainraw; pub use datain as datainraw;
pub use datainbyte as datainrawbyte; pub use datainbyte as datainrawbytes;
pub use Datain as Datainraw; pub use Datain as Datainraw;
pub use Datainbyte as Datainrawbyte; pub use Datainbyte as Datainrawbytes;
#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`] #[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`]
module"] module"]
#[doc(alias = "DATAOUT")] #[doc(alias = "DATAOUT")]
pub type Dataout = crate::Reg<dataout::DataoutSpec>; pub type Dataout = crate::Reg<dataout::DataoutSpec>;
#[doc = "Data Out Register"] #[doc = "Data Out Register"]
pub mod dataout; pub mod dataout;
#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`] #[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`]
module"] module"]
#[doc(alias = "DATAOUTBYTE")] #[doc(alias = "DATAOUTBYTE")]
pub type Dataoutbyte = crate::Reg<dataoutbyte::DataoutbyteSpec>; pub type Dataoutbyte = crate::Reg<dataoutbyte::DataoutbyteSpec>;
@@ -348,25 +254,25 @@ pub use dataout as dataoutraw;
pub use dataout as setout; pub use dataout as setout;
pub use dataout as clrout; pub use dataout as clrout;
pub use dataout as togout; pub use dataout as togout;
pub use dataoutbyte as dataoutrawbyte; pub use dataoutbyte as dataoutrawbytes;
pub use dataoutbyte as setoutbyte; pub use dataoutbyte as setoutbytes;
pub use dataoutbyte as clroutbyte; pub use dataoutbyte as clroutbytes;
pub use dataoutbyte as togoutbyte; pub use dataoutbyte as togoutbytes;
pub use Dataout as Dataoutraw; pub use Dataout as Dataoutraw;
pub use Dataout as Setout; pub use Dataout as Setout;
pub use Dataout as Clrout; pub use Dataout as Clrout;
pub use Dataout as Togout; pub use Dataout as Togout;
pub use Dataoutbyte as Dataoutrawbyte; pub use Dataoutbyte as Dataoutrawbytes;
pub use Dataoutbyte as Setoutbyte; pub use Dataoutbyte as Setoutbytes;
pub use Dataoutbyte as Clroutbyte; pub use Dataoutbyte as Clroutbytes;
pub use Dataoutbyte as Togoutbyte; pub use Dataoutbyte as Togoutbytes;
#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`] #[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`]
module"] module"]
#[doc(alias = "DATAMASK")] #[doc(alias = "DATAMASK")]
pub type Datamask = crate::Reg<datamask::DatamaskSpec>; pub type Datamask = crate::Reg<datamask::DatamaskSpec>;
#[doc = "Data mask Register"] #[doc = "Data mask Register"]
pub mod datamask; pub mod datamask;
#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`] #[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`]
module"] module"]
#[doc(alias = "DATAMASKBYTE")] #[doc(alias = "DATAMASKBYTE")]
pub type Datamaskbyte = crate::Reg<datamaskbyte::DatamaskbyteSpec>; pub type Datamaskbyte = crate::Reg<datamaskbyte::DatamaskbyteSpec>;
@@ -377,64 +283,64 @@ pub use datamask as pulse;
pub use datamask as pulsebase; pub use datamask as pulsebase;
pub use datamask as delay1; pub use datamask as delay1;
pub use datamask as delay2; pub use datamask as delay2;
pub use datamaskbyte as dirbyte; pub use datamaskbyte as dirbytes;
pub use datamaskbyte as pulsebyte; pub use datamaskbyte as pulsebytes;
pub use datamaskbyte as pulsebasebyte; pub use datamaskbyte as pulsebasebytes;
pub use datamaskbyte as delay1byte; pub use datamaskbyte as delay1bytes;
pub use datamaskbyte as delay2byte; pub use datamaskbyte as delay2bytes;
pub use Datamask as Dir; pub use Datamask as Dir;
pub use Datamask as Pulse; pub use Datamask as Pulse;
pub use Datamask as Pulsebase; pub use Datamask as Pulsebase;
pub use Datamask as Delay1; pub use Datamask as Delay1;
pub use Datamask as Delay2; pub use Datamask as Delay2;
pub use Datamaskbyte as Dirbyte; pub use Datamaskbyte as Dirbytes;
pub use Datamaskbyte as Pulsebyte; pub use Datamaskbyte as Pulsebytes;
pub use Datamaskbyte as Pulsebasebyte; pub use Datamaskbyte as Pulsebasebytes;
pub use Datamaskbyte as Delay1byte; pub use Datamaskbyte as Delay1bytes;
pub use Datamaskbyte as Delay2byte; pub use Datamaskbyte as Delay2bytes;
#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`] #[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`]
module"] module"]
#[doc(alias = "IRQ_SEN")] #[doc(alias = "IRQ_SEN")]
pub type IrqSen = crate::Reg<irq_sen::IrqSenSpec>; pub type IrqSen = crate::Reg<irq_sen::IrqSenSpec>;
#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] #[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
pub mod irq_sen; pub mod irq_sen;
#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`] #[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`]
module"] module"]
#[doc(alias = "IRQ_EDGE")] #[doc(alias = "IRQ_EDGE")]
pub type IrqEdge = crate::Reg<irq_edge::IrqEdgeSpec>; pub type IrqEdge = crate::Reg<irq_edge::IrqEdgeSpec>;
#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"] #[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"]
pub mod irq_edge; pub mod irq_edge;
#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`] #[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`]
module"] module"]
#[doc(alias = "IRQ_EVT")] #[doc(alias = "IRQ_EVT")]
pub type IrqEvt = crate::Reg<irq_evt::IrqEvtSpec>; pub type IrqEvt = crate::Reg<irq_evt::IrqEvtSpec>;
#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"] #[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"]
pub mod irq_evt; pub mod irq_evt;
#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] #[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"] module"]
#[doc(alias = "IRQ_ENB")] #[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>; pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
#[doc = "Interrupt Enable Register"] #[doc = "Interrupt Enable Register"]
pub mod irq_enb; pub mod irq_enb;
#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] #[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
module"] module"]
#[doc(alias = "IRQ_RAW")] #[doc(alias = "IRQ_RAW")]
pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>; pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>;
#[doc = "Raw Interrupt Status"] #[doc = "Raw Interrupt Status"]
pub mod irq_raw; pub mod irq_raw;
#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] #[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
module"] module"]
#[doc(alias = "IRQ_END")] #[doc(alias = "IRQ_END")]
pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>; pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>;
#[doc = "Masked Interrupt Status"] #[doc = "Masked Interrupt Status"]
pub mod irq_end; pub mod irq_end;
#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`] #[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`]
module"] module"]
#[doc(alias = "EDGE_STATUS")] #[doc(alias = "EDGE_STATUS")]
pub type EdgeStatus = crate::Reg<edge_status::EdgeStatusSpec>; pub type EdgeStatus = crate::Reg<edge_status::EdgeStatusSpec>;
#[doc = "Edge Status Register"] #[doc = "Edge Status Register"]
pub mod edge_status; pub mod edge_status;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"] module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;

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@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DatainSpec; pub struct DatainSpec;
impl crate::RegisterSpec for DatainSpec { impl crate::RegisterSpec for DatainSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DatainbyteSpec; pub struct DatainbyteSpec;
impl crate::RegisterSpec for DatainbyteSpec { impl crate::RegisterSpec for DatainbyteSpec {
type Ux = u8; type Ux = u8;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DatamaskSpec; pub struct DatamaskSpec;
impl crate::RegisterSpec for DatamaskSpec { impl crate::RegisterSpec for DatamaskSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DatamaskbyteSpec; pub struct DatamaskbyteSpec;
impl crate::RegisterSpec for DatamaskbyteSpec { impl crate::RegisterSpec for DatamaskbyteSpec {
type Ux = u8; type Ux = u8;

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@@ -6,7 +6,7 @@ impl core::fmt::Debug for crate::generic::Reg<DataoutSpec> {
} }
} }
impl W {} impl W {}
#[doc = "Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataoutSpec; pub struct DataoutSpec;
impl crate::RegisterSpec for DataoutSpec { impl crate::RegisterSpec for DataoutSpec {
type Ux = u32; type Ux = u32;

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@@ -6,7 +6,7 @@ impl core::fmt::Debug for crate::generic::Reg<DataoutbyteSpec> {
} }
} }
impl W {} impl W {}
#[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataoutbyteSpec; pub struct DataoutbyteSpec;
impl crate::RegisterSpec for DataoutbyteSpec { impl crate::RegisterSpec for DataoutbyteSpec {
type Ux = u8; type Ux = u8;

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@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EdgeStatusSpec; pub struct EdgeStatusSpec;
impl crate::RegisterSpec for EdgeStatusSpec { impl crate::RegisterSpec for EdgeStatusSpec {
type Ux = u32; type Ux = u32;

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@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEdgeSpec; pub struct IrqEdgeSpec;
impl crate::RegisterSpec for IrqEdgeSpec { impl crate::RegisterSpec for IrqEdgeSpec {
type Ux = u32; type Ux = u32;

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@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec; pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec { impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32; type Ux = u32;

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@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEndSpec; pub struct IrqEndSpec;
impl crate::RegisterSpec for IrqEndSpec { impl crate::RegisterSpec for IrqEndSpec {
type Ux = u32; type Ux = u32;

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@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEvtSpec; pub struct IrqEvtSpec;
impl crate::RegisterSpec for IrqEvtSpec { impl crate::RegisterSpec for IrqEvtSpec {
type Ux = u32; type Ux = u32;

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@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqRawSpec; pub struct IrqRawSpec;
impl crate::RegisterSpec for IrqRawSpec { impl crate::RegisterSpec for IrqRawSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqSenSpec; pub struct IrqSenSpec;
impl crate::RegisterSpec for IrqSenSpec { impl crate::RegisterSpec for IrqSenSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec; pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec { impl crate::RegisterSpec for PeridSpec {
type Ux = u32; type Ux = u32;

View File

@@ -89,37 +89,37 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] #[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
module"] module"]
#[doc(alias = "CTRL0")] #[doc(alias = "CTRL0")]
pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>; pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>;
#[doc = "Control Register 0"] #[doc = "Control Register 0"]
pub mod ctrl0; pub mod ctrl0;
#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] #[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
module"] module"]
#[doc(alias = "CTRL1")] #[doc(alias = "CTRL1")]
pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>; pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>;
#[doc = "Control Register 1"] #[doc = "Control Register 1"]
pub mod ctrl1; pub mod ctrl1;
#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] #[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"] module"]
#[doc(alias = "DATA")] #[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>; pub type Data = crate::Reg<data::DataSpec>;
#[doc = "Data Input/Output"] #[doc = "Data Input/Output"]
pub mod data; pub mod data;
#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] #[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"] module"]
#[doc(alias = "STATUS")] #[doc(alias = "STATUS")]
pub type Status = crate::Reg<status::StatusSpec>; pub type Status = crate::Reg<status::StatusSpec>;
#[doc = "Status Register"] #[doc = "Status Register"]
pub mod status; pub mod status;
#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`] #[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`]
module"] module"]
#[doc(alias = "CLKPRESCALE")] #[doc(alias = "CLKPRESCALE")]
pub type Clkprescale = crate::Reg<clkprescale::ClkprescaleSpec>; pub type Clkprescale = crate::Reg<clkprescale::ClkprescaleSpec>;
#[doc = "Clock Pre Scale divide value"] #[doc = "Clock Pre Scale divide value"]
pub mod clkprescale; pub mod clkprescale;
#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] #[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"] module"]
#[doc(alias = "IRQ_ENB")] #[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>; pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
@@ -131,31 +131,31 @@ pub use irq_enb as irq_clr;
pub use IrqEnb as IrqRaw; pub use IrqEnb as IrqRaw;
pub use IrqEnb as IrqEnd; pub use IrqEnb as IrqEnd;
pub use IrqEnb as IrqClr; pub use IrqEnb as IrqClr;
#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] #[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
module"] module"]
#[doc(alias = "RXFIFOIRQTRG")] #[doc(alias = "RXFIFOIRQTRG")]
pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>; pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
#[doc = "Rx FIFO IRQ Trigger Level"] #[doc = "Rx FIFO IRQ Trigger Level"]
pub mod rxfifoirqtrg; pub mod rxfifoirqtrg;
#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] #[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
module"] module"]
#[doc(alias = "TXFIFOIRQTRG")] #[doc(alias = "TXFIFOIRQTRG")]
pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>; pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
#[doc = "Tx FIFO IRQ Trigger Level"] #[doc = "Tx FIFO IRQ Trigger Level"]
pub mod txfifoirqtrg; pub mod txfifoirqtrg;
#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] #[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
module"] module"]
#[doc(alias = "FIFO_CLR")] #[doc(alias = "FIFO_CLR")]
pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>; pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
#[doc = "Clear FIFO Register"] #[doc = "Clear FIFO Register"]
pub mod fifo_clr; pub mod fifo_clr;
#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] #[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
module"] module"]
#[doc(alias = "STATE")] #[doc(alias = "STATE")]
pub type State = crate::Reg<state::StateSpec>; pub type State = crate::Reg<state::StateSpec>;
#[doc = "Internal STATE of SPI Controller"] #[doc = "Internal STATE of SPI Controller"]
pub mod state; pub mod state;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"] module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClkprescaleSpec; pub struct ClkprescaleSpec;
impl crate::RegisterSpec for ClkprescaleSpec { impl crate::RegisterSpec for ClkprescaleSpec {
type Ux = u32; type Ux = u32;

View File

@@ -43,30 +43,26 @@ impl R {
impl W { impl W {
#[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"] #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn size(&mut self) -> SizeW<Ctrl0Spec> { pub fn size(&mut self) -> SizeW<Ctrl0Spec> {
SizeW::new(self, 0) SizeW::new(self, 0)
} }
#[doc = "Bit 6 - SPI Clock Polarity"] #[doc = "Bit 6 - SPI Clock Polarity"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn spo(&mut self) -> SpoW<Ctrl0Spec> { pub fn spo(&mut self) -> SpoW<Ctrl0Spec> {
SpoW::new(self, 6) SpoW::new(self, 6)
} }
#[doc = "Bit 7 - SPI Clock Phase"] #[doc = "Bit 7 - SPI Clock Phase"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn sph(&mut self) -> SphW<Ctrl0Spec> { pub fn sph(&mut self) -> SphW<Ctrl0Spec> {
SphW::new(self, 7) SphW::new(self, 7)
} }
#[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"] #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn scrdv(&mut self) -> ScrdvW<Ctrl0Spec> { pub fn scrdv(&mut self) -> ScrdvW<Ctrl0Spec> {
ScrdvW::new(self, 8) ScrdvW::new(self, 8)
} }
} }
#[doc = "Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ctrl0Spec; pub struct Ctrl0Spec;
impl crate::RegisterSpec for Ctrl0Spec { impl crate::RegisterSpec for Ctrl0Spec {
type Ux = u32; type Ux = u32;

View File

@@ -97,66 +97,56 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - Loop Back"] #[doc = "Bit 0 - Loop Back"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn lbm(&mut self) -> LbmW<Ctrl1Spec> { pub fn lbm(&mut self) -> LbmW<Ctrl1Spec> {
LbmW::new(self, 0) LbmW::new(self, 0)
} }
#[doc = "Bit 1 - Enable"] #[doc = "Bit 1 - Enable"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn enable(&mut self) -> EnableW<Ctrl1Spec> { pub fn enable(&mut self) -> EnableW<Ctrl1Spec> {
EnableW::new(self, 1) EnableW::new(self, 1)
} }
#[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"] #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn ms(&mut self) -> MsW<Ctrl1Spec> { pub fn ms(&mut self) -> MsW<Ctrl1Spec> {
MsW::new(self, 2) MsW::new(self, 2)
} }
#[doc = "Bit 3 - Slave output Disable"] #[doc = "Bit 3 - Slave output Disable"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn sod(&mut self) -> SodW<Ctrl1Spec> { pub fn sod(&mut self) -> SodW<Ctrl1Spec> {
SodW::new(self, 3) SodW::new(self, 3)
} }
#[doc = "Bits 4:6 - Slave Select"] #[doc = "Bits 4:6 - Slave Select"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn ss(&mut self) -> SsW<Ctrl1Spec> { pub fn ss(&mut self) -> SsW<Ctrl1Spec> {
SsW::new(self, 4) SsW::new(self, 4)
} }
#[doc = "Bit 7 - Block Mode Enable"] #[doc = "Bit 7 - Block Mode Enable"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn blockmode(&mut self) -> BlockmodeW<Ctrl1Spec> { pub fn blockmode(&mut self) -> BlockmodeW<Ctrl1Spec> {
BlockmodeW::new(self, 7) BlockmodeW::new(self, 7)
} }
#[doc = "Bit 8 - Block Mode Start Status Enable"] #[doc = "Bit 8 - Block Mode Start Status Enable"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn bmstart(&mut self) -> BmstartW<Ctrl1Spec> { pub fn bmstart(&mut self) -> BmstartW<Ctrl1Spec> {
BmstartW::new(self, 8) BmstartW::new(self, 8)
} }
#[doc = "Bit 9 - Block Mode Stall Enable"] #[doc = "Bit 9 - Block Mode Stall Enable"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn bmstall(&mut self) -> BmstallW<Ctrl1Spec> { pub fn bmstall(&mut self) -> BmstallW<Ctrl1Spec> {
BmstallW::new(self, 9) BmstallW::new(self, 9)
} }
#[doc = "Bit 10 - Master Delayed Capture Enable"] #[doc = "Bit 10 - Master Delayed Capture Enable"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn mdlycap(&mut self) -> MdlycapW<Ctrl1Spec> { pub fn mdlycap(&mut self) -> MdlycapW<Ctrl1Spec> {
MdlycapW::new(self, 10) MdlycapW::new(self, 10)
} }
#[doc = "Bit 11 - Master Tx Pause Enable"] #[doc = "Bit 11 - Master Tx Pause Enable"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn mtxpause(&mut self) -> MtxpauseW<Ctrl1Spec> { pub fn mtxpause(&mut self) -> MtxpauseW<Ctrl1Spec> {
MtxpauseW::new(self, 11) MtxpauseW::new(self, 11)
} }
} }
#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ctrl1Spec; pub struct Ctrl1Spec;
impl crate::RegisterSpec for Ctrl1Spec { impl crate::RegisterSpec for Ctrl1Spec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec; pub struct DataSpec;
impl crate::RegisterSpec for DataSpec { impl crate::RegisterSpec for DataSpec {
type Ux = u32; type Ux = u32;

View File

@@ -7,18 +7,16 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W { impl W {
#[doc = "Bit 0 - Clear Rx FIFO"] #[doc = "Bit 0 - Clear Rx FIFO"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> { pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
RxfifoW::new(self, 0) RxfifoW::new(self, 0)
} }
#[doc = "Bit 1 - Clear Tx FIFO"] #[doc = "Bit 1 - Clear Tx FIFO"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> { pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
TxfifoW::new(self, 1) TxfifoW::new(self, 1)
} }
} }
#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoClrSpec; pub struct FifoClrSpec;
impl crate::RegisterSpec for FifoClrSpec { impl crate::RegisterSpec for FifoClrSpec {
type Ux = u32; type Ux = u32;

View File

@@ -43,30 +43,26 @@ impl R {
impl W { impl W {
#[doc = "Bit 0 - RX Overrun"] #[doc = "Bit 0 - RX Overrun"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rorim(&mut self) -> RorimW<IrqEnbSpec> { pub fn rorim(&mut self) -> RorimW<IrqEnbSpec> {
RorimW::new(self, 0) RorimW::new(self, 0)
} }
#[doc = "Bit 1 - RX Timeout"] #[doc = "Bit 1 - RX Timeout"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rtim(&mut self) -> RtimW<IrqEnbSpec> { pub fn rtim(&mut self) -> RtimW<IrqEnbSpec> {
RtimW::new(self, 1) RtimW::new(self, 1)
} }
#[doc = "Bit 2 - RX Fifo is at least half full"] #[doc = "Bit 2 - RX Fifo is at least half full"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn rxim(&mut self) -> RximW<IrqEnbSpec> { pub fn rxim(&mut self) -> RximW<IrqEnbSpec> {
RximW::new(self, 2) RximW::new(self, 2)
} }
#[doc = "Bit 3 - TX Fifo is at least half empty"] #[doc = "Bit 3 - TX Fifo is at least half empty"]
#[inline(always)] #[inline(always)]
#[must_use]
pub fn txim(&mut self) -> TximW<IrqEnbSpec> { pub fn txim(&mut self) -> TximW<IrqEnbSpec> {
TximW::new(self, 3) TximW::new(self, 3)
} }
} }
#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec; pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec { impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec; pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec { impl crate::RegisterSpec for PeridSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxfifoirqtrgSpec; pub struct RxfifoirqtrgSpec;
impl crate::RegisterSpec for RxfifoirqtrgSpec { impl crate::RegisterSpec for RxfifoirqtrgSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "Internal STATE of SPI Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StateSpec; pub struct StateSpec;
impl crate::RegisterSpec for StateSpec { impl crate::RegisterSpec for StateSpec {
type Ux = u32; type Ux = u32;

View File

@@ -58,7 +58,7 @@ impl R {
TxtriggerR::new(((self.bits >> 7) & 1) != 0) TxtriggerR::new(((self.bits >> 7) & 1) != 0)
} }
} }
#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatusSpec; pub struct StatusSpec;
impl crate::RegisterSpec for StatusSpec { impl crate::RegisterSpec for StatusSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxfifoirqtrgSpec; pub struct TxfifoirqtrgSpec;
impl crate::RegisterSpec for TxfifoirqtrgSpec { impl crate::RegisterSpec for TxfifoirqtrgSpec {
type Ux = u32; type Ux = u32;

View File

@@ -131,6 +131,8 @@ impl RegisterBlock {
&self.ioconfig_clkdiv0 &self.ioconfig_clkdiv0
} }
#[doc = "0x4c..0x68 - IO Configuration Clock Divider Register"] #[doc = "0x4c..0x68 - IO Configuration Clock Divider Register"]
#[doc = ""]
#[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `IOCONFIG_CLKDIV1` register.</div>"]
#[inline(always)] #[inline(always)]
pub const fn ioconfig_clkdiv(&self, n: usize) -> &IoconfigClkdiv { pub const fn ioconfig_clkdiv(&self, n: usize) -> &IoconfigClkdiv {
&self.ioconfig_clkdiv[n] &self.ioconfig_clkdiv[n]
@@ -232,7 +234,7 @@ impl RegisterBlock {
&self.perid &self.perid
} }
} }
#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`] #[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`]
module"] module"]
#[doc(alias = "RST_STAT")] #[doc(alias = "RST_STAT")]
pub type RstStat = crate::Reg<rst_stat::RstStatSpec>; pub type RstStat = crate::Reg<rst_stat::RstStatSpec>;
@@ -242,13 +244,13 @@ pub use rst_stat as rst_cntl_rom;
pub use rst_stat as rst_cntl_ram; pub use rst_stat as rst_cntl_ram;
pub use RstStat as RstCntlRom; pub use RstStat as RstCntlRom;
pub use RstStat as RstCntlRam; pub use RstStat as RstCntlRam;
#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`] #[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`]
module"] module"]
#[doc(alias = "ROM_PROT")] #[doc(alias = "ROM_PROT")]
pub type RomProt = crate::Reg<rom_prot::RomProtSpec>; pub type RomProt = crate::Reg<rom_prot::RomProtSpec>;
#[doc = "ROM Protection Configuration"] #[doc = "ROM Protection Configuration"]
pub mod rom_prot; pub mod rom_prot;
#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`] #[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`]
module"] module"]
#[doc(alias = "ROM_SCRUB")] #[doc(alias = "ROM_SCRUB")]
pub type RomScrub = crate::Reg<rom_scrub::RomScrubSpec>; pub type RomScrub = crate::Reg<rom_scrub::RomScrubSpec>;
@@ -256,13 +258,13 @@ pub type RomScrub = crate::Reg<rom_scrub::RomScrubSpec>;
pub mod rom_scrub; pub mod rom_scrub;
pub use rom_scrub as ram_scrub; pub use rom_scrub as ram_scrub;
pub use RomScrub as RamScrub; pub use RomScrub as RamScrub;
#[doc = "ROM_TRAP_ADDR (rw) register accessor: ROM Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_addr`] #[doc = "ROM_TRAP_ADDR (rw) register accessor: ROM Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_addr`]
module"] module"]
#[doc(alias = "ROM_TRAP_ADDR")] #[doc(alias = "ROM_TRAP_ADDR")]
pub type RomTrapAddr = crate::Reg<rom_trap_addr::RomTrapAddrSpec>; pub type RomTrapAddr = crate::Reg<rom_trap_addr::RomTrapAddrSpec>;
#[doc = "ROM Trap Address"] #[doc = "ROM Trap Address"]
pub mod rom_trap_addr; pub mod rom_trap_addr;
#[doc = "ROM_TRAP_SYND (rw) register accessor: ROM Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_synd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`] #[doc = "ROM_TRAP_SYND (rw) register accessor: ROM Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`]
module"] module"]
#[doc(alias = "ROM_TRAP_SYND")] #[doc(alias = "ROM_TRAP_SYND")]
pub type RomTrapSynd = crate::Reg<rom_trap_synd::RomTrapSyndSpec>; pub type RomTrapSynd = crate::Reg<rom_trap_synd::RomTrapSyndSpec>;
@@ -272,7 +274,7 @@ pub use rom_trap_addr as ram_trap_addr;
pub use rom_trap_synd as ram_trap_synd; pub use rom_trap_synd as ram_trap_synd;
pub use RomTrapAddr as RamTrapAddr; pub use RomTrapAddr as RamTrapAddr;
pub use RomTrapSynd as RamTrapSynd; pub use RomTrapSynd as RamTrapSynd;
#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] #[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"] module"]
#[doc(alias = "IRQ_ENB")] #[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>; pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
@@ -284,7 +286,7 @@ pub use irq_enb as irq_clr;
pub use IrqEnb as IrqRaw; pub use IrqEnb as IrqRaw;
pub use IrqEnb as IrqEnd; pub use IrqEnb as IrqEnd;
pub use IrqEnb as IrqClr; pub use IrqEnb as IrqClr;
#[doc = "RAM_SBE (rw) register accessor: Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_sbe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_sbe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sbe`] #[doc = "RAM_SBE (rw) register accessor: Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sbe`]
module"] module"]
#[doc(alias = "RAM_SBE")] #[doc(alias = "RAM_SBE")]
pub type RamSbe = crate::Reg<ram_sbe::RamSbeSpec>; pub type RamSbe = crate::Reg<ram_sbe::RamSbeSpec>;
@@ -296,79 +298,79 @@ pub use ram_sbe as rom_mbe;
pub use RamSbe as RamMbe; pub use RamSbe as RamMbe;
pub use RamSbe as RomSbe; pub use RamSbe as RomSbe;
pub use RamSbe as RomMbe; pub use RamSbe as RomMbe;
#[doc = "IOCONFIG_CLKDIV0 (r) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv0`] #[doc = "IOCONFIG_CLKDIV0 (r) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv0`]
module"] module"]
#[doc(alias = "IOCONFIG_CLKDIV0")] #[doc(alias = "IOCONFIG_CLKDIV0")]
pub type IoconfigClkdiv0 = crate::Reg<ioconfig_clkdiv0::IoconfigClkdiv0Spec>; pub type IoconfigClkdiv0 = crate::Reg<ioconfig_clkdiv0::IoconfigClkdiv0Spec>;
#[doc = "IO Configuration Clock Divider Register"] #[doc = "IO Configuration Clock Divider Register"]
pub mod ioconfig_clkdiv0; pub mod ioconfig_clkdiv0;
#[doc = "IOCONFIG_CLKDIV (rw) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv`] #[doc = "IOCONFIG_CLKDIV (rw) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv`]
module"] module"]
#[doc(alias = "IOCONFIG_CLKDIV")] #[doc(alias = "IOCONFIG_CLKDIV")]
pub type IoconfigClkdiv = crate::Reg<ioconfig_clkdiv::IoconfigClkdivSpec>; pub type IoconfigClkdiv = crate::Reg<ioconfig_clkdiv::IoconfigClkdivSpec>;
#[doc = "IO Configuration Clock Divider Register"] #[doc = "IO Configuration Clock Divider Register"]
pub mod ioconfig_clkdiv; pub mod ioconfig_clkdiv;
#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`] #[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`]
module"] module"]
#[doc(alias = "ROM_RETRIES")] #[doc(alias = "ROM_RETRIES")]
pub type RomRetries = crate::Reg<rom_retries::RomRetriesSpec>; pub type RomRetries = crate::Reg<rom_retries::RomRetriesSpec>;
#[doc = "ROM BOOT Retry count"] #[doc = "ROM BOOT Retry count"]
pub mod rom_retries; pub mod rom_retries;
#[doc = "REFRESH_CONFIG (rw) register accessor: Register Refresh Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config`] #[doc = "REFRESH_CONFIG (rw) register accessor: Register Refresh Control\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config`]
module"] module"]
#[doc(alias = "REFRESH_CONFIG")] #[doc(alias = "REFRESH_CONFIG")]
pub type RefreshConfig = crate::Reg<refresh_config::RefreshConfigSpec>; pub type RefreshConfig = crate::Reg<refresh_config::RefreshConfigSpec>;
#[doc = "Register Refresh Control"] #[doc = "Register Refresh Control"]
pub mod refresh_config; pub mod refresh_config;
#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`] #[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`]
module"] module"]
#[doc(alias = "TIM_RESET")] #[doc(alias = "TIM_RESET")]
pub type TimReset = crate::Reg<tim_reset::TimResetSpec>; pub type TimReset = crate::Reg<tim_reset::TimResetSpec>;
#[doc = "TIM Reset Control"] #[doc = "TIM Reset Control"]
pub mod tim_reset; pub mod tim_reset;
#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`] #[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`]
module"] module"]
#[doc(alias = "TIM_CLK_ENABLE")] #[doc(alias = "TIM_CLK_ENABLE")]
pub type TimClkEnable = crate::Reg<tim_clk_enable::TimClkEnableSpec>; pub type TimClkEnable = crate::Reg<tim_clk_enable::TimClkEnableSpec>;
#[doc = "TIM Enable Control"] #[doc = "TIM Enable Control"]
pub mod tim_clk_enable; pub mod tim_clk_enable;
#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`] #[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`]
module"] module"]
#[doc(alias = "PERIPHERAL_RESET")] #[doc(alias = "PERIPHERAL_RESET")]
pub type PeripheralReset = crate::Reg<peripheral_reset::PeripheralResetSpec>; pub type PeripheralReset = crate::Reg<peripheral_reset::PeripheralResetSpec>;
#[doc = "Peripheral Reset Control"] #[doc = "Peripheral Reset Control"]
pub mod peripheral_reset; pub mod peripheral_reset;
#[doc = "PERIPHERAL_CLK_ENABLE (rw) register accessor: Peripheral Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_clk_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_clk_enable`] #[doc = "PERIPHERAL_CLK_ENABLE (rw) register accessor: Peripheral Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_clk_enable`]
module"] module"]
#[doc(alias = "PERIPHERAL_CLK_ENABLE")] #[doc(alias = "PERIPHERAL_CLK_ENABLE")]
pub type PeripheralClkEnable = crate::Reg<peripheral_clk_enable::PeripheralClkEnableSpec>; pub type PeripheralClkEnable = crate::Reg<peripheral_clk_enable::PeripheralClkEnableSpec>;
#[doc = "Peripheral Enable Control"] #[doc = "Peripheral Enable Control"]
pub mod peripheral_clk_enable; pub mod peripheral_clk_enable;
#[doc = "LOCKUP_RESET (rw) register accessor: Lockup Reset Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lockup_reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lockup_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lockup_reset`] #[doc = "LOCKUP_RESET (rw) register accessor: Lockup Reset Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lockup_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockup_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lockup_reset`]
module"] module"]
#[doc(alias = "LOCKUP_RESET")] #[doc(alias = "LOCKUP_RESET")]
pub type LockupReset = crate::Reg<lockup_reset::LockupResetSpec>; pub type LockupReset = crate::Reg<lockup_reset::LockupResetSpec>;
#[doc = "Lockup Reset Configuration"] #[doc = "Lockup Reset Configuration"]
pub mod lockup_reset; pub mod lockup_reset;
#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`] #[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`]
module"] module"]
#[doc(alias = "EF_CONFIG")] #[doc(alias = "EF_CONFIG")]
pub type EfConfig = crate::Reg<ef_config::EfConfigSpec>; pub type EfConfig = crate::Reg<ef_config::EfConfigSpec>;
#[doc = "EFuse Config Register"] #[doc = "EFuse Config Register"]
pub mod ef_config; pub mod ef_config;
#[doc = "EF_ID (r) register accessor: EFuse ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id`] #[doc = "EF_ID (r) register accessor: EFuse ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id`]
module"] module"]
#[doc(alias = "EF_ID")] #[doc(alias = "EF_ID")]
pub type EfId = crate::Reg<ef_id::EfIdSpec>; pub type EfId = crate::Reg<ef_id::EfIdSpec>;
#[doc = "EFuse ID Register"] #[doc = "EFuse ID Register"]
pub mod ef_id; pub mod ef_id;
#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`] #[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`]
module"] module"]
#[doc(alias = "PROCID")] #[doc(alias = "PROCID")]
pub type Procid = crate::Reg<procid::ProcidSpec>; pub type Procid = crate::Reg<procid::ProcidSpec>;
#[doc = "Processor ID Register"] #[doc = "Processor ID Register"]
pub mod procid; pub mod procid;
#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] #[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"] module"]
#[doc(alias = "PERID")] #[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>; pub type Perid = crate::Reg<perid::PeridSpec>;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EfConfigSpec; pub struct EfConfigSpec;
impl crate::RegisterSpec for EfConfigSpec { impl crate::RegisterSpec for EfConfigSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "EFuse ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "EFuse ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EfIdSpec; pub struct EfIdSpec;
impl crate::RegisterSpec for EfIdSpec { impl crate::RegisterSpec for EfIdSpec {
type Ux = u32; type Ux = u32;

View File

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
} }
} }
impl W {} impl W {}
#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IoconfigClkdivSpec; pub struct IoconfigClkdivSpec;
impl crate::RegisterSpec for IoconfigClkdivSpec { impl crate::RegisterSpec for IoconfigClkdivSpec {
type Ux = u32; type Ux = u32;

View File

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits()) write!(f, "{}", self.bits())
} }
} }
#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] #[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IoconfigClkdiv0Spec; pub struct IoconfigClkdiv0Spec;
impl crate::RegisterSpec for IoconfigClkdiv0Spec { impl crate::RegisterSpec for IoconfigClkdiv0Spec {
type Ux = u32; type Ux = u32;

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