update error handling

board-tests/src/main.rs

@@ -17,7 +17,7 @@ use va108xx_hal::{
     pac::{self, interrupt},
     prelude::*,
     time::Hertz,
-    timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer, InterruptConfig},
+    timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer, IrqCfg},
 };
 
 #[allow(dead_code)]
@@ -44,8 +44,8 @@ fn main() -> ! {
     rprintln!("-- VA108xx Test Application --");
     let mut dp = pac::Peripherals::take().unwrap();
     let cp = cortex_m::Peripherals::take().unwrap();
-    let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
-    let pinsb = PinsB::new(&mut dp.sysconfig, dp.portb);
+    let pinsb = PinsB::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.portb);
     let mut led1 = pinsa.pa10.into_readable_push_pull_output();
     let test_case = TestCase::DelayMs;
 
@@ -155,7 +155,7 @@ fn main() -> ! {
         }
         TestCase::DelayMs => {
             let mut ms_timer = set_up_ms_tick(
-                InterruptConfig::new(pac::Interrupt::OC0, true, true),
+                IrqCfg::new(pac::Interrupt::OC0, true, true),
                 &mut dp.sysconfig,
                 Some(&mut dp.irqsel),
                 50.MHz(),

examples/embassy/Cargo.toml

@@ -8,8 +8,6 @@ cfg-if = "1"
 cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7"
 embedded-hal = "1"
-embedded-hal-async = "1"
-embedded-io-async = "0.6"
 
 rtt-target = "0.6"
 panic-rtt-target = "0.2"

examples/embassy/src/bin/async-gpio.rs

@@ -1,258 +0,0 @@
-//! This example demonstrates the usage of async GPIO operations on VA108xx.
-//!
-//! You need to tie the PA0 to the PA1 pin for this example to work. You can optionally tie the PB22 to PB23 pins well
-//! and then set the `CHECK_PB22_TO_PB23` to true to also test async operations on Port B.
-#![no_std]
-#![no_main]
-
-use embassy_executor::Spawner;
-use embassy_sync::channel::{Receiver, Sender};
-use embassy_sync::{blocking_mutex::raw::ThreadModeRawMutex, channel::Channel};
-use embassy_time::{Duration, Instant, Timer};
-use embedded_hal::digital::{InputPin, OutputPin, StatefulOutputPin};
-use embedded_hal_async::digital::Wait;
-use panic_rtt_target as _;
-use rtt_target::{rprintln, rtt_init_print};
-use va108xx_embassy::embassy;
-use va108xx_hal::gpio::{on_interrupt_for_asynch_gpio, InputDynPinAsync, InputPinAsync, PinsB};
-use va108xx_hal::{
-    gpio::{DynPin, PinsA},
-    pac::{self, interrupt},
-    prelude::*,
-};
-
-const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
-
-const CHECK_PA0_TO_PA1: bool = true;
-const CHECK_PB22_TO_PB23: bool = false;
-
-// Can also be set to OC10 and works as well.
-const PB22_TO_PB23_IRQ: pac::Interrupt = pac::Interrupt::OC11;
-
-#[derive(Clone, Copy)]
-pub struct GpioCmd {
-    cmd_type: GpioCmdType,
-    after_delay: u32,
-}
-
-impl GpioCmd {
-    pub fn new(cmd_type: GpioCmdType, after_delay: u32) -> Self {
-        Self {
-            cmd_type,
-            after_delay,
-        }
-    }
-}
-
-#[derive(Clone, Copy)]
-pub enum GpioCmdType {
-    SetHigh,
-    SetLow,
-    RisingEdge,
-    FallingEdge,
-}
-
-// Declare a bounded channel of 3 u32s.
-static CHANNEL_PA0_PA1: Channel<ThreadModeRawMutex, GpioCmd, 3> = Channel::new();
-static CHANNEL_PB22_TO_PB23: Channel<ThreadModeRawMutex, GpioCmd, 3> = Channel::new();
-
-#[embassy_executor::main]
-async fn main(spawner: Spawner) {
-    rtt_init_print!();
-    rprintln!("-- VA108xx Async GPIO Demo --");
-
-    let mut dp = pac::Peripherals::take().unwrap();
-
-    // Safety: Only called once here.
-    unsafe {
-        embassy::init(
-            &mut dp.sysconfig,
-            &dp.irqsel,
-            SYSCLK_FREQ,
-            dp.tim23,
-            dp.tim22,
-        )
-    };
-
-    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
-    let portb = PinsB::new(&mut dp.sysconfig, dp.portb);
-    let mut led0 = porta.pa10.into_readable_push_pull_output();
-    let out_pa0 = porta.pa0.into_readable_push_pull_output();
-    let in_pa1 = porta.pa1.into_floating_input();
-    let out_pb22 = portb.pb22.into_readable_push_pull_output();
-    let in_pb23 = portb.pb23.into_floating_input();
-
-    let in_pa1_async = InputPinAsync::new(in_pa1, pac::Interrupt::OC10);
-    let out_pa0_dyn = out_pa0.downgrade();
-    let in_pb23_async = InputDynPinAsync::new(in_pb23.downgrade(), PB22_TO_PB23_IRQ).unwrap();
-    let out_pb22_dyn = out_pb22.downgrade();
-
-    spawner
-        .spawn(output_task(
-            "PA0 to PA1",
-            out_pa0_dyn,
-            CHANNEL_PA0_PA1.receiver(),
-        ))
-        .unwrap();
-    spawner
-        .spawn(output_task(
-            "PB22 to PB23",
-            out_pb22_dyn,
-            CHANNEL_PB22_TO_PB23.receiver(),
-        ))
-        .unwrap();
-
-    if CHECK_PA0_TO_PA1 {
-        check_pin_to_pin_async_ops("PA0 to PA1", CHANNEL_PA0_PA1.sender(), in_pa1_async).await;
-        rprintln!("Example PA0 to PA1 done");
-    }
-    if CHECK_PB22_TO_PB23 {
-        check_pin_to_pin_async_ops("PB22 to PB23", CHANNEL_PB22_TO_PB23.sender(), in_pb23_async)
-            .await;
-        rprintln!("Example PB22 to PB23 done");
-    }
-
-    rprintln!("Example done, toggling LED0");
-    loop {
-        led0.toggle().unwrap();
-        Timer::after(Duration::from_millis(500)).await;
-    }
-}
-
-async fn check_pin_to_pin_async_ops(
-    ctx: &'static str,
-    sender: Sender<'static, ThreadModeRawMutex, GpioCmd, 3>,
-    mut async_input: impl Wait,
-) {
-    rprintln!(
-        "{}: sending SetHigh command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender.send(GpioCmd::new(GpioCmdType::SetHigh, 20)).await;
-    async_input.wait_for_high().await.unwrap();
-    rprintln!(
-        "{}: Input pin is high now ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-
-    rprintln!(
-        "{}: sending SetLow command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender.send(GpioCmd::new(GpioCmdType::SetLow, 20)).await;
-    async_input.wait_for_low().await.unwrap();
-    rprintln!(
-        "{}: Input pin is low now ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-
-    rprintln!(
-        "{}: sending RisingEdge command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender.send(GpioCmd::new(GpioCmdType::RisingEdge, 20)).await;
-    async_input.wait_for_rising_edge().await.unwrap();
-    rprintln!(
-        "{}: input pin had rising edge ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-
-    rprintln!(
-        "{}: sending Falling command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender
-        .send(GpioCmd::new(GpioCmdType::FallingEdge, 20))
-        .await;
-    async_input.wait_for_falling_edge().await.unwrap();
-    rprintln!(
-        "{}: input pin had a falling edge ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-
-    rprintln!(
-        "{}: sending Falling command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender
-        .send(GpioCmd::new(GpioCmdType::FallingEdge, 20))
-        .await;
-    async_input.wait_for_any_edge().await.unwrap();
-    rprintln!(
-        "{}: input pin had a falling (any) edge ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-
-    rprintln!(
-        "{}: sending Falling command ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-    sender.send(GpioCmd::new(GpioCmdType::RisingEdge, 20)).await;
-    async_input.wait_for_any_edge().await.unwrap();
-    rprintln!(
-        "{}: input pin had a rising (any) edge ({} ms)",
-        ctx,
-        Instant::now().as_millis()
-    );
-}
-
-#[embassy_executor::task(pool_size = 2)]
-async fn output_task(
-    ctx: &'static str,
-    mut out: DynPin,
-    receiver: Receiver<'static, ThreadModeRawMutex, GpioCmd, 3>,
-) {
-    loop {
-        let next_cmd = receiver.receive().await;
-        Timer::after(Duration::from_millis(next_cmd.after_delay.into())).await;
-        match next_cmd.cmd_type {
-            GpioCmdType::SetHigh => {
-                rprintln!("{}: Set output high", ctx);
-                out.set_high().unwrap();
-            }
-            GpioCmdType::SetLow => {
-                rprintln!("{}: Set output low", ctx);
-                out.set_low().unwrap();
-            }
-            GpioCmdType::RisingEdge => {
-                rprintln!("{}: Rising edge", ctx);
-                if !out.is_low().unwrap() {
-                    out.set_low().unwrap();
-                }
-                out.set_high().unwrap();
-            }
-            GpioCmdType::FallingEdge => {
-                rprintln!("{}: Falling edge", ctx);
-                if !out.is_high().unwrap() {
-                    out.set_high().unwrap();
-                }
-                out.set_low().unwrap();
-            }
-        }
-    }
-}
-
-// PB22 to PB23 can be handled by both OC10 and OC11 depending on configuration.
-
-#[interrupt]
-#[allow(non_snake_case)]
-fn OC10() {
-    on_interrupt_for_asynch_gpio();
-}
-
-#[interrupt]
-#[allow(non_snake_case)]
-fn OC11() {
-    on_interrupt_for_asynch_gpio();
-}

examples/embassy/src/bin/async-uart.rs

@@ -1,87 +0,0 @@
-#![no_std]
-#![no_main]
-use embassy_executor::Spawner;
-use embassy_time::{Duration, Instant, Ticker};
-use embedded_hal::digital::StatefulOutputPin;
-use embedded_io_async::Write;
-use panic_rtt_target as _;
-use rtt_target::{rprintln, rtt_init_print};
-use va108xx_embassy::embassy;
-use va108xx_hal::{
-    gpio::PinsA,
-    pac::{self, interrupt},
-    prelude::*,
-    uart::{self, on_interrupt_uart_a_tx, TxAsync},
-    InterruptConfig,
-};
-
-const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
-
-const STR_LIST: &[&str] = &[
-    "Hello World\r\n",
-    "Smoll\r\n",
-    "A string which is larger than the FIFO size\r\n",
-    "A really large string which is significantly larger than the FIFO size\r\n",
-];
-
-// main is itself an async function.
-#[embassy_executor::main]
-async fn main(_spawner: Spawner) {
-    rtt_init_print!();
-    rprintln!("-- VA108xx Embassy Demo --");
-
-    let mut dp = pac::Peripherals::take().unwrap();
-
-    // Safety: Only called once here.
-    unsafe {
-        embassy::init(
-            &mut dp.sysconfig,
-            &dp.irqsel,
-            SYSCLK_FREQ,
-            dp.tim23,
-            dp.tim22,
-        );
-    }
-
-    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
-    let mut led0 = porta.pa10.into_readable_push_pull_output();
-    let mut led1 = porta.pa7.into_readable_push_pull_output();
-    let mut led2 = porta.pa6.into_readable_push_pull_output();
-
-    let tx = porta.pa9.into_funsel_2();
-    let rx = porta.pa8.into_funsel_2();
-
-    let uarta = uart::Uart::new_with_interrupt(
-        &mut dp.sysconfig,
-        50.MHz(),
-        dp.uarta,
-        (tx, rx),
-        115200.Hz(),
-        InterruptConfig::new(pac::Interrupt::OC2, true, true),
-    );
-    let (tx, _rx) = uarta.split();
-    let mut async_tx = TxAsync::new(tx);
-    let mut ticker = Ticker::every(Duration::from_secs(1));
-    let mut idx = 0;
-    loop {
-        rprintln!("Current time: {}", Instant::now().as_secs());
-        led0.toggle().ok();
-        led1.toggle().ok();
-        led2.toggle().ok();
-        let _written = async_tx
-            .write(STR_LIST[idx].as_bytes())
-            .await
-            .expect("writing failed");
-        idx += 1;
-        if idx == STR_LIST.len() {
-            idx = 0;
-        }
-        ticker.next().await;
-    }
-}
-
-#[interrupt]
-#[allow(non_snake_case)]
-fn OC2() {
-    on_interrupt_uart_a_tx();
-}

examples/embassy/src/main.rs

@@ -52,7 +52,7 @@ async fn main(_spawner: Spawner) {
         }
     }
 
-    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
     let mut led0 = porta.pa10.into_readable_push_pull_output();
     let mut led1 = porta.pa7.into_readable_push_pull_output();
     let mut led2 = porta.pa6.into_readable_push_pull_output();

examples/rtic/Cargo.toml

@@ -22,5 +22,5 @@ rtic-sync = { version = "1.3", features = ["defmt-03"] }
 once_cell = {version = "1", default-features = false, features = ["critical-section"]}
 ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
 
-va108xx-hal = { version = "0.8", path = "../../va108xx-hal" }
+va108xx-hal = "0.8"
 vorago-reb1 = { path = "../../vorago-reb1" }

examples/rtic/src/bin/blinky-button-rtic.rs

@@ -12,7 +12,7 @@ mod app {
         gpio::{FilterType, InterruptEdge, PinsA},
         pac,
         prelude::*,
-        timer::{default_ms_irq_handler, set_up_ms_tick, InterruptConfig},
+        timer::{default_ms_irq_handler, set_up_ms_tick, IrqCfg},
     };
     use vorago_reb1::button::Button;
     use vorago_reb1::leds::Leds;
@@ -61,24 +61,23 @@ mod app {
         rprintln!("Using {:?} mode", mode);
 
         let mut dp = cx.device;
-        let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
+        let pinsa = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
         let edge_irq = match mode {
             PressMode::Toggle => InterruptEdge::HighToLow,
             PressMode::Keep => InterruptEdge::BothEdges,
         };
 
         // Configure an edge interrupt on the button and route it to interrupt vector 15
-        let mut button = Button::new(pinsa.pa11.into_floating_input());
+        let mut button = Button::new(pinsa.pa11.into_floating_input()).edge_irq(
-        button.configure_edge_interrupt(
             edge_irq,
-            InterruptConfig::new(pac::interrupt::OC15, true, true),
+            IrqCfg::new(pac::interrupt::OC15, true, true),
             Some(&mut dp.sysconfig),
             Some(&mut dp.irqsel),
         );
 
         if mode == PressMode::Toggle {
             // This filter debounces the switch for edge based interrupts
-            button.configure_filter_type(FilterType::FilterFourClockCycles, FilterClkSel::Clk1);
+            button = button.filter_type(FilterType::FilterFourClockCycles, FilterClkSel::Clk1);
             set_clk_div_register(&mut dp.sysconfig, FilterClkSel::Clk1, 50_000);
         }
         let mut leds = Leds::new(
@@ -90,7 +89,7 @@ mod app {
             led.off();
         }
         set_up_ms_tick(
-            InterruptConfig::new(pac::Interrupt::OC0, true, true),
+            IrqCfg::new(pac::Interrupt::OC0, true, true),
             &mut dp.sysconfig,
             Some(&mut dp.irqsel),
             50.MHz(),

examples/rtic/src/bin/uart-echo-rtic.rs

@@ -23,13 +23,12 @@ mod app {
         gpio::PinsA,
         pac,
         prelude::*,
-        uart::{self, RxWithInterrupt, Tx},
+        uart::{self, RxWithIrq, Tx},
-        InterruptConfig,
     };
 
     #[local]
     struct Local {
-        rx: RxWithInterrupt<pac::Uarta>,
+        rx: RxWithIrq<pac::Uarta>,
         tx: Tx<pac::Uarta>,
     }
 
@@ -48,20 +47,19 @@ mod app {
         Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
 
         let mut dp = cx.device;
-        let gpioa = PinsA::new(&mut dp.sysconfig, dp.porta);
+        let gpioa = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
         let tx = gpioa.pa9.into_funsel_2();
         let rx = gpioa.pa8.into_funsel_2();
 
-        let irq_uart = uart::Uart::new_with_interrupt(
+        let irq_uart = uart::Uart::new(
             &mut dp.sysconfig,
             SYSCLK_FREQ,
             dp.uarta,
             (tx, rx),
             115200.Hz(),
-            InterruptConfig::new(pac::Interrupt::OC3, true, true),
         );
         let (tx, rx) = irq_uart.split();
-        let mut rx = rx.into_rx_with_irq();
+        let mut rx = rx.into_rx_with_irq(&mut dp.sysconfig, &mut dp.irqsel, pac::interrupt::OC3);
 
         rx.start();
 
@@ -92,7 +90,7 @@ mod app {
     fn reception_task(mut cx: reception_task::Context) {
         let mut buf: [u8; 16] = [0; 16];
         let mut ringbuf_full = false;
-        let result = cx.local.rx.on_interrupt(&mut buf);
+        let result = cx.local.rx.irq_handler(&mut buf);
         if result.bytes_read > 0 && result.errors.is_none() {
             cx.shared.rb.lock(|rb| {
                 if rb.vacant_len() < result.bytes_read {

examples/rtic/src/main.rs

@@ -35,7 +35,11 @@ mod app {
 
         Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
 
-        let porta = PinsA::new(&mut cx.device.sysconfig, cx.device.porta);
+        let porta = PinsA::new(
+            &mut cx.device.sysconfig,
+            Some(cx.device.ioconfig),
+            cx.device.porta,
+        );
         let led0 = porta.pa10.into_readable_push_pull_output();
         let led1 = porta.pa7.into_readable_push_pull_output();
         let led2 = porta.pa6.into_readable_push_pull_output();

examples/simple/Cargo.toml

@@ -16,7 +16,6 @@ embedded-io = "0.6"
 cortex-m-semihosting = "0.5.0"
 
 [dependencies.va108xx-hal]
-path = "../../va108xx-hal"
 version = "0.8"
 features = ["rt", "defmt"]
 

examples/simple/examples/blinky.rs

@@ -18,14 +18,14 @@ use va108xx_hal::{
     prelude::*,
     timer::DelayMs,
     timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer},
-    InterruptConfig,
+    IrqCfg,
 };
 
 #[entry]
 fn main() -> ! {
     let mut dp = pac::Peripherals::take().unwrap();
     let mut delay_ms = DelayMs::new(set_up_ms_tick(
-        InterruptConfig::new(interrupt::OC0, true, true),
+        IrqCfg::new(interrupt::OC0, true, true),
         &mut dp.sysconfig,
         Some(&mut dp.irqsel),
         50.MHz(),
@@ -33,7 +33,7 @@ fn main() -> ! {
     ))
     .unwrap();
     let mut delay_tim1 = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim1);
-    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
     let mut led1 = porta.pa10.into_readable_push_pull_output();
     let mut led2 = porta.pa7.into_readable_push_pull_output();
     let mut led3 = porta.pa6.into_readable_push_pull_output();

examples/simple/examples/cascade.rs

@@ -17,7 +17,7 @@ use va108xx_hal::{
     prelude::*,
     timer::{
         default_ms_irq_handler, set_up_ms_delay_provider, CascadeCtrl, CascadeSource,
-        CountdownTimer, Event, InterruptConfig,
+        CountdownTimer, Event, IrqCfg,
     },
 };
 
@@ -39,7 +39,7 @@ fn main() -> ! {
         CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim3).auto_disable(true);
     cascade_triggerer.listen(
         Event::TimeOut,
-        InterruptConfig::new(pac::Interrupt::OC1, true, false),
+        IrqCfg::new(pac::Interrupt::OC1, true, false),
         Some(&mut dp.irqsel),
         Some(&mut dp.sysconfig),
     );
@@ -62,7 +62,7 @@ fn main() -> ! {
     // the timer expires
     cascade_target_1.listen(
         Event::TimeOut,
-        InterruptConfig::new(pac::Interrupt::OC2, true, false),
+        IrqCfg::new(pac::Interrupt::OC2, true, false),
         Some(&mut dp.irqsel),
         Some(&mut dp.sysconfig),
     );
@@ -88,7 +88,7 @@ fn main() -> ! {
     // the timer expires
     cascade_target_2.listen(
         Event::TimeOut,
-        InterruptConfig::new(pac::Interrupt::OC3, true, false),
+        IrqCfg::new(pac::Interrupt::OC3, true, false),
         Some(&mut dp.irqsel),
         Some(&mut dp.sysconfig),
     );

examples/simple/examples/pwm.rs

@@ -19,7 +19,7 @@ fn main() -> ! {
     rtt_init_print!();
     rprintln!("-- VA108xx PWM example application--");
     let mut dp = pac::Peripherals::take().unwrap();
-    let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
     let mut pwm = pwm::PwmPin::new(
         &mut dp.sysconfig,
         50.MHz(),

examples/simple/examples/spi.rs

@@ -17,7 +17,7 @@ use va108xx_hal::{
     prelude::*,
     spi::{self, Spi, SpiBase, SpiClkConfig, TransferConfigWithHwcs},
     timer::{default_ms_irq_handler, set_up_ms_tick},
-    InterruptConfig,
+    IrqCfg,
 };
 
 #[derive(PartialEq, Debug)]
@@ -47,7 +47,7 @@ fn main() -> ! {
     rprintln!("-- VA108xx SPI example application--");
     let mut dp = pac::Peripherals::take().unwrap();
     let mut delay = set_up_ms_tick(
-        InterruptConfig::new(interrupt::OC0, true, true),
+        IrqCfg::new(interrupt::OC0, true, true),
         &mut dp.sysconfig,
         Some(&mut dp.irqsel),
         50.MHz(),
@@ -58,8 +58,8 @@ fn main() -> ! {
         .expect("creating SPI clock config failed");
     let spia_ref: RefCell<Option<SpiBase<pac::Spia, u8>>> = RefCell::new(None);
     let spib_ref: RefCell<Option<SpiBase<pac::Spib, u8>>> = RefCell::new(None);
-    let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
-    let pinsb = PinsB::new(&mut dp.sysconfig, dp.portb);
+    let pinsb = PinsB::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.portb);
 
     let mut spi_cfg = spi::SpiConfig::default();
     if EXAMPLE_SEL == ExampleSelect::Loopback {

examples/simple/examples/timer-ticks.rs

@@ -12,9 +12,7 @@ use va108xx_hal::{
     pac::{self, interrupt},
     prelude::*,
     time::Hertz,
-    timer::{
+    timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer, Event, IrqCfg, MS_COUNTER},
-        default_ms_irq_handler, set_up_ms_tick, CountdownTimer, Event, InterruptConfig, MS_COUNTER,
-    },
 };
 
 #[allow(dead_code)]
@@ -67,7 +65,7 @@ fn main() -> ! {
         }
         LibType::Hal => {
             set_up_ms_tick(
-                InterruptConfig::new(interrupt::OC0, true, true),
+                IrqCfg::new(interrupt::OC0, true, true),
                 &mut dp.sysconfig,
                 Some(&mut dp.irqsel),
                 50.MHz(),
@@ -77,7 +75,7 @@ fn main() -> ! {
                 CountdownTimer::new(&mut dp.sysconfig, get_sys_clock().unwrap(), dp.tim1);
             second_timer.listen(
                 Event::TimeOut,
-                InterruptConfig::new(interrupt::OC1, true, true),
+                IrqCfg::new(interrupt::OC1, true, true),
                 Some(&mut dp.irqsel),
                 Some(&mut dp.sysconfig),
             );

examples/simple/examples/uart.rs

@@ -24,17 +24,11 @@ fn main() -> ! {
 
     let mut dp = pac::Peripherals::take().unwrap();
 
-    let gpioa = PinsA::new(&mut dp.sysconfig, dp.porta);
+    let gpioa = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
     let tx = gpioa.pa9.into_funsel_2();
     let rx = gpioa.pa8.into_funsel_2();
 
-    let uarta = uart::Uart::new_without_interrupt(
+    let uarta = uart::Uart::new(&mut dp.sysconfig, 50.MHz(), dp.uarta, (tx, rx), 115200.Hz());
-        &mut dp.sysconfig,
-        50.MHz(),
-        dp.uarta,
-        (tx, rx),
-        115200.Hz(),
-    );
     let (mut tx, mut rx) = uarta.split();
     writeln!(tx, "Hello World\r").unwrap();
     loop {

flashloader/src/main.rs

@@ -71,7 +71,7 @@ mod app {
     };
     use va108xx_hal::gpio::PinsA;
     use va108xx_hal::uart::IrqContextTimeoutOrMaxSize;
-    use va108xx_hal::{pac, uart, InterruptConfig};
+    use va108xx_hal::{pac, uart};
     use vorago_reb1::m95m01::M95M01;
 
     #[derive(Default, Debug, Copy, Clone, PartialEq, Eq)]
@@ -84,7 +84,7 @@ mod app {
 
     #[local]
     struct Local {
-        uart_rx: uart::RxWithInterrupt<pac::Uarta>,
+        uart_rx: uart::RxWithIrq<pac::Uarta>,
         uart_tx: uart::Tx<pac::Uarta>,
         rx_context: IrqContextTimeoutOrMaxSize,
         verif_reporter: VerificationReportCreator,
@@ -110,21 +110,19 @@ mod app {
         let mut dp = cx.device;
         let nvm = M95M01::new(&mut dp.sysconfig, SYSCLK_FREQ, dp.spic);
 
-        let gpioa = PinsA::new(&mut dp.sysconfig, dp.porta);
+        let gpioa = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
         let tx = gpioa.pa9.into_funsel_2();
         let rx = gpioa.pa8.into_funsel_2();
 
-        let irq_uart = uart::Uart::new_with_interrupt(
+        let irq_uart = uart::Uart::new(
             &mut dp.sysconfig,
             SYSCLK_FREQ,
             dp.uarta,
             (tx, rx),
             UART_BAUDRATE.Hz(),
-            InterruptConfig::new(pac::Interrupt::OC0, true, true),
         );
         let (tx, rx) = irq_uart.split();
-        // Unwrap is okay, we explicitely set the interrupt ID.
+        let mut rx = rx.into_rx_with_irq(&mut dp.sysconfig, &mut dp.irqsel, pac::interrupt::OC0);
-        let mut rx = rx.into_rx_with_irq();
 
         let verif_reporter = VerificationReportCreator::new(0).unwrap();
 
@@ -177,7 +175,7 @@ mod app {
         match cx
             .local
             .uart_rx
-            .on_interrupt_max_size_or_timeout_based(cx.local.rx_context, cx.local.rx_buf)
+            .irq_handler_max_size_or_timeout_based(cx.local.rx_context, cx.local.rx_buf)
         {
             Ok(result) => {
                 if RX_DEBUGGING {

va108xx-embassy/src/lib.rs

@@ -43,7 +43,7 @@ use once_cell::sync::OnceCell;
 use va108xx_hal::pac::interrupt;
 use va108xx_hal::{
     clock::enable_peripheral_clock,
-    enable_nvic_interrupt, pac,
+    enable_interrupt, pac,
     prelude::*,
     timer::{enable_tim_clk, get_tim_raw, TimRegInterface},
     PeripheralSelect,
@@ -221,7 +221,7 @@ impl TimerDriver {
             .tim0(timekeeper_tim.tim_id() as usize)
             .write(|w| unsafe { w.bits(timekeeper_irq as u32) });
         unsafe {
-            enable_nvic_interrupt(timekeeper_irq);
+            enable_interrupt(timekeeper_irq);
         }
         timekeeper_reg_block
             .ctrl()
@@ -239,7 +239,7 @@ impl TimerDriver {
         });
         // Enable general interrupts. The IRQ enable of the peripheral remains cleared.
         unsafe {
-            enable_nvic_interrupt(alarm_irq);
+            enable_interrupt(alarm_irq);
         }
         irqsel
             .tim0(alarm_tim.tim_id() as usize)

va108xx-hal/CHANGELOG.md

@@ -23,30 +23,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - `InvalidPinTypeError` now wraps the pin mode.
 - I2C `TimingCfg` constructor now returns explicit error instead of generic Error.
   Removed the timing configuration error type from the generic I2C error enumeration.
-- `PinsA` and `PinsB` constructor do not expect an optional `pac::Ioconfig` argument anymore.
-- `IrqCfg` renamed to `InterruptConfig`, kept alias for old name.
-- All library provided interrupt handlers now start with common prefix `on_interrupt_*`
-- `RxWithIrq` renamed to `RxWithInterrupt`
-- `Rx::into_rx_with_irq` does not expect any arguments any more.
-- `filter_type` renamed to `configure_filter_type`.
-- `level_irq` renamed to `configure_level_interrupt`.
-- `edge_irq` renamed to `configure_edge_interrupt`.
-- `PinsA` and `PinsB` constructor do not expect an optional IOCONFIG argument anymore.
-- UART interrupt management is now handled by the main constructor instead of later stages to
-  statically ensure one interrupt vector for the UART peripheral. `Uart::new` expects an
-  optional `InterruptConfig` argument.
-- `enable_interrupt` and `disable_interrupt` renamed to `enable_nvic_interrupt` and
-  `disable_nvic_interrupt` to distinguish them from peripheral interrupts more clearly.
-- `port_mux` renamed to `port_function_select`
 
 ## Added
 
 - Add `downgrade` method for `Pin` and `upgrade` method for `DynPin` as explicit conversion
   methods.
-- Asynchronous GPIO support.
-- Asynchronous UART TX support.
 - Add new `get_tim_raw` unsafe method to retrieve TIM peripheral blocks.
-- `Uart::with_with_interrupt` and `Uart::new_without_interrupt`
 
 ## [v0.8.0] 2024-09-30
 

va108xx-hal/Cargo.toml

@@ -16,10 +16,8 @@ cortex-m-rt = "0.7"
 nb = "1"
 paste = "1"
 embedded-hal = "1"
-embedded-hal-async = "1"
 embedded-hal-nb = "1"
 embedded-io = "0.6"
-embedded-io-async = "0.6"
 fugit = "0.3"
 typenum = "1"
 critical-section = "1"
@@ -27,16 +25,10 @@ delegate = ">=0.12, <=0.13"
 thiserror = { version = "2", default-features = false }
 void = { version = "1", default-features = false }
 once_cell = {version = "1", default-features = false }
-va108xx = { version = "0.3", default-features = false, features = ["critical-section"] }
+va108xx = { version = "0.3", default-features = false, features = ["critical-section"]}
-embassy-sync = "0.6"
 
 defmt = { version = "0.3", optional = true }
 
-[target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
-portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
-[target.'cfg(not(all(target_arch = "arm", target_os = "none")))'.dependencies]
-portable-atomic = "1"
-
 [features]
 default = ["rt"]
 rt = ["va108xx/rt"]

va108xx-hal/docs.sh

@@ -1,3 +0,0 @@
-#!/bin/sh
-export RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options"
-cargo +nightly doc --all-features --open

va108xx-hal/src/gpio/asynch.rs

@@ -1,449 +0,0 @@
-//! # Async GPIO functionality for the VA108xx family.
-//!
-//! This module provides the [InputPinAsync] and [InputDynPinAsync] which both implement
-//! the [embedded_hal_async::digital::Wait] trait. These types allow for asynchronous waiting
-//! on GPIO pins. Please note that this module does not specify/declare the interrupt handlers
-//! which must be provided for async support to work. However, it provides one generic
-//! [handler][handle_interrupt_for_async_gpio] which should be called in ALL user interrupt handlers
-//! which handle GPIO interrupts.
-//!
-//! # Example
-//!
-//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs)
-use core::future::Future;
-
-use embassy_sync::waitqueue::AtomicWaker;
-use embedded_hal::digital::InputPin;
-use embedded_hal_async::digital::Wait;
-use portable_atomic::AtomicBool;
-use va108xx::{self as pac, Irqsel, Sysconfig};
-
-use crate::InterruptConfig;
-
-use super::{
-    pin, DynGroup, DynPin, DynPinId, InputConfig, InterruptEdge, InvalidPinTypeError, Pin, PinId,
-    NUM_GPIO_PINS, NUM_PINS_PORT_A,
-};
-
-static WAKERS: [AtomicWaker; NUM_GPIO_PINS] = [const { AtomicWaker::new() }; NUM_GPIO_PINS];
-static EDGE_DETECTION: [AtomicBool; NUM_GPIO_PINS] =
-    [const { AtomicBool::new(false) }; NUM_GPIO_PINS];
-
-#[inline]
-fn pin_id_to_offset(dyn_pin_id: DynPinId) -> usize {
-    match dyn_pin_id.group {
-        DynGroup::A => dyn_pin_id.num as usize,
-        DynGroup::B => NUM_PINS_PORT_A + dyn_pin_id.num as usize,
-    }
-}
-
-/// Generic interrupt handler for GPIO interrupts to support the async functionalities.
-///
-/// This handler will wake the correspoding wakers for the pins which triggered an interrupt
-/// as well as updating the static edge detection structures. This allows the pin future to
-/// complete async operations. The user should call this function in ALL interrupt handlers
-/// which handle any GPIO interrupts.
-#[inline]
-pub fn on_interrupt_for_asynch_gpio() {
-    let periphs = unsafe { pac::Peripherals::steal() };
-
-    handle_interrupt_for_gpio_and_port(
-        periphs.porta.irq_enb().read().bits(),
-        periphs.porta.edge_status().read().bits(),
-        0,
-    );
-    handle_interrupt_for_gpio_and_port(
-        periphs.portb.irq_enb().read().bits(),
-        periphs.portb.edge_status().read().bits(),
-        NUM_PINS_PORT_A,
-    );
-}
-
-// Uses the enabled interrupt register and the persistent edge status to capture all GPIO events.
-#[inline]
-fn handle_interrupt_for_gpio_and_port(mut irq_enb: u32, edge_status: u32, pin_base_offset: usize) {
-    while irq_enb != 0 {
-        let bit_pos = irq_enb.trailing_zeros() as usize;
-        let bit_mask = 1 << bit_pos;
-
-        WAKERS[pin_base_offset + bit_pos].wake();
-
-        if edge_status & bit_mask != 0 {
-            EDGE_DETECTION[pin_base_offset + bit_pos]
-                .store(true, core::sync::atomic::Ordering::Relaxed);
-        }
-
-        // Clear the processed bit
-        irq_enb &= !bit_mask;
-    }
-}
-
-/// Input pin future which implements the [Future] trait.
-///
-/// Generally, you want to use the [InputPinAsync] or [InputDynPinAsync] types instead of this
-/// which also implements the [embedded_hal_async::digital::Wait] trait. However, access to this
-/// struture is granted  to allow writing custom async structures.
-pub struct InputPinFuture {
-    pin_id: DynPinId,
-}
-
-impl InputPinFuture {
-    /// # Safety
-    ///
-    /// This calls [Self::new] but uses [pac::Peripherals::steal] to get the system configuration
-    /// and IRQ selection peripherals. Users must ensure that the registers and configuration
-    /// related to this input pin are not being used elsewhere concurrently.
-    pub unsafe fn new_unchecked_with_dyn_pin(
-        pin: &mut DynPin,
-        irq: pac::Interrupt,
-        edge: InterruptEdge,
-    ) -> Result<Self, InvalidPinTypeError> {
-        let mut periphs = pac::Peripherals::steal();
-        Self::new_with_dyn_pin(pin, irq, edge, &mut periphs.sysconfig, &mut periphs.irqsel)
-    }
-
-    pub fn new_with_dyn_pin(
-        pin: &mut DynPin,
-        irq: pac::Interrupt,
-        edge: InterruptEdge,
-        sys_cfg: &mut Sysconfig,
-        irq_sel: &mut Irqsel,
-    ) -> Result<Self, InvalidPinTypeError> {
-        if !pin.is_input_pin() {
-            return Err(InvalidPinTypeError(pin.mode()));
-        }
-
-        EDGE_DETECTION[pin_id_to_offset(pin.id())]
-            .store(false, core::sync::atomic::Ordering::Relaxed);
-        pin.interrupt_edge(
-            edge,
-            InterruptConfig::new(irq, true, true),
-            Some(sys_cfg),
-            Some(irq_sel),
-        )
-        .unwrap();
-        Ok(Self { pin_id: pin.id() })
-    }
-
-    /// # Safety
-    ///
-    /// This calls [Self::new] but uses [pac::Peripherals::steal] to get the system configuration
-    /// and IRQ selection peripherals. Users must ensure that the registers and configuration
-    /// related to this input pin are not being used elsewhere concurrently.
-    pub unsafe fn new_unchecked_with_pin<I: PinId, C: InputConfig>(
-        pin: &mut Pin<I, pin::Input<C>>,
-        irq: pac::Interrupt,
-        edge: InterruptEdge,
-    ) -> Self {
-        let mut periphs = pac::Peripherals::steal();
-        Self::new_with_pin(pin, irq, edge, &mut periphs.sysconfig, &mut periphs.irqsel)
-    }
-
-    pub fn new_with_pin<I: PinId, C: InputConfig>(
-        pin: &mut Pin<I, pin::Input<C>>,
-        irq: pac::Interrupt,
-        edge: InterruptEdge,
-        sys_cfg: &mut Sysconfig,
-        irq_sel: &mut Irqsel,
-    ) -> Self {
-        EDGE_DETECTION[pin_id_to_offset(pin.id())]
-            .store(false, core::sync::atomic::Ordering::Relaxed);
-        pin.configure_edge_interrupt(
-            edge,
-            InterruptConfig::new(irq, true, true),
-            Some(sys_cfg),
-            Some(irq_sel),
-        );
-        Self { pin_id: pin.id() }
-    }
-}
-
-impl Drop for InputPinFuture {
-    fn drop(&mut self) {
-        let periphs = unsafe { pac::Peripherals::steal() };
-        if self.pin_id.group == DynGroup::A {
-            periphs
-                .porta
-                .irq_enb()
-                .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.pin_id.num)) });
-        } else {
-            periphs
-                .porta
-                .irq_enb()
-                .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.pin_id.num)) });
-        }
-    }
-}
-
-impl Future for InputPinFuture {
-    type Output = ();
-    fn poll(
-        self: core::pin::Pin<&mut Self>,
-        cx: &mut core::task::Context<'_>,
-    ) -> core::task::Poll<Self::Output> {
-        let idx = pin_id_to_offset(self.pin_id);
-        WAKERS[idx].register(cx.waker());
-        if EDGE_DETECTION[idx].swap(false, core::sync::atomic::Ordering::Relaxed) {
-            return core::task::Poll::Ready(());
-        }
-        core::task::Poll::Pending
-    }
-}
-
-pub struct InputDynPinAsync {
-    pin: DynPin,
-    irq: pac::Interrupt,
-}
-
-impl InputDynPinAsync {
-    /// Create a new asynchronous input pin from a [DynPin]. The interrupt ID to be used must be
-    /// passed as well and is used to route and enable the interrupt.
-    ///
-    /// Please note that the interrupt handler itself must be provided by the user and the
-    /// generic [handle_interrupt_for_async_gpio] function must be called inside that function for
-    /// the asynchronous functionality to work.
-    pub fn new(pin: DynPin, irq: pac::Interrupt) -> Result<Self, InvalidPinTypeError> {
-        if !pin.is_input_pin() {
-            return Err(InvalidPinTypeError(pin.mode()));
-        }
-        Ok(Self { pin, irq })
-    }
-
-    /// Asynchronously wait until the pin is high.
-    ///
-    /// This returns immediately if the pin is already high.
-    pub async fn wait_for_high(&mut self) {
-        let fut = unsafe {
-            // Unwrap okay, checked pin in constructor.
-            InputPinFuture::new_unchecked_with_dyn_pin(
-                &mut self.pin,
-                self.irq,
-                InterruptEdge::LowToHigh,
-            )
-            .unwrap()
-        };
-        if self.pin.is_high().unwrap() {
-            return;
-        }
-        fut.await;
-    }
-
-    /// Asynchronously wait until the pin is low.
-    ///
-    /// This returns immediately if the pin is already high.
-    pub async fn wait_for_low(&mut self) {
-        let fut = unsafe {
-            // Unwrap okay, checked pin in constructor.
-            InputPinFuture::new_unchecked_with_dyn_pin(
-                &mut self.pin,
-                self.irq,
-                InterruptEdge::HighToLow,
-            )
-            .unwrap()
-        };
-        if self.pin.is_low().unwrap() {
-            return;
-        }
-        fut.await;
-    }
-
-    /// Asynchronously wait until the pin sees a falling edge.
-    pub async fn wait_for_falling_edge(&mut self) {
-        unsafe {
-            // Unwrap okay, checked pin in constructor.
-            InputPinFuture::new_unchecked_with_dyn_pin(
-                &mut self.pin,
-                self.irq,
-                InterruptEdge::HighToLow,
-            )
-            .unwrap()
-        }
-        .await;
-    }
-
-    /// Asynchronously wait until the pin sees a rising edge.
-    pub async fn wait_for_rising_edge(&mut self) {
-        unsafe {
-            // Unwrap okay, checked pin in constructor.
-            InputPinFuture::new_unchecked_with_dyn_pin(
-                &mut self.pin,
-                self.irq,
-                InterruptEdge::LowToHigh,
-            )
-            .unwrap()
-        }
-        .await;
-    }
-
-    /// Asynchronously wait until the pin sees any edge (either rising or falling).
-    pub async fn wait_for_any_edge(&mut self) {
-        unsafe {
-            // Unwrap okay, checked pin in constructor.
-            InputPinFuture::new_unchecked_with_dyn_pin(
-                &mut self.pin,
-                self.irq,
-                InterruptEdge::BothEdges,
-            )
-            .unwrap()
-        }
-        .await;
-    }
-
-    pub fn release(self) -> DynPin {
-        self.pin
-    }
-}
-
-impl embedded_hal::digital::ErrorType for InputDynPinAsync {
-    type Error = core::convert::Infallible;
-}
-
-impl Wait for InputDynPinAsync {
-    async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_high().await;
-        Ok(())
-    }
-
-    async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_low().await;
-        Ok(())
-    }
-
-    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_rising_edge().await;
-        Ok(())
-    }
-
-    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_falling_edge().await;
-        Ok(())
-    }
-
-    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_any_edge().await;
-        Ok(())
-    }
-}
-
-pub struct InputPinAsync<I: PinId, C: InputConfig> {
-    pin: Pin<I, pin::Input<C>>,
-    irq: pac::Interrupt,
-}
-
-impl<I: PinId, C: InputConfig> InputPinAsync<I, C> {
-    /// Create a new asynchronous input pin from a typed [Pin]. The interrupt ID to be used must be
-    /// passed as well and is used to route and enable the interrupt.
-    ///
-    /// Please note that the interrupt handler itself must be provided by the user and the
-    /// generic [handle_interrupt_for_async_gpio] function must be called inside that function for
-    /// the asynchronous functionality to work.
-    pub fn new(pin: Pin<I, pin::Input<C>>, irq: pac::Interrupt) -> Self {
-        Self { pin, irq }
-    }
-
-    /// Asynchronously wait until the pin is high.
-    ///
-    /// This returns immediately if the pin is already high.
-    pub async fn wait_for_high(&mut self) {
-        let fut = unsafe {
-            InputPinFuture::new_unchecked_with_pin(
-                &mut self.pin,
-                self.irq,
-                InterruptEdge::LowToHigh,
-            )
-        };
-        if self.pin.is_high().unwrap() {
-            return;
-        }
-        fut.await;
-    }
-
-    /// Asynchronously wait until the pin is low.
-    ///
-    /// This returns immediately if the pin is already high.
-    pub async fn wait_for_low(&mut self) {
-        let fut = unsafe {
-            InputPinFuture::new_unchecked_with_pin(
-                &mut self.pin,
-                self.irq,
-                InterruptEdge::HighToLow,
-            )
-        };
-        if self.pin.is_low().unwrap() {
-            return;
-        }
-        fut.await;
-    }
-
-    /// Asynchronously wait until the pin sees falling edge.
-    pub async fn wait_for_falling_edge(&mut self) {
-        unsafe {
-            // Unwrap okay, checked pin in constructor.
-            InputPinFuture::new_unchecked_with_pin(
-                &mut self.pin,
-                self.irq,
-                InterruptEdge::HighToLow,
-            )
-        }
-        .await;
-    }
-
-    /// Asynchronously wait until the pin sees rising edge.
-    pub async fn wait_for_rising_edge(&mut self) {
-        unsafe {
-            // Unwrap okay, checked pin in constructor.
-            InputPinFuture::new_unchecked_with_pin(
-                &mut self.pin,
-                self.irq,
-                InterruptEdge::LowToHigh,
-            )
-        }
-        .await;
-    }
-
-    /// Asynchronously wait until the pin sees any edge (either rising or falling).
-    pub async fn wait_for_any_edge(&mut self) {
-        unsafe {
-            InputPinFuture::new_unchecked_with_pin(
-                &mut self.pin,
-                self.irq,
-                InterruptEdge::BothEdges,
-            )
-        }
-        .await;
-    }
-
-    pub fn release(self) -> Pin<I, pin::Input<C>> {
-        self.pin
-    }
-}
-impl<I: PinId, C: InputConfig> embedded_hal::digital::ErrorType for InputPinAsync<I, C> {
-    type Error = core::convert::Infallible;
-}
-
-impl<I: PinId, C: InputConfig> Wait for InputPinAsync<I, C> {
-    async fn wait_for_high(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_high().await;
-        Ok(())
-    }
-
-    async fn wait_for_low(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_low().await;
-        Ok(())
-    }
-
-    async fn wait_for_rising_edge(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_rising_edge().await;
-        Ok(())
-    }
-
-    async fn wait_for_falling_edge(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_falling_edge().await;
-        Ok(())
-    }
-
-    async fn wait_for_any_edge(&mut self) -> Result<(), Self::Error> {
-        self.wait_for_any_edge().await;
-        Ok(())
-    }
-}

va108xx-hal/src/gpio/dynpin.rs

@@ -59,9 +59,8 @@
 use super::{
     pin::{FilterType, InterruptEdge, InterruptLevel, Pin, PinId, PinMode, PinState},
     reg::RegisterInterface,
-    InputDynPinAsync,
 };
-use crate::{clock::FilterClkSel, enable_nvic_interrupt, pac, FunSel, InterruptConfig};
+use crate::{clock::FilterClkSel, pac, FunSel, IrqCfg};
 
 //==================================================================================================
 //  DynPinMode configurations
@@ -77,7 +76,6 @@ pub enum DynDisabled {
 
 /// Value-level `enum` for input configurations
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum DynInput {
     Floating,
     PullDown,
@@ -86,7 +84,6 @@ pub enum DynInput {
 
 /// Value-level `enum` for output configurations
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum DynOutput {
     PushPull,
     OpenDrain,
@@ -107,7 +104,7 @@ pub type DynAlternate = FunSel;
 #[derive(Debug, PartialEq, Eq, thiserror::Error)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[error("Invalid pin type for operation: {0:?}")]
-pub struct InvalidPinTypeError(pub DynPinMode);
+pub struct InvalidPinTypeError(DynPinMode);
 
 impl embedded_hal::digital::Error for InvalidPinTypeError {
     fn kind(&self) -> embedded_hal::digital::ErrorKind {
@@ -121,7 +118,6 @@ impl embedded_hal::digital::Error for InvalidPinTypeError {
 
 /// Value-level `enum` representing pin modes
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum DynPinMode {
     Input(DynInput),
     Output(DynOutput),
@@ -177,14 +173,16 @@ pub struct DynPinId {
 ///
 /// This `struct` takes ownership of a [`DynPinId`] and provides an API to
 /// access the corresponding regsiters.
-pub(crate) struct DynRegisters(DynPinId);
+pub(crate) struct DynRegisters {
+    id: DynPinId,
+}
 
 // [`DynRegisters`] takes ownership of the [`DynPinId`], and [`DynPin`]
 // guarantees that each pin is a singleton, so this implementation is safe.
 unsafe impl RegisterInterface for DynRegisters {
     #[inline]
     fn id(&self) -> DynPinId {
-        self.0
+        self.id
     }
 }
 
@@ -197,7 +195,7 @@ impl DynRegisters {
     /// the same [`DynPinId`]
     #[inline]
     unsafe fn new(id: DynPinId) -> Self {
-        DynRegisters(id)
+        DynRegisters { id }
     }
 }
 
@@ -233,7 +231,7 @@ impl DynPin {
     /// Return a copy of the pin ID
     #[inline]
     pub fn id(&self) -> DynPinId {
-        self.regs.0
+        self.regs.id
     }
 
     /// Return a copy of the pin mode
@@ -252,11 +250,6 @@ impl DynPin {
         }
     }
 
-    #[inline]
-    pub fn is_input_pin(&self) -> bool {
-        matches!(self.mode, DynPinMode::Input(_))
-    }
-
     #[inline]
     pub fn into_funsel_1(&mut self) {
         self.into_mode(DYN_ALT_FUNC_1);
@@ -351,7 +344,7 @@ impl DynPin {
 
     pub(crate) fn irq_enb(
         &mut self,
-        irq_cfg: crate::InterruptConfig,
+        irq_cfg: crate::IrqCfg,
         syscfg: Option<&mut va108xx::Sysconfig>,
         irqsel: Option<&mut va108xx::Irqsel>,
     ) {
@@ -366,19 +359,16 @@ impl DynPin {
                     DynGroup::A => {
                         irqsel
                             .porta0(self.regs.id().num as usize)
-                            .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
+                            .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
                     }
                     DynGroup::B => {
                         irqsel
                             .portb0(self.regs.id().num as usize)
-                            .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
+                            .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
                     }
                 }
             }
         }
-        if irq_cfg.enable_in_nvic {
-            unsafe { enable_nvic_interrupt(irq_cfg.id) };
-        }
     }
 
     /// See p.53 of the programmers guide for more information.
@@ -435,7 +425,7 @@ impl DynPin {
     pub fn interrupt_edge(
         &mut self,
         edge_type: InterruptEdge,
-        irq_cfg: InterruptConfig,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut pac::Sysconfig>,
         irqsel: Option<&mut pac::Irqsel>,
     ) -> Result<(), InvalidPinTypeError> {
@@ -453,7 +443,7 @@ impl DynPin {
     pub fn interrupt_level(
         &mut self,
         level_type: InterruptLevel,
-        irq_cfg: InterruptConfig,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut pac::Sysconfig>,
         irqsel: Option<&mut pac::Irqsel>,
     ) -> Result<(), InvalidPinTypeError> {
@@ -522,22 +512,13 @@ impl DynPin {
     /// or refuse to perform it.
     #[inline]
     pub fn upgrade<I: PinId, M: PinMode>(self) -> Result<Pin<I, M>, InvalidPinTypeError> {
-        if self.regs.0 == I::DYN && self.mode == M::DYN {
+        if self.regs.id == I::DYN && self.mode == M::DYN {
             // The `DynPin` is consumed, so it is safe to replace it with the
             // corresponding `Pin`
             return Ok(unsafe { Pin::new() });
         }
         Err(InvalidPinTypeError(self.mode))
     }
-
-    /// Convert the pin into an async pin. The pin can be converted back by calling
-    /// [InputDynPinAsync::release]
-    pub fn into_async_input(
-        self,
-        irq: crate::pac::Interrupt,
-    ) -> Result<InputDynPinAsync, InvalidPinTypeError> {
-        InputDynPinAsync::new(self, irq)
-    }
 }
 
 //==================================================================================================

va108xx-hal/src/gpio/mod.rs

@@ -27,17 +27,10 @@
 #[error("The pin is masked")]
 pub struct IsMaskedError;
 
-pub const NUM_PINS_PORT_A: usize = 32;
-pub const NUM_PINS_PORT_B: usize = 24;
-pub const NUM_GPIO_PINS: usize = NUM_PINS_PORT_A + NUM_PINS_PORT_B;
-
 pub mod dynpin;
 pub use dynpin::*;
 
 pub mod pin;
 pub use pin::*;
 
-pub mod asynch;
-pub use asynch::*;
-
 mod reg;

va108xx-hal/src/gpio/pin.rs

@@ -72,11 +72,11 @@
 //! and [`StatefulOutputPin`].
 use super::dynpin::{DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode};
 use super::reg::RegisterInterface;
-use super::{DynPin, InputPinAsync};
+use super::DynPin;
 use crate::{
     pac::{Irqsel, Porta, Portb, Sysconfig},
     typelevel::Sealed,
-    InterruptConfig,
+    IrqCfg,
 };
 use core::convert::Infallible;
 use core::marker::PhantomData;
@@ -342,10 +342,6 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
         }
     }
 
-    pub fn id(&self) -> DynPinId {
-        self.inner.id()
-    }
-
     /// Convert the pin to the requested [`PinMode`]
     #[inline]
     pub fn into_mode<N: PinMode>(mut self) -> Pin<I, N> {
@@ -454,7 +450,7 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
 
     fn irq_enb(
         &mut self,
-        irq_cfg: crate::InterruptConfig,
+        irq_cfg: crate::IrqCfg,
         syscfg: Option<&mut va108xx::Sysconfig>,
         irqsel: Option<&mut va108xx::Irqsel>,
     ) {
@@ -575,16 +571,10 @@ impl<P: AnyPin> AsMut<P> for SpecificPin<P> {
 //==================================================================================================
 
 impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
-    /// Convert the pin into an async pin. The pin can be converted back by calling
+    pub fn interrupt_edge(
-    /// [InputPinAsync::release]
-    pub fn into_async_input(self, irq: crate::pac::Interrupt) -> InputPinAsync<I, C> {
-        InputPinAsync::new(self, irq)
-    }
-
-    pub fn configure_edge_interrupt(
         &mut self,
         edge_type: InterruptEdge,
-        irq_cfg: InterruptConfig,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut Sysconfig>,
         irqsel: Option<&mut Irqsel>,
     ) {
@@ -592,10 +582,10 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
         self.irq_enb(irq_cfg, syscfg, irqsel);
     }
 
-    pub fn configure_level_interrupt(
+    pub fn interrupt_level(
         &mut self,
         level_type: InterruptLevel,
-        irq_cfg: InterruptConfig,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut Sysconfig>,
         irqsel: Option<&mut Irqsel>,
     ) {
@@ -631,7 +621,7 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
     pub fn interrupt_edge(
         &mut self,
         edge_type: InterruptEdge,
-        irq_cfg: InterruptConfig,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut Sysconfig>,
         irqsel: Option<&mut Irqsel>,
     ) {
@@ -642,7 +632,7 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
     pub fn interrupt_level(
         &mut self,
         level_type: InterruptLevel,
-        irq_cfg: InterruptConfig,
+        irq_cfg: IrqCfg,
         syscfg: Option<&mut Sysconfig>,
         irqsel: Option<&mut Irqsel>,
     ) {
@@ -654,7 +644,7 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
 impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
     /// See p.37 and p.38 of the programmers guide for more information.
     #[inline]
-    pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
+    pub fn filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
         self.inner.regs.filter_type(filter, clksel);
     }
 }
@@ -742,6 +732,7 @@ macro_rules! pins {
         paste!(
             /// Collection of all the individual [`Pin`]s for a given port (PORTA or PORTB)
             pub struct $PinsName {
+                iocfg: Option<va108xx::Ioconfig>,
                 port: $Port,
                 $(
                     #[doc = "Pin " $Id]
@@ -756,6 +747,7 @@ macro_rules! pins {
                 #[inline]
                 pub fn new(
                     syscfg: &mut va108xx::Sysconfig,
+                    iocfg: Option<va108xx::Ioconfig>,
                     port: $Port
                 ) -> $PinsName {
                     syscfg.peripheral_clk_enable().modify(|_, w| {
@@ -764,7 +756,7 @@ macro_rules! pins {
                         w.ioconfig().set_bit()
                     });
                     $PinsName {
-                        //iocfg,
+                        iocfg,
                         port,
                         // Safe because we only create one `Pin` per `PinId`
                         $(
@@ -781,8 +773,8 @@ macro_rules! pins {
                 }
 
                 /// Consumes the Pins struct and returns the port definitions
-                pub fn release(self) -> $Port {
+                pub fn release(self) -> (Option<va108xx::Ioconfig>, $Port) {
-                    self.port
+                    (self.iocfg, self.port)
                 }
             }
         );

va108xx-hal/src/gpio/reg.rs

@@ -73,6 +73,13 @@ impl From<DynPinMode> for ModeFields {
 //==================================================================================================
 
 pub type PortReg = ioconfig::Porta;
+/*
+pub type IocfgPort = ioconfig::Porta;
+#[repr(C)]
+pub(super) struct IocfgPortGroup {
+    port: [IocfgPort; 32],
+}
+*/
 
 /// Provide a safe register interface for pin objects
 ///

va108xx-hal/src/lib.rs

@@ -17,7 +17,6 @@ pub mod typelevel;
 pub mod uart;
 
 #[derive(Debug, Eq, Copy, Clone, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum FunSel {
     Sel1 = 0b01,
     Sel2 = 0b10,
@@ -25,14 +24,12 @@ pub enum FunSel {
 }
 
 #[derive(Debug, Copy, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum PortSel {
     PortA,
     PortB,
 }
 
 #[derive(Copy, Clone, PartialEq, Eq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum PeripheralSelect {
     PortA = 0,
     PortB = 1,
@@ -49,38 +46,31 @@ pub enum PeripheralSelect {
     Gpio = 24,
 }
 
-/// Generic interrupt config which can be used to specify whether the HAL driver will
+/// Generic IRQ config which can be used to specify whether the HAL driver will
 /// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the
 /// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might perform
 /// this steps themselves
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
-pub struct InterruptConfig {
+pub struct IrqCfg {
     /// Interrupt target vector. Should always be set, might be required for disabling IRQs
-    pub id: pac::Interrupt,
+    pub irq: pac::Interrupt,
-    /// Specfiy whether IRQ should be routed to an IRQ vector using the IRQSEL peripheral.
+    /// Specfiy whether IRQ should be routed to an IRQ vector using the IRQSEL peripheral
     pub route: bool,
-    /// Specify whether the IRQ is unmasked in the Cortex-M NVIC. If an interrupt is used for
+    /// Specify whether the IRQ is unmasked in the Cortex-M NVIC
-    /// multiple purposes, the user can enable the interrupts themselves.
+    pub enable: bool,
-    pub enable_in_nvic: bool,
 }
 
-impl InterruptConfig {
+impl IrqCfg {
-    pub fn new(id: pac::Interrupt, route: bool, enable_in_nvic: bool) -> Self {
+    pub fn new(irq: pac::Interrupt, route: bool, enable: bool) -> Self {
-        InterruptConfig {
+        IrqCfg { irq, route, enable }
-            id,
-            route,
-            enable_in_nvic,
-        }
     }
 }
 
-pub type IrqCfg = InterruptConfig;
-
 #[derive(Debug, PartialEq, Eq)]
 pub struct InvalidPin(pub(crate) ());
 
 /// Can be used to manually manipulate the function select of port pins
-pub fn port_function_select(
+pub fn port_mux(
     ioconfig: &mut pac::Ioconfig,
     port: PortSel,
     pin: u8,
@@ -114,7 +104,7 @@ pub fn port_function_select(
 ///
 /// This function is `unsafe` because it can break mask-based critical sections.
 #[inline]
-pub unsafe fn enable_nvic_interrupt(irq: pac::Interrupt) {
+pub unsafe fn enable_interrupt(irq: pac::Interrupt) {
     unsafe {
         cortex_m::peripheral::NVIC::unmask(irq);
     }
@@ -122,6 +112,6 @@ pub unsafe fn enable_nvic_interrupt(irq: pac::Interrupt) {
 
 /// Disable a specific interrupt using the NVIC peripheral.
 #[inline]
-pub fn disable_nvic_interrupt(irq: pac::Interrupt) {
+pub fn disable_interrupt(irq: pac::Interrupt) {
     cortex_m::peripheral::NVIC::mask(irq);
 }

va108xx-hal/src/pwm.rs

@@ -80,7 +80,7 @@ where
         pin
     }
 
-    pub fn downgrade(self) -> ReducedPwmPin<Mode> {
+    pub fn reduce(self) -> ReducedPwmPin<Mode> {
         self.inner
     }
 
@@ -213,6 +213,22 @@ impl<Mode> ReducedPwmPin<Mode> {
         }
     }
 }
+/*
+impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim>> for ReducedPwmPin<PwmA> {
+    fn from(pwm_pin: PwmPin<Pin, Tim>) -> Self {
+        ReducedPwmPin {
+            dyn_reg: TimDynRegister {
+
+
+            }
+            // ::from(pwm_pin.reg),
+            common: pwm_pin.pwm_base,
+            pin_id: Pin::DYN,
+            mode: PhantomData,
+        }
+    }
+}
+*/
 
 impl<Mode> ReducedPwmPin<Mode> {
     #[inline]
@@ -277,24 +293,6 @@ impl<Mode> ReducedPwmPin<Mode> {
     }
 }
 
-impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim, PwmA>> for ReducedPwmPin<PwmA>
-where
-    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
-{
-    fn from(value: PwmPin<Pin, Tim, PwmA>) -> Self {
-        value.downgrade()
-    }
-}
-
-impl<Pin: TimPin, Tim: ValidTim> From<PwmPin<Pin, Tim, PwmB>> for ReducedPwmPin<PwmB>
-where
-    (Pin, Tim): ValidTimAndPin<Pin, Tim>,
-{
-    fn from(value: PwmPin<Pin, Tim, PwmB>) -> Self {
-        value.downgrade()
-    }
-}
-
 impl From<ReducedPwmPin<PwmA>> for ReducedPwmPin<PwmB> {
     fn from(other: ReducedPwmPin<PwmA>) -> Self {
         let mut pwmb = Self {

va108xx-hal/src/timer.rs

@@ -4,10 +4,10 @@
 //!
 //! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs)
 //! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/cascade.rs)
-pub use crate::InterruptConfig;
+pub use crate::IrqCfg;
 use crate::{
     clock::{enable_peripheral_clock, PeripheralClocks},
-    enable_nvic_interrupt,
+    enable_interrupt,
     gpio::{
         AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14,
         PA15, PA2, PA24, PA25, PA26, PA27, PA28, PA29, PA3, PA30, PA31, PA4, PA5, PA6, PA7, PA8,
@@ -286,7 +286,7 @@ pub type TimRegBlock = tim0::RegisterBlock;
 ///
 /// # Safety
 ///
-/// Users should only implement the [Self::tim_id] function. No default function
+/// Users should only implement the [`tim_id`] function. No default function
 /// implementations should be overridden. The implementing type must also have
 /// "control" over the corresponding pin ID, i.e. it must guarantee that a each
 /// pin ID is a singleton.
@@ -362,7 +362,7 @@ unsafe impl TimRegInterface for TimDynRegister {
 pub struct CountdownTimer<Tim: ValidTim> {
     tim: Tim,
     curr_freq: Hertz,
-    irq_cfg: Option<InterruptConfig>,
+    irq_cfg: Option<IrqCfg>,
     sys_clk: Hertz,
     rst_val: u32,
     last_cnt: u32,
@@ -415,13 +415,13 @@ impl<Tim: ValidTim> CountdownTimer<Tim> {
     pub fn listen(
         &mut self,
         event: Event,
-        irq_cfg: InterruptConfig,
+        irq_cfg: IrqCfg,
         irq_sel: Option<&mut pac::Irqsel>,
         sys_cfg: Option<&mut pac::Sysconfig>,
     ) {
         match event {
             Event::TimeOut => {
-                cortex_m::peripheral::NVIC::mask(irq_cfg.id);
+                cortex_m::peripheral::NVIC::mask(irq_cfg.irq);
                 self.irq_cfg = Some(irq_cfg);
                 if irq_cfg.route {
                     if let Some(sys_cfg) = sys_cfg {
@@ -430,7 +430,7 @@ impl<Tim: ValidTim> CountdownTimer<Tim> {
                     if let Some(irq_sel) = irq_sel {
                         irq_sel
                             .tim0(Tim::TIM_ID as usize)
-                            .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
+                            .write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
                     }
                 }
                 self.listening = true;
@@ -520,8 +520,8 @@ impl<Tim: ValidTim> CountdownTimer<Tim> {
     pub fn enable(&mut self) {
         if let Some(irq_cfg) = self.irq_cfg {
             self.enable_interrupt();
-            if irq_cfg.enable_in_nvic {
+            if irq_cfg.enable {
-                unsafe { enable_nvic_interrupt(irq_cfg.id) };
+                unsafe { enable_interrupt(irq_cfg.irq) };
             }
         }
         self.tim
@@ -719,7 +719,7 @@ impl<TIM: ValidTim> embedded_hal::delay::DelayNs for CountdownTimer<TIM> {
 // Set up a millisecond timer on TIM0. Please note that the user still has to provide an IRQ handler
 // which should call [default_ms_irq_handler].
 pub fn set_up_ms_tick<TIM: ValidTim>(
-    irq_cfg: InterruptConfig,
+    irq_cfg: IrqCfg,
     sys_cfg: &mut pac::Sysconfig,
     irq_sel: Option<&mut pac::Irqsel>,
     sys_clk: impl Into<Hertz>,

va108xx-hal/src/uart.rs

@@ -9,10 +9,10 @@ use core::{convert::Infallible, ops::Deref};
 use fugit::RateExtU32;
 use va108xx::Uarta;
 
-pub use crate::InterruptConfig;
+pub use crate::IrqCfg;
 use crate::{
     clock::enable_peripheral_clock,
-    enable_nvic_interrupt,
+    enable_interrupt,
     gpio::pin::{
         AltFunc1, AltFunc2, AltFunc3, Pin, PA16, PA17, PA18, PA19, PA2, PA26, PA27, PA3, PA30,
         PA31, PA8, PA9, PB18, PB19, PB20, PB21, PB22, PB23, PB6, PB7, PB8, PB9,
@@ -48,11 +48,6 @@ impl Pins<pac::Uartb> for (Pin<PB21, AltFunc1>, Pin<PB20, AltFunc1>) {}
 // Regular Definitions
 //==================================================================================================
 
-#[derive(Debug, PartialEq, Eq, thiserror::Error)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[error("no interrupt ID was set")]
-pub struct NoInterruptIdWasSet;
-
 #[derive(Debug, PartialEq, Eq, thiserror::Error)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[error("transer is pending")]
@@ -378,16 +373,6 @@ pub trait Instance: Deref<Target = uart_base::RegisterBlock> {
     /// This circumvents the safety guarantees of the HAL.
     unsafe fn steal() -> Self;
     fn ptr() -> *const uart_base::RegisterBlock;
-
-    /// Retrieve the type erased peripheral register block.
-    ///
-    /// # Safety
-    ///
-    /// This circumvents the safety guarantees of the HAL.
-    #[inline(always)]
-    unsafe fn reg_block() -> &'static uart_base::RegisterBlock {
-        unsafe { &(*Self::ptr()) }
-    }
 }
 
 impl Instance for pac::Uarta {
@@ -395,11 +380,9 @@ impl Instance for pac::Uarta {
 
     const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart0;
 
-    #[inline(always)]
     unsafe fn steal() -> Self {
         pac::Peripherals::steal().uarta
     }
-    #[inline(always)]
     fn ptr() -> *const uart_base::RegisterBlock {
         Uarta::ptr() as *const _
     }
@@ -410,11 +393,9 @@ impl Instance for pac::Uartb {
 
     const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart1;
 
-    #[inline(always)]
     unsafe fn steal() -> Self {
         pac::Peripherals::steal().uartb
     }
-    #[inline(always)]
     fn ptr() -> *const uart_base::RegisterBlock {
         Uarta::ptr() as *const _
     }
@@ -611,51 +592,15 @@ where
     UartInstance: Instance,
     PinsInstance: Pins<UartInstance>,
 {
-    /// Calls [Self::new] with the interrupt configuration to some valid value.
-    pub fn new_with_interrupt(
-        syscfg: &mut va108xx::Sysconfig,
-        sys_clk: impl Into<Hertz>,
-        uart: UartInstance,
-        pins: PinsInstance,
-        config: impl Into<Config>,
-        irq_cfg: InterruptConfig,
-    ) -> Self {
-        Self::new(syscfg, sys_clk, uart, pins, config, Some(irq_cfg))
-    }
-
-    /// Calls [Self::new] with the interrupt configuration to [None].
-    pub fn new_without_interrupt(
-        syscfg: &mut va108xx::Sysconfig,
-        sys_clk: impl Into<Hertz>,
-        uart: UartInstance,
-        pins: PinsInstance,
-        config: impl Into<Config>,
-    ) -> Self {
-        Self::new(syscfg, sys_clk, uart, pins, config, None)
-    }
-
-    /// Create a new UART peripheral with an interrupt configuration.
-    ///
-    /// # Arguments
-    ///
-    /// - `syscfg`: The system configuration register block
-    /// - `sys_clk`: The system clock frequency
-    /// - `uart`: The concrete UART peripheral instance.
-    /// - `pins`: UART TX and RX pin tuple.
-    /// - `config`: UART specific configuration parameters like baudrate.
-    /// - `irq_cfg`: Optional interrupt configuration. This should be a valid value if the plan
-    ///    is to use TX or RX functionality relying on interrupts. If only the blocking API without
-    ///    any interrupt support is used, this can be [None].
     pub fn new(
         syscfg: &mut va108xx::Sysconfig,
         sys_clk: impl Into<Hertz>,
         uart: UartInstance,
         pins: PinsInstance,
         config: impl Into<Config>,
-        opt_irq_cfg: Option<InterruptConfig>,
     ) -> Self {
         crate::clock::enable_peripheral_clock(syscfg, UartInstance::PERIPH_SEL);
-        let uart = Uart {
+        Uart {
             inner: UartBase {
                 uart,
                 tx: Tx::new(unsafe { UartInstance::steal() }),
@@ -663,21 +608,7 @@ where
             },
             pins,
         }
-        .init(config.into(), sys_clk.into());
+        .init(config.into(), sys_clk.into())
-
-        if let Some(irq_cfg) = opt_irq_cfg {
-            if irq_cfg.route {
-                enable_peripheral_clock(syscfg, PeripheralSelect::Irqsel);
-                unsafe { pac::Irqsel::steal() }
-                    .uart0(UartInstance::IDX as usize)
-                    .write(|w| unsafe { w.bits(irq_cfg.id as u32) });
-            }
-            if irq_cfg.enable_in_nvic {
-                // Safety: User has specifically configured this.
-                unsafe { enable_nvic_interrupt(irq_cfg.id) };
-            }
-        }
-        uart
     }
 
     /// This function assumes that the peripheral clock was alredy enabled
@@ -755,13 +686,11 @@ where
 /// Serial receiver.
 ///
 /// Can be created by using the [Uart::split] or [UartBase::split] API.
-pub struct Rx<Uart> {
+pub struct Rx<Uart>(Uart);
-    uart: Uart,
-}
 
 impl<Uart: Instance> Rx<Uart> {
     fn new(uart: Uart) -> Self {
-        Self { uart }
+        Self(uart)
     }
 
     /// Direct access to the peripheral structure.
@@ -770,22 +699,22 @@ impl<Uart: Instance> Rx<Uart> {
     ///
     /// You must ensure that only registers related to the operation of the RX side are used.
     pub unsafe fn uart(&self) -> &Uart {
-        &self.uart
+        &self.0
     }
 
     #[inline]
     pub fn clear_fifo(&self) {
-        self.uart.fifo_clr().write(|w| w.rxfifo().set_bit());
+        self.0.fifo_clr().write(|w| w.rxfifo().set_bit());
     }
 
     #[inline]
     pub fn enable(&mut self) {
-        self.uart.enable().modify(|_, w| w.rxenable().set_bit());
+        self.0.enable().modify(|_, w| w.rxenable().set_bit());
     }
 
     #[inline]
     pub fn disable(&mut self) {
-        self.uart.enable().modify(|_, w| w.rxenable().clear_bit());
+        self.0.enable().modify(|_, w| w.rxenable().clear_bit());
     }
 
     /// Low level function to read a word from the UART FIFO.
@@ -796,7 +725,7 @@ impl<Uart: Instance> Rx<Uart> {
     /// value if you use the manual parity mode. See chapter 4.6.2 for more information.
     #[inline(always)]
     pub fn read_fifo(&self) -> nb::Result<u32, Infallible> {
-        if self.uart.rxstatus().read().rdavl().bit_is_clear() {
+        if self.0.rxstatus().read().rdavl().bit_is_clear() {
             return Err(nb::Error::WouldBlock);
         }
         Ok(self.read_fifo_unchecked())
@@ -812,15 +741,20 @@ impl<Uart: Instance> Rx<Uart> {
     /// value if you use the manual parity mode. See chapter 4.6.2 for more information.
     #[inline(always)]
     pub fn read_fifo_unchecked(&self) -> u32 {
-        self.uart.data().read().bits()
+        self.0.data().read().bits()
     }
 
-    pub fn into_rx_with_irq(self) -> RxWithInterrupt<Uart> {
+    pub fn into_rx_with_irq(
-        RxWithInterrupt::new(self)
+        self,
+        sysconfig: &mut pac::Sysconfig,
+        irqsel: &mut pac::Irqsel,
+        interrupt: pac::Interrupt,
+    ) -> RxWithIrq<Uart> {
+        RxWithIrq::new(self, sysconfig, irqsel, interrupt)
     }
 
     pub fn release(self) -> Uart {
-        self.uart
+        self.0
     }
 }
 
@@ -877,51 +811,14 @@ impl<Uart: Instance> embedded_io::Read for Rx<Uart> {
     }
 }
 
-pub fn enable_tx(uart: &uart_base::RegisterBlock) {
-    uart.enable().modify(|_, w| w.txenable().set_bit());
-}
-
-pub fn disable_tx(uart: &uart_base::RegisterBlock) {
-    uart.enable().modify(|_, w| w.txenable().clear_bit());
-}
-
-pub fn enable_tx_interrupts(uart: &uart_base::RegisterBlock) {
-    uart.irq_enb().modify(|_, w| {
-        w.irq_tx().set_bit();
-        w.irq_tx_status().set_bit();
-        w.irq_tx_empty().set_bit()
-    });
-}
-
-pub fn disable_tx_interrupts(uart: &uart_base::RegisterBlock) {
-    uart.irq_enb().modify(|_, w| {
-        w.irq_tx().clear_bit();
-        w.irq_tx_status().clear_bit();
-        w.irq_tx_empty().clear_bit()
-    });
-}
-
 /// Serial transmitter
 ///
 /// Can be created by using the [Uart::split] or [UartBase::split] API.
-pub struct Tx<Uart> {
+pub struct Tx<Uart>(Uart);
-    uart: Uart,
-}
 
 impl<Uart: Instance> Tx<Uart> {
-    /// Retrieve a TX pin without expecting an explicit UART structure
-    ///
-    /// # Safety
-    ///
-    /// Circumvents the HAL safety guarantees.
-    pub unsafe fn steal() -> Self {
-        Self {
-            uart: Uart::steal(),
-        }
-    }
-
     fn new(uart: Uart) -> Self {
-        Self { uart }
+        Self(uart)
     }
 
     /// Direct access to the peripheral structure.
@@ -930,45 +827,22 @@ impl<Uart: Instance> Tx<Uart> {
     ///
     /// You must ensure that only registers related to the operation of the TX side are used.
     pub unsafe fn uart(&self) -> &Uart {
-        &self.uart
+        &self.0
     }
 
     #[inline]
     pub fn clear_fifo(&self) {
-        self.uart.fifo_clr().write(|w| w.txfifo().set_bit());
+        self.0.fifo_clr().write(|w| w.txfifo().set_bit());
     }
 
     #[inline]
     pub fn enable(&mut self) {
-        // Safety: We own the UART structure
+        self.0.enable().modify(|_, w| w.txenable().set_bit());
-        enable_tx(unsafe { Uart::reg_block() });
     }
 
     #[inline]
     pub fn disable(&mut self) {
-        // Safety: We own the UART structure
+        self.0.enable().modify(|_, w| w.txenable().clear_bit());
-        disable_tx(unsafe { Uart::reg_block() });
-    }
-
-    /// Enables the IRQ_TX, IRQ_TX_STATUS and IRQ_TX_EMPTY interrupts.
-    ///
-    /// - The IRQ_TX interrupt is generated when the TX FIFO is at least half empty.
-    /// - The IRQ_TX_STATUS interrupt is generated when write data is lost due to a FIFO overflow
-    /// - The IRQ_TX_EMPTY interrupt is generated when the TX FIFO is empty and the TXBUSY signal
-    ///   is 0
-    #[inline]
-    pub fn enable_interrupts(&self) {
-        // Safety: We own the UART structure
-        enable_tx_interrupts(unsafe { Uart::reg_block() });
-    }
-
-    /// Disables the IRQ_TX, IRQ_TX_STATUS and IRQ_TX_EMPTY interrupts.
-    ///
-    /// [Self::enable_interrupts] documents the interrupts.
-    #[inline]
-    pub fn disable_interrupts(&self) {
-        // Safety: We own the UART structure
-        disable_tx_interrupts(unsafe { Uart::reg_block() });
     }
 
     /// Low level function to write a word to the UART FIFO.
@@ -979,7 +853,7 @@ impl<Uart: Instance> Tx<Uart> {
     /// value if you use the manual parity mode. See chapter 11.4.1 for more information.
     #[inline(always)]
     pub fn write_fifo(&self, data: u32) -> nb::Result<(), Infallible> {
-        if self.uart.txstatus().read().wrrdy().bit_is_clear() {
+        if self.0.txstatus().read().wrrdy().bit_is_clear() {
             return Err(nb::Error::WouldBlock);
         }
         self.write_fifo_unchecked(data);
@@ -994,11 +868,7 @@ impl<Uart: Instance> Tx<Uart> {
     /// API.
     #[inline(always)]
     pub fn write_fifo_unchecked(&self, data: u32) {
-        self.uart.data().write(|w| unsafe { w.bits(data) });
+        self.0.data().write(|w| unsafe { w.bits(data) });
-    }
-
-    pub fn into_async(self) -> TxAsync<Uart> {
-        TxAsync::new(self)
     }
 }
 
@@ -1061,23 +931,36 @@ impl<Uart: Instance> embedded_io::Write for Tx<Uart> {
 ///     then call the [Self::irq_handler_max_size_or_timeout_based] in the interrupt service
 ///     routine. You have to call [Self::read_fixed_len_or_timeout_based_using_irq] in the ISR to
 ///     start reading the next packet.
-pub struct RxWithInterrupt<Uart>(Rx<Uart>);
+pub struct RxWithIrq<Uart> {
+    pub rx: Rx<Uart>,
+    pub interrupt: pac::Interrupt,
+}
 
-impl<Uart: Instance> RxWithInterrupt<Uart> {
+impl<Uart: Instance> RxWithIrq<Uart> {
-    pub fn new(rx: Rx<Uart>) -> Self {
+    pub fn new(
-        Self(rx)
+        rx: Rx<Uart>,
+        syscfg: &mut pac::Sysconfig,
+        irqsel: &mut pac::Irqsel,
+        interrupt: pac::Interrupt,
+    ) -> Self {
+        enable_peripheral_clock(syscfg, PeripheralSelect::Irqsel);
+        irqsel
+            .uart0(Uart::IDX as usize)
+            .write(|w| unsafe { w.bits(interrupt as u32) });
+        Self { rx, interrupt }
     }
 
     /// This function should be called once at initialization time if the regular
     /// [Self::irq_handler] is used to read the UART receiver to enable and start the receiver.
     pub fn start(&mut self) {
-        self.0.enable();
+        self.rx.enable();
         self.enable_rx_irq_sources(true);
+        unsafe { enable_interrupt(self.interrupt) };
     }
 
     #[inline(always)]
     pub fn uart(&self) -> &Uart {
-        &self.0.uart
+        &self.rx.0
     }
 
     /// This function is used together with the [Self::irq_handler_max_size_or_timeout_based]
@@ -1123,7 +1006,7 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
 
     pub fn cancel_transfer(&mut self) {
         self.disable_rx_irq_sources();
-        self.0.clear_fifo();
+        self.rx.clear_fifo();
     }
 
     /// This function should be called in the user provided UART interrupt handler.
@@ -1134,7 +1017,7 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
     /// This function will not disable the RX interrupts, so you don't need to call any other
     /// API after calling this function to continue emptying the FIFO. RX errors are handled
     /// as partial errors and are returned as part of the [IrqResult].
-    pub fn on_interrupt(&mut self, buf: &mut [u8; 16]) -> IrqResult {
+    pub fn irq_handler(&mut self, buf: &mut [u8; 16]) -> IrqResult {
         let mut result = IrqResult::default();
 
         let irq_end = self.uart().irq_end().read();
@@ -1157,7 +1040,7 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
         if irq_end.irq_rx_to().bit_is_set() {
             loop {
                 // While there is data in the FIFO, write it into the reception buffer
-                let read_result = self.0.read();
+                let read_result = self.rx.read();
                 if let Some(byte) = self.read_handler(&mut result.errors, &read_result) {
                     buf[result.bytes_read] = byte;
                     result.bytes_read += 1;
@@ -1191,7 +1074,7 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
     /// If passed buffer is equal to or larger than the specified maximum length, an
     /// [BufferTooShortError] will be returned. Other RX errors are treated as partial errors
     /// and returned inside the [IrqResultMaxSizeOrTimeout] structure.
-    pub fn on_interrupt_max_size_or_timeout_based(
+    pub fn irq_handler_max_size_or_timeout_based(
         &mut self,
         context: &mut IrqContextTimeoutOrMaxSize,
         buf: &mut [u8],
@@ -1240,7 +1123,7 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
                 if context.rx_idx == context.max_len {
                     break;
                 }
-                let read_result = self.0.read();
+                let read_result = self.rx.read();
                 if let Some(byte) = self.read_handler(&mut result.errors, &read_result) {
                     buf[context.rx_idx] = byte;
                     context.rx_idx += 1;
@@ -1314,7 +1197,7 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
         context: &mut IrqContextTimeoutOrMaxSize,
     ) {
         self.disable_rx_irq_sources();
-        self.0.disable();
+        self.rx.disable();
         res.bytes_read = context.rx_idx;
         res.complete = true;
         context.mode = IrqReceptionMode::Idle;
@@ -1327,9 +1210,6 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
     /// The user must ensure that these instances are not used to create multiple overlapping
     /// UART drivers.
     pub unsafe fn release(self) -> Uart {
-        self.0.release()
+        self.rx.release()
     }
 }
-
-pub mod asynch;
-pub use asynch::*;

va108xx-hal/src/uart/asynch.rs

@@ -1,264 +0,0 @@
-//! # Async GPIO functionality for the VA108xx family.
-//!
-//! This module provides the [TxAsync] struct which implements the [embedded_io_async::Write] trait.
-//! This trait allows for asynchronous sending of data streams. Please note that this module does
-//! not specify/declare the interrupt handlers which must be provided for async support to work.
-//! However, it provides two interrupt handlers:
-//!
-//! - [on_interrupt_uart_a_tx]
-//! - [on_interrupt_uart_b_tx]
-//!
-//! Those should be called in ALL user interrupt handlers which handle UART TX interrupts,
-//! depending on which UARTs are used.
-//!
-//! # Example
-//!
-//! - [Async UART example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/async-gpio/examples/embassy/src/bin/async-uart.rs)
-use core::{cell::RefCell, future::Future};
-
-use critical_section::Mutex;
-use embassy_sync::waitqueue::AtomicWaker;
-use embedded_io_async::Write;
-use portable_atomic::AtomicBool;
-
-use super::*;
-
-static UART_WAKERS: [AtomicWaker; 2] = [const { AtomicWaker::new() }; 2];
-static TX_CONTEXTS: [Mutex<RefCell<TxContext>>; 2] =
-    [const { Mutex::new(RefCell::new(TxContext::new())) }; 2];
-// Completion flag. Kept outside of the context structure as an atomic to avoid
-// critical section.
-static TX_DONE: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2];
-
-/// This is a generic interrupt handler to handle asynchronous UART TX operations. The user
-/// has to call this once in the interrupt handler responsible for UART A TX interrupts for
-/// asynchronous operations to work.
-pub fn on_interrupt_uart_a_tx() {
-    on_interrupt_uart_tx(unsafe { pac::Uarta::steal() });
-}
-
-/// This is a generic interrupt handler to handle asynchronous UART TX operations. The user
-/// has to call this once in the interrupt handler responsible for UART B TX interrupts for
-/// asynchronous operations to work.
-pub fn on_interrupt_uart_b_tx() {
-    on_interrupt_uart_tx(unsafe { pac::Uartb::steal() });
-}
-
-fn on_interrupt_uart_tx<Uart: Instance>(uart: Uart) {
-    let irq_enb = uart.irq_enb().read();
-    // IRQ is not related to TX.
-    if irq_enb.irq_tx().bit_is_clear() || irq_enb.irq_tx_empty().bit_is_clear() {
-        return;
-    }
-
-    let tx_status = uart.txstatus().read();
-    let unexpected_overrun = tx_status.wrlost().bit_is_set();
-    let mut context = critical_section::with(|cs| {
-        let context_ref = TX_CONTEXTS[Uart::IDX as usize].borrow(cs);
-        *context_ref.borrow()
-    });
-    context.tx_overrun = unexpected_overrun;
-    if context.progress >= context.slice.len && !tx_status.wrbusy().bit_is_set() {
-        uart.irq_enb().modify(|_, w| {
-            w.irq_tx().clear_bit();
-            w.irq_tx_empty().clear_bit();
-            w.irq_tx_status().clear_bit()
-        });
-        uart.enable().modify(|_, w| w.txenable().clear_bit());
-        // Write back updated context structure.
-        critical_section::with(|cs| {
-            let context_ref = TX_CONTEXTS[Uart::IDX as usize].borrow(cs);
-            *context_ref.borrow_mut() = context;
-        });
-        // Transfer is done.
-        TX_DONE[Uart::IDX as usize].store(true, core::sync::atomic::Ordering::Relaxed);
-        UART_WAKERS[Uart::IDX as usize].wake();
-        return;
-    }
-    // Safety: We documented that the user provided slice must outlive the future, so we convert
-    // the raw pointer back to the slice here.
-    let slice = unsafe { core::slice::from_raw_parts(context.slice.data, context.slice.len) };
-    while context.progress < context.slice.len {
-        let wrrdy = uart.txstatus().read().wrrdy().bit_is_set();
-        if !wrrdy {
-            break;
-        }
-        // Safety: TX structure is owned by the future which does not write into the the data
-        // register, so we can assume we are the only one writing to the data register.
-        uart.data()
-            .write(|w| unsafe { w.bits(slice[context.progress] as u32) });
-        context.progress += 1;
-    }
-
-    // Write back updated context structure.
-    critical_section::with(|cs| {
-        let context_ref = TX_CONTEXTS[Uart::IDX as usize].borrow(cs);
-        *context_ref.borrow_mut() = context;
-    });
-}
-
-#[derive(Debug, Copy, Clone)]
-pub struct TxContext {
-    progress: usize,
-    tx_overrun: bool,
-    slice: RawBufSlice,
-}
-
-#[allow(clippy::new_without_default)]
-impl TxContext {
-    pub const fn new() -> Self {
-        Self {
-            progress: 0,
-            tx_overrun: false,
-            slice: RawBufSlice::new_empty(),
-        }
-    }
-}
-
-#[derive(Debug, Copy, Clone)]
-struct RawBufSlice {
-    data: *const u8,
-    len: usize,
-}
-
-/// Safety: This type MUST be used with mutex to ensure concurrent access is valid.
-unsafe impl Send for RawBufSlice {}
-
-impl RawBufSlice {
-    /// # Safety
-    ///
-    /// This function stores the raw pointer of the passed data slice. The user MUST ensure
-    /// that the slice outlives the data structure.
-    #[allow(dead_code)]
-    const unsafe fn new(data: &[u8]) -> Self {
-        Self {
-            data: data.as_ptr(),
-            len: data.len(),
-        }
-    }
-
-    const fn new_empty() -> Self {
-        Self {
-            data: core::ptr::null(),
-            len: 0,
-        }
-    }
-
-    /// # Safety
-    ///
-    /// This function stores the raw pointer of the passed data slice. The user MUST ensure
-    /// that the slice outlives the data structure.
-    pub unsafe fn set(&mut self, data: &[u8]) {
-        self.data = data.as_ptr();
-        self.len = data.len();
-    }
-}
-
-pub struct TxFuture {
-    uart_idx: usize,
-}
-
-impl TxFuture {
-    /// # Safety
-    ///
-    /// This function stores the raw pointer of the passed data slice. The user MUST ensure
-    /// that the slice outlives the data structure.
-    pub unsafe fn new<Uart: Instance>(tx: &mut Tx<Uart>, data: &[u8]) -> Self {
-        TX_DONE[Uart::IDX as usize].store(false, core::sync::atomic::Ordering::Relaxed);
-        tx.disable_interrupts();
-        tx.disable();
-        tx.clear_fifo();
-
-        let uart_tx = unsafe { tx.uart() };
-        let init_fill_count = core::cmp::min(data.len(), 16);
-        // We fill the FIFO.
-        for data in data.iter().take(init_fill_count) {
-            uart_tx.data().write(|w| unsafe { w.bits(*data as u32) });
-        }
-        critical_section::with(|cs| {
-            let context_ref = TX_CONTEXTS[Uart::IDX as usize].borrow(cs);
-            let mut context = context_ref.borrow_mut();
-            context.slice.set(data);
-            context.progress = init_fill_count;
-
-            // Ensure those are enabled inside a critical section at the same time. Can lead to
-            // weird glitches otherwise.
-            tx.enable_interrupts();
-            tx.enable();
-        });
-        Self {
-            uart_idx: Uart::IDX as usize,
-        }
-    }
-}
-
-impl Future for TxFuture {
-    type Output = Result<usize, TxOverrunError>;
-
-    fn poll(
-        self: core::pin::Pin<&mut Self>,
-        cx: &mut core::task::Context<'_>,
-    ) -> core::task::Poll<Self::Output> {
-        UART_WAKERS[self.uart_idx].register(cx.waker());
-        if TX_DONE[self.uart_idx].swap(false, core::sync::atomic::Ordering::Relaxed) {
-            let progress = critical_section::with(|cs| {
-                TX_CONTEXTS[self.uart_idx].borrow(cs).borrow().progress
-            });
-            return core::task::Poll::Ready(Ok(progress));
-        }
-        core::task::Poll::Pending
-    }
-}
-
-impl Drop for TxFuture {
-    fn drop(&mut self) {
-        let reg_block = match self.uart_idx {
-            0 => unsafe { pac::Uarta::reg_block() },
-            1 => unsafe { pac::Uartb::reg_block() },
-            _ => unreachable!(),
-        };
-
-        disable_tx_interrupts(reg_block);
-        disable_tx(reg_block);
-    }
-}
-
-pub struct TxAsync<Uart: Instance> {
-    tx: Tx<Uart>,
-}
-
-impl<Uart: Instance> TxAsync<Uart> {
-    pub fn new(tx: Tx<Uart>) -> Self {
-        Self { tx }
-    }
-
-    pub fn release(self) -> Tx<Uart> {
-        self.tx
-    }
-}
-
-#[derive(Debug, thiserror::Error)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[error("TX overrun error")]
-pub struct TxOverrunError;
-
-impl embedded_io_async::Error for TxOverrunError {
-    fn kind(&self) -> embedded_io_async::ErrorKind {
-        embedded_io_async::ErrorKind::Other
-    }
-}
-
-impl<Uart: Instance> embedded_io::ErrorType for TxAsync<Uart> {
-    type Error = TxOverrunError;
-}
-
-impl<Uart: Instance> Write for TxAsync<Uart> {
-    /// Write a buffer asynchronously.
-    ///
-    /// This implementation is not side effect free, and a started future might have already
-    /// written part of the passed buffer.
-    async fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
-        let fut = unsafe { TxFuture::new(&mut self.tx, buf) };
-        fut.await
-    }
-}

va108xx/CHANGELOG.md

@@ -8,10 +8,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
-## [v0.4.0] 2025-02-12
-
-- Re-generated PAC with `svd2rust` v0.35.0
-
 ## [v0.3.0] 2024-06-16
 
 - Re-generated PAC with `svd2rust` v0.33.3

va108xx/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx"
-version = "0.4.0"
+version = "0.3.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "PAC for the Vorago VA108xx family of microcontrollers"

va108xx/README.md

@@ -24,7 +24,7 @@ features = ["rt"]
 The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`.
 
 For full details on the autgenerated API, please see the
-[svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/#peripheral-api).
+[svd2rust documentation](https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api).
 
 ## Regenerating the PAC
 

va108xx/gen-helper.sh

@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/bin/sh
 
 # Use installed tool by default
 svd2rust_bin="svd2rust"

va108xx/src/generic.rs

@@ -82,6 +82,169 @@ pub trait Resettable: RegisterSpec {
         Self::RESET_VALUE
     }
 }
+#[doc = " This structure provides volatile access to registers."]
+#[repr(transparent)]
+pub struct Reg<REG: RegisterSpec> {
+    register: vcell::VolatileCell<REG::Ux>,
+    _marker: marker::PhantomData<REG>,
+}
+unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
+impl<REG: RegisterSpec> Reg<REG> {
+    #[doc = " Returns the underlying memory address of register."]
+    #[doc = ""]
+    #[doc = " ```ignore"]
+    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn as_ptr(&self) -> *mut REG::Ux {
+        self.register.as_ptr()
+    }
+}
+impl<REG: Readable> Reg<REG> {
+    #[doc = " Reads the contents of a `Readable` register."]
+    #[doc = ""]
+    #[doc = " You can read the raw contents of a register by using `bits`:"]
+    #[doc = " ```ignore"]
+    #[doc = " let bits = periph.reg.read().bits();"]
+    #[doc = " ```"]
+    #[doc = " or get the content of a particular field of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " let reader = periph.reg.read();"]
+    #[doc = " let bits = reader.field1().bits();"]
+    #[doc = " let flag = reader.field2().bit_is_set();"]
+    #[doc = " ```"]
+    #[inline(always)]
+    pub fn read(&self) -> R<REG> {
+        R {
+            bits: self.register.get(),
+            _reg: marker::PhantomData,
+        }
+    }
+}
+impl<REG: Resettable + Writable> Reg<REG> {
+    #[doc = " Writes the reset value to `Writable` register."]
+    #[doc = ""]
+    #[doc = " Resets the register to its initial state."]
+    #[inline(always)]
+    pub fn reset(&self) {
+        self.register.set(REG::RESET_VALUE)
+    }
+    #[doc = " Writes bits to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " You can write raw bits into a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
+    #[doc = " ```"]
+    #[doc = " or write only the fields you need:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.write(|w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " In the latter case, other fields will be set to their reset value."]
+    #[inline(always)]
+    pub fn write<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut W {
+                bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                    | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                _reg: marker::PhantomData,
+            })
+            .bits,
+        );
+    }
+}
+impl<REG: Writable> Reg<REG> {
+    #[doc = " Writes 0 to a `Writable` register."]
+    #[doc = ""]
+    #[doc = " Similar to `write`, but unused bits will contain 0."]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Unsafe to use with registers which don't allow to write 0."]
+    #[inline(always)]
+    pub unsafe fn write_with_zero<F>(&self, f: F)
+    where
+        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+    {
+        self.register.set(
+            f(&mut W {
+                bits: REG::Ux::default(),
+                _reg: marker::PhantomData,
+            })
+            .bits,
+        );
+    }
+}
+impl<REG: Readable + Writable> Reg<REG> {
+    #[doc = " Modifies the contents of the register by reading and then writing it."]
+    #[doc = ""]
+    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
+    #[doc = "    r.bits() | 3"]
+    #[doc = " ) });"]
+    #[doc = " ```"]
+    #[doc = " or"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| w"]
+    #[doc = "     .field1().bits(newfield1bits)"]
+    #[doc = "     .field2().set_bit()"]
+    #[doc = "     .field3().variant(VARIANT)"]
+    #[doc = " );"]
+    #[doc = " ```"]
+    #[doc = " or an alternative way of saying the same:"]
+    #[doc = " ```ignore"]
+    #[doc = " periph.reg.modify(|_, w| {"]
+    #[doc = "     w.field1().bits(newfield1bits);"]
+    #[doc = "     w.field2().set_bit();"]
+    #[doc = "     w.field3().variant(VARIANT)"]
+    #[doc = " });"]
+    #[doc = " ```"]
+    #[doc = " Other fields will have the value they had before the call to `modify`."]
+    #[inline(always)]
+    pub fn modify<F>(&self, f: F)
+    where
+        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
+    {
+        let bits = self.register.get();
+        self.register.set(
+            f(
+                &R {
+                    bits,
+                    _reg: marker::PhantomData,
+                },
+                &mut W {
+                    bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+                        | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+                    _reg: marker::PhantomData,
+                },
+            )
+            .bits,
+        );
+    }
+}
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+    R<REG>: core::fmt::Debug,
+{
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
 #[doc(hidden)]
 pub mod raw;
 #[doc = " Register reader."]
@@ -206,7 +369,7 @@ pub struct RangeTo<const MAX: u64>;
 #[doc = " Write field Proxy"]
 pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
     raw::FieldWriter<'a, REG, WI, FI, Safety>;
-impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
+impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
 where
     REG: Writable + RegisterSpec,
     FI: FieldSpec,
@@ -453,278 +616,3 @@ where
         self.w
     }
 }
-#[doc = " This structure provides volatile access to registers."]
-#[repr(transparent)]
-pub struct Reg<REG: RegisterSpec> {
-    register: vcell::VolatileCell<REG::Ux>,
-    _marker: marker::PhantomData<REG>,
-}
-unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
-impl<REG: RegisterSpec> Reg<REG> {
-    #[doc = " Returns the underlying memory address of register."]
-    #[doc = ""]
-    #[doc = " ```ignore"]
-    #[doc = " let reg_ptr = periph.reg.as_ptr();"]
-    #[doc = " ```"]
-    #[inline(always)]
-    pub fn as_ptr(&self) -> *mut REG::Ux {
-        self.register.as_ptr()
-    }
-}
-impl<REG: Readable> Reg<REG> {
-    #[doc = " Reads the contents of a `Readable` register."]
-    #[doc = ""]
-    #[doc = " You can read the raw contents of a register by using `bits`:"]
-    #[doc = " ```ignore"]
-    #[doc = " let bits = periph.reg.read().bits();"]
-    #[doc = " ```"]
-    #[doc = " or get the content of a particular field of a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " let reader = periph.reg.read();"]
-    #[doc = " let bits = reader.field1().bits();"]
-    #[doc = " let flag = reader.field2().bit_is_set();"]
-    #[doc = " ```"]
-    #[inline(always)]
-    pub fn read(&self) -> R<REG> {
-        R {
-            bits: self.register.get(),
-            _reg: marker::PhantomData,
-        }
-    }
-}
-impl<REG: Resettable + Writable> Reg<REG> {
-    #[doc = " Writes the reset value to `Writable` register."]
-    #[doc = ""]
-    #[doc = " Resets the register to its initial state."]
-    #[inline(always)]
-    pub fn reset(&self) {
-        self.register.set(REG::RESET_VALUE)
-    }
-    #[doc = " Writes bits to a `Writable` register."]
-    #[doc = ""]
-    #[doc = " You can write raw bits into a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
-    #[doc = " ```"]
-    #[doc = " or write only the fields you need:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write(|w| w"]
-    #[doc = "     .field1().bits(newfield1bits)"]
-    #[doc = "     .field2().set_bit()"]
-    #[doc = "     .field3().variant(VARIANT)"]
-    #[doc = " );"]
-    #[doc = " ```"]
-    #[doc = " or an alternative way of saying the same:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write(|w| {"]
-    #[doc = "     w.field1().bits(newfield1bits);"]
-    #[doc = "     w.field2().set_bit();"]
-    #[doc = "     w.field3().variant(VARIANT)"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " In the latter case, other fields will be set to their reset value."]
-    #[inline(always)]
-    pub fn write<F>(&self, f: F) -> REG::Ux
-    where
-        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
-    {
-        let value = f(&mut W {
-            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-            _reg: marker::PhantomData,
-        })
-        .bits;
-        self.register.set(value);
-        value
-    }
-    #[doc = " Writes bits to a `Writable` register and produce a value."]
-    #[doc = ""]
-    #[doc = " You can write raw bits into a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
-    #[doc = " ```"]
-    #[doc = " or write only the fields you need:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write_and(|w| {"]
-    #[doc = "     w.field1().bits(newfield1bits)"]
-    #[doc = "         .field2().set_bit()"]
-    #[doc = "         .field3().variant(VARIANT);"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " or an alternative way of saying the same:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.write_and(|w| {"]
-    #[doc = "     w.field1().bits(newfield1bits);"]
-    #[doc = "     w.field2().set_bit();"]
-    #[doc = "     w.field3().variant(VARIANT);"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " In the latter case, other fields will be set to their reset value."]
-    #[doc = ""]
-    #[doc = " Values can be returned from the closure:"]
-    #[doc = " ```ignore"]
-    #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
-    #[doc = " ```"]
-    #[inline(always)]
-    pub fn from_write<F, T>(&self, f: F) -> T
-    where
-        F: FnOnce(&mut W<REG>) -> T,
-    {
-        let mut writer = W {
-            bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
-                | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-            _reg: marker::PhantomData,
-        };
-        let result = f(&mut writer);
-        self.register.set(writer.bits);
-        result
-    }
-}
-impl<REG: Writable> Reg<REG> {
-    #[doc = " Writes 0 to a `Writable` register."]
-    #[doc = ""]
-    #[doc = " Similar to `write`, but unused bits will contain 0."]
-    #[doc = ""]
-    #[doc = " # Safety"]
-    #[doc = ""]
-    #[doc = " Unsafe to use with registers which don't allow to write 0."]
-    #[inline(always)]
-    pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
-    where
-        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
-    {
-        let value = f(&mut W {
-            bits: REG::Ux::default(),
-            _reg: marker::PhantomData,
-        })
-        .bits;
-        self.register.set(value);
-        value
-    }
-    #[doc = " Writes 0 to a `Writable` register and produces a value."]
-    #[doc = ""]
-    #[doc = " Similar to `write`, but unused bits will contain 0."]
-    #[doc = ""]
-    #[doc = " # Safety"]
-    #[doc = ""]
-    #[doc = " Unsafe to use with registers which don't allow to write 0."]
-    #[inline(always)]
-    pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
-    where
-        F: FnOnce(&mut W<REG>) -> T,
-    {
-        let mut writer = W {
-            bits: REG::Ux::default(),
-            _reg: marker::PhantomData,
-        };
-        let result = f(&mut writer);
-        self.register.set(writer.bits);
-        result
-    }
-}
-impl<REG: Readable + Writable> Reg<REG> {
-    #[doc = " Modifies the contents of the register by reading and then writing it."]
-    #[doc = ""]
-    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
-    #[doc = "    r.bits() | 3"]
-    #[doc = " ) });"]
-    #[doc = " ```"]
-    #[doc = " or"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|_, w| w"]
-    #[doc = "     .field1().bits(newfield1bits)"]
-    #[doc = "     .field2().set_bit()"]
-    #[doc = "     .field3().variant(VARIANT)"]
-    #[doc = " );"]
-    #[doc = " ```"]
-    #[doc = " or an alternative way of saying the same:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|_, w| {"]
-    #[doc = "     w.field1().bits(newfield1bits);"]
-    #[doc = "     w.field2().set_bit();"]
-    #[doc = "     w.field3().variant(VARIANT)"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " Other fields will have the value they had before the call to `modify`."]
-    #[inline(always)]
-    pub fn modify<F>(&self, f: F) -> REG::Ux
-    where
-        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
-    {
-        let bits = self.register.get();
-        let value = f(
-            &R {
-                bits,
-                _reg: marker::PhantomData,
-            },
-            &mut W {
-                bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-                _reg: marker::PhantomData,
-            },
-        )
-        .bits;
-        self.register.set(value);
-        value
-    }
-    #[doc = " Modifies the contents of the register by reading and then writing it"]
-    #[doc = " and produces a value."]
-    #[doc = ""]
-    #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
-    #[doc = " ```ignore"]
-    #[doc = " let bits = periph.reg.modify(|r, w| {"]
-    #[doc = "     let new_bits = r.bits() | 3;"]
-    #[doc = "     unsafe {"]
-    #[doc = "         w.bits(new_bits);"]
-    #[doc = "     }"]
-    #[doc = ""]
-    #[doc = "     new_bits"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " or"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|_, w| {"]
-    #[doc = "     w.field1().bits(newfield1bits)"]
-    #[doc = "         .field2().set_bit()"]
-    #[doc = "         .field3().variant(VARIANT);"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " or an alternative way of saying the same:"]
-    #[doc = " ```ignore"]
-    #[doc = " periph.reg.modify(|_, w| {"]
-    #[doc = "     w.field1().bits(newfield1bits);"]
-    #[doc = "     w.field2().set_bit();"]
-    #[doc = "     w.field3().variant(VARIANT);"]
-    #[doc = " });"]
-    #[doc = " ```"]
-    #[doc = " Other fields will have the value they had before the call to `modify`."]
-    #[inline(always)]
-    pub fn from_modify<F, T>(&self, f: F) -> T
-    where
-        for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
-    {
-        let bits = self.register.get();
-        let mut writer = W {
-            bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
-            _reg: marker::PhantomData,
-        };
-        let result = f(
-            &R {
-                bits,
-                _reg: marker::PhantomData,
-            },
-            &mut writer,
-        );
-        self.register.set(writer.bits);
-        result
-    }
-}
-impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
-where
-    R<REG>: core::fmt::Debug,
-{
-    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
-        core::fmt::Debug::fmt(&self.read(), f)
-    }
-}

va108xx/src/generic/raw.rs

@@ -41,7 +41,6 @@ impl<FI> BitReader<FI> {
         }
     }
 }
-#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
 pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
 where
     REG: Writable + RegisterSpec,
@@ -67,7 +66,6 @@ where
         }
     }
 }
-#[must_use = "after creating `BitWriter` you need to call bit setting method"]
 pub struct BitWriter<'a, REG, FI = bool, M = BitM>
 where
     REG: Writable + RegisterSpec,

va108xx/src/i2ca.rs

@@ -240,67 +240,67 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
 module"]
 #[doc(alias = "CTRL")]
 pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
 #[doc = "Control Register"]
 pub mod ctrl;
-#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
+#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
 module"]
 #[doc(alias = "CLKSCALE")]
 pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
 #[doc = "Clock Scale divide value"]
 pub mod clkscale;
-#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
+#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
 module"]
 #[doc(alias = "WORDS")]
 pub type Words = crate::Reg<words::WordsSpec>;
 #[doc = "Word Count value"]
 pub mod words;
-#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
+#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
 module"]
 #[doc(alias = "ADDRESS")]
 pub type Address = crate::Reg<address::AddressSpec>;
 #[doc = "I2C Address value"]
 pub mod address;
-#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
 module"]
 #[doc(alias = "DATA")]
 pub type Data = crate::Reg<data::DataSpec>;
 #[doc = "Data Input/Output"]
 pub mod data;
-#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
+#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
 module"]
 #[doc(alias = "CMD")]
 pub type Cmd = crate::Reg<cmd::CmdSpec>;
 #[doc = "Command Register"]
 pub mod cmd;
-#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
+#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
 module"]
 #[doc(alias = "STATUS")]
 pub type Status = crate::Reg<status::StatusSpec>;
 #[doc = "I2C Controller Status Register"]
 pub mod status;
-#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
 module"]
 #[doc(alias = "STATE")]
 pub type State = crate::Reg<state::StateSpec>;
 #[doc = "Internal STATE of I2C Master Controller"]
 pub mod state;
-#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
+#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
 module"]
 #[doc(alias = "TXCOUNT")]
 pub type Txcount = crate::Reg<txcount::TxcountSpec>;
 #[doc = "TX Count Register"]
 pub mod txcount;
-#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
+#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
 module"]
 #[doc(alias = "RXCOUNT")]
 pub type Rxcount = crate::Reg<rxcount::RxcountSpec>;
 #[doc = "RX Count Register"]
 pub mod rxcount;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
 module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
@@ -312,97 +312,97 @@ pub use irq_enb as irq_clr;
 pub use IrqEnb as IrqRaw;
 pub use IrqEnb as IrqEnd;
 pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
 module"]
 #[doc(alias = "RXFIFOIRQTRG")]
 pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
 #[doc = "Rx FIFO IRQ Trigger Level"]
 pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
 module"]
 #[doc(alias = "TXFIFOIRQTRG")]
 pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
 #[doc = "Tx FIFO IRQ Trigger Level"]
 pub mod txfifoirqtrg;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
 module"]
 #[doc(alias = "FIFO_CLR")]
 pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
 #[doc = "Clear FIFO Register"]
 pub mod fifo_clr;
-#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
+#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
 module"]
 #[doc(alias = "TMCONFIG")]
 pub type Tmconfig = crate::Reg<tmconfig::TmconfigSpec>;
 #[doc = "Timing Config Register"]
 pub mod tmconfig;
-#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
+#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
 module"]
 #[doc(alias = "CLKTOLIMIT")]
 pub type Clktolimit = crate::Reg<clktolimit::ClktolimitSpec>;
 #[doc = "Clock Low Timeout Limit Register"]
 pub mod clktolimit;
-#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
+#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
 module"]
 #[doc(alias = "S0_CTRL")]
 pub type S0Ctrl = crate::Reg<s0_ctrl::S0CtrlSpec>;
 #[doc = "Slave Control Register"]
 pub mod s0_ctrl;
-#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
+#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
 module"]
 #[doc(alias = "S0_MAXWORDS")]
 pub type S0Maxwords = crate::Reg<s0_maxwords::S0MaxwordsSpec>;
 #[doc = "Slave MaxWords Register"]
 pub mod s0_maxwords;
-#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
+#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
 module"]
 #[doc(alias = "S0_ADDRESS")]
 pub type S0Address = crate::Reg<s0_address::S0AddressSpec>;
 #[doc = "Slave I2C Address Value"]
 pub mod s0_address;
-#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
+#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
 module"]
 #[doc(alias = "S0_ADDRESSMASK")]
 pub type S0Addressmask = crate::Reg<s0_addressmask::S0AddressmaskSpec>;
 #[doc = "Slave I2C Address Mask value"]
 pub mod s0_addressmask;
-#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
+#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
 module"]
 #[doc(alias = "S0_DATA")]
 pub type S0Data = crate::Reg<s0_data::S0DataSpec>;
 #[doc = "Slave Data Input/Output"]
 pub mod s0_data;
-#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
+#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
 module"]
 #[doc(alias = "S0_LASTADDRESS")]
 pub type S0Lastaddress = crate::Reg<s0_lastaddress::S0LastaddressSpec>;
 #[doc = "Slave I2C Last Address value"]
 pub mod s0_lastaddress;
-#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
+#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
 module"]
 #[doc(alias = "S0_STATUS")]
 pub type S0Status = crate::Reg<s0_status::S0StatusSpec>;
 #[doc = "Slave I2C Controller Status Register"]
 pub mod s0_status;
-#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
+#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
 module"]
 #[doc(alias = "S0_STATE")]
 pub type S0State = crate::Reg<s0_state::S0StateSpec>;
 #[doc = "Internal STATE of I2C Slave Controller"]
 pub mod s0_state;
-#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
+#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
 module"]
 #[doc(alias = "S0_TXCOUNT")]
 pub type S0Txcount = crate::Reg<s0_txcount::S0TxcountSpec>;
 #[doc = "Slave TX Count Register"]
 pub mod s0_txcount;
-#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
+#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
 module"]
 #[doc(alias = "S0_RXCOUNT")]
 pub type S0Rxcount = crate::Reg<s0_rxcount::S0RxcountSpec>;
 #[doc = "Slave RX Count Register"]
 pub mod s0_rxcount;
-#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
+#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
 module"]
 #[doc(alias = "S0_IRQ_ENB")]
 pub type S0IrqEnb = crate::Reg<s0_irq_enb::S0IrqEnbSpec>;
@@ -414,37 +414,37 @@ pub use s0_irq_enb as s0_irq_clr;
 pub use S0IrqEnb as S0IrqRaw;
 pub use S0IrqEnb as S0IrqEnd;
 pub use S0IrqEnb as S0IrqClr;
-#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
+#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
 module"]
 #[doc(alias = "S0_RXFIFOIRQTRG")]
 pub type S0Rxfifoirqtrg = crate::Reg<s0_rxfifoirqtrg::S0RxfifoirqtrgSpec>;
 #[doc = "Slave Rx FIFO IRQ Trigger Level"]
 pub mod s0_rxfifoirqtrg;
-#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
+#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
 module"]
 #[doc(alias = "S0_TXFIFOIRQTRG")]
 pub type S0Txfifoirqtrg = crate::Reg<s0_txfifoirqtrg::S0TxfifoirqtrgSpec>;
 #[doc = "Slave Tx FIFO IRQ Trigger Level"]
 pub mod s0_txfifoirqtrg;
-#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
+#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
 module"]
 #[doc(alias = "S0_FIFO_CLR")]
 pub type S0FifoClr = crate::Reg<s0_fifo_clr::S0FifoClrSpec>;
 #[doc = "Slave Clear FIFO Register"]
 pub mod s0_fifo_clr;
-#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
+#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
 module"]
 #[doc(alias = "S0_ADDRESSB")]
 pub type S0Addressb = crate::Reg<s0_addressb::S0AddressbSpec>;
 #[doc = "Slave I2C Address B Value"]
 pub mod s0_addressb;
-#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
+#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
 module"]
 #[doc(alias = "S0_ADDRESSMASKB")]
 pub type S0Addressmaskb = crate::Reg<s0_addressmaskb::S0AddressmaskbSpec>;
 #[doc = "Slave I2C Address B Mask value"]
 pub mod s0_addressmaskb;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
 module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;

va108xx/src/i2ca/address.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct AddressSpec;
 impl crate::RegisterSpec for AddressSpec {
     type Ux = u32;

va108xx/src/i2ca/clkscale.rs

@@ -25,16 +25,18 @@ impl R {
 impl W {
     #[doc = "Bits 0:30 - Enable FastMode"]
     #[inline(always)]
+    #[must_use]
     pub fn value(&mut self) -> ValueW<ClkscaleSpec> {
         ValueW::new(self, 0)
     }
     #[doc = "Bit 31 - Enable FastMode"]
     #[inline(always)]
+    #[must_use]
     pub fn fastmode(&mut self) -> FastmodeW<ClkscaleSpec> {
         FastmodeW::new(self, 31)
     }
 }
-#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ClkscaleSpec;
 impl crate::RegisterSpec for ClkscaleSpec {
     type Ux = u32;

va108xx/src/i2ca/clktolimit.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ClktolimitSpec;
 impl crate::RegisterSpec for ClktolimitSpec {
     type Ux = u32;

va108xx/src/i2ca/cmd.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CmdSpec;
 impl crate::RegisterSpec for CmdSpec {
     type Ux = u32;

va108xx/src/i2ca/ctrl.rs

@@ -88,51 +88,60 @@ impl R {
 impl W {
     #[doc = "Bit 0 - I2C CLK Enabled"]
     #[inline(always)]
+    #[must_use]
     pub fn clkenabled(&mut self) -> ClkenabledW<CtrlSpec> {
         ClkenabledW::new(self, 0)
     }
     #[doc = "Bit 1 - I2C Activated"]
     #[inline(always)]
+    #[must_use]
     pub fn enabled(&mut self) -> EnabledW<CtrlSpec> {
         EnabledW::new(self, 1)
     }
     #[doc = "Bit 2 - I2C Active"]
     #[inline(always)]
+    #[must_use]
     pub fn enable(&mut self) -> EnableW<CtrlSpec> {
         EnableW::new(self, 2)
     }
     #[doc = "Bit 3 - TX FIFIO Empty Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn txfemd(&mut self) -> TxfemdW<CtrlSpec> {
         TxfemdW::new(self, 3)
     }
     #[doc = "Bit 4 - RX FIFO Full Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn rxffmd(&mut self) -> RxffmdW<CtrlSpec> {
         RxffmdW::new(self, 4)
     }
     #[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
     #[inline(always)]
+    #[must_use]
     pub fn algfilter(&mut self) -> AlgfilterW<CtrlSpec> {
         AlgfilterW::new(self, 5)
     }
     #[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
     #[inline(always)]
+    #[must_use]
     pub fn dlgfilter(&mut self) -> DlgfilterW<CtrlSpec> {
         DlgfilterW::new(self, 6)
     }
     #[doc = "Bit 8 - Enable LoopBack Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
         LoopbackW::new(self, 8)
     }
     #[doc = "Bit 9 - Enable Timing Config Register"]
     #[inline(always)]
+    #[must_use]
     pub fn tmconfigenb(&mut self) -> TmconfigenbW<CtrlSpec> {
         TmconfigenbW::new(self, 9)
     }
 }
-#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CtrlSpec;
 impl crate::RegisterSpec for CtrlSpec {
     type Ux = u32;

va108xx/src/i2ca/data.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DataSpec;
 impl crate::RegisterSpec for DataSpec {
     type Ux = u32;

va108xx/src/i2ca/fifo_clr.rs

@@ -7,16 +7,18 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bit 0 - Clear Rx FIFO"]
     #[inline(always)]
+    #[must_use]
     pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
         RxfifoW::new(self, 0)
     }
     #[doc = "Bit 1 - Clear Tx FIFO"]
     #[inline(always)]
+    #[must_use]
     pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
         TxfifoW::new(self, 1)
     }
 }
-#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FifoClrSpec;
 impl crate::RegisterSpec for FifoClrSpec {
     type Ux = u32;

va108xx/src/i2ca/irq_enb.rs

@@ -133,76 +133,90 @@ impl R {
 impl W {
     #[doc = "Bit 0 - I2C Bus is Idle"]
     #[inline(always)]
+    #[must_use]
     pub fn i2cidle(&mut self) -> I2cidleW<IrqEnbSpec> {
         I2cidleW::new(self, 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
+    #[must_use]
     pub fn idle(&mut self) -> IdleW<IrqEnbSpec> {
         IdleW::new(self, 1)
     }
     #[doc = "Bit 2 - Controller is Waiting"]
     #[inline(always)]
+    #[must_use]
     pub fn waiting(&mut self) -> WaitingW<IrqEnbSpec> {
         WaitingW::new(self, 2)
     }
     #[doc = "Bit 3 - Controller is Stalled"]
     #[inline(always)]
+    #[must_use]
     pub fn stalled(&mut self) -> StalledW<IrqEnbSpec> {
         StalledW::new(self, 3)
     }
     #[doc = "Bit 4 - I2C Arbitration was lost"]
     #[inline(always)]
+    #[must_use]
     pub fn arblost(&mut self) -> ArblostW<IrqEnbSpec> {
         ArblostW::new(self, 4)
     }
     #[doc = "Bit 5 - I2C Address was not Acknowledged"]
     #[inline(always)]
+    #[must_use]
     pub fn nackaddr(&mut self) -> NackaddrW<IrqEnbSpec> {
         NackaddrW::new(self, 5)
     }
     #[doc = "Bit 6 - I2C Data was not Acknowledged"]
     #[inline(always)]
+    #[must_use]
     pub fn nackdata(&mut self) -> NackdataW<IrqEnbSpec> {
         NackdataW::new(self, 6)
     }
     #[doc = "Bit 7 - I2C Clock Low Timeout"]
     #[inline(always)]
+    #[must_use]
     pub fn clkloto(&mut self) -> ClklotoW<IrqEnbSpec> {
         ClklotoW::new(self, 7)
     }
     #[doc = "Bit 10 - TX FIFO Overflowed"]
     #[inline(always)]
+    #[must_use]
     pub fn txoverflow(&mut self) -> TxoverflowW<IrqEnbSpec> {
         TxoverflowW::new(self, 10)
     }
     #[doc = "Bit 11 - TX FIFO Overflowed"]
     #[inline(always)]
+    #[must_use]
     pub fn rxoverflow(&mut self) -> RxoverflowW<IrqEnbSpec> {
         RxoverflowW::new(self, 11)
     }
     #[doc = "Bit 12 - TX FIFO Ready"]
     #[inline(always)]
+    #[must_use]
     pub fn txready(&mut self) -> TxreadyW<IrqEnbSpec> {
         TxreadyW::new(self, 12)
     }
     #[doc = "Bit 13 - RX FIFO Ready"]
     #[inline(always)]
+    #[must_use]
     pub fn rxready(&mut self) -> RxreadyW<IrqEnbSpec> {
         RxreadyW::new(self, 13)
     }
     #[doc = "Bit 14 - TX FIFO Empty"]
     #[inline(always)]
+    #[must_use]
     pub fn txempty(&mut self) -> TxemptyW<IrqEnbSpec> {
         TxemptyW::new(self, 14)
     }
     #[doc = "Bit 15 - RX FIFO Full"]
     #[inline(always)]
+    #[must_use]
     pub fn rxfull(&mut self) -> RxfullW<IrqEnbSpec> {
         RxfullW::new(self, 15)
     }
 }
-#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IrqEnbSpec;
 impl crate::RegisterSpec for IrqEnbSpec {
     type Ux = u32;

va108xx/src/i2ca/perid.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PeridSpec;
 impl crate::RegisterSpec for PeridSpec {
     type Ux = u32;

va108xx/src/i2ca/rxcount.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RxcountSpec;
 impl crate::RegisterSpec for RxcountSpec {
     type Ux = u32;

va108xx/src/i2ca/rxfifoirqtrg.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct RxfifoirqtrgSpec;
 impl crate::RegisterSpec for RxfifoirqtrgSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_address.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0AddressSpec;
 impl crate::RegisterSpec for S0AddressSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_addressb.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0AddressbSpec;
 impl crate::RegisterSpec for S0AddressbSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_addressmask.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0AddressmaskSpec;
 impl crate::RegisterSpec for S0AddressmaskSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_addressmaskb.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0AddressmaskbSpec;
 impl crate::RegisterSpec for S0AddressmaskbSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_ctrl.rs

@@ -52,31 +52,36 @@ impl R {
 impl W {
     #[doc = "Bit 0 - I2C Enabled"]
     #[inline(always)]
+    #[must_use]
     pub fn clkenabled(&mut self) -> ClkenabledW<S0CtrlSpec> {
         ClkenabledW::new(self, 0)
     }
     #[doc = "Bit 1 - I2C Activated"]
     #[inline(always)]
+    #[must_use]
     pub fn enabled(&mut self) -> EnabledW<S0CtrlSpec> {
         EnabledW::new(self, 1)
     }
     #[doc = "Bit 2 - I2C Active"]
     #[inline(always)]
+    #[must_use]
     pub fn enable(&mut self) -> EnableW<S0CtrlSpec> {
         EnableW::new(self, 2)
     }
     #[doc = "Bit 3 - TX FIFIO Empty Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn txfemd(&mut self) -> TxfemdW<S0CtrlSpec> {
         TxfemdW::new(self, 3)
     }
     #[doc = "Bit 4 - RX FIFO Full Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn rxffmd(&mut self) -> RxffmdW<S0CtrlSpec> {
         RxffmdW::new(self, 4)
     }
 }
-#[doc = "Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0CtrlSpec;
 impl crate::RegisterSpec for S0CtrlSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_data.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0DataSpec;
 impl crate::RegisterSpec for S0DataSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_fifo_clr.rs

@@ -7,16 +7,18 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bit 0 - Clear Rx FIFO"]
     #[inline(always)]
+    #[must_use]
     pub fn rxfifo(&mut self) -> RxfifoW<S0FifoClrSpec> {
         RxfifoW::new(self, 0)
     }
     #[doc = "Bit 1 - Clear Tx FIFO"]
     #[inline(always)]
+    #[must_use]
     pub fn txfifo(&mut self) -> TxfifoW<S0FifoClrSpec> {
         TxfifoW::new(self, 1)
     }
 }
-#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0FifoClrSpec;
 impl crate::RegisterSpec for S0FifoClrSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_irq_enb.rs

@@ -151,86 +151,102 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
+    #[must_use]
     pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> {
         CompletedW::new(self, 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
+    #[must_use]
     pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> {
         IdleW::new(self, 1)
     }
     #[doc = "Bit 2 - Controller is Waiting"]
     #[inline(always)]
+    #[must_use]
     pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> {
         WaitingW::new(self, 2)
     }
     #[doc = "Bit 3 - Controller is Tx Stalled"]
     #[inline(always)]
+    #[must_use]
     pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> {
         TxstalledW::new(self, 3)
     }
     #[doc = "Bit 4 - Controller is Rx Stalled"]
     #[inline(always)]
+    #[must_use]
     pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> {
         RxstalledW::new(self, 4)
     }
     #[doc = "Bit 5 - I2C Address Match"]
     #[inline(always)]
+    #[must_use]
     pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> {
         AddressmatchW::new(self, 5)
     }
     #[doc = "Bit 6 - I2C Data was not Acknowledged"]
     #[inline(always)]
+    #[must_use]
     pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> {
         NackdataW::new(self, 6)
     }
     #[doc = "Bit 7 - Pending Data is first Byte following Address"]
     #[inline(always)]
+    #[must_use]
     pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> {
         RxdatafirstW::new(self, 7)
     }
     #[doc = "Bit 8 - I2C Start Condition"]
     #[inline(always)]
+    #[must_use]
     pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> {
         I2cStartW::new(self, 8)
     }
     #[doc = "Bit 9 - I2C Stop Condition"]
     #[inline(always)]
+    #[must_use]
     pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> {
         I2cStopW::new(self, 9)
     }
     #[doc = "Bit 10 - TX FIFO Underflowed"]
     #[inline(always)]
+    #[must_use]
     pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> {
         TxunderflowW::new(self, 10)
     }
     #[doc = "Bit 11 - TX FIFO Overflowed"]
     #[inline(always)]
+    #[must_use]
     pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> {
         RxoverflowW::new(self, 11)
     }
     #[doc = "Bit 12 - TX FIFO Ready"]
     #[inline(always)]
+    #[must_use]
     pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> {
         TxreadyW::new(self, 12)
     }
     #[doc = "Bit 13 - RX FIFO Ready"]
     #[inline(always)]
+    #[must_use]
     pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> {
         RxreadyW::new(self, 13)
     }
     #[doc = "Bit 14 - TX FIFO Empty"]
     #[inline(always)]
+    #[must_use]
     pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> {
         TxemptyW::new(self, 14)
     }
     #[doc = "Bit 15 - RX FIFO Full"]
     #[inline(always)]
+    #[must_use]
     pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> {
         RxfullW::new(self, 15)
     }
 }
-#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0IrqEnbSpec;
 impl crate::RegisterSpec for S0IrqEnbSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_lastaddress.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0LastaddressSpec;
 impl crate::RegisterSpec for S0LastaddressSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_maxwords.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0MaxwordsSpec;
 impl crate::RegisterSpec for S0MaxwordsSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_rxcount.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0RxcountSpec;
 impl crate::RegisterSpec for S0RxcountSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_rxfifoirqtrg.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0RxfifoirqtrgSpec;
 impl crate::RegisterSpec for S0RxfifoirqtrgSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_state.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0StateSpec;
 impl crate::RegisterSpec for S0StateSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_status.rs

@@ -121,7 +121,7 @@ impl R {
         RawSclR::new(((self.bits >> 31) & 1) != 0)
     }
 }
-#[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0StatusSpec;
 impl crate::RegisterSpec for S0StatusSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_txcount.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0TxcountSpec;
 impl crate::RegisterSpec for S0TxcountSpec {
     type Ux = u32;

va108xx/src/i2ca/s0_txfifoirqtrg.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct S0TxfifoirqtrgSpec;
 impl crate::RegisterSpec for S0TxfifoirqtrgSpec {
     type Ux = u32;

va108xx/src/i2ca/state.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct StateSpec;
 impl crate::RegisterSpec for StateSpec {
     type Ux = u32;

va108xx/src/i2ca/status.rs

@@ -107,7 +107,7 @@ impl R {
         RawSclR::new(((self.bits >> 31) & 1) != 0)
     }
 }
-#[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct StatusSpec;
 impl crate::RegisterSpec for StatusSpec {
     type Ux = u32;

va108xx/src/i2ca/tmconfig.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TmconfigSpec;
 impl crate::RegisterSpec for TmconfigSpec {
     type Ux = u32;

va108xx/src/i2ca/txcount.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TxcountSpec;
 impl crate::RegisterSpec for TxcountSpec {
     type Ux = u32;

va108xx/src/i2ca/txfifoirqtrg.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct TxfifoirqtrgSpec;
 impl crate::RegisterSpec for TxfifoirqtrgSpec {
     type Ux = u32;

va108xx/src/i2ca/words.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct WordsSpec;
 impl crate::RegisterSpec for WordsSpec {
     type Ux = u32;

va108xx/src/ioconfig.rs

@@ -35,7 +35,7 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`]
+#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`]
 module"]
 #[doc(alias = "PORTA")]
 pub type Porta = crate::Reg<porta::PortaSpec>;
@@ -43,7 +43,7 @@ pub type Porta = crate::Reg<porta::PortaSpec>;
 pub mod porta;
 pub use porta as portb;
 pub use Porta as Portb;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
 module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;

va108xx/src/ioconfig/perid.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PeridSpec;
 impl crate::RegisterSpec for PeridSpec {
     type Ux = u32;

va108xx/src/ioconfig/porta.rs

@@ -214,61 +214,72 @@ impl R {
 impl W {
     #[doc = "Bits 0:2 - Input Filter Selectoin"]
     #[inline(always)]
+    #[must_use]
     pub fn flttype(&mut self) -> FlttypeW<PortaSpec> {
         FlttypeW::new(self, 0)
     }
     #[doc = "Bits 3:5 - Input Filter Clock Selection"]
     #[inline(always)]
+    #[must_use]
     pub fn fltclk(&mut self) -> FltclkW<PortaSpec> {
         FltclkW::new(self, 3)
     }
     #[doc = "Bit 6 - Input Invert Selection"]
     #[inline(always)]
+    #[must_use]
     pub fn invinp(&mut self) -> InvinpW<PortaSpec> {
         InvinpW::new(self, 6)
     }
     #[doc = "Bit 7 - Input Enable While Output enabled"]
     #[inline(always)]
+    #[must_use]
     pub fn iewo(&mut self) -> IewoW<PortaSpec> {
         IewoW::new(self, 7)
     }
     #[doc = "Bit 8 - Output Open Drain Mode"]
     #[inline(always)]
+    #[must_use]
     pub fn opendrn(&mut self) -> OpendrnW<PortaSpec> {
         OpendrnW::new(self, 8)
     }
     #[doc = "Bit 9 - Output Invert Selection"]
     #[inline(always)]
+    #[must_use]
     pub fn invout(&mut self) -> InvoutW<PortaSpec> {
         InvoutW::new(self, 9)
     }
     #[doc = "Bit 10 - Internal Pull up/down level"]
     #[inline(always)]
+    #[must_use]
     pub fn plevel(&mut self) -> PlevelW<PortaSpec> {
         PlevelW::new(self, 10)
     }
     #[doc = "Bit 11 - Enable Internal Pull up/down"]
     #[inline(always)]
+    #[must_use]
     pub fn pen(&mut self) -> PenW<PortaSpec> {
         PenW::new(self, 11)
     }
     #[doc = "Bit 12 - Enable Pull when output active"]
     #[inline(always)]
+    #[must_use]
     pub fn pwoa(&mut self) -> PwoaW<PortaSpec> {
         PwoaW::new(self, 12)
     }
     #[doc = "Bits 13:15 - Pin Function Selection"]
     #[inline(always)]
+    #[must_use]
     pub fn funsel(&mut self) -> FunselW<PortaSpec> {
         FunselW::new(self, 13)
     }
     #[doc = "Bit 16 - IO Pin Disable"]
     #[inline(always)]
+    #[must_use]
     pub fn iodis(&mut self) -> IodisW<PortaSpec> {
         IodisW::new(self, 16)
     }
 }
-#[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PortaSpec;
 impl crate::RegisterSpec for PortaSpec {
     type Ux = u32;

va108xx/src/irqsel.rs

@@ -169,7 +169,7 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`]
+#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ram_sbe::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`]
 module"]
 #[doc(alias = "INT_RAM_SBE")]
 pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>;
@@ -197,7 +197,7 @@ pub use IntRamSbe as IntRamMbe;
 pub use IntRamSbe as IntRomSbe;
 pub use IntRamSbe as IntRomMbe;
 pub use IntRamSbe as Txev;
-#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`]
+#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmi::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`]
 module"]
 #[doc(alias = "NMI")]
 pub type Nmi = crate::Reg<nmi::NmiSpec>;
@@ -213,7 +213,7 @@ pub use Nmi as Watchdog;
 pub use Nmi as Mereset;
 pub use Nmi as Edbgrq;
 pub use Nmi as Irqs;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
 module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;

va108xx/src/irqsel/int_ram_sbe.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ram_sbe::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ram_sbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IntRamSbeSpec;
 impl crate::RegisterSpec for IntRamSbeSpec {
     type Ux = u32;

va108xx/src/irqsel/nmi.rs

@@ -9,7 +9,7 @@ impl R {
         ActiveR::new((self.bits & 1) != 0)
     }
 }
-#[doc = "NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "NMI Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmi::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct NmiSpec;
 impl crate::RegisterSpec for NmiSpec {
     type Ux = u32;

va108xx/src/irqsel/perid.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PeridSpec;
 impl crate::RegisterSpec for PeridSpec {
     type Ux = u32;

va108xx/src/lib.rs

@@ -1,5 +1,5 @@
-#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.35.0 (e10f920 2025-02-12))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
+#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
-svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.35.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![allow(non_camel_case_types)]
 #![allow(non_snake_case)]
 #![no_std]
@@ -1974,43 +1974,117 @@ impl Peripherals {
     pub unsafe fn steal() -> Self {
         DEVICE_PERIPHERALS = true;
         Peripherals {
-            sysconfig: Sysconfig::steal(),
+            sysconfig: Sysconfig {
-            irqsel: Irqsel::steal(),
+                _marker: PhantomData,
-            ioconfig: Ioconfig::steal(),
+            },
-            utility: Utility::steal(),
+            irqsel: Irqsel {
-            porta: Porta::steal(),
+                _marker: PhantomData,
-            portb: Portb::steal(),
+            },
-            tim0: Tim0::steal(),
+            ioconfig: Ioconfig {
-            tim1: Tim1::steal(),
+                _marker: PhantomData,
-            tim2: Tim2::steal(),
+            },
-            tim3: Tim3::steal(),
+            utility: Utility {
-            tim4: Tim4::steal(),
+                _marker: PhantomData,
-            tim5: Tim5::steal(),
+            },
-            tim6: Tim6::steal(),
+            porta: Porta {
-            tim7: Tim7::steal(),
+                _marker: PhantomData,
-            tim8: Tim8::steal(),
+            },
-            tim9: Tim9::steal(),
+            portb: Portb {
-            tim10: Tim10::steal(),
+                _marker: PhantomData,
-            tim11: Tim11::steal(),
+            },
-            tim12: Tim12::steal(),
+            tim0: Tim0 {
-            tim13: Tim13::steal(),
+                _marker: PhantomData,
-            tim14: Tim14::steal(),
+            },
-            tim15: Tim15::steal(),
+            tim1: Tim1 {
-            tim16: Tim16::steal(),
+                _marker: PhantomData,
-            tim17: Tim17::steal(),
+            },
-            tim18: Tim18::steal(),
+            tim2: Tim2 {
-            tim19: Tim19::steal(),
+                _marker: PhantomData,
-            tim20: Tim20::steal(),
+            },
-            tim21: Tim21::steal(),
+            tim3: Tim3 {
-            tim22: Tim22::steal(),
+                _marker: PhantomData,
-            tim23: Tim23::steal(),
+            },
-            uarta: Uarta::steal(),
+            tim4: Tim4 {
-            uartb: Uartb::steal(),
+                _marker: PhantomData,
-            spia: Spia::steal(),
+            },
-            spib: Spib::steal(),
+            tim5: Tim5 {
-            spic: Spic::steal(),
+                _marker: PhantomData,
-            i2ca: I2ca::steal(),
+            },
-            i2cb: I2cb::steal(),
+            tim6: Tim6 {
+                _marker: PhantomData,
+            },
+            tim7: Tim7 {
+                _marker: PhantomData,
+            },
+            tim8: Tim8 {
+                _marker: PhantomData,
+            },
+            tim9: Tim9 {
+                _marker: PhantomData,
+            },
+            tim10: Tim10 {
+                _marker: PhantomData,
+            },
+            tim11: Tim11 {
+                _marker: PhantomData,
+            },
+            tim12: Tim12 {
+                _marker: PhantomData,
+            },
+            tim13: Tim13 {
+                _marker: PhantomData,
+            },
+            tim14: Tim14 {
+                _marker: PhantomData,
+            },
+            tim15: Tim15 {
+                _marker: PhantomData,
+            },
+            tim16: Tim16 {
+                _marker: PhantomData,
+            },
+            tim17: Tim17 {
+                _marker: PhantomData,
+            },
+            tim18: Tim18 {
+                _marker: PhantomData,
+            },
+            tim19: Tim19 {
+                _marker: PhantomData,
+            },
+            tim20: Tim20 {
+                _marker: PhantomData,
+            },
+            tim21: Tim21 {
+                _marker: PhantomData,
+            },
+            tim22: Tim22 {
+                _marker: PhantomData,
+            },
+            tim23: Tim23 {
+                _marker: PhantomData,
+            },
+            uarta: Uarta {
+                _marker: PhantomData,
+            },
+            uartb: Uartb {
+                _marker: PhantomData,
+            },
+            spia: Spia {
+                _marker: PhantomData,
+            },
+            spib: Spib {
+                _marker: PhantomData,
+            },
+            spic: Spic {
+                _marker: PhantomData,
+            },
+            i2ca: I2ca {
+                _marker: PhantomData,
+            },
+            i2cb: I2cb {
+                _marker: PhantomData,
+            },
         }
     }
 }

va108xx/src/porta.rs

@@ -1,3 +1,6 @@
+// Manually inserted.
+#![allow(clippy::identity_op)]
+
 #[repr(C)]
 #[doc = "Register block"]
 pub struct RegisterBlock {
@@ -30,246 +33,247 @@ impl RegisterBlock {
     pub const fn datainbyte(&self, n: usize) -> &Datainbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(0).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x00 - Data In Register by Byte"]
     #[inline(always)]
     pub fn datainbyte_iter(&self) -> impl Iterator<Item = &Datainbyte> {
-        (0..4).map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(n).cast() })
+        (0..4)
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(0).add(1 * n).cast() })
     }
     #[doc = "0x00 - Data In Register"]
     #[inline(always)]
     pub const fn datain(&self) -> &Datain {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(0).cast() }
     }
     #[doc = "0x04 - Data In Raw Register by Byte"]
     #[inline(always)]
     pub const fn datainrawbyte0(&self, n: usize) -> &Datainrawbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(4).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x04 - Data In Raw Register by Byte"]
     #[inline(always)]
     pub fn datainrawbyte0_iter(&self) -> impl Iterator<Item = &Datainrawbyte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(4).add(1 * n).cast() })
     }
     #[doc = "0x04 - Data In Raw Register"]
     #[inline(always)]
     pub const fn datainraw(&self) -> &Datainraw {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(4).cast() }
     }
     #[doc = "0x08 - Data Out Register by Byte"]
     #[inline(always)]
     pub const fn dataoutbyte(&self, n: usize) -> &Dataoutbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(8).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x08 - Data Out Register by Byte"]
     #[inline(always)]
     pub fn dataoutbyte_iter(&self) -> impl Iterator<Item = &Dataoutbyte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(8).add(1 * n).cast() })
     }
     #[doc = "0x08 - Data Out Register"]
     #[inline(always)]
     pub const fn dataout(&self) -> &Dataout {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(8).cast() }
     }
     #[doc = "0x0c - Data Out Register by Byte"]
     #[inline(always)]
     pub const fn dataoutrawbyte0(&self, n: usize) -> &Dataoutrawbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(12).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x0c - Data Out Register by Byte"]
     #[inline(always)]
     pub fn dataoutrawbyte0_iter(&self) -> impl Iterator<Item = &Dataoutrawbyte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(12).add(1 * n).cast() })
     }
     #[doc = "0x0c - Data Out Register"]
     #[inline(always)]
     pub const fn dataoutraw(&self) -> &Dataoutraw {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(12).cast() }
     }
     #[doc = "0x10 - Set Out Register by Byte"]
     #[inline(always)]
     pub const fn setoutbyte0(&self, n: usize) -> &Setoutbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(16).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x10 - Set Out Register by Byte"]
     #[inline(always)]
     pub fn setoutbyte0_iter(&self) -> impl Iterator<Item = &Setoutbyte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(16).add(1 * n).cast() })
     }
     #[doc = "0x10 - Set Out Register"]
     #[inline(always)]
     pub const fn setout(&self) -> &Setout {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(16).cast() }
     }
     #[doc = "0x14 - Clear Out Register by Byte"]
     #[inline(always)]
     pub const fn clroutbyte0(&self, n: usize) -> &Clroutbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(20).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x14 - Clear Out Register by Byte"]
     #[inline(always)]
     pub fn clroutbyte0_iter(&self) -> impl Iterator<Item = &Clroutbyte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(20).add(1 * n).cast() })
     }
     #[doc = "0x14 - Clear Out Register"]
     #[inline(always)]
     pub const fn clrout(&self) -> &Clrout {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(20).cast() }
     }
     #[doc = "0x18 - Toggle Out Register by Byte"]
     #[inline(always)]
     pub const fn togoutbyte0(&self, n: usize) -> &Togoutbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(24).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x18 - Toggle Out Register by Byte"]
     #[inline(always)]
     pub fn togoutbyte0_iter(&self) -> impl Iterator<Item = &Togoutbyte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(24).add(1 * n).cast() })
     }
     #[doc = "0x18 - Toggle Out Register"]
     #[inline(always)]
     pub const fn togout(&self) -> &Togout {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(24).cast() }
     }
     #[doc = "0x1c - Data Out Register by Byte"]
     #[inline(always)]
     pub const fn datamaskbyte(&self, n: usize) -> &Datamaskbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(28).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x1c - Data Out Register by Byte"]
     #[inline(always)]
     pub fn datamaskbyte_iter(&self) -> impl Iterator<Item = &Datamaskbyte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(28).add(1 * n).cast() })
     }
     #[doc = "0x1c - Data mask Register"]
     #[inline(always)]
     pub const fn datamask(&self) -> &Datamask {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(28).cast() }
     }
     #[doc = "0x20 - Direction Register by Byte"]
     #[inline(always)]
     pub const fn dirbyte0(&self, n: usize) -> &Dirbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(32).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x20 - Direction Register by Byte"]
     #[inline(always)]
     pub fn dirbyte0_iter(&self) -> impl Iterator<Item = &Dirbyte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(32).add(1 * n).cast() })
     }
     #[doc = "0x20 - Direction Register (1:Output, 0:Input)"]
     #[inline(always)]
     pub const fn dir(&self) -> &Dir {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() }
     }
     #[doc = "0x24 - Pulse Mode Register by Byte"]
     #[inline(always)]
     pub const fn pulsebyte0(&self, n: usize) -> &Pulsebyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(36).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x24 - Pulse Mode Register by Byte"]
     #[inline(always)]
     pub fn pulsebyte0_iter(&self) -> impl Iterator<Item = &Pulsebyte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(36).add(1 * n).cast() })
     }
     #[doc = "0x24 - Pulse Mode Register"]
     #[inline(always)]
     pub const fn pulse(&self) -> &Pulse {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(36).cast() }
     }
     #[doc = "0x28 - Pulse Base Mode Register by Byte"]
     #[inline(always)]
     pub const fn pulsebasebyte0(&self, n: usize) -> &Pulsebasebyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(40).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x28 - Pulse Base Mode Register by Byte"]
     #[inline(always)]
     pub fn pulsebasebyte0_iter(&self) -> impl Iterator<Item = &Pulsebasebyte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(40).add(1 * n).cast() })
     }
     #[doc = "0x28 - Pulse Base Value Register"]
     #[inline(always)]
     pub const fn pulsebase(&self) -> &Pulsebase {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(40).cast() }
     }
     #[doc = "0x2c - Delay1 Register by Byte"]
     #[inline(always)]
     pub const fn delay1byte0(&self, n: usize) -> &Delay1byte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(44).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x2c - Delay1 Register by Byte"]
     #[inline(always)]
     pub fn delay1byte0_iter(&self) -> impl Iterator<Item = &Delay1byte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(44).add(1 * n).cast() })
     }
     #[doc = "0x2c - Delay1 Register"]
     #[inline(always)]
     pub const fn delay1(&self) -> &Delay1 {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(44).cast() }
     }
     #[doc = "0x30 - Delay2 Register by Byte"]
     #[inline(always)]
     pub const fn delay2byte0(&self, n: usize) -> &Delay2byte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(48).add(1 * n).cast() }
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x30 - Delay2 Register by Byte"]
     #[inline(always)]
     pub fn delay2byte0_iter(&self) -> impl Iterator<Item = &Delay2byte> {
         (0..4)
-            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() })
+            .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(48).add(1 * n).cast() })
     }
     #[doc = "0x30 - Delay2 Register"]
     #[inline(always)]
     pub const fn delay2(&self) -> &Delay2 {
-        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).cast() }
+        unsafe { &*(self as *const Self).cast::<u8>().add(48).cast() }
     }
     #[doc = "0x34 - Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
     #[inline(always)]
@@ -312,13 +316,13 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`]
+#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`]
 module"]
 #[doc(alias = "DATAIN")]
 pub type Datain = crate::Reg<datain::DatainSpec>;
 #[doc = "Data In Register"]
 pub mod datain;
-#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`]
+#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`]
 module"]
 #[doc(alias = "DATAINBYTE")]
 pub type Datainbyte = crate::Reg<datainbyte::DatainbyteSpec>;
@@ -328,13 +332,13 @@ pub use datain as datainraw;
 pub use datainbyte as datainrawbyte;
 pub use Datain as Datainraw;
 pub use Datainbyte as Datainrawbyte;
-#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`]
+#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`]
 module"]
 #[doc(alias = "DATAOUT")]
 pub type Dataout = crate::Reg<dataout::DataoutSpec>;
 #[doc = "Data Out Register"]
 pub mod dataout;
-#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`]
+#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`]
 module"]
 #[doc(alias = "DATAOUTBYTE")]
 pub type Dataoutbyte = crate::Reg<dataoutbyte::DataoutbyteSpec>;
@@ -356,13 +360,13 @@ pub use Dataoutbyte as Dataoutrawbyte;
 pub use Dataoutbyte as Setoutbyte;
 pub use Dataoutbyte as Clroutbyte;
 pub use Dataoutbyte as Togoutbyte;
-#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`]
+#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`]
 module"]
 #[doc(alias = "DATAMASK")]
 pub type Datamask = crate::Reg<datamask::DatamaskSpec>;
 #[doc = "Data mask Register"]
 pub mod datamask;
-#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`]
+#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`]
 module"]
 #[doc(alias = "DATAMASKBYTE")]
 pub type Datamaskbyte = crate::Reg<datamaskbyte::DatamaskbyteSpec>;
@@ -388,49 +392,49 @@ pub use Datamaskbyte as Pulsebyte;
 pub use Datamaskbyte as Pulsebasebyte;
 pub use Datamaskbyte as Delay1byte;
 pub use Datamaskbyte as Delay2byte;
-#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`]
+#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`]
 module"]
 #[doc(alias = "IRQ_SEN")]
 pub type IrqSen = crate::Reg<irq_sen::IrqSenSpec>;
 #[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
 pub mod irq_sen;
-#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`]
+#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`]
 module"]
 #[doc(alias = "IRQ_EDGE")]
 pub type IrqEdge = crate::Reg<irq_edge::IrqEdgeSpec>;
 #[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"]
 pub mod irq_edge;
-#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`]
+#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`]
 module"]
 #[doc(alias = "IRQ_EVT")]
 pub type IrqEvt = crate::Reg<irq_evt::IrqEvtSpec>;
 #[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"]
 pub mod irq_evt;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
 module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
 #[doc = "Interrupt Enable Register"]
 pub mod irq_enb;
-#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
+#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
 module"]
 #[doc(alias = "IRQ_RAW")]
 pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>;
 #[doc = "Raw Interrupt Status"]
 pub mod irq_raw;
-#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
+#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
 module"]
 #[doc(alias = "IRQ_END")]
 pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>;
 #[doc = "Masked Interrupt Status"]
 pub mod irq_end;
-#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`]
+#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`]
 module"]
 #[doc(alias = "EDGE_STATUS")]
 pub type EdgeStatus = crate::Reg<edge_status::EdgeStatusSpec>;
 #[doc = "Edge Status Register"]
 pub mod edge_status;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
 module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;

va108xx/src/porta/datain.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DatainSpec;
 impl crate::RegisterSpec for DatainSpec {
     type Ux = u32;

va108xx/src/porta/datainbyte.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DatainbyteSpec;
 impl crate::RegisterSpec for DatainbyteSpec {
     type Ux = u8;

va108xx/src/porta/datamask.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DatamaskSpec;
 impl crate::RegisterSpec for DatamaskSpec {
     type Ux = u32;

va108xx/src/porta/datamaskbyte.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DatamaskbyteSpec;
 impl crate::RegisterSpec for DatamaskbyteSpec {
     type Ux = u8;

va108xx/src/porta/dataout.rs

@@ -6,7 +6,7 @@ impl core::fmt::Debug for crate::generic::Reg<DataoutSpec> {
     }
 }
 impl W {}
-#[doc = "Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DataoutSpec;
 impl crate::RegisterSpec for DataoutSpec {
     type Ux = u32;

va108xx/src/porta/dataoutbyte.rs

@@ -6,7 +6,7 @@ impl core::fmt::Debug for crate::generic::Reg<DataoutbyteSpec> {
     }
 }
 impl W {}
-#[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DataoutbyteSpec;
 impl crate::RegisterSpec for DataoutbyteSpec {
     type Ux = u8;

va108xx/src/porta/edge_status.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct EdgeStatusSpec;
 impl crate::RegisterSpec for EdgeStatusSpec {
     type Ux = u32;

va108xx/src/porta/irq_edge.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IrqEdgeSpec;
 impl crate::RegisterSpec for IrqEdgeSpec {
     type Ux = u32;

va108xx/src/porta/irq_enb.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IrqEnbSpec;
 impl crate::RegisterSpec for IrqEnbSpec {
     type Ux = u32;

va108xx/src/porta/irq_end.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IrqEndSpec;
 impl crate::RegisterSpec for IrqEndSpec {
     type Ux = u32;

va108xx/src/porta/irq_evt.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IrqEvtSpec;
 impl crate::RegisterSpec for IrqEvtSpec {
     type Ux = u32;

va108xx/src/porta/irq_raw.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IrqRawSpec;
 impl crate::RegisterSpec for IrqRawSpec {
     type Ux = u32;

va108xx/src/porta/irq_sen.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct IrqSenSpec;
 impl crate::RegisterSpec for IrqSenSpec {
     type Ux = u32;

va108xx/src/porta/perid.rs

@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
         write!(f, "{}", self.bits())
     }
 }
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct PeridSpec;
 impl crate::RegisterSpec for PeridSpec {
     type Ux = u32;

va108xx/src/spia.rs

@@ -89,37 +89,37 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
+#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
 module"]
 #[doc(alias = "CTRL0")]
 pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>;
 #[doc = "Control Register 0"]
 pub mod ctrl0;
-#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
+#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
 module"]
 #[doc(alias = "CTRL1")]
 pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>;
 #[doc = "Control Register 1"]
 pub mod ctrl1;
-#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
 module"]
 #[doc(alias = "DATA")]
 pub type Data = crate::Reg<data::DataSpec>;
 #[doc = "Data Input/Output"]
 pub mod data;
-#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
+#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
 module"]
 #[doc(alias = "STATUS")]
 pub type Status = crate::Reg<status::StatusSpec>;
 #[doc = "Status Register"]
 pub mod status;
-#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`]
+#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`]
 module"]
 #[doc(alias = "CLKPRESCALE")]
 pub type Clkprescale = crate::Reg<clkprescale::ClkprescaleSpec>;
 #[doc = "Clock Pre Scale divide value"]
 pub mod clkprescale;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
 module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
@@ -131,31 +131,31 @@ pub use irq_enb as irq_clr;
 pub use IrqEnb as IrqRaw;
 pub use IrqEnb as IrqEnd;
 pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
 module"]
 #[doc(alias = "RXFIFOIRQTRG")]
 pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
 #[doc = "Rx FIFO IRQ Trigger Level"]
 pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
 module"]
 #[doc(alias = "TXFIFOIRQTRG")]
 pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
 #[doc = "Tx FIFO IRQ Trigger Level"]
 pub mod txfifoirqtrg;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
 module"]
 #[doc(alias = "FIFO_CLR")]
 pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
 #[doc = "Clear FIFO Register"]
 pub mod fifo_clr;
-#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
 module"]
 #[doc(alias = "STATE")]
 pub type State = crate::Reg<state::StateSpec>;
 #[doc = "Internal STATE of SPI Controller"]
 pub mod state;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
 module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;

va108xx/src/spia/clkprescale.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct ClkprescaleSpec;
 impl crate::RegisterSpec for ClkprescaleSpec {
     type Ux = u32;

va108xx/src/spia/ctrl0.rs

@@ -43,26 +43,30 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
     #[inline(always)]
+    #[must_use]
     pub fn size(&mut self) -> SizeW<Ctrl0Spec> {
         SizeW::new(self, 0)
     }
     #[doc = "Bit 6 - SPI Clock Polarity"]
     #[inline(always)]
+    #[must_use]
     pub fn spo(&mut self) -> SpoW<Ctrl0Spec> {
         SpoW::new(self, 6)
     }
     #[doc = "Bit 7 - SPI Clock Phase"]
     #[inline(always)]
+    #[must_use]
     pub fn sph(&mut self) -> SphW<Ctrl0Spec> {
         SphW::new(self, 7)
     }
     #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
     #[inline(always)]
+    #[must_use]
     pub fn scrdv(&mut self) -> ScrdvW<Ctrl0Spec> {
         ScrdvW::new(self, 8)
     }
 }
-#[doc = "Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Ctrl0Spec;
 impl crate::RegisterSpec for Ctrl0Spec {
     type Ux = u32;

va108xx/src/spia/ctrl1.rs

@@ -97,56 +97,66 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Loop Back"]
     #[inline(always)]
+    #[must_use]
     pub fn lbm(&mut self) -> LbmW<Ctrl1Spec> {
         LbmW::new(self, 0)
     }
     #[doc = "Bit 1 - Enable"]
     #[inline(always)]
+    #[must_use]
     pub fn enable(&mut self) -> EnableW<Ctrl1Spec> {
         EnableW::new(self, 1)
     }
     #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"]
     #[inline(always)]
+    #[must_use]
     pub fn ms(&mut self) -> MsW<Ctrl1Spec> {
         MsW::new(self, 2)
     }
     #[doc = "Bit 3 - Slave output Disable"]
     #[inline(always)]
+    #[must_use]
     pub fn sod(&mut self) -> SodW<Ctrl1Spec> {
         SodW::new(self, 3)
     }
     #[doc = "Bits 4:6 - Slave Select"]
     #[inline(always)]
+    #[must_use]
     pub fn ss(&mut self) -> SsW<Ctrl1Spec> {
         SsW::new(self, 4)
     }
     #[doc = "Bit 7 - Block Mode Enable"]
     #[inline(always)]
+    #[must_use]
     pub fn blockmode(&mut self) -> BlockmodeW<Ctrl1Spec> {
         BlockmodeW::new(self, 7)
     }
     #[doc = "Bit 8 - Block Mode Start Status Enable"]
     #[inline(always)]
+    #[must_use]
     pub fn bmstart(&mut self) -> BmstartW<Ctrl1Spec> {
         BmstartW::new(self, 8)
     }
     #[doc = "Bit 9 - Block Mode Stall Enable"]
     #[inline(always)]
+    #[must_use]
     pub fn bmstall(&mut self) -> BmstallW<Ctrl1Spec> {
         BmstallW::new(self, 9)
     }
     #[doc = "Bit 10 - Master Delayed Capture Enable"]
     #[inline(always)]
+    #[must_use]
     pub fn mdlycap(&mut self) -> MdlycapW<Ctrl1Spec> {
         MdlycapW::new(self, 10)
     }
     #[doc = "Bit 11 - Master Tx Pause Enable"]
     #[inline(always)]
+    #[must_use]
     pub fn mtxpause(&mut self) -> MtxpauseW<Ctrl1Spec> {
         MtxpauseW::new(self, 11)
     }
 }
-#[doc = "Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct Ctrl1Spec;
 impl crate::RegisterSpec for Ctrl1Spec {
     type Ux = u32;

va108xx/src/spia/data.rs

@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
     }
 }
 impl W {}
-#[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DataSpec;
 impl crate::RegisterSpec for DataSpec {
     type Ux = u32;

va108xx/src/spia/fifo_clr.rs

@@ -7,16 +7,18 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bit 0 - Clear Rx FIFO"]
     #[inline(always)]
+    #[must_use]
     pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
         RxfifoW::new(self, 0)
     }
     #[doc = "Bit 1 - Clear Tx FIFO"]
     #[inline(always)]
+    #[must_use]
     pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
         TxfifoW::new(self, 1)
     }
 }
-#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct FifoClrSpec;
 impl crate::RegisterSpec for FifoClrSpec {
     type Ux = u32;