diff --git a/va108xx/CHANGELOG.md b/va108xx/CHANGELOG.md
index 663566a..5ddd82e 100644
--- a/va108xx/CHANGELOG.md
+++ b/va108xx/CHANGELOG.md
@@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased]
+## [v0.4.0] 2025-02-12
+
+- Re-generated PAC with `svd2rust` v0.35.0
+
## [v0.3.0] 2024-06-16
- Re-generated PAC with `svd2rust` v0.33.3
diff --git a/va108xx/Cargo.toml b/va108xx/Cargo.toml
index 7e434c1..ff8ee8b 100644
--- a/va108xx/Cargo.toml
+++ b/va108xx/Cargo.toml
@@ -1,6 +1,6 @@
[package]
name = "va108xx"
-version = "0.3.0"
+version = "0.4.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "PAC for the Vorago VA108xx family of microcontrollers"
diff --git a/va108xx/README.md b/va108xx/README.md
index 7830d6a..90910f0 100644
--- a/va108xx/README.md
+++ b/va108xx/README.md
@@ -24,7 +24,7 @@ features = ["rt"]
The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`.
For full details on the autgenerated API, please see the
-[svd2rust documentation](https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api).
+[svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/#peripheral-api).
## Regenerating the PAC
diff --git a/va108xx/gen-helper.sh b/va108xx/gen-helper.sh
index ed8cfb9..051dc2a 100755
--- a/va108xx/gen-helper.sh
+++ b/va108xx/gen-helper.sh
@@ -1,4 +1,4 @@
-#!/bin/sh
+#!/bin/bash
# Use installed tool by default
svd2rust_bin="svd2rust"
diff --git a/va108xx/src/generic.rs b/va108xx/src/generic.rs
index 45ebed1..59eec56 100644
--- a/va108xx/src/generic.rs
+++ b/va108xx/src/generic.rs
@@ -82,169 +82,6 @@ pub trait Resettable: RegisterSpec {
Self::RESET_VALUE
}
}
-#[doc = " This structure provides volatile access to registers."]
-#[repr(transparent)]
-pub struct Reg<REG: RegisterSpec> {
- register: vcell::VolatileCell<REG::Ux>,
- _marker: marker::PhantomData<REG>,
-}
-unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
-impl<REG: RegisterSpec> Reg<REG> {
- #[doc = " Returns the underlying memory address of register."]
- #[doc = ""]
- #[doc = " ```ignore"]
- #[doc = " let reg_ptr = periph.reg.as_ptr();"]
- #[doc = " ```"]
- #[inline(always)]
- pub fn as_ptr(&self) -> *mut REG::Ux {
- self.register.as_ptr()
- }
-}
-impl<REG: Readable> Reg<REG> {
- #[doc = " Reads the contents of a `Readable` register."]
- #[doc = ""]
- #[doc = " You can read the raw contents of a register by using `bits`:"]
- #[doc = " ```ignore"]
- #[doc = " let bits = periph.reg.read().bits();"]
- #[doc = " ```"]
- #[doc = " or get the content of a particular field of a register:"]
- #[doc = " ```ignore"]
- #[doc = " let reader = periph.reg.read();"]
- #[doc = " let bits = reader.field1().bits();"]
- #[doc = " let flag = reader.field2().bit_is_set();"]
- #[doc = " ```"]
- #[inline(always)]
- pub fn read(&self) -> R<REG> {
- R {
- bits: self.register.get(),
- _reg: marker::PhantomData,
- }
- }
-}
-impl<REG: Resettable + Writable> Reg<REG> {
- #[doc = " Writes the reset value to `Writable` register."]
- #[doc = ""]
- #[doc = " Resets the register to its initial state."]
- #[inline(always)]
- pub fn reset(&self) {
- self.register.set(REG::RESET_VALUE)
- }
- #[doc = " Writes bits to a `Writable` register."]
- #[doc = ""]
- #[doc = " You can write raw bits into a register:"]
- #[doc = " ```ignore"]
- #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
- #[doc = " ```"]
- #[doc = " or write only the fields you need:"]
- #[doc = " ```ignore"]
- #[doc = " periph.reg.write(|w| w"]
- #[doc = " .field1().bits(newfield1bits)"]
- #[doc = " .field2().set_bit()"]
- #[doc = " .field3().variant(VARIANT)"]
- #[doc = " );"]
- #[doc = " ```"]
- #[doc = " or an alternative way of saying the same:"]
- #[doc = " ```ignore"]
- #[doc = " periph.reg.write(|w| {"]
- #[doc = " w.field1().bits(newfield1bits);"]
- #[doc = " w.field2().set_bit();"]
- #[doc = " w.field3().variant(VARIANT)"]
- #[doc = " });"]
- #[doc = " ```"]
- #[doc = " In the latter case, other fields will be set to their reset value."]
- #[inline(always)]
- pub fn write<F>(&self, f: F)
- where
- F: FnOnce(&mut W<REG>) -> &mut W<REG>,
- {
- self.register.set(
- f(&mut W {
- bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
- | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
- _reg: marker::PhantomData,
- })
- .bits,
- );
- }
-}
-impl<REG: Writable> Reg<REG> {
- #[doc = " Writes 0 to a `Writable` register."]
- #[doc = ""]
- #[doc = " Similar to `write`, but unused bits will contain 0."]
- #[doc = ""]
- #[doc = " # Safety"]
- #[doc = ""]
- #[doc = " Unsafe to use with registers which don't allow to write 0."]
- #[inline(always)]
- pub unsafe fn write_with_zero<F>(&self, f: F)
- where
- F: FnOnce(&mut W<REG>) -> &mut W<REG>,
- {
- self.register.set(
- f(&mut W {
- bits: REG::Ux::default(),
- _reg: marker::PhantomData,
- })
- .bits,
- );
- }
-}
-impl<REG: Readable + Writable> Reg<REG> {
- #[doc = " Modifies the contents of the register by reading and then writing it."]
- #[doc = ""]
- #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
- #[doc = " ```ignore"]
- #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
- #[doc = " r.bits() | 3"]
- #[doc = " ) });"]
- #[doc = " ```"]
- #[doc = " or"]
- #[doc = " ```ignore"]
- #[doc = " periph.reg.modify(|_, w| w"]
- #[doc = " .field1().bits(newfield1bits)"]
- #[doc = " .field2().set_bit()"]
- #[doc = " .field3().variant(VARIANT)"]
- #[doc = " );"]
- #[doc = " ```"]
- #[doc = " or an alternative way of saying the same:"]
- #[doc = " ```ignore"]
- #[doc = " periph.reg.modify(|_, w| {"]
- #[doc = " w.field1().bits(newfield1bits);"]
- #[doc = " w.field2().set_bit();"]
- #[doc = " w.field3().variant(VARIANT)"]
- #[doc = " });"]
- #[doc = " ```"]
- #[doc = " Other fields will have the value they had before the call to `modify`."]
- #[inline(always)]
- pub fn modify<F>(&self, f: F)
- where
- for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
- {
- let bits = self.register.get();
- self.register.set(
- f(
- &R {
- bits,
- _reg: marker::PhantomData,
- },
- &mut W {
- bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
- | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
- _reg: marker::PhantomData,
- },
- )
- .bits,
- );
- }
-}
-impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
-where
- R<REG>: core::fmt::Debug,
-{
- fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
- core::fmt::Debug::fmt(&self.read(), f)
- }
-}
#[doc(hidden)]
pub mod raw;
#[doc = " Register reader."]
@@ -369,7 +206,7 @@ pub struct RangeTo<const MAX: u64>;
#[doc = " Write field Proxy"]
pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
raw::FieldWriter<'a, REG, WI, FI, Safety>;
-impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
+impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
where
REG: Writable + RegisterSpec,
FI: FieldSpec,
@@ -616,3 +453,278 @@ where
self.w
}
}
+#[doc = " This structure provides volatile access to registers."]
+#[repr(transparent)]
+pub struct Reg<REG: RegisterSpec> {
+ register: vcell::VolatileCell<REG::Ux>,
+ _marker: marker::PhantomData<REG>,
+}
+unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
+impl<REG: RegisterSpec> Reg<REG> {
+ #[doc = " Returns the underlying memory address of register."]
+ #[doc = ""]
+ #[doc = " ```ignore"]
+ #[doc = " let reg_ptr = periph.reg.as_ptr();"]
+ #[doc = " ```"]
+ #[inline(always)]
+ pub fn as_ptr(&self) -> *mut REG::Ux {
+ self.register.as_ptr()
+ }
+}
+impl<REG: Readable> Reg<REG> {
+ #[doc = " Reads the contents of a `Readable` register."]
+ #[doc = ""]
+ #[doc = " You can read the raw contents of a register by using `bits`:"]
+ #[doc = " ```ignore"]
+ #[doc = " let bits = periph.reg.read().bits();"]
+ #[doc = " ```"]
+ #[doc = " or get the content of a particular field of a register:"]
+ #[doc = " ```ignore"]
+ #[doc = " let reader = periph.reg.read();"]
+ #[doc = " let bits = reader.field1().bits();"]
+ #[doc = " let flag = reader.field2().bit_is_set();"]
+ #[doc = " ```"]
+ #[inline(always)]
+ pub fn read(&self) -> R<REG> {
+ R {
+ bits: self.register.get(),
+ _reg: marker::PhantomData,
+ }
+ }
+}
+impl<REG: Resettable + Writable> Reg<REG> {
+ #[doc = " Writes the reset value to `Writable` register."]
+ #[doc = ""]
+ #[doc = " Resets the register to its initial state."]
+ #[inline(always)]
+ pub fn reset(&self) {
+ self.register.set(REG::RESET_VALUE)
+ }
+ #[doc = " Writes bits to a `Writable` register."]
+ #[doc = ""]
+ #[doc = " You can write raw bits into a register:"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
+ #[doc = " ```"]
+ #[doc = " or write only the fields you need:"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.write(|w| w"]
+ #[doc = " .field1().bits(newfield1bits)"]
+ #[doc = " .field2().set_bit()"]
+ #[doc = " .field3().variant(VARIANT)"]
+ #[doc = " );"]
+ #[doc = " ```"]
+ #[doc = " or an alternative way of saying the same:"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.write(|w| {"]
+ #[doc = " w.field1().bits(newfield1bits);"]
+ #[doc = " w.field2().set_bit();"]
+ #[doc = " w.field3().variant(VARIANT)"]
+ #[doc = " });"]
+ #[doc = " ```"]
+ #[doc = " In the latter case, other fields will be set to their reset value."]
+ #[inline(always)]
+ pub fn write<F>(&self, f: F) -> REG::Ux
+ where
+ F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+ {
+ let value = f(&mut W {
+ bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+ | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+ _reg: marker::PhantomData,
+ })
+ .bits;
+ self.register.set(value);
+ value
+ }
+ #[doc = " Writes bits to a `Writable` register and produce a value."]
+ #[doc = ""]
+ #[doc = " You can write raw bits into a register:"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
+ #[doc = " ```"]
+ #[doc = " or write only the fields you need:"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.write_and(|w| {"]
+ #[doc = " w.field1().bits(newfield1bits)"]
+ #[doc = " .field2().set_bit()"]
+ #[doc = " .field3().variant(VARIANT);"]
+ #[doc = " });"]
+ #[doc = " ```"]
+ #[doc = " or an alternative way of saying the same:"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.write_and(|w| {"]
+ #[doc = " w.field1().bits(newfield1bits);"]
+ #[doc = " w.field2().set_bit();"]
+ #[doc = " w.field3().variant(VARIANT);"]
+ #[doc = " });"]
+ #[doc = " ```"]
+ #[doc = " In the latter case, other fields will be set to their reset value."]
+ #[doc = ""]
+ #[doc = " Values can be returned from the closure:"]
+ #[doc = " ```ignore"]
+ #[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
+ #[doc = " ```"]
+ #[inline(always)]
+ pub fn from_write<F, T>(&self, f: F) -> T
+ where
+ F: FnOnce(&mut W<REG>) -> T,
+ {
+ let mut writer = W {
+ bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
+ | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+ _reg: marker::PhantomData,
+ };
+ let result = f(&mut writer);
+ self.register.set(writer.bits);
+ result
+ }
+}
+impl<REG: Writable> Reg<REG> {
+ #[doc = " Writes 0 to a `Writable` register."]
+ #[doc = ""]
+ #[doc = " Similar to `write`, but unused bits will contain 0."]
+ #[doc = ""]
+ #[doc = " # Safety"]
+ #[doc = ""]
+ #[doc = " Unsafe to use with registers which don't allow to write 0."]
+ #[inline(always)]
+ pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
+ where
+ F: FnOnce(&mut W<REG>) -> &mut W<REG>,
+ {
+ let value = f(&mut W {
+ bits: REG::Ux::default(),
+ _reg: marker::PhantomData,
+ })
+ .bits;
+ self.register.set(value);
+ value
+ }
+ #[doc = " Writes 0 to a `Writable` register and produces a value."]
+ #[doc = ""]
+ #[doc = " Similar to `write`, but unused bits will contain 0."]
+ #[doc = ""]
+ #[doc = " # Safety"]
+ #[doc = ""]
+ #[doc = " Unsafe to use with registers which don't allow to write 0."]
+ #[inline(always)]
+ pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
+ where
+ F: FnOnce(&mut W<REG>) -> T,
+ {
+ let mut writer = W {
+ bits: REG::Ux::default(),
+ _reg: marker::PhantomData,
+ };
+ let result = f(&mut writer);
+ self.register.set(writer.bits);
+ result
+ }
+}
+impl<REG: Readable + Writable> Reg<REG> {
+ #[doc = " Modifies the contents of the register by reading and then writing it."]
+ #[doc = ""]
+ #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
+ #[doc = " r.bits() | 3"]
+ #[doc = " ) });"]
+ #[doc = " ```"]
+ #[doc = " or"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.modify(|_, w| w"]
+ #[doc = " .field1().bits(newfield1bits)"]
+ #[doc = " .field2().set_bit()"]
+ #[doc = " .field3().variant(VARIANT)"]
+ #[doc = " );"]
+ #[doc = " ```"]
+ #[doc = " or an alternative way of saying the same:"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.modify(|_, w| {"]
+ #[doc = " w.field1().bits(newfield1bits);"]
+ #[doc = " w.field2().set_bit();"]
+ #[doc = " w.field3().variant(VARIANT)"]
+ #[doc = " });"]
+ #[doc = " ```"]
+ #[doc = " Other fields will have the value they had before the call to `modify`."]
+ #[inline(always)]
+ pub fn modify<F>(&self, f: F) -> REG::Ux
+ where
+ for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
+ {
+ let bits = self.register.get();
+ let value = f(
+ &R {
+ bits,
+ _reg: marker::PhantomData,
+ },
+ &mut W {
+ bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+ _reg: marker::PhantomData,
+ },
+ )
+ .bits;
+ self.register.set(value);
+ value
+ }
+ #[doc = " Modifies the contents of the register by reading and then writing it"]
+ #[doc = " and produces a value."]
+ #[doc = ""]
+ #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
+ #[doc = " ```ignore"]
+ #[doc = " let bits = periph.reg.modify(|r, w| {"]
+ #[doc = " let new_bits = r.bits() | 3;"]
+ #[doc = " unsafe {"]
+ #[doc = " w.bits(new_bits);"]
+ #[doc = " }"]
+ #[doc = ""]
+ #[doc = " new_bits"]
+ #[doc = " });"]
+ #[doc = " ```"]
+ #[doc = " or"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.modify(|_, w| {"]
+ #[doc = " w.field1().bits(newfield1bits)"]
+ #[doc = " .field2().set_bit()"]
+ #[doc = " .field3().variant(VARIANT);"]
+ #[doc = " });"]
+ #[doc = " ```"]
+ #[doc = " or an alternative way of saying the same:"]
+ #[doc = " ```ignore"]
+ #[doc = " periph.reg.modify(|_, w| {"]
+ #[doc = " w.field1().bits(newfield1bits);"]
+ #[doc = " w.field2().set_bit();"]
+ #[doc = " w.field3().variant(VARIANT);"]
+ #[doc = " });"]
+ #[doc = " ```"]
+ #[doc = " Other fields will have the value they had before the call to `modify`."]
+ #[inline(always)]
+ pub fn from_modify<F, T>(&self, f: F) -> T
+ where
+ for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
+ {
+ let bits = self.register.get();
+ let mut writer = W {
+ bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
+ _reg: marker::PhantomData,
+ };
+ let result = f(
+ &R {
+ bits,
+ _reg: marker::PhantomData,
+ },
+ &mut writer,
+ );
+ self.register.set(writer.bits);
+ result
+ }
+}
+impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
+where
+ R<REG>: core::fmt::Debug,
+{
+ fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+ core::fmt::Debug::fmt(&self.read(), f)
+ }
+}
diff --git a/va108xx/src/generic/raw.rs b/va108xx/src/generic/raw.rs
index 81f5779..d60a23a 100644
--- a/va108xx/src/generic/raw.rs
+++ b/va108xx/src/generic/raw.rs
@@ -41,6 +41,7 @@ impl<FI> BitReader<FI> {
}
}
}
+#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
where
REG: Writable + RegisterSpec,
@@ -66,6 +67,7 @@ where
}
}
}
+#[must_use = "after creating `BitWriter` you need to call bit setting method"]
pub struct BitWriter<'a, REG, FI = bool, M = BitM>
where
REG: Writable + RegisterSpec,
diff --git a/va108xx/src/i2ca.rs b/va108xx/src/i2ca.rs
index 7c03e50..7a4be1a 100644
--- a/va108xx/src/i2ca.rs
+++ b/va108xx/src/i2ca.rs
@@ -240,67 +240,67 @@ impl RegisterBlock {
&self.perid
}
}
-#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
module"]
#[doc(alias = "CTRL")]
pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
#[doc = "Control Register"]
pub mod ctrl;
-#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
+#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
module"]
#[doc(alias = "CLKSCALE")]
pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
#[doc = "Clock Scale divide value"]
pub mod clkscale;
-#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
+#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
module"]
#[doc(alias = "WORDS")]
pub type Words = crate::Reg<words::WordsSpec>;
#[doc = "Word Count value"]
pub mod words;
-#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
+#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
module"]
#[doc(alias = "ADDRESS")]
pub type Address = crate::Reg<address::AddressSpec>;
#[doc = "I2C Address value"]
pub mod address;
-#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
#[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>;
#[doc = "Data Input/Output"]
pub mod data;
-#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
+#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
module"]
#[doc(alias = "CMD")]
pub type Cmd = crate::Reg<cmd::CmdSpec>;
#[doc = "Command Register"]
pub mod cmd;
-#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
+#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
#[doc(alias = "STATUS")]
pub type Status = crate::Reg<status::StatusSpec>;
#[doc = "I2C Controller Status Register"]
pub mod status;
-#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
module"]
#[doc(alias = "STATE")]
pub type State = crate::Reg<state::StateSpec>;
#[doc = "Internal STATE of I2C Master Controller"]
pub mod state;
-#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
+#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
module"]
#[doc(alias = "TXCOUNT")]
pub type Txcount = crate::Reg<txcount::TxcountSpec>;
#[doc = "TX Count Register"]
pub mod txcount;
-#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
+#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
module"]
#[doc(alias = "RXCOUNT")]
pub type Rxcount = crate::Reg<rxcount::RxcountSpec>;
#[doc = "RX Count Register"]
pub mod rxcount;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"]
#[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
@@ -312,97 +312,97 @@ pub use irq_enb as irq_clr;
pub use IrqEnb as IrqRaw;
pub use IrqEnb as IrqEnd;
pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
module"]
#[doc(alias = "RXFIFOIRQTRG")]
pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
#[doc = "Rx FIFO IRQ Trigger Level"]
pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
module"]
#[doc(alias = "TXFIFOIRQTRG")]
pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
#[doc = "Tx FIFO IRQ Trigger Level"]
pub mod txfifoirqtrg;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
module"]
#[doc(alias = "FIFO_CLR")]
pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
#[doc = "Clear FIFO Register"]
pub mod fifo_clr;
-#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
+#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
module"]
#[doc(alias = "TMCONFIG")]
pub type Tmconfig = crate::Reg<tmconfig::TmconfigSpec>;
#[doc = "Timing Config Register"]
pub mod tmconfig;
-#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
+#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
module"]
#[doc(alias = "CLKTOLIMIT")]
pub type Clktolimit = crate::Reg<clktolimit::ClktolimitSpec>;
#[doc = "Clock Low Timeout Limit Register"]
pub mod clktolimit;
-#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
+#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
module"]
#[doc(alias = "S0_CTRL")]
pub type S0Ctrl = crate::Reg<s0_ctrl::S0CtrlSpec>;
#[doc = "Slave Control Register"]
pub mod s0_ctrl;
-#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
+#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
module"]
#[doc(alias = "S0_MAXWORDS")]
pub type S0Maxwords = crate::Reg<s0_maxwords::S0MaxwordsSpec>;
#[doc = "Slave MaxWords Register"]
pub mod s0_maxwords;
-#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
+#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
module"]
#[doc(alias = "S0_ADDRESS")]
pub type S0Address = crate::Reg<s0_address::S0AddressSpec>;
#[doc = "Slave I2C Address Value"]
pub mod s0_address;
-#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
+#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
module"]
#[doc(alias = "S0_ADDRESSMASK")]
pub type S0Addressmask = crate::Reg<s0_addressmask::S0AddressmaskSpec>;
#[doc = "Slave I2C Address Mask value"]
pub mod s0_addressmask;
-#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
+#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
module"]
#[doc(alias = "S0_DATA")]
pub type S0Data = crate::Reg<s0_data::S0DataSpec>;
#[doc = "Slave Data Input/Output"]
pub mod s0_data;
-#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
+#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
module"]
#[doc(alias = "S0_LASTADDRESS")]
pub type S0Lastaddress = crate::Reg<s0_lastaddress::S0LastaddressSpec>;
#[doc = "Slave I2C Last Address value"]
pub mod s0_lastaddress;
-#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
+#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
module"]
#[doc(alias = "S0_STATUS")]
pub type S0Status = crate::Reg<s0_status::S0StatusSpec>;
#[doc = "Slave I2C Controller Status Register"]
pub mod s0_status;
-#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
+#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
module"]
#[doc(alias = "S0_STATE")]
pub type S0State = crate::Reg<s0_state::S0StateSpec>;
#[doc = "Internal STATE of I2C Slave Controller"]
pub mod s0_state;
-#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
+#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
module"]
#[doc(alias = "S0_TXCOUNT")]
pub type S0Txcount = crate::Reg<s0_txcount::S0TxcountSpec>;
#[doc = "Slave TX Count Register"]
pub mod s0_txcount;
-#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
+#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
module"]
#[doc(alias = "S0_RXCOUNT")]
pub type S0Rxcount = crate::Reg<s0_rxcount::S0RxcountSpec>;
#[doc = "Slave RX Count Register"]
pub mod s0_rxcount;
-#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
+#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
module"]
#[doc(alias = "S0_IRQ_ENB")]
pub type S0IrqEnb = crate::Reg<s0_irq_enb::S0IrqEnbSpec>;
@@ -414,37 +414,37 @@ pub use s0_irq_enb as s0_irq_clr;
pub use S0IrqEnb as S0IrqRaw;
pub use S0IrqEnb as S0IrqEnd;
pub use S0IrqEnb as S0IrqClr;
-#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
+#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
module"]
#[doc(alias = "S0_RXFIFOIRQTRG")]
pub type S0Rxfifoirqtrg = crate::Reg<s0_rxfifoirqtrg::S0RxfifoirqtrgSpec>;
#[doc = "Slave Rx FIFO IRQ Trigger Level"]
pub mod s0_rxfifoirqtrg;
-#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
+#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
module"]
#[doc(alias = "S0_TXFIFOIRQTRG")]
pub type S0Txfifoirqtrg = crate::Reg<s0_txfifoirqtrg::S0TxfifoirqtrgSpec>;
#[doc = "Slave Tx FIFO IRQ Trigger Level"]
pub mod s0_txfifoirqtrg;
-#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
+#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
module"]
#[doc(alias = "S0_FIFO_CLR")]
pub type S0FifoClr = crate::Reg<s0_fifo_clr::S0FifoClrSpec>;
#[doc = "Slave Clear FIFO Register"]
pub mod s0_fifo_clr;
-#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
+#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
module"]
#[doc(alias = "S0_ADDRESSB")]
pub type S0Addressb = crate::Reg<s0_addressb::S0AddressbSpec>;
#[doc = "Slave I2C Address B Value"]
pub mod s0_addressb;
-#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
+#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
module"]
#[doc(alias = "S0_ADDRESSMASKB")]
pub type S0Addressmaskb = crate::Reg<s0_addressmaskb::S0AddressmaskbSpec>;
#[doc = "Slave I2C Address B Mask value"]
pub mod s0_addressmaskb;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>;
diff --git a/va108xx/src/i2ca/address.rs b/va108xx/src/i2ca/address.rs
index 4733ce9..51f6c13 100644
--- a/va108xx/src/i2ca/address.rs
+++ b/va108xx/src/i2ca/address.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AddressSpec;
impl crate::RegisterSpec for AddressSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/clkscale.rs b/va108xx/src/i2ca/clkscale.rs
index ad9dbd5..2989232 100644
--- a/va108xx/src/i2ca/clkscale.rs
+++ b/va108xx/src/i2ca/clkscale.rs
@@ -25,18 +25,16 @@ impl R {
impl W {
#[doc = "Bits 0:30 - Enable FastMode"]
#[inline(always)]
- #[must_use]
pub fn value(&mut self) -> ValueW<ClkscaleSpec> {
ValueW::new(self, 0)
}
#[doc = "Bit 31 - Enable FastMode"]
#[inline(always)]
- #[must_use]
pub fn fastmode(&mut self) -> FastmodeW<ClkscaleSpec> {
FastmodeW::new(self, 31)
}
}
-#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClkscaleSpec;
impl crate::RegisterSpec for ClkscaleSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/clktolimit.rs b/va108xx/src/i2ca/clktolimit.rs
index 2c0569d..7816c03 100644
--- a/va108xx/src/i2ca/clktolimit.rs
+++ b/va108xx/src/i2ca/clktolimit.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClktolimitSpec;
impl crate::RegisterSpec for ClktolimitSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/cmd.rs b/va108xx/src/i2ca/cmd.rs
index aee7ef2..67d22b0 100644
--- a/va108xx/src/i2ca/cmd.rs
+++ b/va108xx/src/i2ca/cmd.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CmdSpec;
impl crate::RegisterSpec for CmdSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/ctrl.rs b/va108xx/src/i2ca/ctrl.rs
index 203c9d3..bda794b 100644
--- a/va108xx/src/i2ca/ctrl.rs
+++ b/va108xx/src/i2ca/ctrl.rs
@@ -88,60 +88,51 @@ impl R {
impl W {
#[doc = "Bit 0 - I2C CLK Enabled"]
#[inline(always)]
- #[must_use]
pub fn clkenabled(&mut self) -> ClkenabledW<CtrlSpec> {
ClkenabledW::new(self, 0)
}
#[doc = "Bit 1 - I2C Activated"]
#[inline(always)]
- #[must_use]
pub fn enabled(&mut self) -> EnabledW<CtrlSpec> {
EnabledW::new(self, 1)
}
#[doc = "Bit 2 - I2C Active"]
#[inline(always)]
- #[must_use]
pub fn enable(&mut self) -> EnableW<CtrlSpec> {
EnableW::new(self, 2)
}
#[doc = "Bit 3 - TX FIFIO Empty Mode"]
#[inline(always)]
- #[must_use]
pub fn txfemd(&mut self) -> TxfemdW<CtrlSpec> {
TxfemdW::new(self, 3)
}
#[doc = "Bit 4 - RX FIFO Full Mode"]
#[inline(always)]
- #[must_use]
pub fn rxffmd(&mut self) -> RxffmdW<CtrlSpec> {
RxffmdW::new(self, 4)
}
#[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
#[inline(always)]
- #[must_use]
pub fn algfilter(&mut self) -> AlgfilterW<CtrlSpec> {
AlgfilterW::new(self, 5)
}
#[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
#[inline(always)]
- #[must_use]
pub fn dlgfilter(&mut self) -> DlgfilterW<CtrlSpec> {
DlgfilterW::new(self, 6)
}
#[doc = "Bit 8 - Enable LoopBack Mode"]
#[inline(always)]
- #[must_use]
pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
LoopbackW::new(self, 8)
}
#[doc = "Bit 9 - Enable Timing Config Register"]
#[inline(always)]
- #[must_use]
pub fn tmconfigenb(&mut self) -> TmconfigenbW<CtrlSpec> {
TmconfigenbW::new(self, 9)
}
}
-#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec;
impl crate::RegisterSpec for CtrlSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/data.rs b/va108xx/src/i2ca/data.rs
index 30b85c9..b981752 100644
--- a/va108xx/src/i2ca/data.rs
+++ b/va108xx/src/i2ca/data.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec;
impl crate::RegisterSpec for DataSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/fifo_clr.rs b/va108xx/src/i2ca/fifo_clr.rs
index 156da87..af272ab 100644
--- a/va108xx/src/i2ca/fifo_clr.rs
+++ b/va108xx/src/i2ca/fifo_clr.rs
@@ -7,18 +7,16 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Clear Rx FIFO"]
#[inline(always)]
- #[must_use]
pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
RxfifoW::new(self, 0)
}
#[doc = "Bit 1 - Clear Tx FIFO"]
#[inline(always)]
- #[must_use]
pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
TxfifoW::new(self, 1)
}
}
-#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoClrSpec;
impl crate::RegisterSpec for FifoClrSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/irq_enb.rs b/va108xx/src/i2ca/irq_enb.rs
index 4eba067..e6ef1c7 100644
--- a/va108xx/src/i2ca/irq_enb.rs
+++ b/va108xx/src/i2ca/irq_enb.rs
@@ -133,90 +133,76 @@ impl R {
impl W {
#[doc = "Bit 0 - I2C Bus is Idle"]
#[inline(always)]
- #[must_use]
pub fn i2cidle(&mut self) -> I2cidleW<IrqEnbSpec> {
I2cidleW::new(self, 0)
}
#[doc = "Bit 1 - Controller is Idle"]
#[inline(always)]
- #[must_use]
pub fn idle(&mut self) -> IdleW<IrqEnbSpec> {
IdleW::new(self, 1)
}
#[doc = "Bit 2 - Controller is Waiting"]
#[inline(always)]
- #[must_use]
pub fn waiting(&mut self) -> WaitingW<IrqEnbSpec> {
WaitingW::new(self, 2)
}
#[doc = "Bit 3 - Controller is Stalled"]
#[inline(always)]
- #[must_use]
pub fn stalled(&mut self) -> StalledW<IrqEnbSpec> {
StalledW::new(self, 3)
}
#[doc = "Bit 4 - I2C Arbitration was lost"]
#[inline(always)]
- #[must_use]
pub fn arblost(&mut self) -> ArblostW<IrqEnbSpec> {
ArblostW::new(self, 4)
}
#[doc = "Bit 5 - I2C Address was not Acknowledged"]
#[inline(always)]
- #[must_use]
pub fn nackaddr(&mut self) -> NackaddrW<IrqEnbSpec> {
NackaddrW::new(self, 5)
}
#[doc = "Bit 6 - I2C Data was not Acknowledged"]
#[inline(always)]
- #[must_use]
pub fn nackdata(&mut self) -> NackdataW<IrqEnbSpec> {
NackdataW::new(self, 6)
}
#[doc = "Bit 7 - I2C Clock Low Timeout"]
#[inline(always)]
- #[must_use]
pub fn clkloto(&mut self) -> ClklotoW<IrqEnbSpec> {
ClklotoW::new(self, 7)
}
#[doc = "Bit 10 - TX FIFO Overflowed"]
#[inline(always)]
- #[must_use]
pub fn txoverflow(&mut self) -> TxoverflowW<IrqEnbSpec> {
TxoverflowW::new(self, 10)
}
#[doc = "Bit 11 - TX FIFO Overflowed"]
#[inline(always)]
- #[must_use]
pub fn rxoverflow(&mut self) -> RxoverflowW<IrqEnbSpec> {
RxoverflowW::new(self, 11)
}
#[doc = "Bit 12 - TX FIFO Ready"]
#[inline(always)]
- #[must_use]
pub fn txready(&mut self) -> TxreadyW<IrqEnbSpec> {
TxreadyW::new(self, 12)
}
#[doc = "Bit 13 - RX FIFO Ready"]
#[inline(always)]
- #[must_use]
pub fn rxready(&mut self) -> RxreadyW<IrqEnbSpec> {
RxreadyW::new(self, 13)
}
#[doc = "Bit 14 - TX FIFO Empty"]
#[inline(always)]
- #[must_use]
pub fn txempty(&mut self) -> TxemptyW<IrqEnbSpec> {
TxemptyW::new(self, 14)
}
#[doc = "Bit 15 - RX FIFO Full"]
#[inline(always)]
- #[must_use]
pub fn rxfull(&mut self) -> RxfullW<IrqEnbSpec> {
RxfullW::new(self, 15)
}
}
-#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/perid.rs b/va108xx/src/i2ca/perid.rs
index 38c66fd..c420161 100644
--- a/va108xx/src/i2ca/perid.rs
+++ b/va108xx/src/i2ca/perid.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/rxcount.rs b/va108xx/src/i2ca/rxcount.rs
index b7b6d5a..f0d332e 100644
--- a/va108xx/src/i2ca/rxcount.rs
+++ b/va108xx/src/i2ca/rxcount.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxcountSpec;
impl crate::RegisterSpec for RxcountSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/rxfifoirqtrg.rs b/va108xx/src/i2ca/rxfifoirqtrg.rs
index 46124d5..8376847 100644
--- a/va108xx/src/i2ca/rxfifoirqtrg.rs
+++ b/va108xx/src/i2ca/rxfifoirqtrg.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxfifoirqtrgSpec;
impl crate::RegisterSpec for RxfifoirqtrgSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_address.rs b/va108xx/src/i2ca/s0_address.rs
index a6e6eef..314a593 100644
--- a/va108xx/src/i2ca/s0_address.rs
+++ b/va108xx/src/i2ca/s0_address.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0AddressSpec;
impl crate::RegisterSpec for S0AddressSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_addressb.rs b/va108xx/src/i2ca/s0_addressb.rs
index 38e3c77..394b9fb 100644
--- a/va108xx/src/i2ca/s0_addressb.rs
+++ b/va108xx/src/i2ca/s0_addressb.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0AddressbSpec;
impl crate::RegisterSpec for S0AddressbSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_addressmask.rs b/va108xx/src/i2ca/s0_addressmask.rs
index b858f8e..442fb95 100644
--- a/va108xx/src/i2ca/s0_addressmask.rs
+++ b/va108xx/src/i2ca/s0_addressmask.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0AddressmaskSpec;
impl crate::RegisterSpec for S0AddressmaskSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_addressmaskb.rs b/va108xx/src/i2ca/s0_addressmaskb.rs
index e79e241..572f2dd 100644
--- a/va108xx/src/i2ca/s0_addressmaskb.rs
+++ b/va108xx/src/i2ca/s0_addressmaskb.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0AddressmaskbSpec;
impl crate::RegisterSpec for S0AddressmaskbSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_ctrl.rs b/va108xx/src/i2ca/s0_ctrl.rs
index c22d6de..ef6554f 100644
--- a/va108xx/src/i2ca/s0_ctrl.rs
+++ b/va108xx/src/i2ca/s0_ctrl.rs
@@ -52,36 +52,31 @@ impl R {
impl W {
#[doc = "Bit 0 - I2C Enabled"]
#[inline(always)]
- #[must_use]
pub fn clkenabled(&mut self) -> ClkenabledW<S0CtrlSpec> {
ClkenabledW::new(self, 0)
}
#[doc = "Bit 1 - I2C Activated"]
#[inline(always)]
- #[must_use]
pub fn enabled(&mut self) -> EnabledW<S0CtrlSpec> {
EnabledW::new(self, 1)
}
#[doc = "Bit 2 - I2C Active"]
#[inline(always)]
- #[must_use]
pub fn enable(&mut self) -> EnableW<S0CtrlSpec> {
EnableW::new(self, 2)
}
#[doc = "Bit 3 - TX FIFIO Empty Mode"]
#[inline(always)]
- #[must_use]
pub fn txfemd(&mut self) -> TxfemdW<S0CtrlSpec> {
TxfemdW::new(self, 3)
}
#[doc = "Bit 4 - RX FIFO Full Mode"]
#[inline(always)]
- #[must_use]
pub fn rxffmd(&mut self) -> RxffmdW<S0CtrlSpec> {
RxffmdW::new(self, 4)
}
}
-#[doc = "Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0CtrlSpec;
impl crate::RegisterSpec for S0CtrlSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_data.rs b/va108xx/src/i2ca/s0_data.rs
index 6e7375b..b9796ec 100644
--- a/va108xx/src/i2ca/s0_data.rs
+++ b/va108xx/src/i2ca/s0_data.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0DataSpec;
impl crate::RegisterSpec for S0DataSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_fifo_clr.rs b/va108xx/src/i2ca/s0_fifo_clr.rs
index 0d5dd60..84cc53a 100644
--- a/va108xx/src/i2ca/s0_fifo_clr.rs
+++ b/va108xx/src/i2ca/s0_fifo_clr.rs
@@ -7,18 +7,16 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Clear Rx FIFO"]
#[inline(always)]
- #[must_use]
pub fn rxfifo(&mut self) -> RxfifoW<S0FifoClrSpec> {
RxfifoW::new(self, 0)
}
#[doc = "Bit 1 - Clear Tx FIFO"]
#[inline(always)]
- #[must_use]
pub fn txfifo(&mut self) -> TxfifoW<S0FifoClrSpec> {
TxfifoW::new(self, 1)
}
}
-#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0FifoClrSpec;
impl crate::RegisterSpec for S0FifoClrSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_irq_enb.rs b/va108xx/src/i2ca/s0_irq_enb.rs
index a6a30e2..5779751 100644
--- a/va108xx/src/i2ca/s0_irq_enb.rs
+++ b/va108xx/src/i2ca/s0_irq_enb.rs
@@ -151,102 +151,86 @@ impl R {
impl W {
#[doc = "Bit 0 - Controller Complted a Transaction"]
#[inline(always)]
- #[must_use]
pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> {
CompletedW::new(self, 0)
}
#[doc = "Bit 1 - Controller is Idle"]
#[inline(always)]
- #[must_use]
pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> {
IdleW::new(self, 1)
}
#[doc = "Bit 2 - Controller is Waiting"]
#[inline(always)]
- #[must_use]
pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> {
WaitingW::new(self, 2)
}
#[doc = "Bit 3 - Controller is Tx Stalled"]
#[inline(always)]
- #[must_use]
pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> {
TxstalledW::new(self, 3)
}
#[doc = "Bit 4 - Controller is Rx Stalled"]
#[inline(always)]
- #[must_use]
pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> {
RxstalledW::new(self, 4)
}
#[doc = "Bit 5 - I2C Address Match"]
#[inline(always)]
- #[must_use]
pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> {
AddressmatchW::new(self, 5)
}
#[doc = "Bit 6 - I2C Data was not Acknowledged"]
#[inline(always)]
- #[must_use]
pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> {
NackdataW::new(self, 6)
}
#[doc = "Bit 7 - Pending Data is first Byte following Address"]
#[inline(always)]
- #[must_use]
pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> {
RxdatafirstW::new(self, 7)
}
#[doc = "Bit 8 - I2C Start Condition"]
#[inline(always)]
- #[must_use]
pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> {
I2cStartW::new(self, 8)
}
#[doc = "Bit 9 - I2C Stop Condition"]
#[inline(always)]
- #[must_use]
pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> {
I2cStopW::new(self, 9)
}
#[doc = "Bit 10 - TX FIFO Underflowed"]
#[inline(always)]
- #[must_use]
pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> {
TxunderflowW::new(self, 10)
}
#[doc = "Bit 11 - TX FIFO Overflowed"]
#[inline(always)]
- #[must_use]
pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> {
RxoverflowW::new(self, 11)
}
#[doc = "Bit 12 - TX FIFO Ready"]
#[inline(always)]
- #[must_use]
pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> {
TxreadyW::new(self, 12)
}
#[doc = "Bit 13 - RX FIFO Ready"]
#[inline(always)]
- #[must_use]
pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> {
RxreadyW::new(self, 13)
}
#[doc = "Bit 14 - TX FIFO Empty"]
#[inline(always)]
- #[must_use]
pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> {
TxemptyW::new(self, 14)
}
#[doc = "Bit 15 - RX FIFO Full"]
#[inline(always)]
- #[must_use]
pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> {
RxfullW::new(self, 15)
}
}
-#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0IrqEnbSpec;
impl crate::RegisterSpec for S0IrqEnbSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_lastaddress.rs b/va108xx/src/i2ca/s0_lastaddress.rs
index 4bf751f..da55435 100644
--- a/va108xx/src/i2ca/s0_lastaddress.rs
+++ b/va108xx/src/i2ca/s0_lastaddress.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0LastaddressSpec;
impl crate::RegisterSpec for S0LastaddressSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_maxwords.rs b/va108xx/src/i2ca/s0_maxwords.rs
index b079396..34a2f2c 100644
--- a/va108xx/src/i2ca/s0_maxwords.rs
+++ b/va108xx/src/i2ca/s0_maxwords.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0MaxwordsSpec;
impl crate::RegisterSpec for S0MaxwordsSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_rxcount.rs b/va108xx/src/i2ca/s0_rxcount.rs
index b1dbc2c..3ba8a74 100644
--- a/va108xx/src/i2ca/s0_rxcount.rs
+++ b/va108xx/src/i2ca/s0_rxcount.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0RxcountSpec;
impl crate::RegisterSpec for S0RxcountSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_rxfifoirqtrg.rs b/va108xx/src/i2ca/s0_rxfifoirqtrg.rs
index b2a5632..065b9f2 100644
--- a/va108xx/src/i2ca/s0_rxfifoirqtrg.rs
+++ b/va108xx/src/i2ca/s0_rxfifoirqtrg.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0RxfifoirqtrgSpec;
impl crate::RegisterSpec for S0RxfifoirqtrgSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_state.rs b/va108xx/src/i2ca/s0_state.rs
index 473fd77..9be0a91 100644
--- a/va108xx/src/i2ca/s0_state.rs
+++ b/va108xx/src/i2ca/s0_state.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0StateSpec;
impl crate::RegisterSpec for S0StateSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_status.rs b/va108xx/src/i2ca/s0_status.rs
index 1a79596..d6b5208 100644
--- a/va108xx/src/i2ca/s0_status.rs
+++ b/va108xx/src/i2ca/s0_status.rs
@@ -121,7 +121,7 @@ impl R {
RawSclR::new(((self.bits >> 31) & 1) != 0)
}
}
-#[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0StatusSpec;
impl crate::RegisterSpec for S0StatusSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_txcount.rs b/va108xx/src/i2ca/s0_txcount.rs
index a125c56..afba048 100644
--- a/va108xx/src/i2ca/s0_txcount.rs
+++ b/va108xx/src/i2ca/s0_txcount.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0TxcountSpec;
impl crate::RegisterSpec for S0TxcountSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/s0_txfifoirqtrg.rs b/va108xx/src/i2ca/s0_txfifoirqtrg.rs
index 1c8f27a..407167b 100644
--- a/va108xx/src/i2ca/s0_txfifoirqtrg.rs
+++ b/va108xx/src/i2ca/s0_txfifoirqtrg.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct S0TxfifoirqtrgSpec;
impl crate::RegisterSpec for S0TxfifoirqtrgSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/state.rs b/va108xx/src/i2ca/state.rs
index fe3c04e..81fe633 100644
--- a/va108xx/src/i2ca/state.rs
+++ b/va108xx/src/i2ca/state.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StateSpec;
impl crate::RegisterSpec for StateSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/status.rs b/va108xx/src/i2ca/status.rs
index f8f340e..dda6bfe 100644
--- a/va108xx/src/i2ca/status.rs
+++ b/va108xx/src/i2ca/status.rs
@@ -107,7 +107,7 @@ impl R {
RawSclR::new(((self.bits >> 31) & 1) != 0)
}
}
-#[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatusSpec;
impl crate::RegisterSpec for StatusSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/tmconfig.rs b/va108xx/src/i2ca/tmconfig.rs
index 2d0e025..aa219ba 100644
--- a/va108xx/src/i2ca/tmconfig.rs
+++ b/va108xx/src/i2ca/tmconfig.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TmconfigSpec;
impl crate::RegisterSpec for TmconfigSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/txcount.rs b/va108xx/src/i2ca/txcount.rs
index ae64e43..41e1987 100644
--- a/va108xx/src/i2ca/txcount.rs
+++ b/va108xx/src/i2ca/txcount.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxcountSpec;
impl crate::RegisterSpec for TxcountSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/txfifoirqtrg.rs b/va108xx/src/i2ca/txfifoirqtrg.rs
index 0d13e54..8d0ae92 100644
--- a/va108xx/src/i2ca/txfifoirqtrg.rs
+++ b/va108xx/src/i2ca/txfifoirqtrg.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxfifoirqtrgSpec;
impl crate::RegisterSpec for TxfifoirqtrgSpec {
type Ux = u32;
diff --git a/va108xx/src/i2ca/words.rs b/va108xx/src/i2ca/words.rs
index 9aedb52..2b890bf 100644
--- a/va108xx/src/i2ca/words.rs
+++ b/va108xx/src/i2ca/words.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WordsSpec;
impl crate::RegisterSpec for WordsSpec {
type Ux = u32;
diff --git a/va108xx/src/ioconfig.rs b/va108xx/src/ioconfig.rs
index 3e06b07..9dcc92b 100644
--- a/va108xx/src/ioconfig.rs
+++ b/va108xx/src/ioconfig.rs
@@ -35,7 +35,7 @@ impl RegisterBlock {
&self.perid
}
}
-#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`]
+#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`]
module"]
#[doc(alias = "PORTA")]
pub type Porta = crate::Reg<porta::PortaSpec>;
@@ -43,7 +43,7 @@ pub type Porta = crate::Reg<porta::PortaSpec>;
pub mod porta;
pub use porta as portb;
pub use Porta as Portb;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>;
diff --git a/va108xx/src/ioconfig/perid.rs b/va108xx/src/ioconfig/perid.rs
index 7b4aa79..6638b5f 100644
--- a/va108xx/src/ioconfig/perid.rs
+++ b/va108xx/src/ioconfig/perid.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;
diff --git a/va108xx/src/ioconfig/porta.rs b/va108xx/src/ioconfig/porta.rs
index b068faa..32e9ef5 100644
--- a/va108xx/src/ioconfig/porta.rs
+++ b/va108xx/src/ioconfig/porta.rs
@@ -214,72 +214,61 @@ impl R {
impl W {
#[doc = "Bits 0:2 - Input Filter Selectoin"]
#[inline(always)]
- #[must_use]
pub fn flttype(&mut self) -> FlttypeW<PortaSpec> {
FlttypeW::new(self, 0)
}
#[doc = "Bits 3:5 - Input Filter Clock Selection"]
#[inline(always)]
- #[must_use]
pub fn fltclk(&mut self) -> FltclkW<PortaSpec> {
FltclkW::new(self, 3)
}
#[doc = "Bit 6 - Input Invert Selection"]
#[inline(always)]
- #[must_use]
pub fn invinp(&mut self) -> InvinpW<PortaSpec> {
InvinpW::new(self, 6)
}
#[doc = "Bit 7 - Input Enable While Output enabled"]
#[inline(always)]
- #[must_use]
pub fn iewo(&mut self) -> IewoW<PortaSpec> {
IewoW::new(self, 7)
}
#[doc = "Bit 8 - Output Open Drain Mode"]
#[inline(always)]
- #[must_use]
pub fn opendrn(&mut self) -> OpendrnW<PortaSpec> {
OpendrnW::new(self, 8)
}
#[doc = "Bit 9 - Output Invert Selection"]
#[inline(always)]
- #[must_use]
pub fn invout(&mut self) -> InvoutW<PortaSpec> {
InvoutW::new(self, 9)
}
#[doc = "Bit 10 - Internal Pull up/down level"]
#[inline(always)]
- #[must_use]
pub fn plevel(&mut self) -> PlevelW<PortaSpec> {
PlevelW::new(self, 10)
}
#[doc = "Bit 11 - Enable Internal Pull up/down"]
#[inline(always)]
- #[must_use]
pub fn pen(&mut self) -> PenW<PortaSpec> {
PenW::new(self, 11)
}
#[doc = "Bit 12 - Enable Pull when output active"]
#[inline(always)]
- #[must_use]
pub fn pwoa(&mut self) -> PwoaW<PortaSpec> {
PwoaW::new(self, 12)
}
#[doc = "Bits 13:15 - Pin Function Selection"]
#[inline(always)]
- #[must_use]
pub fn funsel(&mut self) -> FunselW<PortaSpec> {
FunselW::new(self, 13)
}
#[doc = "Bit 16 - IO Pin Disable"]
#[inline(always)]
- #[must_use]
pub fn iodis(&mut self) -> IodisW<PortaSpec> {
IodisW::new(self, 16)
}
}
-#[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PortaSpec;
impl crate::RegisterSpec for PortaSpec {
type Ux = u32;
diff --git a/va108xx/src/irqsel.rs b/va108xx/src/irqsel.rs
index c90a7e0..3d2eb88 100644
--- a/va108xx/src/irqsel.rs
+++ b/va108xx/src/irqsel.rs
@@ -169,7 +169,7 @@ impl RegisterBlock {
&self.perid
}
}
-#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`]
+#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`]
module"]
#[doc(alias = "INT_RAM_SBE")]
pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>;
@@ -197,7 +197,7 @@ pub use IntRamSbe as IntRamMbe;
pub use IntRamSbe as IntRomSbe;
pub use IntRamSbe as IntRomMbe;
pub use IntRamSbe as Txev;
-#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`]
+#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`]
module"]
#[doc(alias = "NMI")]
pub type Nmi = crate::Reg<nmi::NmiSpec>;
@@ -213,7 +213,7 @@ pub use Nmi as Watchdog;
pub use Nmi as Mereset;
pub use Nmi as Edbgrq;
pub use Nmi as Irqs;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>;
diff --git a/va108xx/src/irqsel/int_ram_sbe.rs b/va108xx/src/irqsel/int_ram_sbe.rs
index 5d1f412..ea83fe8 100644
--- a/va108xx/src/irqsel/int_ram_sbe.rs
+++ b/va108xx/src/irqsel/int_ram_sbe.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ram_sbe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ram_sbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IntRamSbeSpec;
impl crate::RegisterSpec for IntRamSbeSpec {
type Ux = u32;
diff --git a/va108xx/src/irqsel/nmi.rs b/va108xx/src/irqsel/nmi.rs
index 9dde175..93fb91a 100644
--- a/va108xx/src/irqsel/nmi.rs
+++ b/va108xx/src/irqsel/nmi.rs
@@ -9,7 +9,7 @@ impl R {
ActiveR::new((self.bits & 1) != 0)
}
}
-#[doc = "NMI Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NmiSpec;
impl crate::RegisterSpec for NmiSpec {
type Ux = u32;
diff --git a/va108xx/src/irqsel/perid.rs b/va108xx/src/irqsel/perid.rs
index 5a84e29..716aa3f 100644
--- a/va108xx/src/irqsel/perid.rs
+++ b/va108xx/src/irqsel/perid.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;
diff --git a/va108xx/src/lib.rs b/va108xx/src/lib.rs
index 098df25..55a9a23 100644
--- a/va108xx/src/lib.rs
+++ b/va108xx/src/lib.rs
@@ -1,10 +1,8 @@
-#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
-svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
+#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.35.0 (e10f920 2025-02-12))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
+svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.35.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![allow(non_camel_case_types)]
#![allow(non_snake_case)]
#![no_std]
-// Manually inserted.
-#![cfg_attr(docsrs, feature(doc_auto_cfg))]
use core::marker::PhantomData;
use core::ops::Deref;
#[doc = r"Number available in the NVIC for configuring priority"]
@@ -1974,117 +1972,43 @@ impl Peripherals {
pub unsafe fn steal() -> Self {
DEVICE_PERIPHERALS = true;
Peripherals {
- sysconfig: Sysconfig {
- _marker: PhantomData,
- },
- irqsel: Irqsel {
- _marker: PhantomData,
- },
- ioconfig: Ioconfig {
- _marker: PhantomData,
- },
- utility: Utility {
- _marker: PhantomData,
- },
- porta: Porta {
- _marker: PhantomData,
- },
- portb: Portb {
- _marker: PhantomData,
- },
- tim0: Tim0 {
- _marker: PhantomData,
- },
- tim1: Tim1 {
- _marker: PhantomData,
- },
- tim2: Tim2 {
- _marker: PhantomData,
- },
- tim3: Tim3 {
- _marker: PhantomData,
- },
- tim4: Tim4 {
- _marker: PhantomData,
- },
- tim5: Tim5 {
- _marker: PhantomData,
- },
- tim6: Tim6 {
- _marker: PhantomData,
- },
- tim7: Tim7 {
- _marker: PhantomData,
- },
- tim8: Tim8 {
- _marker: PhantomData,
- },
- tim9: Tim9 {
- _marker: PhantomData,
- },
- tim10: Tim10 {
- _marker: PhantomData,
- },
- tim11: Tim11 {
- _marker: PhantomData,
- },
- tim12: Tim12 {
- _marker: PhantomData,
- },
- tim13: Tim13 {
- _marker: PhantomData,
- },
- tim14: Tim14 {
- _marker: PhantomData,
- },
- tim15: Tim15 {
- _marker: PhantomData,
- },
- tim16: Tim16 {
- _marker: PhantomData,
- },
- tim17: Tim17 {
- _marker: PhantomData,
- },
- tim18: Tim18 {
- _marker: PhantomData,
- },
- tim19: Tim19 {
- _marker: PhantomData,
- },
- tim20: Tim20 {
- _marker: PhantomData,
- },
- tim21: Tim21 {
- _marker: PhantomData,
- },
- tim22: Tim22 {
- _marker: PhantomData,
- },
- tim23: Tim23 {
- _marker: PhantomData,
- },
- uarta: Uarta {
- _marker: PhantomData,
- },
- uartb: Uartb {
- _marker: PhantomData,
- },
- spia: Spia {
- _marker: PhantomData,
- },
- spib: Spib {
- _marker: PhantomData,
- },
- spic: Spic {
- _marker: PhantomData,
- },
- i2ca: I2ca {
- _marker: PhantomData,
- },
- i2cb: I2cb {
- _marker: PhantomData,
- },
+ sysconfig: Sysconfig::steal(),
+ irqsel: Irqsel::steal(),
+ ioconfig: Ioconfig::steal(),
+ utility: Utility::steal(),
+ porta: Porta::steal(),
+ portb: Portb::steal(),
+ tim0: Tim0::steal(),
+ tim1: Tim1::steal(),
+ tim2: Tim2::steal(),
+ tim3: Tim3::steal(),
+ tim4: Tim4::steal(),
+ tim5: Tim5::steal(),
+ tim6: Tim6::steal(),
+ tim7: Tim7::steal(),
+ tim8: Tim8::steal(),
+ tim9: Tim9::steal(),
+ tim10: Tim10::steal(),
+ tim11: Tim11::steal(),
+ tim12: Tim12::steal(),
+ tim13: Tim13::steal(),
+ tim14: Tim14::steal(),
+ tim15: Tim15::steal(),
+ tim16: Tim16::steal(),
+ tim17: Tim17::steal(),
+ tim18: Tim18::steal(),
+ tim19: Tim19::steal(),
+ tim20: Tim20::steal(),
+ tim21: Tim21::steal(),
+ tim22: Tim22::steal(),
+ tim23: Tim23::steal(),
+ uarta: Uarta::steal(),
+ uartb: Uartb::steal(),
+ spia: Spia::steal(),
+ spib: Spib::steal(),
+ spic: Spic::steal(),
+ i2ca: I2ca::steal(),
+ i2cb: I2cb::steal(),
}
}
}
diff --git a/va108xx/src/porta.rs b/va108xx/src/porta.rs
index e315416..6429238 100644
--- a/va108xx/src/porta.rs
+++ b/va108xx/src/porta.rs
@@ -1,6 +1,3 @@
-// Manually inserted.
-#![allow(clippy::identity_op)]
-
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
@@ -33,247 +30,246 @@ impl RegisterBlock {
pub const fn datainbyte(&self, n: usize) -> &Datainbyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(0).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x00 - Data In Register by Byte"]
#[inline(always)]
pub fn datainbyte_iter(&self) -> impl Iterator<Item = &Datainbyte> {
- (0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(0).add(1 * n).cast() })
+ (0..4).map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(n).cast() })
}
#[doc = "0x00 - Data In Register"]
#[inline(always)]
pub const fn datain(&self) -> &Datain {
- unsafe { &*(self as *const Self).cast::<u8>().add(0).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().cast() }
}
#[doc = "0x04 - Data In Raw Register by Byte"]
#[inline(always)]
pub const fn datainrawbyte0(&self, n: usize) -> &Datainrawbyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(4).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x04 - Data In Raw Register by Byte"]
#[inline(always)]
pub fn datainrawbyte0_iter(&self) -> impl Iterator<Item = &Datainrawbyte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(4).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() })
}
#[doc = "0x04 - Data In Raw Register"]
#[inline(always)]
pub const fn datainraw(&self) -> &Datainraw {
- unsafe { &*(self as *const Self).cast::<u8>().add(4).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).cast() }
}
#[doc = "0x08 - Data Out Register by Byte"]
#[inline(always)]
pub const fn dataoutbyte(&self, n: usize) -> &Dataoutbyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(8).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x08 - Data Out Register by Byte"]
#[inline(always)]
pub fn dataoutbyte_iter(&self) -> impl Iterator<Item = &Dataoutbyte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(8).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).add(n).cast() })
}
#[doc = "0x08 - Data Out Register"]
#[inline(always)]
pub const fn dataout(&self) -> &Dataout {
- unsafe { &*(self as *const Self).cast::<u8>().add(8).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).cast() }
}
#[doc = "0x0c - Data Out Register by Byte"]
#[inline(always)]
pub const fn dataoutrawbyte0(&self, n: usize) -> &Dataoutrawbyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(12).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x0c - Data Out Register by Byte"]
#[inline(always)]
pub fn dataoutrawbyte0_iter(&self) -> impl Iterator<Item = &Dataoutrawbyte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(12).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() })
}
#[doc = "0x0c - Data Out Register"]
#[inline(always)]
pub const fn dataoutraw(&self) -> &Dataoutraw {
- unsafe { &*(self as *const Self).cast::<u8>().add(12).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).cast() }
}
#[doc = "0x10 - Set Out Register by Byte"]
#[inline(always)]
pub const fn setoutbyte0(&self, n: usize) -> &Setoutbyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(16).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x10 - Set Out Register by Byte"]
#[inline(always)]
pub fn setoutbyte0_iter(&self) -> impl Iterator<Item = &Setoutbyte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(16).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() })
}
#[doc = "0x10 - Set Out Register"]
#[inline(always)]
pub const fn setout(&self) -> &Setout {
- unsafe { &*(self as *const Self).cast::<u8>().add(16).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).cast() }
}
#[doc = "0x14 - Clear Out Register by Byte"]
#[inline(always)]
pub const fn clroutbyte0(&self, n: usize) -> &Clroutbyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(20).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x14 - Clear Out Register by Byte"]
#[inline(always)]
pub fn clroutbyte0_iter(&self) -> impl Iterator<Item = &Clroutbyte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(20).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() })
}
#[doc = "0x14 - Clear Out Register"]
#[inline(always)]
pub const fn clrout(&self) -> &Clrout {
- unsafe { &*(self as *const Self).cast::<u8>().add(20).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).cast() }
}
#[doc = "0x18 - Toggle Out Register by Byte"]
#[inline(always)]
pub const fn togoutbyte0(&self, n: usize) -> &Togoutbyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(24).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x18 - Toggle Out Register by Byte"]
#[inline(always)]
pub fn togoutbyte0_iter(&self) -> impl Iterator<Item = &Togoutbyte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(24).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() })
}
#[doc = "0x18 - Toggle Out Register"]
#[inline(always)]
pub const fn togout(&self) -> &Togout {
- unsafe { &*(self as *const Self).cast::<u8>().add(24).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
}
#[doc = "0x1c - Data Out Register by Byte"]
#[inline(always)]
pub const fn datamaskbyte(&self, n: usize) -> &Datamaskbyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(28).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x1c - Data Out Register by Byte"]
#[inline(always)]
pub fn datamaskbyte_iter(&self) -> impl Iterator<Item = &Datamaskbyte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(28).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).add(n).cast() })
}
#[doc = "0x1c - Data mask Register"]
#[inline(always)]
pub const fn datamask(&self) -> &Datamask {
- unsafe { &*(self as *const Self).cast::<u8>().add(28).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
}
#[doc = "0x20 - Direction Register by Byte"]
#[inline(always)]
pub const fn dirbyte0(&self, n: usize) -> &Dirbyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(32).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x20 - Direction Register by Byte"]
#[inline(always)]
pub fn dirbyte0_iter(&self) -> impl Iterator<Item = &Dirbyte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(32).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() })
}
#[doc = "0x20 - Direction Register (1:Output, 0:Input)"]
#[inline(always)]
pub const fn dir(&self) -> &Dir {
- unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
}
#[doc = "0x24 - Pulse Mode Register by Byte"]
#[inline(always)]
pub const fn pulsebyte0(&self, n: usize) -> &Pulsebyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(36).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x24 - Pulse Mode Register by Byte"]
#[inline(always)]
pub fn pulsebyte0_iter(&self) -> impl Iterator<Item = &Pulsebyte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(36).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() })
}
#[doc = "0x24 - Pulse Mode Register"]
#[inline(always)]
pub const fn pulse(&self) -> &Pulse {
- unsafe { &*(self as *const Self).cast::<u8>().add(36).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).cast() }
}
#[doc = "0x28 - Pulse Base Mode Register by Byte"]
#[inline(always)]
pub const fn pulsebasebyte0(&self, n: usize) -> &Pulsebasebyte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(40).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x28 - Pulse Base Mode Register by Byte"]
#[inline(always)]
pub fn pulsebasebyte0_iter(&self) -> impl Iterator<Item = &Pulsebasebyte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(40).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() })
}
#[doc = "0x28 - Pulse Base Value Register"]
#[inline(always)]
pub const fn pulsebase(&self) -> &Pulsebase {
- unsafe { &*(self as *const Self).cast::<u8>().add(40).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
}
#[doc = "0x2c - Delay1 Register by Byte"]
#[inline(always)]
pub const fn delay1byte0(&self, n: usize) -> &Delay1byte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(44).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x2c - Delay1 Register by Byte"]
#[inline(always)]
pub fn delay1byte0_iter(&self) -> impl Iterator<Item = &Delay1byte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(44).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() })
}
#[doc = "0x2c - Delay1 Register"]
#[inline(always)]
pub const fn delay1(&self) -> &Delay1 {
- unsafe { &*(self as *const Self).cast::<u8>().add(44).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).cast() }
}
#[doc = "0x30 - Delay2 Register by Byte"]
#[inline(always)]
pub const fn delay2byte0(&self, n: usize) -> &Delay2byte {
#[allow(clippy::no_effect)]
[(); 4][n];
- unsafe { &*(self as *const Self).cast::<u8>().add(48).add(1 * n).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() }
}
#[doc = "Iterator for array of:"]
#[doc = "0x30 - Delay2 Register by Byte"]
#[inline(always)]
pub fn delay2byte0_iter(&self) -> impl Iterator<Item = &Delay2byte> {
(0..4)
- .map(move |n| unsafe { &*(self as *const Self).cast::<u8>().add(48).add(1 * n).cast() })
+ .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() })
}
#[doc = "0x30 - Delay2 Register"]
#[inline(always)]
pub const fn delay2(&self) -> &Delay2 {
- unsafe { &*(self as *const Self).cast::<u8>().add(48).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).cast() }
}
#[doc = "0x34 - Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
#[inline(always)]
@@ -316,13 +312,13 @@ impl RegisterBlock {
&self.perid
}
}
-#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`]
+#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`]
module"]
#[doc(alias = "DATAIN")]
pub type Datain = crate::Reg<datain::DatainSpec>;
#[doc = "Data In Register"]
pub mod datain;
-#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`]
+#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`]
module"]
#[doc(alias = "DATAINBYTE")]
pub type Datainbyte = crate::Reg<datainbyte::DatainbyteSpec>;
@@ -332,13 +328,13 @@ pub use datain as datainraw;
pub use datainbyte as datainrawbyte;
pub use Datain as Datainraw;
pub use Datainbyte as Datainrawbyte;
-#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`]
+#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`]
module"]
#[doc(alias = "DATAOUT")]
pub type Dataout = crate::Reg<dataout::DataoutSpec>;
#[doc = "Data Out Register"]
pub mod dataout;
-#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`]
+#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`]
module"]
#[doc(alias = "DATAOUTBYTE")]
pub type Dataoutbyte = crate::Reg<dataoutbyte::DataoutbyteSpec>;
@@ -360,13 +356,13 @@ pub use Dataoutbyte as Dataoutrawbyte;
pub use Dataoutbyte as Setoutbyte;
pub use Dataoutbyte as Clroutbyte;
pub use Dataoutbyte as Togoutbyte;
-#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`]
+#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`]
module"]
#[doc(alias = "DATAMASK")]
pub type Datamask = crate::Reg<datamask::DatamaskSpec>;
#[doc = "Data mask Register"]
pub mod datamask;
-#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`]
+#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`]
module"]
#[doc(alias = "DATAMASKBYTE")]
pub type Datamaskbyte = crate::Reg<datamaskbyte::DatamaskbyteSpec>;
@@ -392,49 +388,49 @@ pub use Datamaskbyte as Pulsebyte;
pub use Datamaskbyte as Pulsebasebyte;
pub use Datamaskbyte as Delay1byte;
pub use Datamaskbyte as Delay2byte;
-#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`]
+#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`]
module"]
#[doc(alias = "IRQ_SEN")]
pub type IrqSen = crate::Reg<irq_sen::IrqSenSpec>;
#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
pub mod irq_sen;
-#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`]
+#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`]
module"]
#[doc(alias = "IRQ_EDGE")]
pub type IrqEdge = crate::Reg<irq_edge::IrqEdgeSpec>;
#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"]
pub mod irq_edge;
-#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`]
+#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`]
module"]
#[doc(alias = "IRQ_EVT")]
pub type IrqEvt = crate::Reg<irq_evt::IrqEvtSpec>;
#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"]
pub mod irq_evt;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"]
#[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
#[doc = "Interrupt Enable Register"]
pub mod irq_enb;
-#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
+#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
module"]
#[doc(alias = "IRQ_RAW")]
pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>;
#[doc = "Raw Interrupt Status"]
pub mod irq_raw;
-#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
+#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
module"]
#[doc(alias = "IRQ_END")]
pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>;
#[doc = "Masked Interrupt Status"]
pub mod irq_end;
-#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`]
+#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`]
module"]
#[doc(alias = "EDGE_STATUS")]
pub type EdgeStatus = crate::Reg<edge_status::EdgeStatusSpec>;
#[doc = "Edge Status Register"]
pub mod edge_status;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>;
diff --git a/va108xx/src/porta/datain.rs b/va108xx/src/porta/datain.rs
index 5f6a720..10c0f7c 100644
--- a/va108xx/src/porta/datain.rs
+++ b/va108xx/src/porta/datain.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DatainSpec;
impl crate::RegisterSpec for DatainSpec {
type Ux = u32;
diff --git a/va108xx/src/porta/datainbyte.rs b/va108xx/src/porta/datainbyte.rs
index 06d7f67..975ec65 100644
--- a/va108xx/src/porta/datainbyte.rs
+++ b/va108xx/src/porta/datainbyte.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DatainbyteSpec;
impl crate::RegisterSpec for DatainbyteSpec {
type Ux = u8;
diff --git a/va108xx/src/porta/datamask.rs b/va108xx/src/porta/datamask.rs
index 6df9aac..5185323 100644
--- a/va108xx/src/porta/datamask.rs
+++ b/va108xx/src/porta/datamask.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DatamaskSpec;
impl crate::RegisterSpec for DatamaskSpec {
type Ux = u32;
diff --git a/va108xx/src/porta/datamaskbyte.rs b/va108xx/src/porta/datamaskbyte.rs
index 29ecd88..5ac5d4c 100644
--- a/va108xx/src/porta/datamaskbyte.rs
+++ b/va108xx/src/porta/datamaskbyte.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DatamaskbyteSpec;
impl crate::RegisterSpec for DatamaskbyteSpec {
type Ux = u8;
diff --git a/va108xx/src/porta/dataout.rs b/va108xx/src/porta/dataout.rs
index 6250016..f36ae05 100644
--- a/va108xx/src/porta/dataout.rs
+++ b/va108xx/src/porta/dataout.rs
@@ -6,7 +6,7 @@ impl core::fmt::Debug for crate::generic::Reg<DataoutSpec> {
}
}
impl W {}
-#[doc = "Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataoutSpec;
impl crate::RegisterSpec for DataoutSpec {
type Ux = u32;
diff --git a/va108xx/src/porta/dataoutbyte.rs b/va108xx/src/porta/dataoutbyte.rs
index a712f13..3344ad6 100644
--- a/va108xx/src/porta/dataoutbyte.rs
+++ b/va108xx/src/porta/dataoutbyte.rs
@@ -6,7 +6,7 @@ impl core::fmt::Debug for crate::generic::Reg<DataoutbyteSpec> {
}
}
impl W {}
-#[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataoutbyteSpec;
impl crate::RegisterSpec for DataoutbyteSpec {
type Ux = u8;
diff --git a/va108xx/src/porta/edge_status.rs b/va108xx/src/porta/edge_status.rs
index 0a90d70..2c33d2a 100644
--- a/va108xx/src/porta/edge_status.rs
+++ b/va108xx/src/porta/edge_status.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EdgeStatusSpec;
impl crate::RegisterSpec for EdgeStatusSpec {
type Ux = u32;
diff --git a/va108xx/src/porta/irq_edge.rs b/va108xx/src/porta/irq_edge.rs
index fddfc1c..1f24586 100644
--- a/va108xx/src/porta/irq_edge.rs
+++ b/va108xx/src/porta/irq_edge.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEdgeSpec;
impl crate::RegisterSpec for IrqEdgeSpec {
type Ux = u32;
diff --git a/va108xx/src/porta/irq_enb.rs b/va108xx/src/porta/irq_enb.rs
index 2696b81..3f1c60e 100644
--- a/va108xx/src/porta/irq_enb.rs
+++ b/va108xx/src/porta/irq_enb.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32;
diff --git a/va108xx/src/porta/irq_end.rs b/va108xx/src/porta/irq_end.rs
index cf88a8a..9cc9e4e 100644
--- a/va108xx/src/porta/irq_end.rs
+++ b/va108xx/src/porta/irq_end.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEndSpec;
impl crate::RegisterSpec for IrqEndSpec {
type Ux = u32;
diff --git a/va108xx/src/porta/irq_evt.rs b/va108xx/src/porta/irq_evt.rs
index 1e98fa4..f23485c 100644
--- a/va108xx/src/porta/irq_evt.rs
+++ b/va108xx/src/porta/irq_evt.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEvtSpec;
impl crate::RegisterSpec for IrqEvtSpec {
type Ux = u32;
diff --git a/va108xx/src/porta/irq_raw.rs b/va108xx/src/porta/irq_raw.rs
index 0e153ef..d30086c 100644
--- a/va108xx/src/porta/irq_raw.rs
+++ b/va108xx/src/porta/irq_raw.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqRawSpec;
impl crate::RegisterSpec for IrqRawSpec {
type Ux = u32;
diff --git a/va108xx/src/porta/irq_sen.rs b/va108xx/src/porta/irq_sen.rs
index 5b4c44a..70346cc 100644
--- a/va108xx/src/porta/irq_sen.rs
+++ b/va108xx/src/porta/irq_sen.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqSenSpec;
impl crate::RegisterSpec for IrqSenSpec {
type Ux = u32;
diff --git a/va108xx/src/porta/perid.rs b/va108xx/src/porta/perid.rs
index 7c53b75..8dc80da 100644
--- a/va108xx/src/porta/perid.rs
+++ b/va108xx/src/porta/perid.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;
diff --git a/va108xx/src/spia.rs b/va108xx/src/spia.rs
index 9b6a264..9246281 100644
--- a/va108xx/src/spia.rs
+++ b/va108xx/src/spia.rs
@@ -89,37 +89,37 @@ impl RegisterBlock {
&self.perid
}
}
-#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
+#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
module"]
#[doc(alias = "CTRL0")]
pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>;
#[doc = "Control Register 0"]
pub mod ctrl0;
-#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
+#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
module"]
#[doc(alias = "CTRL1")]
pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>;
#[doc = "Control Register 1"]
pub mod ctrl1;
-#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
#[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>;
#[doc = "Data Input/Output"]
pub mod data;
-#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
+#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
#[doc(alias = "STATUS")]
pub type Status = crate::Reg<status::StatusSpec>;
#[doc = "Status Register"]
pub mod status;
-#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`]
+#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`]
module"]
#[doc(alias = "CLKPRESCALE")]
pub type Clkprescale = crate::Reg<clkprescale::ClkprescaleSpec>;
#[doc = "Clock Pre Scale divide value"]
pub mod clkprescale;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"]
#[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
@@ -131,31 +131,31 @@ pub use irq_enb as irq_clr;
pub use IrqEnb as IrqRaw;
pub use IrqEnb as IrqEnd;
pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
module"]
#[doc(alias = "RXFIFOIRQTRG")]
pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
#[doc = "Rx FIFO IRQ Trigger Level"]
pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
module"]
#[doc(alias = "TXFIFOIRQTRG")]
pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
#[doc = "Tx FIFO IRQ Trigger Level"]
pub mod txfifoirqtrg;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
module"]
#[doc(alias = "FIFO_CLR")]
pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
#[doc = "Clear FIFO Register"]
pub mod fifo_clr;
-#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
module"]
#[doc(alias = "STATE")]
pub type State = crate::Reg<state::StateSpec>;
#[doc = "Internal STATE of SPI Controller"]
pub mod state;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>;
diff --git a/va108xx/src/spia/clkprescale.rs b/va108xx/src/spia/clkprescale.rs
index ea5249f..bcf8350 100644
--- a/va108xx/src/spia/clkprescale.rs
+++ b/va108xx/src/spia/clkprescale.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClkprescaleSpec;
impl crate::RegisterSpec for ClkprescaleSpec {
type Ux = u32;
diff --git a/va108xx/src/spia/ctrl0.rs b/va108xx/src/spia/ctrl0.rs
index 4e41012..a596dfe 100644
--- a/va108xx/src/spia/ctrl0.rs
+++ b/va108xx/src/spia/ctrl0.rs
@@ -43,30 +43,26 @@ impl R {
impl W {
#[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
#[inline(always)]
- #[must_use]
pub fn size(&mut self) -> SizeW<Ctrl0Spec> {
SizeW::new(self, 0)
}
#[doc = "Bit 6 - SPI Clock Polarity"]
#[inline(always)]
- #[must_use]
pub fn spo(&mut self) -> SpoW<Ctrl0Spec> {
SpoW::new(self, 6)
}
#[doc = "Bit 7 - SPI Clock Phase"]
#[inline(always)]
- #[must_use]
pub fn sph(&mut self) -> SphW<Ctrl0Spec> {
SphW::new(self, 7)
}
#[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
#[inline(always)]
- #[must_use]
pub fn scrdv(&mut self) -> ScrdvW<Ctrl0Spec> {
ScrdvW::new(self, 8)
}
}
-#[doc = "Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ctrl0Spec;
impl crate::RegisterSpec for Ctrl0Spec {
type Ux = u32;
diff --git a/va108xx/src/spia/ctrl1.rs b/va108xx/src/spia/ctrl1.rs
index 45d9ec8..461ed99 100644
--- a/va108xx/src/spia/ctrl1.rs
+++ b/va108xx/src/spia/ctrl1.rs
@@ -97,66 +97,56 @@ impl R {
impl W {
#[doc = "Bit 0 - Loop Back"]
#[inline(always)]
- #[must_use]
pub fn lbm(&mut self) -> LbmW<Ctrl1Spec> {
LbmW::new(self, 0)
}
#[doc = "Bit 1 - Enable"]
#[inline(always)]
- #[must_use]
pub fn enable(&mut self) -> EnableW<Ctrl1Spec> {
EnableW::new(self, 1)
}
#[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"]
#[inline(always)]
- #[must_use]
pub fn ms(&mut self) -> MsW<Ctrl1Spec> {
MsW::new(self, 2)
}
#[doc = "Bit 3 - Slave output Disable"]
#[inline(always)]
- #[must_use]
pub fn sod(&mut self) -> SodW<Ctrl1Spec> {
SodW::new(self, 3)
}
#[doc = "Bits 4:6 - Slave Select"]
#[inline(always)]
- #[must_use]
pub fn ss(&mut self) -> SsW<Ctrl1Spec> {
SsW::new(self, 4)
}
#[doc = "Bit 7 - Block Mode Enable"]
#[inline(always)]
- #[must_use]
pub fn blockmode(&mut self) -> BlockmodeW<Ctrl1Spec> {
BlockmodeW::new(self, 7)
}
#[doc = "Bit 8 - Block Mode Start Status Enable"]
#[inline(always)]
- #[must_use]
pub fn bmstart(&mut self) -> BmstartW<Ctrl1Spec> {
BmstartW::new(self, 8)
}
#[doc = "Bit 9 - Block Mode Stall Enable"]
#[inline(always)]
- #[must_use]
pub fn bmstall(&mut self) -> BmstallW<Ctrl1Spec> {
BmstallW::new(self, 9)
}
#[doc = "Bit 10 - Master Delayed Capture Enable"]
#[inline(always)]
- #[must_use]
pub fn mdlycap(&mut self) -> MdlycapW<Ctrl1Spec> {
MdlycapW::new(self, 10)
}
#[doc = "Bit 11 - Master Tx Pause Enable"]
#[inline(always)]
- #[must_use]
pub fn mtxpause(&mut self) -> MtxpauseW<Ctrl1Spec> {
MtxpauseW::new(self, 11)
}
}
-#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ctrl1Spec;
impl crate::RegisterSpec for Ctrl1Spec {
type Ux = u32;
diff --git a/va108xx/src/spia/data.rs b/va108xx/src/spia/data.rs
index 30b85c9..b981752 100644
--- a/va108xx/src/spia/data.rs
+++ b/va108xx/src/spia/data.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec;
impl crate::RegisterSpec for DataSpec {
type Ux = u32;
diff --git a/va108xx/src/spia/fifo_clr.rs b/va108xx/src/spia/fifo_clr.rs
index 156da87..af272ab 100644
--- a/va108xx/src/spia/fifo_clr.rs
+++ b/va108xx/src/spia/fifo_clr.rs
@@ -7,18 +7,16 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Clear Rx FIFO"]
#[inline(always)]
- #[must_use]
pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
RxfifoW::new(self, 0)
}
#[doc = "Bit 1 - Clear Tx FIFO"]
#[inline(always)]
- #[must_use]
pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
TxfifoW::new(self, 1)
}
}
-#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoClrSpec;
impl crate::RegisterSpec for FifoClrSpec {
type Ux = u32;
diff --git a/va108xx/src/spia/irq_enb.rs b/va108xx/src/spia/irq_enb.rs
index 68d93bc..d2af91a 100644
--- a/va108xx/src/spia/irq_enb.rs
+++ b/va108xx/src/spia/irq_enb.rs
@@ -43,30 +43,26 @@ impl R {
impl W {
#[doc = "Bit 0 - RX Overrun"]
#[inline(always)]
- #[must_use]
pub fn rorim(&mut self) -> RorimW<IrqEnbSpec> {
RorimW::new(self, 0)
}
#[doc = "Bit 1 - RX Timeout"]
#[inline(always)]
- #[must_use]
pub fn rtim(&mut self) -> RtimW<IrqEnbSpec> {
RtimW::new(self, 1)
}
#[doc = "Bit 2 - RX Fifo is at least half full"]
#[inline(always)]
- #[must_use]
pub fn rxim(&mut self) -> RximW<IrqEnbSpec> {
RximW::new(self, 2)
}
#[doc = "Bit 3 - TX Fifo is at least half empty"]
#[inline(always)]
- #[must_use]
pub fn txim(&mut self) -> TximW<IrqEnbSpec> {
TximW::new(self, 3)
}
}
-#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32;
diff --git a/va108xx/src/spia/perid.rs b/va108xx/src/spia/perid.rs
index fe8dddc..de2abb0 100644
--- a/va108xx/src/spia/perid.rs
+++ b/va108xx/src/spia/perid.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;
diff --git a/va108xx/src/spia/rxfifoirqtrg.rs b/va108xx/src/spia/rxfifoirqtrg.rs
index 46124d5..8376847 100644
--- a/va108xx/src/spia/rxfifoirqtrg.rs
+++ b/va108xx/src/spia/rxfifoirqtrg.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxfifoirqtrgSpec;
impl crate::RegisterSpec for RxfifoirqtrgSpec {
type Ux = u32;
diff --git a/va108xx/src/spia/state.rs b/va108xx/src/spia/state.rs
index aaa69d0..96de72f 100644
--- a/va108xx/src/spia/state.rs
+++ b/va108xx/src/spia/state.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Internal STATE of SPI Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StateSpec;
impl crate::RegisterSpec for StateSpec {
type Ux = u32;
diff --git a/va108xx/src/spia/status.rs b/va108xx/src/spia/status.rs
index d076d06..1bb2587 100644
--- a/va108xx/src/spia/status.rs
+++ b/va108xx/src/spia/status.rs
@@ -58,7 +58,7 @@ impl R {
TxtriggerR::new(((self.bits >> 7) & 1) != 0)
}
}
-#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatusSpec;
impl crate::RegisterSpec for StatusSpec {
type Ux = u32;
diff --git a/va108xx/src/spia/txfifoirqtrg.rs b/va108xx/src/spia/txfifoirqtrg.rs
index 0d13e54..8d0ae92 100644
--- a/va108xx/src/spia/txfifoirqtrg.rs
+++ b/va108xx/src/spia/txfifoirqtrg.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxfifoirqtrgSpec;
impl crate::RegisterSpec for TxfifoirqtrgSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig.rs b/va108xx/src/sysconfig.rs
index 482b2e4..2f1dc5c 100644
--- a/va108xx/src/sysconfig.rs
+++ b/va108xx/src/sysconfig.rs
@@ -131,6 +131,8 @@ impl RegisterBlock {
&self.ioconfig_clkdiv0
}
#[doc = "0x4c..0x68 - IO Configuration Clock Divider Register"]
+ #[doc = ""]
+ #[doc = "<div class=\"warning\">`n` is the index of register in the array. `n == 0` corresponds to `IOCONFIG_CLKDIV1` register.</div>"]
#[inline(always)]
pub const fn ioconfig_clkdiv(&self, n: usize) -> &IoconfigClkdiv {
&self.ioconfig_clkdiv[n]
@@ -232,7 +234,7 @@ impl RegisterBlock {
&self.perid
}
}
-#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`]
+#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`]
module"]
#[doc(alias = "RST_STAT")]
pub type RstStat = crate::Reg<rst_stat::RstStatSpec>;
@@ -242,13 +244,13 @@ pub use rst_stat as rst_cntl_rom;
pub use rst_stat as rst_cntl_ram;
pub use RstStat as RstCntlRom;
pub use RstStat as RstCntlRam;
-#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`]
+#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`]
module"]
#[doc(alias = "ROM_PROT")]
pub type RomProt = crate::Reg<rom_prot::RomProtSpec>;
#[doc = "ROM Protection Configuration"]
pub mod rom_prot;
-#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`]
+#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`]
module"]
#[doc(alias = "ROM_SCRUB")]
pub type RomScrub = crate::Reg<rom_scrub::RomScrubSpec>;
@@ -256,13 +258,13 @@ pub type RomScrub = crate::Reg<rom_scrub::RomScrubSpec>;
pub mod rom_scrub;
pub use rom_scrub as ram_scrub;
pub use RomScrub as RamScrub;
-#[doc = "ROM_TRAP_ADDR (rw) register accessor: ROM Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_addr`]
+#[doc = "ROM_TRAP_ADDR (rw) register accessor: ROM Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_addr`]
module"]
#[doc(alias = "ROM_TRAP_ADDR")]
pub type RomTrapAddr = crate::Reg<rom_trap_addr::RomTrapAddrSpec>;
#[doc = "ROM Trap Address"]
pub mod rom_trap_addr;
-#[doc = "ROM_TRAP_SYND (rw) register accessor: ROM Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_synd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`]
+#[doc = "ROM_TRAP_SYND (rw) register accessor: ROM Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`]
module"]
#[doc(alias = "ROM_TRAP_SYND")]
pub type RomTrapSynd = crate::Reg<rom_trap_synd::RomTrapSyndSpec>;
@@ -272,7 +274,7 @@ pub use rom_trap_addr as ram_trap_addr;
pub use rom_trap_synd as ram_trap_synd;
pub use RomTrapAddr as RamTrapAddr;
pub use RomTrapSynd as RamTrapSynd;
-#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"]
#[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
@@ -284,7 +286,7 @@ pub use irq_enb as irq_clr;
pub use IrqEnb as IrqRaw;
pub use IrqEnb as IrqEnd;
pub use IrqEnb as IrqClr;
-#[doc = "RAM_SBE (rw) register accessor: Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_sbe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_sbe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sbe`]
+#[doc = "RAM_SBE (rw) register accessor: Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sbe`]
module"]
#[doc(alias = "RAM_SBE")]
pub type RamSbe = crate::Reg<ram_sbe::RamSbeSpec>;
@@ -296,79 +298,79 @@ pub use ram_sbe as rom_mbe;
pub use RamSbe as RamMbe;
pub use RamSbe as RomSbe;
pub use RamSbe as RomMbe;
-#[doc = "IOCONFIG_CLKDIV0 (r) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv0`]
+#[doc = "IOCONFIG_CLKDIV0 (r) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv0`]
module"]
#[doc(alias = "IOCONFIG_CLKDIV0")]
pub type IoconfigClkdiv0 = crate::Reg<ioconfig_clkdiv0::IoconfigClkdiv0Spec>;
#[doc = "IO Configuration Clock Divider Register"]
pub mod ioconfig_clkdiv0;
-#[doc = "IOCONFIG_CLKDIV (rw) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv`]
+#[doc = "IOCONFIG_CLKDIV (rw) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv`]
module"]
#[doc(alias = "IOCONFIG_CLKDIV")]
pub type IoconfigClkdiv = crate::Reg<ioconfig_clkdiv::IoconfigClkdivSpec>;
#[doc = "IO Configuration Clock Divider Register"]
pub mod ioconfig_clkdiv;
-#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`]
+#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`]
module"]
#[doc(alias = "ROM_RETRIES")]
pub type RomRetries = crate::Reg<rom_retries::RomRetriesSpec>;
#[doc = "ROM BOOT Retry count"]
pub mod rom_retries;
-#[doc = "REFRESH_CONFIG (rw) register accessor: Register Refresh Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config`]
+#[doc = "REFRESH_CONFIG (rw) register accessor: Register Refresh Control\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config`]
module"]
#[doc(alias = "REFRESH_CONFIG")]
pub type RefreshConfig = crate::Reg<refresh_config::RefreshConfigSpec>;
#[doc = "Register Refresh Control"]
pub mod refresh_config;
-#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`]
+#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`]
module"]
#[doc(alias = "TIM_RESET")]
pub type TimReset = crate::Reg<tim_reset::TimResetSpec>;
#[doc = "TIM Reset Control"]
pub mod tim_reset;
-#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`]
+#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`]
module"]
#[doc(alias = "TIM_CLK_ENABLE")]
pub type TimClkEnable = crate::Reg<tim_clk_enable::TimClkEnableSpec>;
#[doc = "TIM Enable Control"]
pub mod tim_clk_enable;
-#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`]
+#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`]
module"]
#[doc(alias = "PERIPHERAL_RESET")]
pub type PeripheralReset = crate::Reg<peripheral_reset::PeripheralResetSpec>;
#[doc = "Peripheral Reset Control"]
pub mod peripheral_reset;
-#[doc = "PERIPHERAL_CLK_ENABLE (rw) register accessor: Peripheral Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_clk_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_clk_enable`]
+#[doc = "PERIPHERAL_CLK_ENABLE (rw) register accessor: Peripheral Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_clk_enable`]
module"]
#[doc(alias = "PERIPHERAL_CLK_ENABLE")]
pub type PeripheralClkEnable = crate::Reg<peripheral_clk_enable::PeripheralClkEnableSpec>;
#[doc = "Peripheral Enable Control"]
pub mod peripheral_clk_enable;
-#[doc = "LOCKUP_RESET (rw) register accessor: Lockup Reset Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lockup_reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lockup_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lockup_reset`]
+#[doc = "LOCKUP_RESET (rw) register accessor: Lockup Reset Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lockup_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockup_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lockup_reset`]
module"]
#[doc(alias = "LOCKUP_RESET")]
pub type LockupReset = crate::Reg<lockup_reset::LockupResetSpec>;
#[doc = "Lockup Reset Configuration"]
pub mod lockup_reset;
-#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`]
+#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`]
module"]
#[doc(alias = "EF_CONFIG")]
pub type EfConfig = crate::Reg<ef_config::EfConfigSpec>;
#[doc = "EFuse Config Register"]
pub mod ef_config;
-#[doc = "EF_ID (r) register accessor: EFuse ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id`]
+#[doc = "EF_ID (r) register accessor: EFuse ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id`]
module"]
#[doc(alias = "EF_ID")]
pub type EfId = crate::Reg<ef_id::EfIdSpec>;
#[doc = "EFuse ID Register"]
pub mod ef_id;
-#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`]
+#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`]
module"]
#[doc(alias = "PROCID")]
pub type Procid = crate::Reg<procid::ProcidSpec>;
#[doc = "Processor ID Register"]
pub mod procid;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>;
diff --git a/va108xx/src/sysconfig/ef_config.rs b/va108xx/src/sysconfig/ef_config.rs
index f553fbf..db0d3c8 100644
--- a/va108xx/src/sysconfig/ef_config.rs
+++ b/va108xx/src/sysconfig/ef_config.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EfConfigSpec;
impl crate::RegisterSpec for EfConfigSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/ef_id.rs b/va108xx/src/sysconfig/ef_id.rs
index a7a8ccb..08e4a1c 100644
--- a/va108xx/src/sysconfig/ef_id.rs
+++ b/va108xx/src/sysconfig/ef_id.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "EFuse ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "EFuse ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EfIdSpec;
impl crate::RegisterSpec for EfIdSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/ioconfig_clkdiv.rs b/va108xx/src/sysconfig/ioconfig_clkdiv.rs
index 9615226..80d69d3 100644
--- a/va108xx/src/sysconfig/ioconfig_clkdiv.rs
+++ b/va108xx/src/sysconfig/ioconfig_clkdiv.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IoconfigClkdivSpec;
impl crate::RegisterSpec for IoconfigClkdivSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/ioconfig_clkdiv0.rs b/va108xx/src/sysconfig/ioconfig_clkdiv0.rs
index f510375..9fb41a2 100644
--- a/va108xx/src/sysconfig/ioconfig_clkdiv0.rs
+++ b/va108xx/src/sysconfig/ioconfig_clkdiv0.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ioconfig_clkdiv0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IoconfigClkdiv0Spec;
impl crate::RegisterSpec for IoconfigClkdiv0Spec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/irq_enb.rs b/va108xx/src/sysconfig/irq_enb.rs
index bbcd84f..5566dbc 100644
--- a/va108xx/src/sysconfig/irq_enb.rs
+++ b/va108xx/src/sysconfig/irq_enb.rs
@@ -43,30 +43,26 @@ impl R {
impl W {
#[doc = "Bit 0 - RAM Single Bit Interrupt"]
#[inline(always)]
- #[must_use]
pub fn ramsbe(&mut self) -> RamsbeW<IrqEnbSpec> {
RamsbeW::new(self, 0)
}
#[doc = "Bit 1 - RAM Multi Bit Interrupt"]
#[inline(always)]
- #[must_use]
pub fn rammbe(&mut self) -> RammbeW<IrqEnbSpec> {
RammbeW::new(self, 1)
}
#[doc = "Bit 2 - ROM Single Bit Interrupt"]
#[inline(always)]
- #[must_use]
pub fn romsbe(&mut self) -> RomsbeW<IrqEnbSpec> {
RomsbeW::new(self, 2)
}
#[doc = "Bit 3 - ROM Multi Bit Interrupt"]
#[inline(always)]
- #[must_use]
pub fn rommbe(&mut self) -> RommbeW<IrqEnbSpec> {
RommbeW::new(self, 3)
}
}
-#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/lockup_reset.rs b/va108xx/src/sysconfig/lockup_reset.rs
index 0a0afd7..01a8373 100644
--- a/va108xx/src/sysconfig/lockup_reset.rs
+++ b/va108xx/src/sysconfig/lockup_reset.rs
@@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bit 0 - Lockup Reset Enable Bit"]
#[inline(always)]
- #[must_use]
pub fn lren(&mut self) -> LrenW<LockupResetSpec> {
LrenW::new(self, 0)
}
}
-#[doc = "Lockup Reset Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lockup_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lockup_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Lockup Reset Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lockup_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockup_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LockupResetSpec;
impl crate::RegisterSpec for LockupResetSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/perid.rs b/va108xx/src/sysconfig/perid.rs
index 5a84e29..716aa3f 100644
--- a/va108xx/src/sysconfig/perid.rs
+++ b/va108xx/src/sysconfig/perid.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/peripheral_clk_enable.rs b/va108xx/src/sysconfig/peripheral_clk_enable.rs
index 46a6025..e98a9ae 100644
--- a/va108xx/src/sysconfig/peripheral_clk_enable.rs
+++ b/va108xx/src/sysconfig/peripheral_clk_enable.rs
@@ -145,91 +145,78 @@ clock"]
impl W {
#[doc = "Bit 0 - Enable PORTA clock"]
#[inline(always)]
- #[must_use]
pub fn porta(&mut self) -> PortaW<PeripheralClkEnableSpec> {
PortaW::new(self, 0)
}
#[doc = "Bit 1 - Enable PORTB clock"]
#[inline(always)]
- #[must_use]
pub fn portb(&mut self) -> PortbW<PeripheralClkEnableSpec> {
PortbW::new(self, 1)
}
#[doc = "Bit 4 - Enable SPI\\[0\\]
clock"]
#[inline(always)]
- #[must_use]
pub fn spi_0(&mut self) -> Spi0W<PeripheralClkEnableSpec> {
Spi0W::new(self, 4)
}
#[doc = "Bit 5 - Enable SPI\\[1\\]
clock"]
#[inline(always)]
- #[must_use]
pub fn spi_1(&mut self) -> Spi1W<PeripheralClkEnableSpec> {
Spi1W::new(self, 5)
}
#[doc = "Bit 6 - Enable SPI\\[2\\]
clock"]
#[inline(always)]
- #[must_use]
pub fn spi_2(&mut self) -> Spi2W<PeripheralClkEnableSpec> {
Spi2W::new(self, 6)
}
#[doc = "Bit 8 - Enable UART\\[0\\]
clock"]
#[inline(always)]
- #[must_use]
pub fn uart_0(&mut self) -> Uart0W<PeripheralClkEnableSpec> {
Uart0W::new(self, 8)
}
#[doc = "Bit 9 - Enable UART\\[1\\]
clock"]
#[inline(always)]
- #[must_use]
pub fn uart_1(&mut self) -> Uart1W<PeripheralClkEnableSpec> {
Uart1W::new(self, 9)
}
#[doc = "Bit 16 - Enable I2C\\[0\\]
clock"]
#[inline(always)]
- #[must_use]
pub fn i2c_0(&mut self) -> I2c0W<PeripheralClkEnableSpec> {
I2c0W::new(self, 16)
}
#[doc = "Bit 17 - Enable I2C\\[1\\]
clock"]
#[inline(always)]
- #[must_use]
pub fn i2c_1(&mut self) -> I2c1W<PeripheralClkEnableSpec> {
I2c1W::new(self, 17)
}
#[doc = "Bit 21 - Enable IRQ selector clock"]
#[inline(always)]
- #[must_use]
pub fn irqsel(&mut self) -> IrqselW<PeripheralClkEnableSpec> {
IrqselW::new(self, 21)
}
#[doc = "Bit 22 - Enable IO Configuration block clock"]
#[inline(always)]
- #[must_use]
pub fn ioconfig(&mut self) -> IoconfigW<PeripheralClkEnableSpec> {
IoconfigW::new(self, 22)
}
#[doc = "Bit 23 - Enable utility clock"]
#[inline(always)]
- #[must_use]
pub fn utility(&mut self) -> UtilityW<PeripheralClkEnableSpec> {
UtilityW::new(self, 23)
}
#[doc = "Bit 24 - Enable GPIO clock"]
#[inline(always)]
- #[must_use]
pub fn gpio(&mut self) -> GpioW<PeripheralClkEnableSpec> {
GpioW::new(self, 24)
}
}
-#[doc = "Peripheral Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_clk_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_clk_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeripheralClkEnableSpec;
impl crate::RegisterSpec for PeripheralClkEnableSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/peripheral_reset.rs b/va108xx/src/sysconfig/peripheral_reset.rs
index 4f302d7..e12390e 100644
--- a/va108xx/src/sysconfig/peripheral_reset.rs
+++ b/va108xx/src/sysconfig/peripheral_reset.rs
@@ -124,84 +124,71 @@ impl R {
impl W {
#[doc = "Bit 0 - Reset PORTA"]
#[inline(always)]
- #[must_use]
pub fn porta(&mut self) -> PortaW<PeripheralResetSpec> {
PortaW::new(self, 0)
}
#[doc = "Bit 1 - Reset PORTB"]
#[inline(always)]
- #[must_use]
pub fn portb(&mut self) -> PortbW<PeripheralResetSpec> {
PortbW::new(self, 1)
}
#[doc = "Bit 4 - Reset SPI\\[0\\]"]
#[inline(always)]
- #[must_use]
pub fn spi_0(&mut self) -> Spi0W<PeripheralResetSpec> {
Spi0W::new(self, 4)
}
#[doc = "Bit 5 - Reset SPI\\[1\\]"]
#[inline(always)]
- #[must_use]
pub fn spi_1(&mut self) -> Spi1W<PeripheralResetSpec> {
Spi1W::new(self, 5)
}
#[doc = "Bit 6 - Reset SPI\\[2\\]"]
#[inline(always)]
- #[must_use]
pub fn spi_2(&mut self) -> Spi2W<PeripheralResetSpec> {
Spi2W::new(self, 6)
}
#[doc = "Bit 8 - Reset UART\\[0\\]"]
#[inline(always)]
- #[must_use]
pub fn uart_0(&mut self) -> Uart0W<PeripheralResetSpec> {
Uart0W::new(self, 8)
}
#[doc = "Bit 9 - Reset UART\\[1\\]"]
#[inline(always)]
- #[must_use]
pub fn uart_1(&mut self) -> Uart1W<PeripheralResetSpec> {
Uart1W::new(self, 9)
}
#[doc = "Bit 16 - Reset I2C\\[0\\]"]
#[inline(always)]
- #[must_use]
pub fn i2c_0(&mut self) -> I2c0W<PeripheralResetSpec> {
I2c0W::new(self, 16)
}
#[doc = "Bit 17 - Reset I2C\\[1\\]"]
#[inline(always)]
- #[must_use]
pub fn i2c_1(&mut self) -> I2c1W<PeripheralResetSpec> {
I2c1W::new(self, 17)
}
#[doc = "Bit 21 - Reset IRQ selector"]
#[inline(always)]
- #[must_use]
pub fn irqsel(&mut self) -> IrqselW<PeripheralResetSpec> {
IrqselW::new(self, 21)
}
#[doc = "Bit 22 - Reset IO Configuration block"]
#[inline(always)]
- #[must_use]
pub fn ioconfig(&mut self) -> IoconfigW<PeripheralResetSpec> {
IoconfigW::new(self, 22)
}
#[doc = "Bit 23 - Reset Utility Block"]
#[inline(always)]
- #[must_use]
pub fn utility(&mut self) -> UtilityW<PeripheralResetSpec> {
UtilityW::new(self, 23)
}
#[doc = "Bit 24 - Reset GPIO"]
#[inline(always)]
- #[must_use]
pub fn gpio(&mut self) -> GpioW<PeripheralResetSpec> {
GpioW::new(self, 24)
}
}
-#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeripheralResetSpec;
impl crate::RegisterSpec for PeripheralResetSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/procid.rs b/va108xx/src/sysconfig/procid.rs
index 203b2fe..935192f 100644
--- a/va108xx/src/sysconfig/procid.rs
+++ b/va108xx/src/sysconfig/procid.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Processor ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`procid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ProcidSpec;
impl crate::RegisterSpec for ProcidSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/ram_sbe.rs b/va108xx/src/sysconfig/ram_sbe.rs
index e3ae75c..635d14e 100644
--- a/va108xx/src/sysconfig/ram_sbe.rs
+++ b/va108xx/src/sysconfig/ram_sbe.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_sbe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_sbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RamSbeSpec;
impl crate::RegisterSpec for RamSbeSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/refresh_config.rs b/va108xx/src/sysconfig/refresh_config.rs
index fd34ab4..5df8ab0 100644
--- a/va108xx/src/sysconfig/refresh_config.rs
+++ b/va108xx/src/sysconfig/refresh_config.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Register Refresh Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Register Refresh Control\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RefreshConfigSpec;
impl crate::RegisterSpec for RefreshConfigSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/rom_prot.rs b/va108xx/src/sysconfig/rom_prot.rs
index 525344e..82e4218 100644
--- a/va108xx/src/sysconfig/rom_prot.rs
+++ b/va108xx/src/sysconfig/rom_prot.rs
@@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bit 0 - ROM Write Enable Bit"]
#[inline(always)]
- #[must_use]
pub fn wren(&mut self) -> WrenW<RomProtSpec> {
WrenW::new(self, 0)
}
}
-#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_prot::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomProtSpec;
impl crate::RegisterSpec for RomProtSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/rom_retries.rs b/va108xx/src/sysconfig/rom_retries.rs
index 2278e6e..35e0d33 100644
--- a/va108xx/src/sysconfig/rom_retries.rs
+++ b/va108xx/src/sysconfig/rom_retries.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_retries::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomRetriesSpec;
impl crate::RegisterSpec for RomRetriesSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/rom_scrub.rs b/va108xx/src/sysconfig/rom_scrub.rs
index 20d5262..906cfdc 100644
--- a/va108xx/src/sysconfig/rom_scrub.rs
+++ b/va108xx/src/sysconfig/rom_scrub.rs
@@ -18,18 +18,16 @@ impl R {
impl W {
#[doc = "Bits 0:23 - Counter divide value"]
#[inline(always)]
- #[must_use]
pub fn value(&mut self) -> ValueW<RomScrubSpec> {
ValueW::new(self, 0)
}
#[doc = "Bit 31 - Reset Counter"]
#[inline(always)]
- #[must_use]
pub fn reset(&mut self) -> ResetW<RomScrubSpec> {
ResetW::new(self, 31)
}
}
-#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_scrub::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomScrubSpec;
impl crate::RegisterSpec for RomScrubSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/rom_trap_addr.rs b/va108xx/src/sysconfig/rom_trap_addr.rs
index a2c45db..0fab1d1 100644
--- a/va108xx/src/sysconfig/rom_trap_addr.rs
+++ b/va108xx/src/sysconfig/rom_trap_addr.rs
@@ -25,18 +25,16 @@ impl R {
impl W {
#[doc = "Bits 2:15 - Trap Address Match Bits"]
#[inline(always)]
- #[must_use]
pub fn addr(&mut self) -> AddrW<RomTrapAddrSpec> {
AddrW::new(self, 2)
}
#[doc = "Bit 31 - Trap Enable Bit"]
#[inline(always)]
- #[must_use]
pub fn enable(&mut self) -> EnableW<RomTrapAddrSpec> {
EnableW::new(self, 31)
}
}
-#[doc = "ROM Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "ROM Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomTrapAddrSpec;
impl crate::RegisterSpec for RomTrapAddrSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/rom_trap_synd.rs b/va108xx/src/sysconfig/rom_trap_synd.rs
index cb7a4e6..0fa69de 100644
--- a/va108xx/src/sysconfig/rom_trap_synd.rs
+++ b/va108xx/src/sysconfig/rom_trap_synd.rs
@@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:19 - Trap Syndrom Bits"]
#[inline(always)]
- #[must_use]
pub fn synd(&mut self) -> SyndW<RomTrapSyndSpec> {
SyndW::new(self, 0)
}
}
-#[doc = "ROM Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_synd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_synd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "ROM Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomTrapSyndSpec;
impl crate::RegisterSpec for RomTrapSyndSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/rst_stat.rs b/va108xx/src/sysconfig/rst_stat.rs
index e671bbd..9d17268 100644
--- a/va108xx/src/sysconfig/rst_stat.rs
+++ b/va108xx/src/sysconfig/rst_stat.rs
@@ -61,42 +61,36 @@ impl R {
impl W {
#[doc = "Bit 0 - Power On Reset Status"]
#[inline(always)]
- #[must_use]
pub fn por(&mut self) -> PorW<RstStatSpec> {
PorW::new(self, 0)
}
#[doc = "Bit 1 - External Reset Status"]
#[inline(always)]
- #[must_use]
pub fn extrst(&mut self) -> ExtrstW<RstStatSpec> {
ExtrstW::new(self, 1)
}
#[doc = "Bit 2 - SYSRESETREQ Reset Status"]
#[inline(always)]
- #[must_use]
pub fn sysrstreq(&mut self) -> SysrstreqW<RstStatSpec> {
SysrstreqW::new(self, 2)
}
#[doc = "Bit 3 - LOOKUP Reset Status"]
#[inline(always)]
- #[must_use]
pub fn lookup(&mut self) -> LookupW<RstStatSpec> {
LookupW::new(self, 3)
}
#[doc = "Bit 4 - WATCHDOG Reset Status"]
#[inline(always)]
- #[must_use]
pub fn watchdog(&mut self) -> WatchdogW<RstStatSpec> {
WatchdogW::new(self, 4)
}
#[doc = "Bit 5 - Memory Error Reset Status"]
#[inline(always)]
- #[must_use]
pub fn memerr(&mut self) -> MemerrW<RstStatSpec> {
MemerrW::new(self, 5)
}
}
-#[doc = "System Reset Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstStatSpec;
impl crate::RegisterSpec for RstStatSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/tim_clk_enable.rs b/va108xx/src/sysconfig/tim_clk_enable.rs
index f0b91e7..d636e34 100644
--- a/va108xx/src/sysconfig/tim_clk_enable.rs
+++ b/va108xx/src/sysconfig/tim_clk_enable.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "TIM Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_clk_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TimClkEnableSpec;
impl crate::RegisterSpec for TimClkEnableSpec {
type Ux = u32;
diff --git a/va108xx/src/sysconfig/tim_reset.rs b/va108xx/src/sysconfig/tim_reset.rs
index 82aceb4..db62288 100644
--- a/va108xx/src/sysconfig/tim_reset.rs
+++ b/va108xx/src/sysconfig/tim_reset.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "TIM Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TimResetSpec;
impl crate::RegisterSpec for TimResetSpec {
type Ux = u32;
diff --git a/va108xx/src/tim0.rs b/va108xx/src/tim0.rs
index 7b3ad32..82190a3 100644
--- a/va108xx/src/tim0.rs
+++ b/va108xx/src/tim0.rs
@@ -58,12 +58,12 @@ impl RegisterBlock {
#[doc = "0x20 - The Pulse Width Modulation ValueA"]
#[inline(always)]
pub const fn pwma_value(&self) -> &PwmaValue {
- unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
}
#[doc = "0x20 - The Pulse Width Modulation Value"]
#[inline(always)]
pub const fn pwm_value(&self) -> &PwmValue {
- unsafe { &*(self as *const Self).cast::<u8>().add(32).cast() }
+ unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).cast() }
}
#[doc = "0x24 - The Pulse Width Modulation ValueB"]
#[inline(always)]
@@ -76,37 +76,37 @@ impl RegisterBlock {
&self.perid
}
}
-#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
module"]
#[doc(alias = "CTRL")]
pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
#[doc = "Control Register"]
pub mod ctrl;
-#[doc = "RST_VALUE (rw) register accessor: The value that counter start from after reaching 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_value`]
+#[doc = "RST_VALUE (rw) register accessor: The value that counter start from after reaching 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_value`]
module"]
#[doc(alias = "RST_VALUE")]
pub type RstValue = crate::Reg<rst_value::RstValueSpec>;
#[doc = "The value that counter start from after reaching 0."]
pub mod rst_value;
-#[doc = "CNT_VALUE (rw) register accessor: The current value of the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt_value`]
+#[doc = "CNT_VALUE (rw) register accessor: The current value of the counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt_value`]
module"]
#[doc(alias = "CNT_VALUE")]
pub type CntValue = crate::Reg<cnt_value::CntValueSpec>;
#[doc = "The current value of the counter"]
pub mod cnt_value;
-#[doc = "ENABLE (rw) register accessor: Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`]
+#[doc = "ENABLE (rw) register accessor: Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`]
module"]
#[doc(alias = "ENABLE")]
pub type Enable = crate::Reg<enable::EnableSpec>;
#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register"]
pub mod enable;
-#[doc = "CSD_CTRL (rw) register accessor: The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csd_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csd_ctrl`]
+#[doc = "CSD_CTRL (rw) register accessor: The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::Reg::read) this register and get [`csd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csd_ctrl`]
module"]
#[doc(alias = "CSD_CTRL")]
pub type CsdCtrl = crate::Reg<csd_ctrl::CsdCtrlSpec>;
#[doc = "The Cascade Control Register. Controls the counter external enable signals"]
pub mod csd_ctrl;
-#[doc = "CASCADE0 (rw) register accessor: Cascade Enable Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cascade0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cascade0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cascade0`]
+#[doc = "CASCADE0 (rw) register accessor: Cascade Enable Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`cascade0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cascade0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cascade0`]
module"]
#[doc(alias = "CASCADE0")]
pub type Cascade0 = crate::Reg<cascade0::Cascade0Spec>;
@@ -116,25 +116,25 @@ pub use cascade0 as cascade1;
pub use cascade0 as cascade2;
pub use Cascade0 as Cascade1;
pub use Cascade0 as Cascade2;
-#[doc = "PWM_VALUE (rw) register accessor: The Pulse Width Modulation Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_value`]
+#[doc = "PWM_VALUE (rw) register accessor: The Pulse Width Modulation Value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_value`]
module"]
#[doc(alias = "PWM_VALUE")]
pub type PwmValue = crate::Reg<pwm_value::PwmValueSpec>;
#[doc = "The Pulse Width Modulation Value"]
pub mod pwm_value;
-#[doc = "PWMA_VALUE (rw) register accessor: The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwma_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwma_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwma_value`]
+#[doc = "PWMA_VALUE (rw) register accessor: The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::Reg::read) this register and get [`pwma_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwma_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwma_value`]
module"]
#[doc(alias = "PWMA_VALUE")]
pub type PwmaValue = crate::Reg<pwma_value::PwmaValueSpec>;
#[doc = "The Pulse Width Modulation ValueA"]
pub mod pwma_value;
-#[doc = "PWMB_VALUE (rw) register accessor: The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmb_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmb_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmb_value`]
+#[doc = "PWMB_VALUE (rw) register accessor: The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmb_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmb_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmb_value`]
module"]
#[doc(alias = "PWMB_VALUE")]
pub type PwmbValue = crate::Reg<pwmb_value::PwmbValueSpec>;
#[doc = "The Pulse Width Modulation ValueB"]
pub mod pwmb_value;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>;
diff --git a/va108xx/src/tim0/cascade0.rs b/va108xx/src/tim0/cascade0.rs
index 984dd73..3714cd5 100644
--- a/va108xx/src/tim0/cascade0.rs
+++ b/va108xx/src/tim0/cascade0.rs
@@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:7 - Cascade Selection"]
#[inline(always)]
- #[must_use]
pub fn cassel(&mut self) -> CasselW<Cascade0Spec> {
CasselW::new(self, 0)
}
}
-#[doc = "Cascade Enable Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cascade0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cascade0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Cascade Enable Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`cascade0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cascade0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cascade0Spec;
impl crate::RegisterSpec for Cascade0Spec {
type Ux = u32;
diff --git a/va108xx/src/tim0/cnt_value.rs b/va108xx/src/tim0/cnt_value.rs
index f5ee38a..7ae8efe 100644
--- a/va108xx/src/tim0/cnt_value.rs
+++ b/va108xx/src/tim0/cnt_value.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "The current value of the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "The current value of the counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntValueSpec;
impl crate::RegisterSpec for CntValueSpec {
type Ux = u32;
diff --git a/va108xx/src/tim0/csd_ctrl.rs b/va108xx/src/tim0/csd_ctrl.rs
index 2a53a5b..6e17a7d 100644
--- a/va108xx/src/tim0/csd_ctrl.rs
+++ b/va108xx/src/tim0/csd_ctrl.rs
@@ -106,72 +106,61 @@ impl R {
impl W {
#[doc = "Bit 0 - Cascade 0 Enable"]
#[inline(always)]
- #[must_use]
pub fn csden0(&mut self) -> Csden0W<CsdCtrlSpec> {
Csden0W::new(self, 0)
}
#[doc = "Bit 1 - Cascade 0 Invert"]
#[inline(always)]
- #[must_use]
pub fn csdinv0(&mut self) -> Csdinv0W<CsdCtrlSpec> {
Csdinv0W::new(self, 1)
}
#[doc = "Bit 2 - Cascade 1 Enable"]
#[inline(always)]
- #[must_use]
pub fn csden1(&mut self) -> Csden1W<CsdCtrlSpec> {
Csden1W::new(self, 2)
}
#[doc = "Bit 3 - Cascade 1 Invert"]
#[inline(always)]
- #[must_use]
pub fn csdinv1(&mut self) -> Csdinv1W<CsdCtrlSpec> {
Csdinv1W::new(self, 3)
}
#[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"]
#[inline(always)]
- #[must_use]
pub fn dcasop(&mut self) -> DcasopW<CsdCtrlSpec> {
DcasopW::new(self, 4)
}
#[doc = "Bit 6 - Cascade 0 Enabled as Trigger"]
#[inline(always)]
- #[must_use]
pub fn csdtrg0(&mut self) -> Csdtrg0W<CsdCtrlSpec> {
Csdtrg0W::new(self, 6)
}
#[doc = "Bit 7 - Cascade 1 Enabled as Trigger"]
#[inline(always)]
- #[must_use]
pub fn csdtrg1(&mut self) -> Csdtrg1W<CsdCtrlSpec> {
Csdtrg1W::new(self, 7)
}
#[doc = "Bit 8 - Cascade 2 Enable"]
#[inline(always)]
- #[must_use]
pub fn csden2(&mut self) -> Csden2W<CsdCtrlSpec> {
Csden2W::new(self, 8)
}
#[doc = "Bit 9 - Cascade 2 Invert"]
#[inline(always)]
- #[must_use]
pub fn csdinv2(&mut self) -> Csdinv2W<CsdCtrlSpec> {
Csdinv2W::new(self, 9)
}
#[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
#[inline(always)]
- #[must_use]
pub fn csdtrg2(&mut self) -> Csdtrg2W<CsdCtrlSpec> {
Csdtrg2W::new(self, 10)
}
#[doc = "Bit 11 - Cascade 2 test mode"]
#[inline(always)]
- #[must_use]
pub fn csdxxx2(&mut self) -> Csdxxx2W<CsdCtrlSpec> {
Csdxxx2W::new(self, 11)
}
}
-#[doc = "The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csd_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csd_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::Reg::read) this register and get [`csd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CsdCtrlSpec;
impl crate::RegisterSpec for CsdCtrlSpec {
type Ux = u32;
diff --git a/va108xx/src/tim0/ctrl.rs b/va108xx/src/tim0/ctrl.rs
index 32b2b66..ca33018 100644
--- a/va108xx/src/tim0/ctrl.rs
+++ b/va108xx/src/tim0/ctrl.rs
@@ -32,11 +32,11 @@ pub enum StatusSel {
Toggle = 2,
#[doc = "3: Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"]
Pwma = 3,
- #[doc = "4: Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
+ #[doc = "4: Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
Pwmb = 4,
#[doc = "5: Returns the counter ENABLED bit"]
Enabled = 5,
- #[doc = "6: Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
+ #[doc = "6: Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
PwmaActive = 6,
}
impl From<StatusSel> for u8 {
@@ -86,7 +86,7 @@ impl StatusSelR {
pub fn is_pwma(&self) -> bool {
*self == StatusSel::Pwma
}
- #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
+ #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
#[inline(always)]
pub fn is_pwmb(&self) -> bool {
*self == StatusSel::Pwmb
@@ -96,7 +96,7 @@ impl StatusSelR {
pub fn is_enabled(&self) -> bool {
*self == StatusSel::Enabled
}
- #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
+ #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
#[inline(always)]
pub fn is_pwma_active(&self) -> bool {
*self == StatusSel::PwmaActive
@@ -129,7 +129,7 @@ where
pub fn pwma(self) -> &'a mut crate::W<REG> {
self.variant(StatusSel::Pwma)
}
- #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
+ #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
#[inline(always)]
pub fn pwmb(self) -> &'a mut crate::W<REG> {
self.variant(StatusSel::Pwmb)
@@ -139,7 +139,7 @@ where
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(StatusSel::Enabled)
}
- #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
+ #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
#[inline(always)]
pub fn pwma_active(self) -> &'a mut crate::W<REG> {
self.variant(StatusSel::PwmaActive)
@@ -198,48 +198,41 @@ impl R {
impl W {
#[doc = "Bit 0 - Counter Enable"]
#[inline(always)]
- #[must_use]
pub fn enable(&mut self) -> EnableW<CtrlSpec> {
EnableW::new(self, 0)
}
#[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
#[inline(always)]
- #[must_use]
pub fn auto_disable(&mut self) -> AutoDisableW<CtrlSpec> {
AutoDisableW::new(self, 2)
}
#[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
#[inline(always)]
- #[must_use]
pub fn auto_deactivate(&mut self) -> AutoDeactivateW<CtrlSpec> {
AutoDeactivateW::new(self, 3)
}
#[doc = "Bit 4 - Interrupt Enable"]
#[inline(always)]
- #[must_use]
pub fn irq_enb(&mut self) -> IrqEnbW<CtrlSpec> {
IrqEnbW::new(self, 4)
}
#[doc = "Bits 5:7 - Counter Status Selection"]
#[inline(always)]
- #[must_use]
pub fn status_sel(&mut self) -> StatusSelW<CtrlSpec> {
StatusSelW::new(self, 5)
}
#[doc = "Bit 8 - Invert the Output Status"]
#[inline(always)]
- #[must_use]
pub fn status_inv(&mut self) -> StatusInvW<CtrlSpec> {
StatusInvW::new(self, 8)
}
#[doc = "Bit 9 - Stop Request"]
#[inline(always)]
- #[must_use]
pub fn req_stop(&mut self) -> ReqStopW<CtrlSpec> {
ReqStopW::new(self, 9)
}
}
-#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec;
impl crate::RegisterSpec for CtrlSpec {
type Ux = u32;
diff --git a/va108xx/src/tim0/enable.rs b/va108xx/src/tim0/enable.rs
index 2064cab..924e2a8 100644
--- a/va108xx/src/tim0/enable.rs
+++ b/va108xx/src/tim0/enable.rs
@@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bit 0 - Counter Enable"]
#[inline(always)]
- #[must_use]
pub fn enable(&mut self) -> EnableW<EnableSpec> {
EnableW::new(self, 0)
}
}
-#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EnableSpec;
impl crate::RegisterSpec for EnableSpec {
type Ux = u32;
diff --git a/va108xx/src/tim0/perid.rs b/va108xx/src/tim0/perid.rs
index 75f49ab..3d405f8 100644
--- a/va108xx/src/tim0/perid.rs
+++ b/va108xx/src/tim0/perid.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;
diff --git a/va108xx/src/tim0/pwm_value.rs b/va108xx/src/tim0/pwm_value.rs
index b3b1480..0501c17 100644
--- a/va108xx/src/tim0/pwm_value.rs
+++ b/va108xx/src/tim0/pwm_value.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "The Pulse Width Modulation Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "The Pulse Width Modulation Value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PwmValueSpec;
impl crate::RegisterSpec for PwmValueSpec {
type Ux = u32;
diff --git a/va108xx/src/tim0/pwma_value.rs b/va108xx/src/tim0/pwma_value.rs
index ec26532..9536145 100644
--- a/va108xx/src/tim0/pwma_value.rs
+++ b/va108xx/src/tim0/pwma_value.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwma_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwma_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::Reg::read) this register and get [`pwma_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwma_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PwmaValueSpec;
impl crate::RegisterSpec for PwmaValueSpec {
type Ux = u32;
diff --git a/va108xx/src/tim0/pwmb_value.rs b/va108xx/src/tim0/pwmb_value.rs
index 587cb50..803f9df 100644
--- a/va108xx/src/tim0/pwmb_value.rs
+++ b/va108xx/src/tim0/pwmb_value.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmb_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmb_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmb_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmb_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PwmbValueSpec;
impl crate::RegisterSpec for PwmbValueSpec {
type Ux = u32;
diff --git a/va108xx/src/tim0/rst_value.rs b/va108xx/src/tim0/rst_value.rs
index 2dfa5b4..76c0ddb 100644
--- a/va108xx/src/tim0/rst_value.rs
+++ b/va108xx/src/tim0/rst_value.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "The value that counter start from after reaching 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "The value that counter start from after reaching 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstValueSpec;
impl crate::RegisterSpec for RstValueSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta.rs b/va108xx/src/uarta.rs
index 71aa47b..0a056ad 100644
--- a/va108xx/src/uarta.rs
+++ b/va108xx/src/uarta.rs
@@ -119,67 +119,67 @@ impl RegisterBlock {
&self.perid
}
}
-#[doc = "DATA (rw) register accessor: Data In/Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+#[doc = "DATA (rw) register accessor: Data In/Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
module"]
#[doc(alias = "DATA")]
pub type Data = crate::Reg<data::DataSpec>;
#[doc = "Data In/Out Register"]
pub mod data;
-#[doc = "ENABLE (rw) register accessor: Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`]
+#[doc = "ENABLE (rw) register accessor: Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`]
module"]
#[doc(alias = "ENABLE")]
pub type Enable = crate::Reg<enable::EnableSpec>;
#[doc = "Enable Register"]
pub mod enable;
-#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
module"]
#[doc(alias = "CTRL")]
pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
#[doc = "Control Register"]
pub mod ctrl;
-#[doc = "CLKSCALE (rw) register accessor: Clock Scale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
+#[doc = "CLKSCALE (rw) register accessor: Clock Scale Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
module"]
#[doc(alias = "CLKSCALE")]
pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
#[doc = "Clock Scale Register"]
pub mod clkscale;
-#[doc = "RXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxstatus`]
+#[doc = "RXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxstatus`]
module"]
#[doc(alias = "RXSTATUS")]
pub type Rxstatus = crate::Reg<rxstatus::RxstatusSpec>;
#[doc = "Status Register"]
pub mod rxstatus;
-#[doc = "TXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txstatus`]
+#[doc = "TXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txstatus`]
module"]
#[doc(alias = "TXSTATUS")]
pub type Txstatus = crate::Reg<txstatus::TxstatusSpec>;
#[doc = "Status Register"]
pub mod txstatus;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
module"]
#[doc(alias = "FIFO_CLR")]
pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
#[doc = "Clear FIFO Register"]
pub mod fifo_clr;
-#[doc = "TXBREAK (w) register accessor: Break Transmit Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbreak::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbreak`]
+#[doc = "TXBREAK (w) register accessor: Break Transmit Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbreak::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbreak`]
module"]
#[doc(alias = "TXBREAK")]
pub type Txbreak = crate::Reg<txbreak::TxbreakSpec>;
#[doc = "Break Transmit Register"]
pub mod txbreak;
-#[doc = "ADDR9 (rw) register accessor: Address9 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9`]
+#[doc = "ADDR9 (rw) register accessor: Address9 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9`]
module"]
#[doc(alias = "ADDR9")]
pub type Addr9 = crate::Reg<addr9::Addr9Spec>;
#[doc = "Address9 Register"]
pub mod addr9;
-#[doc = "ADDR9MASK (rw) register accessor: Address9 Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9mask`]
+#[doc = "ADDR9MASK (rw) register accessor: Address9 Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9mask`]
module"]
#[doc(alias = "ADDR9MASK")]
pub type Addr9mask = crate::Reg<addr9mask::Addr9maskSpec>;
#[doc = "Address9 Mask Register"]
pub mod addr9mask;
-#[doc = "IRQ_ENB (rw) register accessor: IRQ Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: IRQ Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
module"]
#[doc(alias = "IRQ_ENB")]
pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
@@ -191,31 +191,31 @@ pub use irq_enb as irq_clr;
pub use IrqEnb as IrqRaw;
pub use IrqEnb as IrqEnd;
pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
module"]
#[doc(alias = "RXFIFOIRQTRG")]
pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
#[doc = "Rx FIFO IRQ Trigger Level"]
pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
module"]
#[doc(alias = "TXFIFOIRQTRG")]
pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
#[doc = "Tx FIFO IRQ Trigger Level"]
pub mod txfifoirqtrg;
-#[doc = "RXFIFORTSTRG (rw) register accessor: Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifortstrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifortstrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifortstrg`]
+#[doc = "RXFIFORTSTRG (rw) register accessor: Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifortstrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifortstrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifortstrg`]
module"]
#[doc(alias = "RXFIFORTSTRG")]
pub type Rxfifortstrg = crate::Reg<rxfifortstrg::RxfifortstrgSpec>;
#[doc = "Rx FIFO RTS Trigger Level"]
pub mod rxfifortstrg;
-#[doc = "STATE (r) register accessor: Internal STATE of UART Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+#[doc = "STATE (r) register accessor: Internal STATE of UART Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
module"]
#[doc(alias = "STATE")]
pub type State = crate::Reg<state::StateSpec>;
#[doc = "Internal STATE of UART Controller"]
pub mod state;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>;
diff --git a/va108xx/src/uarta/addr9.rs b/va108xx/src/uarta/addr9.rs
index bca4484..0c011f2 100644
--- a/va108xx/src/uarta/addr9.rs
+++ b/va108xx/src/uarta/addr9.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Address9 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Address9 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Addr9Spec;
impl crate::RegisterSpec for Addr9Spec {
type Ux = u32;
diff --git a/va108xx/src/uarta/addr9mask.rs b/va108xx/src/uarta/addr9mask.rs
index f96e772..d130f41 100644
--- a/va108xx/src/uarta/addr9mask.rs
+++ b/va108xx/src/uarta/addr9mask.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Address9 Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Address9 Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Addr9maskSpec;
impl crate::RegisterSpec for Addr9maskSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/clkscale.rs b/va108xx/src/uarta/clkscale.rs
index 14a5e79..a8943ac 100644
--- a/va108xx/src/uarta/clkscale.rs
+++ b/va108xx/src/uarta/clkscale.rs
@@ -27,24 +27,21 @@ impl R {
impl W {
#[doc = "Bits 0:5 - Fractional Divide (64ths)"]
#[inline(always)]
- #[must_use]
pub fn frac(&mut self) -> FracW<ClkscaleSpec> {
FracW::new(self, 0)
}
#[doc = "Bits 6:23 - Integer Divide"]
#[inline(always)]
- #[must_use]
pub fn int(&mut self) -> IntW<ClkscaleSpec> {
IntW::new(self, 6)
}
#[doc = "Bit 31 - Reset Baud Counter"]
#[inline(always)]
- #[must_use]
pub fn reset(&mut self) -> ResetW<ClkscaleSpec> {
ResetW::new(self, 31)
}
}
-#[doc = "Clock Scale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clock Scale Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClkscaleSpec;
impl crate::RegisterSpec for ClkscaleSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/ctrl.rs b/va108xx/src/uarta/ctrl.rs
index 965c45a..f802a55 100644
--- a/va108xx/src/uarta/ctrl.rs
+++ b/va108xx/src/uarta/ctrl.rs
@@ -106,72 +106,61 @@ impl R {
impl W {
#[doc = "Bit 0 - Parity Enable"]
#[inline(always)]
- #[must_use]
pub fn paren(&mut self) -> ParenW<CtrlSpec> {
ParenW::new(self, 0)
}
#[doc = "Bit 1 - Parity Even/Odd(1/0)"]
#[inline(always)]
- #[must_use]
pub fn pareven(&mut self) -> ParevenW<CtrlSpec> {
ParevenW::new(self, 1)
}
#[doc = "Bit 2 - Parity Sticky"]
#[inline(always)]
- #[must_use]
pub fn parstk(&mut self) -> ParstkW<CtrlSpec> {
ParstkW::new(self, 2)
}
#[doc = "Bit 3 - Stop Bits 1/2(0/1)"]
#[inline(always)]
- #[must_use]
pub fn stopbits(&mut self) -> StopbitsW<CtrlSpec> {
StopbitsW::new(self, 3)
}
#[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"]
#[inline(always)]
- #[must_use]
pub fn wordsize(&mut self) -> WordsizeW<CtrlSpec> {
WordsizeW::new(self, 4)
}
#[doc = "Bit 6 - Loopback Enable"]
#[inline(always)]
- #[must_use]
pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
LoopbackW::new(self, 6)
}
#[doc = "Bit 7 - Loopback Block"]
#[inline(always)]
- #[must_use]
pub fn loopbackblk(&mut self) -> LoopbackblkW<CtrlSpec> {
LoopbackblkW::new(self, 7)
}
#[doc = "Bit 8 - Enable Auto CTS mode"]
#[inline(always)]
- #[must_use]
pub fn autocts(&mut self) -> AutoctsW<CtrlSpec> {
AutoctsW::new(self, 8)
}
#[doc = "Bit 9 - Default RTSn value"]
#[inline(always)]
- #[must_use]
pub fn defrts(&mut self) -> DefrtsW<CtrlSpec> {
DefrtsW::new(self, 9)
}
#[doc = "Bit 10 - Enable Auto RTS mode"]
#[inline(always)]
- #[must_use]
pub fn autorts(&mut self) -> AutortsW<CtrlSpec> {
AutortsW::new(self, 10)
}
#[doc = "Bit 11 - Enable BAUD8 mode"]
#[inline(always)]
- #[must_use]
pub fn baud8(&mut self) -> Baud8W<CtrlSpec> {
Baud8W::new(self, 11)
}
}
-#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec;
impl crate::RegisterSpec for CtrlSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/data.rs b/va108xx/src/uarta/data.rs
index bc64a6c..f4f09cb 100644
--- a/va108xx/src/uarta/data.rs
+++ b/va108xx/src/uarta/data.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Data In/Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Data In/Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec;
impl crate::RegisterSpec for DataSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/enable.rs b/va108xx/src/uarta/enable.rs
index ad6f797..1ca5964 100644
--- a/va108xx/src/uarta/enable.rs
+++ b/va108xx/src/uarta/enable.rs
@@ -25,18 +25,16 @@ impl R {
impl W {
#[doc = "Bit 0 - Rx Enable"]
#[inline(always)]
- #[must_use]
pub fn rxenable(&mut self) -> RxenableW<EnableSpec> {
RxenableW::new(self, 0)
}
#[doc = "Bit 1 - Tx Enable"]
#[inline(always)]
- #[must_use]
pub fn txenable(&mut self) -> TxenableW<EnableSpec> {
TxenableW::new(self, 1)
}
}
-#[doc = "Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EnableSpec;
impl crate::RegisterSpec for EnableSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/fifo_clr.rs b/va108xx/src/uarta/fifo_clr.rs
index c7e88b4..2d8a0c7 100644
--- a/va108xx/src/uarta/fifo_clr.rs
+++ b/va108xx/src/uarta/fifo_clr.rs
@@ -11,30 +11,26 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Clear Rx Status"]
#[inline(always)]
- #[must_use]
pub fn rxsts(&mut self) -> RxstsW<FifoClrSpec> {
RxstsW::new(self, 0)
}
#[doc = "Bit 1 - Clear Tx Status"]
#[inline(always)]
- #[must_use]
pub fn txsts(&mut self) -> TxstsW<FifoClrSpec> {
TxstsW::new(self, 1)
}
#[doc = "Bit 2 - Clear Rx FIFO"]
#[inline(always)]
- #[must_use]
pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
RxfifoW::new(self, 2)
}
#[doc = "Bit 3 - Clear Tx FIFO"]
#[inline(always)]
- #[must_use]
pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
TxfifoW::new(self, 3)
}
}
-#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoClrSpec;
impl crate::RegisterSpec for FifoClrSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/irq_enb.rs b/va108xx/src/uarta/irq_enb.rs
index 6702628..afadd51 100644
--- a/va108xx/src/uarta/irq_enb.rs
+++ b/va108xx/src/uarta/irq_enb.rs
@@ -70,48 +70,41 @@ impl R {
impl W {
#[doc = "Bit 0 - RX Interrupt"]
#[inline(always)]
- #[must_use]
pub fn irq_rx(&mut self) -> IrqRxW<IrqEnbSpec> {
IrqRxW::new(self, 0)
}
#[doc = "Bit 1 - RX Status Interrupt"]
#[inline(always)]
- #[must_use]
pub fn irq_rx_status(&mut self) -> IrqRxStatusW<IrqEnbSpec> {
IrqRxStatusW::new(self, 1)
}
#[doc = "Bit 2 - RX Timeout Interrupt"]
#[inline(always)]
- #[must_use]
pub fn irq_rx_to(&mut self) -> IrqRxToW<IrqEnbSpec> {
IrqRxToW::new(self, 2)
}
#[doc = "Bit 4 - TX Interrupt"]
#[inline(always)]
- #[must_use]
pub fn irq_tx(&mut self) -> IrqTxW<IrqEnbSpec> {
IrqTxW::new(self, 4)
}
#[doc = "Bit 5 - TX Status Interrupt"]
#[inline(always)]
- #[must_use]
pub fn irq_tx_status(&mut self) -> IrqTxStatusW<IrqEnbSpec> {
IrqTxStatusW::new(self, 5)
}
#[doc = "Bit 6 - TX Empty Interrupt"]
#[inline(always)]
- #[must_use]
pub fn irq_tx_empty(&mut self) -> IrqTxEmptyW<IrqEnbSpec> {
IrqTxEmptyW::new(self, 6)
}
#[doc = "Bit 7 - TX CTS Change Interrupt"]
#[inline(always)]
- #[must_use]
pub fn irq_tx_cts(&mut self) -> IrqTxCtsW<IrqEnbSpec> {
IrqTxCtsW::new(self, 7)
}
}
-#[doc = "IRQ Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "IRQ Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/perid.rs b/va108xx/src/uarta/perid.rs
index fe8dddc..de2abb0 100644
--- a/va108xx/src/uarta/perid.rs
+++ b/va108xx/src/uarta/perid.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/rxfifoirqtrg.rs b/va108xx/src/uarta/rxfifoirqtrg.rs
index 46124d5..8376847 100644
--- a/va108xx/src/uarta/rxfifoirqtrg.rs
+++ b/va108xx/src/uarta/rxfifoirqtrg.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxfifoirqtrgSpec;
impl crate::RegisterSpec for RxfifoirqtrgSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/rxfifortstrg.rs b/va108xx/src/uarta/rxfifortstrg.rs
index dd8afea..2938f15 100644
--- a/va108xx/src/uarta/rxfifortstrg.rs
+++ b/va108xx/src/uarta/rxfifortstrg.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifortstrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifortstrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifortstrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifortstrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxfifortstrgSpec;
impl crate::RegisterSpec for RxfifortstrgSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/rxstatus.rs b/va108xx/src/uarta/rxstatus.rs
index c519eb8..ce5172d 100644
--- a/va108xx/src/uarta/rxstatus.rs
+++ b/va108xx/src/uarta/rxstatus.rs
@@ -79,7 +79,7 @@ impl R {
RxrtsnR::new(((self.bits >> 15) & 1) != 0)
}
}
-#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxstatusSpec;
impl crate::RegisterSpec for RxstatusSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/state.rs b/va108xx/src/uarta/state.rs
index 17ec5bc..ecdf97f 100644
--- a/va108xx/src/uarta/state.rs
+++ b/va108xx/src/uarta/state.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Internal STATE of UART Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Internal STATE of UART Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StateSpec;
impl crate::RegisterSpec for StateSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/txbreak.rs b/va108xx/src/uarta/txbreak.rs
index 69a167f..5e5002f 100644
--- a/va108xx/src/uarta/txbreak.rs
+++ b/va108xx/src/uarta/txbreak.rs
@@ -6,7 +6,7 @@ impl core::fmt::Debug for crate::generic::Reg<TxbreakSpec> {
}
}
impl W {}
-#[doc = "Break Transmit Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbreak::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Break Transmit Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbreak::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbreakSpec;
impl crate::RegisterSpec for TxbreakSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/txfifoirqtrg.rs b/va108xx/src/uarta/txfifoirqtrg.rs
index 0d13e54..8d0ae92 100644
--- a/va108xx/src/uarta/txfifoirqtrg.rs
+++ b/va108xx/src/uarta/txfifoirqtrg.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxfifoirqtrgSpec;
impl crate::RegisterSpec for TxfifoirqtrgSpec {
type Ux = u32;
diff --git a/va108xx/src/uarta/txstatus.rs b/va108xx/src/uarta/txstatus.rs
index 42852d9..76789f2 100644
--- a/va108xx/src/uarta/txstatus.rs
+++ b/va108xx/src/uarta/txstatus.rs
@@ -37,7 +37,7 @@ impl R {
TxctsnR::new(((self.bits >> 15) & 1) != 0)
}
}
-#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxstatusSpec;
impl crate::RegisterSpec for TxstatusSpec {
type Ux = u32;
diff --git a/va108xx/src/utility.rs b/va108xx/src/utility.rs
index 66aba28..9c687a8 100644
--- a/va108xx/src/utility.rs
+++ b/va108xx/src/utility.rs
@@ -89,85 +89,85 @@ impl RegisterBlock {
&self.perid
}
}
-#[doc = "SYND_DATA0 (rw) register accessor: Synd Data 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_data0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_data0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_data0`]
+#[doc = "SYND_DATA0 (rw) register accessor: Synd Data 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_data0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_data0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_data0`]
module"]
#[doc(alias = "SYND_DATA0")]
pub type SyndData0 = crate::Reg<synd_data0::SyndData0Spec>;
#[doc = "Synd Data 0 Register"]
pub mod synd_data0;
-#[doc = "SYND_DATA1 (rw) register accessor: Synd Data 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_data1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_data1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_data1`]
+#[doc = "SYND_DATA1 (rw) register accessor: Synd Data 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_data1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_data1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_data1`]
module"]
#[doc(alias = "SYND_DATA1")]
pub type SyndData1 = crate::Reg<synd_data1::SyndData1Spec>;
#[doc = "Synd Data 1 Register"]
pub mod synd_data1;
-#[doc = "SYND_SYND (rw) register accessor: Synd Parity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_synd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_synd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_synd`]
+#[doc = "SYND_SYND (rw) register accessor: Synd Parity Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_synd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_synd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_synd`]
module"]
#[doc(alias = "SYND_SYND")]
pub type SyndSynd = crate::Reg<synd_synd::SyndSyndSpec>;
#[doc = "Synd Parity Register"]
pub mod synd_synd;
-#[doc = "SYND_ENC_32 (r) register accessor: Synd 32 bit Encoded Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_enc_32::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_32`]
+#[doc = "SYND_ENC_32 (r) register accessor: Synd 32 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_32`]
module"]
#[doc(alias = "SYND_ENC_32")]
pub type SyndEnc32 = crate::Reg<synd_enc_32::SyndEnc32Spec>;
#[doc = "Synd 32 bit Encoded Syndrome"]
pub mod synd_enc_32;
-#[doc = "SYND_CHECK_32_DATA (r) register accessor: Synd 32 bit Corrected Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_data`]
+#[doc = "SYND_CHECK_32_DATA (r) register accessor: Synd 32 bit Corrected Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_data`]
module"]
#[doc(alias = "SYND_CHECK_32_DATA")]
pub type SyndCheck32Data = crate::Reg<synd_check_32_data::SyndCheck32DataSpec>;
#[doc = "Synd 32 bit Corrected Data"]
pub mod synd_check_32_data;
-#[doc = "SYND_CHECK_32_SYND (r) register accessor: Synd 32 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_synd`]
+#[doc = "SYND_CHECK_32_SYND (r) register accessor: Synd 32 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_synd`]
module"]
#[doc(alias = "SYND_CHECK_32_SYND")]
pub type SyndCheck32Synd = crate::Reg<synd_check_32_synd::SyndCheck32SyndSpec>;
#[doc = "Synd 32 bit Corrected Syndrome and Status"]
pub mod synd_check_32_synd;
-#[doc = "SYND_ENC_64 (r) register accessor: Synd 64 bit Encoded Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_enc_64::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_64`]
+#[doc = "SYND_ENC_64 (r) register accessor: Synd 64 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_64::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_64`]
module"]
#[doc(alias = "SYND_ENC_64")]
pub type SyndEnc64 = crate::Reg<synd_enc_64::SyndEnc64Spec>;
#[doc = "Synd 64 bit Encoded Syndrome"]
pub mod synd_enc_64;
-#[doc = "SYND_CHECK_64_DATA0 (r) register accessor: Synd 64 bit Corrected Data 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_64_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_64_data0`]
+#[doc = "SYND_CHECK_64_DATA0 (r) register accessor: Synd 64 bit Corrected Data 0\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_64_data0`]
module"]
#[doc(alias = "SYND_CHECK_64_DATA0")]
pub type SyndCheck64Data0 = crate::Reg<synd_check_64_data0::SyndCheck64Data0Spec>;
#[doc = "Synd 64 bit Corrected Data 0"]
pub mod synd_check_64_data0;
-#[doc = "SYND_CHECK_64_DATA1 (r) register accessor: Synd 64 bit Corrected Data 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_64_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_64_data1`]
+#[doc = "SYND_CHECK_64_DATA1 (r) register accessor: Synd 64 bit Corrected Data 1\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_data1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_64_data1`]
module"]
#[doc(alias = "SYND_CHECK_64_DATA1")]
pub type SyndCheck64Data1 = crate::Reg<synd_check_64_data1::SyndCheck64Data1Spec>;
#[doc = "Synd 64 bit Corrected Data 1"]
pub mod synd_check_64_data1;
-#[doc = "SYND_CHECK_64_SYND (r) register accessor: Synd 64 bit Corrected Parity and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_64_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_64_synd`]
+#[doc = "SYND_CHECK_64_SYND (r) register accessor: Synd 64 bit Corrected Parity and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_64_synd`]
module"]
#[doc(alias = "SYND_CHECK_64_SYND")]
pub type SyndCheck64Synd = crate::Reg<synd_check_64_synd::SyndCheck64SyndSpec>;
#[doc = "Synd 64 bit Corrected Parity and Status"]
pub mod synd_check_64_synd;
-#[doc = "SYND_ENC_32_52 (r) register accessor: Synd 32/52 bit Encoded Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_enc_32_52::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_32_52`]
+#[doc = "SYND_ENC_32_52 (r) register accessor: Synd 32/52 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32_52::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_32_52`]
module"]
#[doc(alias = "SYND_ENC_32_52")]
pub type SyndEnc32_52 = crate::Reg<synd_enc_32_52::SyndEnc32_52Spec>;
#[doc = "Synd 32/52 bit Encoded Syndrome"]
pub mod synd_enc_32_52;
-#[doc = "SYND_CHECK_32_52_DATA (r) register accessor: Synd 32/52 bit Corrected Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_52_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_52_data`]
+#[doc = "SYND_CHECK_32_52_DATA (r) register accessor: Synd 32/52 bit Corrected Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_52_data`]
module"]
#[doc(alias = "SYND_CHECK_32_52_DATA")]
pub type SyndCheck32_52Data = crate::Reg<synd_check_32_52_data::SyndCheck32_52DataSpec>;
#[doc = "Synd 32/52 bit Corrected Data"]
pub mod synd_check_32_52_data;
-#[doc = "SYND_CHECK_32_52_SYND (r) register accessor: Synd 32/52 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_52_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_52_synd`]
+#[doc = "SYND_CHECK_32_52_SYND (r) register accessor: Synd 32/52 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_52_synd`]
module"]
#[doc(alias = "SYND_CHECK_32_52_SYND")]
pub type SyndCheck32_52Synd = crate::Reg<synd_check_32_52_synd::SyndCheck32_52SyndSpec>;
#[doc = "Synd 32/52 bit Corrected Syndrome and Status"]
pub mod synd_check_32_52_synd;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
module"]
#[doc(alias = "PERID")]
pub type Perid = crate::Reg<perid::PeridSpec>;
diff --git a/va108xx/src/utility/perid.rs b/va108xx/src/utility/perid.rs
index 7b4aa79..6638b5f 100644
--- a/va108xx/src/utility/perid.rs
+++ b/va108xx/src/utility/perid.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_check_32_52_data.rs b/va108xx/src/utility/synd_check_32_52_data.rs
index 4eda35c..f9cb4a8 100644
--- a/va108xx/src/utility/synd_check_32_52_data.rs
+++ b/va108xx/src/utility/synd_check_32_52_data.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Synd 32/52 bit Corrected Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_52_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd 32/52 bit Corrected Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndCheck32_52DataSpec;
impl crate::RegisterSpec for SyndCheck32_52DataSpec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_check_32_52_synd.rs b/va108xx/src/utility/synd_check_32_52_synd.rs
index eb4dc79..0788d1b 100644
--- a/va108xx/src/utility/synd_check_32_52_synd.rs
+++ b/va108xx/src/utility/synd_check_32_52_synd.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Synd 32/52 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_52_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd 32/52 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_52_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndCheck32_52SyndSpec;
impl crate::RegisterSpec for SyndCheck32_52SyndSpec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_check_32_data.rs b/va108xx/src/utility/synd_check_32_data.rs
index 544e1be..0328c0b 100644
--- a/va108xx/src/utility/synd_check_32_data.rs
+++ b/va108xx/src/utility/synd_check_32_data.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Synd 32 bit Corrected Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd 32 bit Corrected Data\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndCheck32DataSpec;
impl crate::RegisterSpec for SyndCheck32DataSpec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_check_32_synd.rs b/va108xx/src/utility/synd_check_32_synd.rs
index 78393af..5e8aabe 100644
--- a/va108xx/src/utility/synd_check_32_synd.rs
+++ b/va108xx/src/utility/synd_check_32_synd.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Synd 32 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd 32 bit Corrected Syndrome and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_32_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndCheck32SyndSpec;
impl crate::RegisterSpec for SyndCheck32SyndSpec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_check_64_data0.rs b/va108xx/src/utility/synd_check_64_data0.rs
index 294925a..a59e21d 100644
--- a/va108xx/src/utility/synd_check_64_data0.rs
+++ b/va108xx/src/utility/synd_check_64_data0.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Synd 64 bit Corrected Data 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_64_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd 64 bit Corrected Data 0\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndCheck64Data0Spec;
impl crate::RegisterSpec for SyndCheck64Data0Spec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_check_64_data1.rs b/va108xx/src/utility/synd_check_64_data1.rs
index f5c1ef2..3ef8f2c 100644
--- a/va108xx/src/utility/synd_check_64_data1.rs
+++ b/va108xx/src/utility/synd_check_64_data1.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Synd 64 bit Corrected Data 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_64_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd 64 bit Corrected Data 1\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_data1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndCheck64Data1Spec;
impl crate::RegisterSpec for SyndCheck64Data1Spec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_check_64_synd.rs b/va108xx/src/utility/synd_check_64_synd.rs
index 4b216d0..7054208 100644
--- a/va108xx/src/utility/synd_check_64_synd.rs
+++ b/va108xx/src/utility/synd_check_64_synd.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Synd 64 bit Corrected Parity and Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_64_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd 64 bit Corrected Parity and Status\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_check_64_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndCheck64SyndSpec;
impl crate::RegisterSpec for SyndCheck64SyndSpec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_data0.rs b/va108xx/src/utility/synd_data0.rs
index 5bb9d05..ce0ffe2 100644
--- a/va108xx/src/utility/synd_data0.rs
+++ b/va108xx/src/utility/synd_data0.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Synd Data 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_data0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_data0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd Data 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_data0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_data0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndData0Spec;
impl crate::RegisterSpec for SyndData0Spec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_data1.rs b/va108xx/src/utility/synd_data1.rs
index 6d226f5..af2e6f7 100644
--- a/va108xx/src/utility/synd_data1.rs
+++ b/va108xx/src/utility/synd_data1.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Synd Data 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_data1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_data1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd Data 1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_data1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_data1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndData1Spec;
impl crate::RegisterSpec for SyndData1Spec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_enc_32.rs b/va108xx/src/utility/synd_enc_32.rs
index eff6f93..7251b0c 100644
--- a/va108xx/src/utility/synd_enc_32.rs
+++ b/va108xx/src/utility/synd_enc_32.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Synd 32 bit Encoded Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_enc_32::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd 32 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndEnc32Spec;
impl crate::RegisterSpec for SyndEnc32Spec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_enc_32_52.rs b/va108xx/src/utility/synd_enc_32_52.rs
index e88ad29..cc58b32 100644
--- a/va108xx/src/utility/synd_enc_32_52.rs
+++ b/va108xx/src/utility/synd_enc_32_52.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Synd 32/52 bit Encoded Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_enc_32_52::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd 32/52 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_32_52::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndEnc32_52Spec;
impl crate::RegisterSpec for SyndEnc32_52Spec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_enc_64.rs b/va108xx/src/utility/synd_enc_64.rs
index 61c5730..4b58150 100644
--- a/va108xx/src/utility/synd_enc_64.rs
+++ b/va108xx/src/utility/synd_enc_64.rs
@@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
-#[doc = "Synd 64 bit Encoded Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_enc_64::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd 64 bit Encoded Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_enc_64::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndEnc64Spec;
impl crate::RegisterSpec for SyndEnc64Spec {
type Ux = u32;
diff --git a/va108xx/src/utility/synd_synd.rs b/va108xx/src/utility/synd_synd.rs
index ec2f17f..1f7abc4 100644
--- a/va108xx/src/utility/synd_synd.rs
+++ b/va108xx/src/utility/synd_synd.rs
@@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
-#[doc = "Synd Parity Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_synd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_synd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "Synd Parity Register\n\nYou can [`read`](crate::Reg::read) this register and get [`synd_synd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`synd_synd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SyndSyndSpec;
impl crate::RegisterSpec for SyndSyndSpec {
type Ux = u32;