board-tests/src/main.rs

@@ -122,14 +122,14 @@ fn main() -> ! {
         }
         TestCase::Pulse => {
             let mut output_pulsed = pinsa.pa0.into_push_pull_output();
-            output_pulsed.pulse_mode(true, PinState::Low);
+            output_pulsed.configure_pulse_mode(true, PinState::Low);
             rprintln!("Pulsing high 10 times..");
             output_pulsed.set_low().unwrap();
             for _ in 0..10 {
                 output_pulsed.set_high().unwrap();
                 cortex_m::asm::delay(25_000_000);
             }
-            output_pulsed.pulse_mode(true, PinState::High);
+            output_pulsed.configure_pulse_mode(true, PinState::High);
             rprintln!("Pulsing low 10 times..");
             for _ in 0..10 {
                 output_pulsed.set_low().unwrap();
@@ -140,12 +140,12 @@ fn main() -> ! {
             let mut out_0 = pinsa
                 .pa0
                 .into_readable_push_pull_output()
-                .delay(true, false);
+                .configure_delay(true, false);
             let mut out_1 = pinsa
                 .pa1
                 .into_readable_push_pull_output()
-                .delay(false, true);
+                .configure_delay(false, true);
-            let mut out_2 = pinsa.pa3.into_readable_push_pull_output().delay(true, true);
+            let mut out_2 = pinsa.pa3.into_readable_push_pull_output().configure_delay(true, true);
             for _ in 0..20 {
                 out_0.toggle().unwrap();
                 out_1.toggle().unwrap();

va108xx-hal/src/gpio/asynch.rs

@@ -115,7 +115,7 @@ impl InputPinFuture {
 
         EDGE_DETECTION[pin_id_to_offset(pin.id())]
             .store(false, core::sync::atomic::Ordering::Relaxed);
-        pin.interrupt_edge(
+        pin.configure_edge_interrupt(
             edge,
             InterruptConfig::new(irq, true, true),
             Some(sys_cfg),

va108xx-hal/src/gpio/dynpin.rs

@@ -181,6 +181,7 @@ pub struct DynPinId {
 /// This `struct` takes ownership of a [`DynPinId`] and provides an API to
 /// access the corresponding regsiters.
 #[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub(crate) struct DynRegisters(DynPinId);
 
 // [`DynRegisters`] takes ownership of the [`DynPinId`], and [`DynPin`]
@@ -392,11 +393,15 @@ impl DynPin {
     ///  - Delay 2: 2
     ///  - Delay 1 + Delay 2: 3
     #[inline]
-    pub fn delay(self, delay_1: bool, delay_2: bool) -> Result<Self, InvalidPinTypeError> {
+    pub fn configure_delay(
+        &mut self,
+        delay_1: bool,
+        delay_2: bool,
+    ) -> Result<(), InvalidPinTypeError> {
         match self.mode {
             DynPinMode::Output(_) => {
-                self.regs.delay(delay_1, delay_2);
+                self.regs.configure_delay(delay_1, delay_2);
-                Ok(self)
+                Ok(())
             }
             _ => Err(InvalidPinTypeError(self.mode)),
         }
@@ -406,7 +411,7 @@ impl DynPin {
     /// When configured for pulse mode, a given pin will set the non-default state for exactly
     /// one clock cycle before returning to the configured default state
     #[inline]
-    pub fn pulse_mode(
+    pub fn configure_pulse_mode(
         &mut self,
         enable: bool,
         default_state: PinState,
@@ -422,14 +427,14 @@ impl DynPin {
 
     /// See p.37 and p.38 of the programmers guide for more information.
     #[inline]
-    pub fn filter_type(
+    pub fn configure_filter_type(
         &mut self,
         filter: FilterType,
         clksel: FilterClkSel,
     ) -> Result<(), InvalidPinTypeError> {
         match self.mode {
             DynPinMode::Input(_) => {
-                self.regs.filter_type(filter, clksel);
+                self.regs.configure_filter_type(filter, clksel);
                 Ok(())
             }
             _ => Err(InvalidPinTypeError(self.mode)),
@@ -437,7 +442,7 @@ impl DynPin {
     }
 
     #[inline]
-    pub fn interrupt_edge(
+    pub fn configure_edge_interrupt(
         &mut self,
         edge_type: InterruptEdge,
         irq_cfg: InterruptConfig,
@@ -446,7 +451,7 @@ impl DynPin {
     ) -> Result<(), InvalidPinTypeError> {
         match self.mode {
             DynPinMode::Input(_) | DynPinMode::Output(_) => {
-                self.regs.interrupt_edge(edge_type);
+                self.regs.configure_edge_interrupt(edge_type);
                 self.irq_enb(irq_cfg, syscfg, irqsel);
                 Ok(())
             }
@@ -455,7 +460,7 @@ impl DynPin {
     }
 
     #[inline]
-    pub fn interrupt_level(
+    pub fn configure_level_interrupt(
         &mut self,
         level_type: InterruptLevel,
         irq_cfg: InterruptConfig,
@@ -464,7 +469,7 @@ impl DynPin {
     ) -> Result<(), InvalidPinTypeError> {
         match self.mode {
             DynPinMode::Input(_) | DynPinMode::Output(_) => {
-                self.regs.interrupt_level(level_type);
+                self.regs.configure_level_interrupt(level_type);
                 self.irq_enb(irq_cfg, syscfg, irqsel);
                 Ok(())
             }

va108xx-hal/src/gpio/pin.rs

@@ -89,6 +89,7 @@ use paste::paste;
 //==================================================================================================
 
 #[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum InterruptEdge {
     HighToLow,
     LowToHigh,
@@ -96,12 +97,14 @@ pub enum InterruptEdge {
 }
 
 #[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum InterruptLevel {
     Low = 0,
     High = 1,
 }
 
 #[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum PinState {
     Low = 0,
     High = 1,
@@ -353,6 +356,7 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
         }
     }
 
+    #[inline]
     pub fn id(&self) -> DynPinId {
         self.inner.id()
     }
@@ -599,7 +603,7 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
         syscfg: Option<&mut Sysconfig>,
         irqsel: Option<&mut Irqsel>,
     ) {
-        self.inner.regs.interrupt_edge(edge_type);
+        self.inner.regs.configure_edge_interrupt(edge_type);
         self.irq_enb(irq_cfg, syscfg, irqsel);
     }
 
@@ -610,7 +614,7 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
         syscfg: Option<&mut Sysconfig>,
         irqsel: Option<&mut Irqsel>,
     ) {
-        self.inner.regs.interrupt_level(level_type);
+        self.inner.regs.configure_level_interrupt(level_type);
         self.irq_enb(irq_cfg, syscfg, irqsel);
     }
 }
@@ -622,9 +626,8 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
     ///  - Delay 2: 2
     ///  - Delay 1 + Delay 2: 3
     #[inline]
-    pub fn delay(self, delay_1: bool, delay_2: bool) -> Self {
+    pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool)  {
-        self.inner.regs.delay(delay_1, delay_2);
+        self.inner.regs.configure_delay(delay_1, delay_2);
-        self
     }
 
     #[inline]
@@ -632,13 +635,25 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
         self._toggle_with_toggle_reg()
     }
 
+    #[deprecated(
+        since = "0.9.0",
+        note = "Please use the `configure_pulse_mode` method instead"
+    )]
+    pub fn pulse_mode(&mut self, enable: bool, default_state: PinState) {
+        self.configure_pulse_mode(enable, default_state);
+    }
+
     /// See p.52 of the programmers guide for more information.
     /// When configured for pulse mode, a given pin will set the non-default state for exactly
     /// one clock cycle before returning to the configured default state
-    pub fn pulse_mode(&mut self, enable: bool, default_state: PinState) {
+    pub fn configure_pulse_mode(&mut self, enable: bool, default_state: PinState) {
         self.inner.regs.pulse_mode(enable, default_state);
     }
 
+    #[deprecated(
+        since = "0.9.0",
+        note = "Please use the `configure_edge_interrupt` method instead"
+    )]
     pub fn interrupt_edge(
         &mut self,
         edge_type: InterruptEdge,
@@ -646,18 +661,43 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
         syscfg: Option<&mut Sysconfig>,
         irqsel: Option<&mut Irqsel>,
     ) {
-        self.inner.regs.interrupt_edge(edge_type);
+        self.inner.regs.configure_edge_interrupt(edge_type);
         self.irq_enb(irq_cfg, syscfg, irqsel);
     }
 
-    pub fn interrupt_level(
+    pub fn configure_edge_interrupt(
+        &mut self,
+        edge_type: InterruptEdge,
+        irq_cfg: InterruptConfig,
+        syscfg: Option<&mut Sysconfig>,
+        irqsel: Option<&mut Irqsel>,
+    ) {
+        self.inner.regs.configure_edge_interrupt(edge_type);
+        self.irq_enb(irq_cfg, syscfg, irqsel);
+    }
+
+    #[deprecated(
+        since = "0.9.0",
+        note = "Please use the `configure_level_interrupt` method instead"
+    )]
+    pub fn level_interrupt(
         &mut self,
         level_type: InterruptLevel,
         irq_cfg: InterruptConfig,
         syscfg: Option<&mut Sysconfig>,
         irqsel: Option<&mut Irqsel>,
     ) {
-        self.inner.regs.interrupt_level(level_type);
+        self.configure_level_interrupt(level_type, irq_cfg, syscfg, irqsel);
+    }
+
+    pub fn configure_level_interrupt(
+        &mut self,
+        level_type: InterruptLevel,
+        irq_cfg: InterruptConfig,
+        syscfg: Option<&mut Sysconfig>,
+        irqsel: Option<&mut Irqsel>,
+    ) {
+        self.inner.regs.configure_level_interrupt(level_type);
         self.irq_enb(irq_cfg, syscfg, irqsel);
     }
 }
@@ -666,7 +706,7 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
     /// See p.37 and p.38 of the programmers guide for more information.
     #[inline]
     pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
-        self.inner.regs.filter_type(filter, clksel);
+        self.inner.regs.configure_filter_type(filter, clksel);
     }
 }
 

va108xx-hal/src/gpio/reg.rs

@@ -240,7 +240,7 @@ pub(super) unsafe trait RegisterInterface {
     /// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure
     /// When using edge mode, it is possible to generate interrupts on both edges as well
     #[inline]
-    fn interrupt_edge(&mut self, edge_type: InterruptEdge) {
+    fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) {
         unsafe {
             self.port_reg()
                 .irq_sen()
@@ -267,7 +267,7 @@ pub(super) unsafe trait RegisterInterface {
 
     /// Configure which edge or level type triggers an interrupt
     #[inline]
-    fn interrupt_level(&mut self, level: InterruptLevel) {
+    fn configure_level_interrupt(&mut self, level: InterruptLevel) {
         unsafe {
             self.port_reg()
                 .irq_sen()
@@ -286,7 +286,7 @@ pub(super) unsafe trait RegisterInterface {
 
     /// Only useful for input pins
     #[inline]
-    fn filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
+    fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
         self.iocfg_port().modify(|_, w| {
             // Safety: Only write to register for this Pin ID
             unsafe {
@@ -349,7 +349,7 @@ pub(super) unsafe trait RegisterInterface {
     }
 
     /// Only useful for output pins
-    fn delay(&self, delay_1: bool, delay_2: bool) {
+    fn configure_delay(&mut self, delay_1: bool, delay_2: bool) {
         let portreg = self.port_reg();
         unsafe {
             if delay_1 {