va108xx/CHANGELOG.md

@@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
+## [v0.6.0] 2025-09-03
+
+- Re-generated PAC with `svd2rust` v0.37.0
+
 ## [v0.5.1] 2025-07-22
 
 defmt version v1
@@ -84,6 +88,7 @@ defmt version v1
 - First version of the PAC which builds. Uses a patched version
   of `svd2rust`: https://github.com/rust-embedded/svd2rust
 
-[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.5.1...HEAD
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.6.0...HEAD
+[v0.6.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.5.1...va108xx-v0.6.0
 [v0.5.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.5.0...va108xx-v0.5.1
 [v0.5.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.4.0...va108xx-v0.5.0

va108xx/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx"
-version = "0.5.1"
+version = "0.6.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "PAC for the Vorago VA108xx family of microcontrollers"

va108xx/src/generic.rs

@@ -1,8 +1,46 @@
 use core::marker;
+#[doc = " Generic peripheral accessor"]
+pub struct Periph<RB, const A: usize> {
+    _marker: marker::PhantomData<RB>,
+}
+unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
+impl<RB, const A: usize> Periph<RB, A> {
+    #[doc = "Pointer to the register block"]
+    pub const PTR: *const RB = A as *const _;
+    #[doc = "Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const RB {
+        Self::PTR
+    }
+    #[doc = " Steal an instance of this peripheral"]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Ensure that the new instance of the peripheral cannot be used in a way"]
+    #[doc = " that may race with any existing instances, for example by only"]
+    #[doc = " accessing read-only or write-only registers, or by consuming the"]
+    #[doc = " original peripheral and using critical sections to coordinate"]
+    #[doc = " access between multiple new instances."]
+    #[doc = ""]
+    #[doc = " Additionally, other software such as HALs may rely on only one"]
+    #[doc = " peripheral instance existing to ensure memory safety; ensure"]
+    #[doc = " no stolen instances are passed to such software."]
+    pub unsafe fn steal() -> Self {
+        Self {
+            _marker: marker::PhantomData,
+        }
+    }
+}
+impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
+    type Target = RB;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
 #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
 pub trait RawReg:
     Copy
-    + Default
     + From<bool>
     + core::ops::BitOr<Output = Self>
     + core::ops::BitAnd<Output = Self>
@@ -13,8 +51,10 @@ pub trait RawReg:
 {
     #[doc = " Mask for bits of width `WI`"]
     fn mask<const WI: u8>() -> Self;
-    #[doc = " Mask for bits of width 1"]
+    #[doc = " `0`"]
-    fn one() -> Self;
+    const ZERO: Self;
+    #[doc = " `1`"]
+    const ONE: Self;
 }
 macro_rules! raw_reg {
     ($ U : ty , $ size : literal , $ mask : ident) => {
@@ -23,10 +63,8 @@ macro_rules! raw_reg {
             fn mask<const WI: u8>() -> Self {
                 $mask::<WI>()
             }
-            #[inline(always)]
+            const ZERO: Self = 0;
-            fn one() -> Self {
+            const ONE: Self = 1;
-                1
-            }
         }
         const fn $mask<const WI: u8>() -> $U {
             <$U>::MAX >> ($size - WI)
@@ -65,9 +103,9 @@ pub trait Writable: RegisterSpec {
     #[doc = " Is it safe to write any bits to register"]
     type Safety;
     #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
     #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
-    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
 }
 #[doc = " Reset value of the register."]
 #[doc = ""]
@@ -75,7 +113,7 @@ pub trait Writable: RegisterSpec {
 #[doc = " register by using the `reset` method."]
 pub trait Resettable: RegisterSpec {
     #[doc = " Reset value of the register."]
-    const RESET_VALUE: Self::Ux;
+    const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
     #[doc = " Reset value of the register."]
     #[inline(always)]
     fn reset_value() -> Self::Ux {
@@ -344,8 +382,8 @@ macro_rules! bit_proxy {
             #[doc = " Writes bit to the field"]
             #[inline(always)]
             pub fn bit(self, value: bool) -> &'a mut W<REG> {
-                self.w.bits &= !(REG::Ux::one() << self.o);
+                self.w.bits &= !(REG::Ux::ONE << self.o);
-                self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o;
+                self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
                 self.w
             }
             #[doc = " Writes `variant` to the field"]
@@ -371,13 +409,13 @@ where
     #[doc = " Sets the field bit"]
     #[inline(always)]
     pub fn set_bit(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
         self.w
     }
     #[doc = " Clears the field bit"]
     #[inline(always)]
     pub fn clear_bit(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
         self.w
     }
 }
@@ -389,7 +427,7 @@ where
     #[doc = " Sets the field bit"]
     #[inline(always)]
     pub fn set_bit(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
         self.w
     }
 }
@@ -401,7 +439,7 @@ where
     #[doc = " Clears the field bit"]
     #[inline(always)]
     pub fn clear_bit(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
         self.w
     }
 }
@@ -413,7 +451,7 @@ where
     #[doc = "Clears the field bit by passing one"]
     #[inline(always)]
     pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
         self.w
     }
 }
@@ -425,7 +463,7 @@ where
     #[doc = "Sets the field bit by passing zero"]
     #[inline(always)]
     pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
         self.w
     }
 }
@@ -437,7 +475,7 @@ where
     #[doc = "Toggle the field bit by passing one"]
     #[inline(always)]
     pub fn toggle_bit(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
         self.w
     }
 }
@@ -449,7 +487,7 @@ where
     #[doc = "Toggle the field bit by passing zero"]
     #[inline(always)]
     pub fn toggle_bit(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
         self.w
     }
 }
@@ -594,7 +632,7 @@ impl<REG: Writable> Reg<REG> {
         F: FnOnce(&mut W<REG>) -> &mut W<REG>,
     {
         let value = f(&mut W {
-            bits: REG::Ux::default(),
+            bits: REG::Ux::ZERO,
             _reg: marker::PhantomData,
         })
         .bits;
@@ -614,7 +652,7 @@ impl<REG: Writable> Reg<REG> {
         F: FnOnce(&mut W<REG>) -> T,
     {
         let mut writer = W {
-            bits: REG::Ux::default(),
+            bits: REG::Ux::ZERO,
             _reg: marker::PhantomData,
         };
         let result = f(&mut writer);

va108xx/src/i2ca.rs

@@ -240,68 +240,57 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
-module"]
 #[doc(alias = "CTRL")]
 pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
 #[doc = "Control Register"]
 pub mod ctrl;
-#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
+#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] module"]
-module"]
 #[doc(alias = "CLKSCALE")]
 pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
 #[doc = "Clock Scale divide value"]
 pub mod clkscale;
-#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
+#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`] module"]
-module"]
 #[doc(alias = "WORDS")]
 pub type Words = crate::Reg<words::WordsSpec>;
 #[doc = "Word Count value"]
 pub mod words;
-#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
+#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`] module"]
-module"]
 #[doc(alias = "ADDRESS")]
 pub type Address = crate::Reg<address::AddressSpec>;
 #[doc = "I2C Address value"]
 pub mod address;
-#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
-module"]
 #[doc(alias = "DATA")]
 pub type Data = crate::Reg<data::DataSpec>;
 #[doc = "Data Input/Output"]
 pub mod data;
-#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
+#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"]
-module"]
 #[doc(alias = "CMD")]
 pub type Cmd = crate::Reg<cmd::CmdSpec>;
 #[doc = "Command Register"]
 pub mod cmd;
-#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
+#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
-module"]
 #[doc(alias = "STATUS")]
 pub type Status = crate::Reg<status::StatusSpec>;
 #[doc = "I2C Controller Status Register"]
 pub mod status;
-#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"]
-module"]
 #[doc(alias = "STATE")]
 pub type State = crate::Reg<state::StateSpec>;
 #[doc = "Internal STATE of I2C Master Controller"]
 pub mod state;
-#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
+#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`] module"]
-module"]
 #[doc(alias = "TXCOUNT")]
 pub type Txcount = crate::Reg<txcount::TxcountSpec>;
 #[doc = "TX Count Register"]
 pub mod txcount;
-#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
+#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`] module"]
-module"]
 #[doc(alias = "RXCOUNT")]
 pub type Rxcount = crate::Reg<rxcount::RxcountSpec>;
 #[doc = "RX Count Register"]
 pub mod rxcount;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
-module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
 #[doc = "Interrupt Enable Register"]
@@ -312,98 +301,82 @@ pub use irq_enb as irq_clr;
 pub use IrqEnb as IrqRaw;
 pub use IrqEnb as IrqEnd;
 pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"]
-module"]
 #[doc(alias = "RXFIFOIRQTRG")]
 pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
 #[doc = "Rx FIFO IRQ Trigger Level"]
 pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"]
-module"]
 #[doc(alias = "TXFIFOIRQTRG")]
 pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
 #[doc = "Tx FIFO IRQ Trigger Level"]
 pub mod txfifoirqtrg;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"]
-module"]
 #[doc(alias = "FIFO_CLR")]
 pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
 #[doc = "Clear FIFO Register"]
 pub mod fifo_clr;
-#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
+#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`] module"]
-module"]
 #[doc(alias = "TMCONFIG")]
 pub type Tmconfig = crate::Reg<tmconfig::TmconfigSpec>;
 #[doc = "Timing Config Register"]
 pub mod tmconfig;
-#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
+#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`] module"]
-module"]
 #[doc(alias = "CLKTOLIMIT")]
 pub type Clktolimit = crate::Reg<clktolimit::ClktolimitSpec>;
 #[doc = "Clock Low Timeout Limit Register"]
 pub mod clktolimit;
-#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
+#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`] module"]
-module"]
 #[doc(alias = "S0_CTRL")]
 pub type S0Ctrl = crate::Reg<s0_ctrl::S0CtrlSpec>;
 #[doc = "Slave Control Register"]
 pub mod s0_ctrl;
-#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
+#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`] module"]
-module"]
 #[doc(alias = "S0_MAXWORDS")]
 pub type S0Maxwords = crate::Reg<s0_maxwords::S0MaxwordsSpec>;
 #[doc = "Slave MaxWords Register"]
 pub mod s0_maxwords;
-#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
+#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`] module"]
-module"]
 #[doc(alias = "S0_ADDRESS")]
 pub type S0Address = crate::Reg<s0_address::S0AddressSpec>;
 #[doc = "Slave I2C Address Value"]
 pub mod s0_address;
-#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
+#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`] module"]
-module"]
 #[doc(alias = "S0_ADDRESSMASK")]
 pub type S0Addressmask = crate::Reg<s0_addressmask::S0AddressmaskSpec>;
 #[doc = "Slave I2C Address Mask value"]
 pub mod s0_addressmask;
-#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
+#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`] module"]
-module"]
 #[doc(alias = "S0_DATA")]
 pub type S0Data = crate::Reg<s0_data::S0DataSpec>;
 #[doc = "Slave Data Input/Output"]
 pub mod s0_data;
-#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
+#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`] module"]
-module"]
 #[doc(alias = "S0_LASTADDRESS")]
 pub type S0Lastaddress = crate::Reg<s0_lastaddress::S0LastaddressSpec>;
 #[doc = "Slave I2C Last Address value"]
 pub mod s0_lastaddress;
-#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
+#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`] module"]
-module"]
 #[doc(alias = "S0_STATUS")]
 pub type S0Status = crate::Reg<s0_status::S0StatusSpec>;
 #[doc = "Slave I2C Controller Status Register"]
 pub mod s0_status;
-#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
+#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`] module"]
-module"]
 #[doc(alias = "S0_STATE")]
 pub type S0State = crate::Reg<s0_state::S0StateSpec>;
 #[doc = "Internal STATE of I2C Slave Controller"]
 pub mod s0_state;
-#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
+#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`] module"]
-module"]
 #[doc(alias = "S0_TXCOUNT")]
 pub type S0Txcount = crate::Reg<s0_txcount::S0TxcountSpec>;
 #[doc = "Slave TX Count Register"]
 pub mod s0_txcount;
-#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
+#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`] module"]
-module"]
 #[doc(alias = "S0_RXCOUNT")]
 pub type S0Rxcount = crate::Reg<s0_rxcount::S0RxcountSpec>;
 #[doc = "Slave RX Count Register"]
 pub mod s0_rxcount;
-#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
+#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`] module"]
-module"]
 #[doc(alias = "S0_IRQ_ENB")]
 pub type S0IrqEnb = crate::Reg<s0_irq_enb::S0IrqEnbSpec>;
 #[doc = "Slave Interrupt Enable Register"]
@@ -414,38 +387,32 @@ pub use s0_irq_enb as s0_irq_clr;
 pub use S0IrqEnb as S0IrqRaw;
 pub use S0IrqEnb as S0IrqEnd;
 pub use S0IrqEnb as S0IrqClr;
-#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
+#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`] module"]
-module"]
 #[doc(alias = "S0_RXFIFOIRQTRG")]
 pub type S0Rxfifoirqtrg = crate::Reg<s0_rxfifoirqtrg::S0RxfifoirqtrgSpec>;
 #[doc = "Slave Rx FIFO IRQ Trigger Level"]
 pub mod s0_rxfifoirqtrg;
-#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
+#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`] module"]
-module"]
 #[doc(alias = "S0_TXFIFOIRQTRG")]
 pub type S0Txfifoirqtrg = crate::Reg<s0_txfifoirqtrg::S0TxfifoirqtrgSpec>;
 #[doc = "Slave Tx FIFO IRQ Trigger Level"]
 pub mod s0_txfifoirqtrg;
-#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
+#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`] module"]
-module"]
 #[doc(alias = "S0_FIFO_CLR")]
 pub type S0FifoClr = crate::Reg<s0_fifo_clr::S0FifoClrSpec>;
 #[doc = "Slave Clear FIFO Register"]
 pub mod s0_fifo_clr;
-#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
+#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`] module"]
-module"]
 #[doc(alias = "S0_ADDRESSB")]
 pub type S0Addressb = crate::Reg<s0_addressb::S0AddressbSpec>;
 #[doc = "Slave I2C Address B Value"]
 pub mod s0_addressb;
-#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
+#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`] module"]
-module"]
 #[doc(alias = "S0_ADDRESSMASKB")]
 pub type S0Addressmaskb = crate::Reg<s0_addressmaskb::S0AddressmaskbSpec>;
 #[doc = "Slave I2C Address B Mask value"]
 pub mod s0_addressmaskb;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
-module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]

va108xx/src/i2ca/address.rs

@@ -19,10 +19,6 @@ impl crate::Readable for AddressSpec {}
 #[doc = "`write(|w| ..)` method takes [`address::W`](W) writer structure"]
 impl crate::Writable for AddressSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets ADDRESS to value 0"]
-impl crate::Resettable for AddressSpec {
+impl crate::Resettable for AddressSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/clkscale.rs

@@ -25,12 +25,12 @@ impl R {
 impl W {
     #[doc = "Bits 0:30 - Enable FastMode"]
     #[inline(always)]
-    pub fn value(&mut self) -> ValueW<ClkscaleSpec> {
+    pub fn value(&mut self) -> ValueW<'_, ClkscaleSpec> {
         ValueW::new(self, 0)
     }
     #[doc = "Bit 31 - Enable FastMode"]
     #[inline(always)]
-    pub fn fastmode(&mut self) -> FastmodeW<ClkscaleSpec> {
+    pub fn fastmode(&mut self) -> FastmodeW<'_, ClkscaleSpec> {
         FastmodeW::new(self, 31)
     }
 }
@@ -44,10 +44,6 @@ impl crate::Readable for ClkscaleSpec {}
 #[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"]
 impl crate::Writable for ClkscaleSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CLKSCALE to value 0"]
-impl crate::Resettable for ClkscaleSpec {
+impl crate::Resettable for ClkscaleSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/clktolimit.rs

@@ -19,10 +19,6 @@ impl crate::Readable for ClktolimitSpec {}
 #[doc = "`write(|w| ..)` method takes [`clktolimit::W`](W) writer structure"]
 impl crate::Writable for ClktolimitSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CLKTOLIMIT to value 0"]
-impl crate::Resettable for ClktolimitSpec {
+impl crate::Resettable for ClktolimitSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/cmd.rs

@@ -19,10 +19,6 @@ impl crate::Readable for CmdSpec {}
 #[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
 impl crate::Writable for CmdSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CMD to value 0"]
-impl crate::Resettable for CmdSpec {
+impl crate::Resettable for CmdSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/ctrl.rs

@@ -88,47 +88,47 @@ impl R {
 impl W {
     #[doc = "Bit 0 - I2C CLK Enabled"]
     #[inline(always)]
-    pub fn clkenabled(&mut self) -> ClkenabledW<CtrlSpec> {
+    pub fn clkenabled(&mut self) -> ClkenabledW<'_, CtrlSpec> {
         ClkenabledW::new(self, 0)
     }
     #[doc = "Bit 1 - I2C Activated"]
     #[inline(always)]
-    pub fn enabled(&mut self) -> EnabledW<CtrlSpec> {
+    pub fn enabled(&mut self) -> EnabledW<'_, CtrlSpec> {
         EnabledW::new(self, 1)
     }
     #[doc = "Bit 2 - I2C Active"]
     #[inline(always)]
-    pub fn enable(&mut self) -> EnableW<CtrlSpec> {
+    pub fn enable(&mut self) -> EnableW<'_, CtrlSpec> {
         EnableW::new(self, 2)
     }
     #[doc = "Bit 3 - TX FIFIO Empty Mode"]
     #[inline(always)]
-    pub fn txfemd(&mut self) -> TxfemdW<CtrlSpec> {
+    pub fn txfemd(&mut self) -> TxfemdW<'_, CtrlSpec> {
         TxfemdW::new(self, 3)
     }
     #[doc = "Bit 4 - RX FIFO Full Mode"]
     #[inline(always)]
-    pub fn rxffmd(&mut self) -> RxffmdW<CtrlSpec> {
+    pub fn rxffmd(&mut self) -> RxffmdW<'_, CtrlSpec> {
         RxffmdW::new(self, 4)
     }
     #[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
     #[inline(always)]
-    pub fn algfilter(&mut self) -> AlgfilterW<CtrlSpec> {
+    pub fn algfilter(&mut self) -> AlgfilterW<'_, CtrlSpec> {
         AlgfilterW::new(self, 5)
     }
     #[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
     #[inline(always)]
-    pub fn dlgfilter(&mut self) -> DlgfilterW<CtrlSpec> {
+    pub fn dlgfilter(&mut self) -> DlgfilterW<'_, CtrlSpec> {
         DlgfilterW::new(self, 6)
     }
     #[doc = "Bit 8 - Enable LoopBack Mode"]
     #[inline(always)]
-    pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
+    pub fn loopback(&mut self) -> LoopbackW<'_, CtrlSpec> {
         LoopbackW::new(self, 8)
     }
     #[doc = "Bit 9 - Enable Timing Config Register"]
     #[inline(always)]
-    pub fn tmconfigenb(&mut self) -> TmconfigenbW<CtrlSpec> {
+    pub fn tmconfigenb(&mut self) -> TmconfigenbW<'_, CtrlSpec> {
         TmconfigenbW::new(self, 9)
     }
 }
@@ -142,10 +142,6 @@ impl crate::Readable for CtrlSpec {}
 #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
 impl crate::Writable for CtrlSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CTRL to value 0"]
-impl crate::Resettable for CtrlSpec {
+impl crate::Resettable for CtrlSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/data.rs

@@ -19,10 +19,6 @@ impl crate::Readable for DataSpec {}
 #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
 impl crate::Writable for DataSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets DATA to value 0"]
-impl crate::Resettable for DataSpec {
+impl crate::Resettable for DataSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/fifo_clr.rs

@@ -7,12 +7,12 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bit 0 - Clear Rx FIFO"]
     #[inline(always)]
-    pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
+    pub fn rxfifo(&mut self) -> RxfifoW<'_, FifoClrSpec> {
         RxfifoW::new(self, 0)
     }
     #[doc = "Bit 1 - Clear Tx FIFO"]
     #[inline(always)]
-    pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
+    pub fn txfifo(&mut self) -> TxfifoW<'_, FifoClrSpec> {
         TxfifoW::new(self, 1)
     }
 }
@@ -24,10 +24,6 @@ impl crate::RegisterSpec for FifoClrSpec {
 #[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"]
 impl crate::Writable for FifoClrSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets FIFO_CLR to value 0"]
-impl crate::Resettable for FifoClrSpec {
+impl crate::Resettable for FifoClrSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/irq_enb.rs

@@ -133,72 +133,72 @@ impl R {
 impl W {
     #[doc = "Bit 0 - I2C Bus is Idle"]
     #[inline(always)]
-    pub fn i2cidle(&mut self) -> I2cidleW<IrqEnbSpec> {
+    pub fn i2cidle(&mut self) -> I2cidleW<'_, IrqEnbSpec> {
         I2cidleW::new(self, 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
-    pub fn idle(&mut self) -> IdleW<IrqEnbSpec> {
+    pub fn idle(&mut self) -> IdleW<'_, IrqEnbSpec> {
         IdleW::new(self, 1)
     }
     #[doc = "Bit 2 - Controller is Waiting"]
     #[inline(always)]
-    pub fn waiting(&mut self) -> WaitingW<IrqEnbSpec> {
+    pub fn waiting(&mut self) -> WaitingW<'_, IrqEnbSpec> {
         WaitingW::new(self, 2)
     }
     #[doc = "Bit 3 - Controller is Stalled"]
     #[inline(always)]
-    pub fn stalled(&mut self) -> StalledW<IrqEnbSpec> {
+    pub fn stalled(&mut self) -> StalledW<'_, IrqEnbSpec> {
         StalledW::new(self, 3)
     }
     #[doc = "Bit 4 - I2C Arbitration was lost"]
     #[inline(always)]
-    pub fn arblost(&mut self) -> ArblostW<IrqEnbSpec> {
+    pub fn arblost(&mut self) -> ArblostW<'_, IrqEnbSpec> {
         ArblostW::new(self, 4)
     }
     #[doc = "Bit 5 - I2C Address was not Acknowledged"]
     #[inline(always)]
-    pub fn nackaddr(&mut self) -> NackaddrW<IrqEnbSpec> {
+    pub fn nackaddr(&mut self) -> NackaddrW<'_, IrqEnbSpec> {
         NackaddrW::new(self, 5)
     }
     #[doc = "Bit 6 - I2C Data was not Acknowledged"]
     #[inline(always)]
-    pub fn nackdata(&mut self) -> NackdataW<IrqEnbSpec> {
+    pub fn nackdata(&mut self) -> NackdataW<'_, IrqEnbSpec> {
         NackdataW::new(self, 6)
     }
     #[doc = "Bit 7 - I2C Clock Low Timeout"]
     #[inline(always)]
-    pub fn clkloto(&mut self) -> ClklotoW<IrqEnbSpec> {
+    pub fn clkloto(&mut self) -> ClklotoW<'_, IrqEnbSpec> {
         ClklotoW::new(self, 7)
     }
     #[doc = "Bit 10 - TX FIFO Overflowed"]
     #[inline(always)]
-    pub fn txoverflow(&mut self) -> TxoverflowW<IrqEnbSpec> {
+    pub fn txoverflow(&mut self) -> TxoverflowW<'_, IrqEnbSpec> {
         TxoverflowW::new(self, 10)
     }
     #[doc = "Bit 11 - TX FIFO Overflowed"]
     #[inline(always)]
-    pub fn rxoverflow(&mut self) -> RxoverflowW<IrqEnbSpec> {
+    pub fn rxoverflow(&mut self) -> RxoverflowW<'_, IrqEnbSpec> {
         RxoverflowW::new(self, 11)
     }
     #[doc = "Bit 12 - TX FIFO Ready"]
     #[inline(always)]
-    pub fn txready(&mut self) -> TxreadyW<IrqEnbSpec> {
+    pub fn txready(&mut self) -> TxreadyW<'_, IrqEnbSpec> {
         TxreadyW::new(self, 12)
     }
     #[doc = "Bit 13 - RX FIFO Ready"]
     #[inline(always)]
-    pub fn rxready(&mut self) -> RxreadyW<IrqEnbSpec> {
+    pub fn rxready(&mut self) -> RxreadyW<'_, IrqEnbSpec> {
         RxreadyW::new(self, 13)
     }
     #[doc = "Bit 14 - TX FIFO Empty"]
     #[inline(always)]
-    pub fn txempty(&mut self) -> TxemptyW<IrqEnbSpec> {
+    pub fn txempty(&mut self) -> TxemptyW<'_, IrqEnbSpec> {
         TxemptyW::new(self, 14)
     }
     #[doc = "Bit 15 - RX FIFO Full"]
     #[inline(always)]
-    pub fn rxfull(&mut self) -> RxfullW<IrqEnbSpec> {
+    pub fn rxfull(&mut self) -> RxfullW<'_, IrqEnbSpec> {
         RxfullW::new(self, 15)
     }
 }
@@ -212,10 +212,6 @@ impl crate::Readable for IrqEnbSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
 impl crate::Writable for IrqEnbSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_ENB to value 0"]
-impl crate::Resettable for IrqEnbSpec {
+impl crate::Resettable for IrqEnbSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/rxcount.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for RxcountSpec {
 #[doc = "`read()` method returns [`rxcount::R`](R) reader structure"]
 impl crate::Readable for RxcountSpec {}
 #[doc = "`reset()` method sets RXCOUNT to value 0"]
-impl crate::Resettable for RxcountSpec {
+impl crate::Resettable for RxcountSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/rxfifoirqtrg.rs

@@ -19,10 +19,6 @@ impl crate::Readable for RxfifoirqtrgSpec {}
 #[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"]
 impl crate::Writable for RxfifoirqtrgSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"]
-impl crate::Resettable for RxfifoirqtrgSpec {
+impl crate::Resettable for RxfifoirqtrgSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_address.rs

@@ -19,10 +19,6 @@ impl crate::Readable for S0AddressSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_address::W`](W) writer structure"]
 impl crate::Writable for S0AddressSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_ADDRESS to value 0"]
-impl crate::Resettable for S0AddressSpec {
+impl crate::Resettable for S0AddressSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_addressb.rs

@@ -19,10 +19,6 @@ impl crate::Readable for S0AddressbSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_addressb::W`](W) writer structure"]
 impl crate::Writable for S0AddressbSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_ADDRESSB to value 0"]
-impl crate::Resettable for S0AddressbSpec {
+impl crate::Resettable for S0AddressbSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_addressmask.rs

@@ -19,10 +19,6 @@ impl crate::Readable for S0AddressmaskSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_addressmask::W`](W) writer structure"]
 impl crate::Writable for S0AddressmaskSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"]
-impl crate::Resettable for S0AddressmaskSpec {
+impl crate::Resettable for S0AddressmaskSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_addressmaskb.rs

@@ -19,10 +19,6 @@ impl crate::Readable for S0AddressmaskbSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_addressmaskb::W`](W) writer structure"]
 impl crate::Writable for S0AddressmaskbSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0"]
-impl crate::Resettable for S0AddressmaskbSpec {
+impl crate::Resettable for S0AddressmaskbSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_ctrl.rs

@@ -52,27 +52,27 @@ impl R {
 impl W {
     #[doc = "Bit 0 - I2C Enabled"]
     #[inline(always)]
-    pub fn clkenabled(&mut self) -> ClkenabledW<S0CtrlSpec> {
+    pub fn clkenabled(&mut self) -> ClkenabledW<'_, S0CtrlSpec> {
         ClkenabledW::new(self, 0)
     }
     #[doc = "Bit 1 - I2C Activated"]
     #[inline(always)]
-    pub fn enabled(&mut self) -> EnabledW<S0CtrlSpec> {
+    pub fn enabled(&mut self) -> EnabledW<'_, S0CtrlSpec> {
         EnabledW::new(self, 1)
     }
     #[doc = "Bit 2 - I2C Active"]
     #[inline(always)]
-    pub fn enable(&mut self) -> EnableW<S0CtrlSpec> {
+    pub fn enable(&mut self) -> EnableW<'_, S0CtrlSpec> {
         EnableW::new(self, 2)
     }
     #[doc = "Bit 3 - TX FIFIO Empty Mode"]
     #[inline(always)]
-    pub fn txfemd(&mut self) -> TxfemdW<S0CtrlSpec> {
+    pub fn txfemd(&mut self) -> TxfemdW<'_, S0CtrlSpec> {
         TxfemdW::new(self, 3)
     }
     #[doc = "Bit 4 - RX FIFO Full Mode"]
     #[inline(always)]
-    pub fn rxffmd(&mut self) -> RxffmdW<S0CtrlSpec> {
+    pub fn rxffmd(&mut self) -> RxffmdW<'_, S0CtrlSpec> {
         RxffmdW::new(self, 4)
     }
 }
@@ -86,10 +86,6 @@ impl crate::Readable for S0CtrlSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_ctrl::W`](W) writer structure"]
 impl crate::Writable for S0CtrlSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_CTRL to value 0"]
-impl crate::Resettable for S0CtrlSpec {
+impl crate::Resettable for S0CtrlSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_data.rs

@@ -19,10 +19,6 @@ impl crate::Readable for S0DataSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_data::W`](W) writer structure"]
 impl crate::Writable for S0DataSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_DATA to value 0"]
-impl crate::Resettable for S0DataSpec {
+impl crate::Resettable for S0DataSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_fifo_clr.rs

@@ -7,12 +7,12 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bit 0 - Clear Rx FIFO"]
     #[inline(always)]
-    pub fn rxfifo(&mut self) -> RxfifoW<S0FifoClrSpec> {
+    pub fn rxfifo(&mut self) -> RxfifoW<'_, S0FifoClrSpec> {
         RxfifoW::new(self, 0)
     }
     #[doc = "Bit 1 - Clear Tx FIFO"]
     #[inline(always)]
-    pub fn txfifo(&mut self) -> TxfifoW<S0FifoClrSpec> {
+    pub fn txfifo(&mut self) -> TxfifoW<'_, S0FifoClrSpec> {
         TxfifoW::new(self, 1)
     }
 }
@@ -24,10 +24,6 @@ impl crate::RegisterSpec for S0FifoClrSpec {
 #[doc = "`write(|w| ..)` method takes [`s0_fifo_clr::W`](W) writer structure"]
 impl crate::Writable for S0FifoClrSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_FIFO_CLR to value 0"]
-impl crate::Resettable for S0FifoClrSpec {
+impl crate::Resettable for S0FifoClrSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_irq_enb.rs

@@ -151,82 +151,82 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
-    pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> {
+    pub fn completed(&mut self) -> CompletedW<'_, S0IrqEnbSpec> {
         CompletedW::new(self, 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
-    pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> {
+    pub fn idle(&mut self) -> IdleW<'_, S0IrqEnbSpec> {
         IdleW::new(self, 1)
     }
     #[doc = "Bit 2 - Controller is Waiting"]
     #[inline(always)]
-    pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> {
+    pub fn waiting(&mut self) -> WaitingW<'_, S0IrqEnbSpec> {
         WaitingW::new(self, 2)
     }
     #[doc = "Bit 3 - Controller is Tx Stalled"]
     #[inline(always)]
-    pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> {
+    pub fn txstalled(&mut self) -> TxstalledW<'_, S0IrqEnbSpec> {
         TxstalledW::new(self, 3)
     }
     #[doc = "Bit 4 - Controller is Rx Stalled"]
     #[inline(always)]
-    pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> {
+    pub fn rxstalled(&mut self) -> RxstalledW<'_, S0IrqEnbSpec> {
         RxstalledW::new(self, 4)
     }
     #[doc = "Bit 5 - I2C Address Match"]
     #[inline(always)]
-    pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> {
+    pub fn addressmatch(&mut self) -> AddressmatchW<'_, S0IrqEnbSpec> {
         AddressmatchW::new(self, 5)
     }
     #[doc = "Bit 6 - I2C Data was not Acknowledged"]
     #[inline(always)]
-    pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> {
+    pub fn nackdata(&mut self) -> NackdataW<'_, S0IrqEnbSpec> {
         NackdataW::new(self, 6)
     }
     #[doc = "Bit 7 - Pending Data is first Byte following Address"]
     #[inline(always)]
-    pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> {
+    pub fn rxdatafirst(&mut self) -> RxdatafirstW<'_, S0IrqEnbSpec> {
         RxdatafirstW::new(self, 7)
     }
     #[doc = "Bit 8 - I2C Start Condition"]
     #[inline(always)]
-    pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> {
+    pub fn i2c_start(&mut self) -> I2cStartW<'_, S0IrqEnbSpec> {
         I2cStartW::new(self, 8)
     }
     #[doc = "Bit 9 - I2C Stop Condition"]
     #[inline(always)]
-    pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> {
+    pub fn i2c_stop(&mut self) -> I2cStopW<'_, S0IrqEnbSpec> {
         I2cStopW::new(self, 9)
     }
     #[doc = "Bit 10 - TX FIFO Underflowed"]
     #[inline(always)]
-    pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> {
+    pub fn txunderflow(&mut self) -> TxunderflowW<'_, S0IrqEnbSpec> {
         TxunderflowW::new(self, 10)
     }
     #[doc = "Bit 11 - TX FIFO Overflowed"]
     #[inline(always)]
-    pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> {
+    pub fn rxoverflow(&mut self) -> RxoverflowW<'_, S0IrqEnbSpec> {
         RxoverflowW::new(self, 11)
     }
     #[doc = "Bit 12 - TX FIFO Ready"]
     #[inline(always)]
-    pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> {
+    pub fn txready(&mut self) -> TxreadyW<'_, S0IrqEnbSpec> {
         TxreadyW::new(self, 12)
     }
     #[doc = "Bit 13 - RX FIFO Ready"]
     #[inline(always)]
-    pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> {
+    pub fn rxready(&mut self) -> RxreadyW<'_, S0IrqEnbSpec> {
         RxreadyW::new(self, 13)
     }
     #[doc = "Bit 14 - TX FIFO Empty"]
     #[inline(always)]
-    pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> {
+    pub fn txempty(&mut self) -> TxemptyW<'_, S0IrqEnbSpec> {
         TxemptyW::new(self, 14)
     }
     #[doc = "Bit 15 - RX FIFO Full"]
     #[inline(always)]
-    pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> {
+    pub fn rxfull(&mut self) -> RxfullW<'_, S0IrqEnbSpec> {
         RxfullW::new(self, 15)
     }
 }
@@ -240,10 +240,6 @@ impl crate::Readable for S0IrqEnbSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_irq_enb::W`](W) writer structure"]
 impl crate::Writable for S0IrqEnbSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_IRQ_ENB to value 0"]
-impl crate::Resettable for S0IrqEnbSpec {
+impl crate::Resettable for S0IrqEnbSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_lastaddress.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for S0LastaddressSpec {
 #[doc = "`read()` method returns [`s0_lastaddress::R`](R) reader structure"]
 impl crate::Readable for S0LastaddressSpec {}
 #[doc = "`reset()` method sets S0_LASTADDRESS to value 0"]
-impl crate::Resettable for S0LastaddressSpec {
+impl crate::Resettable for S0LastaddressSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_maxwords.rs

@@ -19,10 +19,6 @@ impl crate::Readable for S0MaxwordsSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_maxwords::W`](W) writer structure"]
 impl crate::Writable for S0MaxwordsSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_MAXWORDS to value 0"]
-impl crate::Resettable for S0MaxwordsSpec {
+impl crate::Resettable for S0MaxwordsSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_rxcount.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for S0RxcountSpec {
 #[doc = "`read()` method returns [`s0_rxcount::R`](R) reader structure"]
 impl crate::Readable for S0RxcountSpec {}
 #[doc = "`reset()` method sets S0_RXCOUNT to value 0"]
-impl crate::Resettable for S0RxcountSpec {
+impl crate::Resettable for S0RxcountSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_rxfifoirqtrg.rs

@@ -19,10 +19,6 @@ impl crate::Readable for S0RxfifoirqtrgSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_rxfifoirqtrg::W`](W) writer structure"]
 impl crate::Writable for S0RxfifoirqtrgSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"]
-impl crate::Resettable for S0RxfifoirqtrgSpec {
+impl crate::Resettable for S0RxfifoirqtrgSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_state.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for S0StateSpec {
 #[doc = "`read()` method returns [`s0_state::R`](R) reader structure"]
 impl crate::Readable for S0StateSpec {}
 #[doc = "`reset()` method sets S0_STATE to value 0"]
-impl crate::Resettable for S0StateSpec {
+impl crate::Resettable for S0StateSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_status.rs

@@ -129,6 +129,4 @@ impl crate::RegisterSpec for S0StatusSpec {
 #[doc = "`read()` method returns [`s0_status::R`](R) reader structure"]
 impl crate::Readable for S0StatusSpec {}
 #[doc = "`reset()` method sets S0_STATUS to value 0"]
-impl crate::Resettable for S0StatusSpec {
+impl crate::Resettable for S0StatusSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_txcount.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for S0TxcountSpec {
 #[doc = "`read()` method returns [`s0_txcount::R`](R) reader structure"]
 impl crate::Readable for S0TxcountSpec {}
 #[doc = "`reset()` method sets S0_TXCOUNT to value 0"]
-impl crate::Resettable for S0TxcountSpec {
+impl crate::Resettable for S0TxcountSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/s0_txfifoirqtrg.rs

@@ -19,10 +19,6 @@ impl crate::Readable for S0TxfifoirqtrgSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_txfifoirqtrg::W`](W) writer structure"]
 impl crate::Writable for S0TxfifoirqtrgSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0"]
-impl crate::Resettable for S0TxfifoirqtrgSpec {
+impl crate::Resettable for S0TxfifoirqtrgSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/state.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for StateSpec {
 #[doc = "`read()` method returns [`state::R`](R) reader structure"]
 impl crate::Readable for StateSpec {}
 #[doc = "`reset()` method sets STATE to value 0"]
-impl crate::Resettable for StateSpec {
+impl crate::Resettable for StateSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/status.rs

@@ -115,6 +115,4 @@ impl crate::RegisterSpec for StatusSpec {
 #[doc = "`read()` method returns [`status::R`](R) reader structure"]
 impl crate::Readable for StatusSpec {}
 #[doc = "`reset()` method sets STATUS to value 0"]
-impl crate::Resettable for StatusSpec {
+impl crate::Resettable for StatusSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/tmconfig.rs

@@ -19,10 +19,6 @@ impl crate::Readable for TmconfigSpec {}
 #[doc = "`write(|w| ..)` method takes [`tmconfig::W`](W) writer structure"]
 impl crate::Writable for TmconfigSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets TMCONFIG to value 0"]
-impl crate::Resettable for TmconfigSpec {
+impl crate::Resettable for TmconfigSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/txcount.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for TxcountSpec {
 #[doc = "`read()` method returns [`txcount::R`](R) reader structure"]
 impl crate::Readable for TxcountSpec {}
 #[doc = "`reset()` method sets TXCOUNT to value 0"]
-impl crate::Resettable for TxcountSpec {
+impl crate::Resettable for TxcountSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/txfifoirqtrg.rs

@@ -19,10 +19,6 @@ impl crate::Readable for TxfifoirqtrgSpec {}
 #[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"]
 impl crate::Writable for TxfifoirqtrgSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"]
-impl crate::Resettable for TxfifoirqtrgSpec {
+impl crate::Resettable for TxfifoirqtrgSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/i2ca/words.rs

@@ -19,10 +19,6 @@ impl crate::Readable for WordsSpec {}
 #[doc = "`write(|w| ..)` method takes [`words::W`](W) writer structure"]
 impl crate::Writable for WordsSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets WORDS to value 0"]
-impl crate::Resettable for WordsSpec {
+impl crate::Resettable for WordsSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/ioconfig.rs

@@ -2,7 +2,7 @@
 #[doc = "Register block"]
 pub struct RegisterBlock {
     porta: [Porta; 32],
-    portb0: [Portb; 32],
+    portb: [Portb; 32],
     _reserved2: [u8; 0x0efc],
     perid: Perid,
 }
@@ -20,14 +20,14 @@ impl RegisterBlock {
     }
     #[doc = "0x80..0x100 - PORTB Pin Configuration Register"]
     #[inline(always)]
-    pub const fn portb0(&self, n: usize) -> &Portb {
+    pub const fn portb(&self, n: usize) -> &Portb {
-        &self.portb0[n]
+        &self.portb[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x80..0x100 - PORTB Pin Configuration Register"]
     #[inline(always)]
-    pub fn portb0_iter(&self) -> impl Iterator<Item = &Portb> {
+    pub fn portb_iter(&self) -> impl Iterator<Item = &Portb> {
-        self.portb0.iter()
+        self.portb.iter()
     }
     #[doc = "0xffc - Peripheral ID Register"]
     #[inline(always)]
@@ -35,16 +35,14 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`]
+#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`] module"]
-module"]
 #[doc(alias = "PORTA")]
 pub type Porta = crate::Reg<porta::PortaSpec>;
 #[doc = "PORTA Pin Configuration Register"]
 pub mod porta;
 pub use porta as portb;
 pub use Porta as Portb;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
-module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]

va108xx/src/ioconfig/porta.rs

@@ -215,57 +215,57 @@ impl R {
 impl W {
     #[doc = "Bits 0:2 - Input Filter Selectoin"]
     #[inline(always)]
-    pub fn flttype(&mut self) -> FlttypeW<PortaSpec> {
+    pub fn flttype(&mut self) -> FlttypeW<'_, PortaSpec> {
         FlttypeW::new(self, 0)
     }
     #[doc = "Bits 3:5 - Input Filter Clock Selection"]
     #[inline(always)]
-    pub fn fltclk(&mut self) -> FltclkW<PortaSpec> {
+    pub fn fltclk(&mut self) -> FltclkW<'_, PortaSpec> {
         FltclkW::new(self, 3)
     }
     #[doc = "Bit 6 - Input Invert Selection"]
     #[inline(always)]
-    pub fn invinp(&mut self) -> InvinpW<PortaSpec> {
+    pub fn invinp(&mut self) -> InvinpW<'_, PortaSpec> {
         InvinpW::new(self, 6)
     }
     #[doc = "Bit 7 - Input Enable While Output enabled"]
     #[inline(always)]
-    pub fn iewo(&mut self) -> IewoW<PortaSpec> {
+    pub fn iewo(&mut self) -> IewoW<'_, PortaSpec> {
         IewoW::new(self, 7)
     }
     #[doc = "Bit 8 - Output Open Drain Mode"]
     #[inline(always)]
-    pub fn opendrn(&mut self) -> OpendrnW<PortaSpec> {
+    pub fn opendrn(&mut self) -> OpendrnW<'_, PortaSpec> {
         OpendrnW::new(self, 8)
     }
     #[doc = "Bit 9 - Output Invert Selection"]
     #[inline(always)]
-    pub fn invout(&mut self) -> InvoutW<PortaSpec> {
+    pub fn invout(&mut self) -> InvoutW<'_, PortaSpec> {
         InvoutW::new(self, 9)
     }
     #[doc = "Bit 10 - Internal Pull up/down level"]
     #[inline(always)]
-    pub fn plevel(&mut self) -> PlevelW<PortaSpec> {
+    pub fn plevel(&mut self) -> PlevelW<'_, PortaSpec> {
         PlevelW::new(self, 10)
     }
     #[doc = "Bit 11 - Enable Internal Pull up/down"]
     #[inline(always)]
-    pub fn pen(&mut self) -> PenW<PortaSpec> {
+    pub fn pen(&mut self) -> PenW<'_, PortaSpec> {
         PenW::new(self, 11)
     }
     #[doc = "Bit 12 - Enable Pull when output active"]
     #[inline(always)]
-    pub fn pwoa(&mut self) -> PwoaW<PortaSpec> {
+    pub fn pwoa(&mut self) -> PwoaW<'_, PortaSpec> {
         PwoaW::new(self, 12)
     }
     #[doc = "Bits 13:15 - Pin Function Selection"]
     #[inline(always)]
-    pub fn funsel(&mut self) -> FunselW<PortaSpec> {
+    pub fn funsel(&mut self) -> FunselW<'_, PortaSpec> {
         FunselW::new(self, 13)
     }
     #[doc = "Bit 16 - IO Pin Disable"]
     #[inline(always)]
-    pub fn iodis(&mut self) -> IodisW<PortaSpec> {
+    pub fn iodis(&mut self) -> IodisW<'_, PortaSpec> {
         IodisW::new(self, 16)
     }
 }
@@ -279,11 +279,6 @@ impl crate::Readable for PortaSpec {}
 #[doc = "`write(|w| ..)` method takes [`porta::W`](W) writer structure"]
 impl crate::Writable for PortaSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-}
-#[doc = "`reset()` method sets PORTA[%s]
-to value 0"]
-impl crate::Resettable for PortaSpec {
-    const RESET_VALUE: u32 = 0;
 }
+#[doc = "`reset()` method sets PORTA[%s] to value 0"]
+impl crate::Resettable for PortaSpec {}

va108xx/src/irqsel.rs

@@ -1,20 +1,20 @@
 #[repr(C)]
 #[doc = "Register block"]
 pub struct RegisterBlock {
-    porta0: [Porta; 32],
+    porta: [Porta; 32],
-    portb0: [Portb; 32],
+    portb: [Portb; 32],
-    tim0: [Tim; 32],
+    tim: [Tim; 32],
-    uart0: [Uart; 4],
+    uart: [Uart; 4],
-    spi0: [Spi; 4],
+    spi: [Spi; 4],
-    i2c_ms0: [I2cMs; 4],
+    i2c_ms: [I2cMs; 4],
-    i2c_sl0: [I2cSl; 4],
+    i2c_sl: [I2cSl; 4],
     int_ram_sbe: IntRamSbe,
     int_ram_mbe: IntRamMbe,
     int_rom_sbe: IntRomSbe,
     int_rom_mbe: IntRomMbe,
     txev: Txev,
     _reserved12: [u8; 0x062c],
-    irqs0: [Irqs; 32],
+    irqs: [Irqs; 32],
     _reserved13: [u8; 0x68],
     edbgrq: Edbgrq,
     mereset: Mereset,
@@ -27,80 +27,80 @@ pub struct RegisterBlock {
 impl RegisterBlock {
     #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
     #[inline(always)]
-    pub const fn porta0(&self, n: usize) -> &Porta {
+    pub const fn porta(&self, n: usize) -> &Porta {
-        &self.porta0[n]
+        &self.porta[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
     #[inline(always)]
-    pub fn porta0_iter(&self) -> impl Iterator<Item = &Porta> {
+    pub fn porta_iter(&self) -> impl Iterator<Item = &Porta> {
-        self.porta0.iter()
+        self.porta.iter()
     }
     #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
     #[inline(always)]
-    pub const fn portb0(&self, n: usize) -> &Portb {
+    pub const fn portb(&self, n: usize) -> &Portb {
-        &self.portb0[n]
+        &self.portb[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
     #[inline(always)]
-    pub fn portb0_iter(&self) -> impl Iterator<Item = &Portb> {
+    pub fn portb_iter(&self) -> impl Iterator<Item = &Portb> {
-        self.portb0.iter()
+        self.portb.iter()
     }
     #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
     #[inline(always)]
-    pub const fn tim0(&self, n: usize) -> &Tim {
+    pub const fn tim(&self, n: usize) -> &Tim {
-        &self.tim0[n]
+        &self.tim[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
     #[inline(always)]
-    pub fn tim0_iter(&self) -> impl Iterator<Item = &Tim> {
+    pub fn tim_iter(&self) -> impl Iterator<Item = &Tim> {
-        self.tim0.iter()
+        self.tim.iter()
     }
     #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
     #[inline(always)]
-    pub const fn uart0(&self, n: usize) -> &Uart {
+    pub const fn uart(&self, n: usize) -> &Uart {
-        &self.uart0[n]
+        &self.uart[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
     #[inline(always)]
-    pub fn uart0_iter(&self) -> impl Iterator<Item = &Uart> {
+    pub fn uart_iter(&self) -> impl Iterator<Item = &Uart> {
-        self.uart0.iter()
+        self.uart.iter()
     }
     #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
     #[inline(always)]
-    pub const fn spi0(&self, n: usize) -> &Spi {
+    pub const fn spi(&self, n: usize) -> &Spi {
-        &self.spi0[n]
+        &self.spi[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
     #[inline(always)]
-    pub fn spi0_iter(&self) -> impl Iterator<Item = &Spi> {
+    pub fn spi_iter(&self) -> impl Iterator<Item = &Spi> {
-        self.spi0.iter()
+        self.spi.iter()
     }
     #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
     #[inline(always)]
-    pub const fn i2c_ms0(&self, n: usize) -> &I2cMs {
+    pub const fn i2c_ms(&self, n: usize) -> &I2cMs {
-        &self.i2c_ms0[n]
+        &self.i2c_ms[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
     #[inline(always)]
-    pub fn i2c_ms0_iter(&self) -> impl Iterator<Item = &I2cMs> {
+    pub fn i2c_ms_iter(&self) -> impl Iterator<Item = &I2cMs> {
-        self.i2c_ms0.iter()
+        self.i2c_ms.iter()
     }
     #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
     #[inline(always)]
-    pub const fn i2c_sl0(&self, n: usize) -> &I2cSl {
+    pub const fn i2c_sl(&self, n: usize) -> &I2cSl {
-        &self.i2c_sl0[n]
+        &self.i2c_sl[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
     #[inline(always)]
-    pub fn i2c_sl0_iter(&self) -> impl Iterator<Item = &I2cSl> {
+    pub fn i2c_sl_iter(&self) -> impl Iterator<Item = &I2cSl> {
-        self.i2c_sl0.iter()
+        self.i2c_sl.iter()
     }
     #[doc = "0x1c0 - Internal Memory RAM SBE Interrupt Redirect Selection"]
     #[inline(always)]
@@ -129,14 +129,14 @@ impl RegisterBlock {
     }
     #[doc = "0x800..0x880 - Interrupt Status Register"]
     #[inline(always)]
-    pub const fn irqs0(&self, n: usize) -> &Irqs {
+    pub const fn irqs(&self, n: usize) -> &Irqs {
-        &self.irqs0[n]
+        &self.irqs[n]
     }
     #[doc = "Iterator for array of:"]
     #[doc = "0x800..0x880 - Interrupt Status Register"]
     #[inline(always)]
-    pub fn irqs0_iter(&self) -> impl Iterator<Item = &Irqs> {
+    pub fn irqs_iter(&self) -> impl Iterator<Item = &Irqs> {
-        self.irqs0.iter()
+        self.irqs.iter()
     }
     #[doc = "0x8e8 - EDBGRQ Status Register"]
     #[inline(always)]
@@ -169,8 +169,7 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`]
+#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`] module"]
-module"]
 #[doc(alias = "INT_RAM_SBE")]
 pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>;
 #[doc = "Internal Memory RAM SBE Interrupt Redirect Selection"]
@@ -197,8 +196,7 @@ pub use IntRamSbe as IntRamMbe;
 pub use IntRamSbe as IntRomSbe;
 pub use IntRamSbe as IntRomMbe;
 pub use IntRamSbe as Txev;
-#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`]
+#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`] module"]
-module"]
 #[doc(alias = "NMI")]
 pub type Nmi = crate::Reg<nmi::NmiSpec>;
 #[doc = "NMI Status Register"]
@@ -213,8 +211,7 @@ pub use Nmi as Watchdog;
 pub use Nmi as Mereset;
 pub use Nmi as Edbgrq;
 pub use Nmi as Irqs;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
-module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]

va108xx/src/irqsel/int_ram_sbe.rs

@@ -19,8 +19,6 @@ impl crate::Readable for IntRamSbeSpec {}
 #[doc = "`write(|w| ..)` method takes [`int_ram_sbe::W`](W) writer structure"]
 impl crate::Writable for IntRamSbeSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets INT_RAM_SBE to value 0xffff_ffff"]
 impl crate::Resettable for IntRamSbeSpec {

va108xx/src/irqsel/nmi.rs

@@ -17,6 +17,4 @@ impl crate::RegisterSpec for NmiSpec {
 #[doc = "`read()` method returns [`nmi::R`](R) reader structure"]
 impl crate::Readable for NmiSpec {}
 #[doc = "`reset()` method sets NMI to value 0"]
-impl crate::Resettable for NmiSpec {
+impl crate::Resettable for NmiSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/porta.rs

@@ -45,7 +45,7 @@ impl RegisterBlock {
     }
     #[doc = "0x04 - Data In Raw Register by Byte"]
     #[inline(always)]
-    pub const fn datainrawbyte0(&self, n: usize) -> &Datainrawbyte {
+    pub const fn datainrawbyte(&self, n: usize) -> &Datainrawbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
         unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() }
@@ -53,7 +53,7 @@ impl RegisterBlock {
     #[doc = "Iterator for array of:"]
     #[doc = "0x04 - Data In Raw Register by Byte"]
     #[inline(always)]
-    pub fn datainrawbyte0_iter(&self) -> impl Iterator<Item = &Datainrawbyte> {
+    pub fn datainrawbyte_iter(&self) -> impl Iterator<Item = &Datainrawbyte> {
         (0..4)
             .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() })
     }
@@ -83,7 +83,7 @@ impl RegisterBlock {
     }
     #[doc = "0x0c - Data Out Register by Byte"]
     #[inline(always)]
-    pub const fn dataoutrawbyte0(&self, n: usize) -> &Dataoutrawbyte {
+    pub const fn dataoutrawbyte(&self, n: usize) -> &Dataoutrawbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
         unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() }
@@ -91,7 +91,7 @@ impl RegisterBlock {
     #[doc = "Iterator for array of:"]
     #[doc = "0x0c - Data Out Register by Byte"]
     #[inline(always)]
-    pub fn dataoutrawbyte0_iter(&self) -> impl Iterator<Item = &Dataoutrawbyte> {
+    pub fn dataoutrawbyte_iter(&self) -> impl Iterator<Item = &Dataoutrawbyte> {
         (0..4)
             .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() })
     }
@@ -102,7 +102,7 @@ impl RegisterBlock {
     }
     #[doc = "0x10 - Set Out Register by Byte"]
     #[inline(always)]
-    pub const fn setoutbyte0(&self, n: usize) -> &Setoutbyte {
+    pub const fn setoutbyte(&self, n: usize) -> &Setoutbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
         unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() }
@@ -110,7 +110,7 @@ impl RegisterBlock {
     #[doc = "Iterator for array of:"]
     #[doc = "0x10 - Set Out Register by Byte"]
     #[inline(always)]
-    pub fn setoutbyte0_iter(&self) -> impl Iterator<Item = &Setoutbyte> {
+    pub fn setoutbyte_iter(&self) -> impl Iterator<Item = &Setoutbyte> {
         (0..4)
             .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() })
     }
@@ -121,7 +121,7 @@ impl RegisterBlock {
     }
     #[doc = "0x14 - Clear Out Register by Byte"]
     #[inline(always)]
-    pub const fn clroutbyte0(&self, n: usize) -> &Clroutbyte {
+    pub const fn clroutbyte(&self, n: usize) -> &Clroutbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
         unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() }
@@ -129,7 +129,7 @@ impl RegisterBlock {
     #[doc = "Iterator for array of:"]
     #[doc = "0x14 - Clear Out Register by Byte"]
     #[inline(always)]
-    pub fn clroutbyte0_iter(&self) -> impl Iterator<Item = &Clroutbyte> {
+    pub fn clroutbyte_iter(&self) -> impl Iterator<Item = &Clroutbyte> {
         (0..4)
             .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() })
     }
@@ -140,7 +140,7 @@ impl RegisterBlock {
     }
     #[doc = "0x18 - Toggle Out Register by Byte"]
     #[inline(always)]
-    pub const fn togoutbyte0(&self, n: usize) -> &Togoutbyte {
+    pub const fn togoutbyte(&self, n: usize) -> &Togoutbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
         unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() }
@@ -148,7 +148,7 @@ impl RegisterBlock {
     #[doc = "Iterator for array of:"]
     #[doc = "0x18 - Toggle Out Register by Byte"]
     #[inline(always)]
-    pub fn togoutbyte0_iter(&self) -> impl Iterator<Item = &Togoutbyte> {
+    pub fn togoutbyte_iter(&self) -> impl Iterator<Item = &Togoutbyte> {
         (0..4)
             .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() })
     }
@@ -178,7 +178,7 @@ impl RegisterBlock {
     }
     #[doc = "0x20 - Direction Register by Byte"]
     #[inline(always)]
-    pub const fn dirbyte0(&self, n: usize) -> &Dirbyte {
+    pub const fn dirbyte(&self, n: usize) -> &Dirbyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
         unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() }
@@ -186,7 +186,7 @@ impl RegisterBlock {
     #[doc = "Iterator for array of:"]
     #[doc = "0x20 - Direction Register by Byte"]
     #[inline(always)]
-    pub fn dirbyte0_iter(&self) -> impl Iterator<Item = &Dirbyte> {
+    pub fn dirbyte_iter(&self) -> impl Iterator<Item = &Dirbyte> {
         (0..4)
             .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() })
     }
@@ -197,7 +197,7 @@ impl RegisterBlock {
     }
     #[doc = "0x24 - Pulse Mode Register by Byte"]
     #[inline(always)]
-    pub const fn pulsebyte0(&self, n: usize) -> &Pulsebyte {
+    pub const fn pulsebyte(&self, n: usize) -> &Pulsebyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
         unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() }
@@ -205,7 +205,7 @@ impl RegisterBlock {
     #[doc = "Iterator for array of:"]
     #[doc = "0x24 - Pulse Mode Register by Byte"]
     #[inline(always)]
-    pub fn pulsebyte0_iter(&self) -> impl Iterator<Item = &Pulsebyte> {
+    pub fn pulsebyte_iter(&self) -> impl Iterator<Item = &Pulsebyte> {
         (0..4)
             .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() })
     }
@@ -216,7 +216,7 @@ impl RegisterBlock {
     }
     #[doc = "0x28 - Pulse Base Mode Register by Byte"]
     #[inline(always)]
-    pub const fn pulsebasebyte0(&self, n: usize) -> &Pulsebasebyte {
+    pub const fn pulsebasebyte(&self, n: usize) -> &Pulsebasebyte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
         unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() }
@@ -224,7 +224,7 @@ impl RegisterBlock {
     #[doc = "Iterator for array of:"]
     #[doc = "0x28 - Pulse Base Mode Register by Byte"]
     #[inline(always)]
-    pub fn pulsebasebyte0_iter(&self) -> impl Iterator<Item = &Pulsebasebyte> {
+    pub fn pulsebasebyte_iter(&self) -> impl Iterator<Item = &Pulsebasebyte> {
         (0..4)
             .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() })
     }
@@ -235,7 +235,7 @@ impl RegisterBlock {
     }
     #[doc = "0x2c - Delay1 Register by Byte"]
     #[inline(always)]
-    pub const fn delay1byte0(&self, n: usize) -> &Delay1byte {
+    pub const fn delay1byte(&self, n: usize) -> &Delay1byte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
         unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() }
@@ -243,7 +243,7 @@ impl RegisterBlock {
     #[doc = "Iterator for array of:"]
     #[doc = "0x2c - Delay1 Register by Byte"]
     #[inline(always)]
-    pub fn delay1byte0_iter(&self) -> impl Iterator<Item = &Delay1byte> {
+    pub fn delay1byte_iter(&self) -> impl Iterator<Item = &Delay1byte> {
         (0..4)
             .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() })
     }
@@ -254,7 +254,7 @@ impl RegisterBlock {
     }
     #[doc = "0x30 - Delay2 Register by Byte"]
     #[inline(always)]
-    pub const fn delay2byte0(&self, n: usize) -> &Delay2byte {
+    pub const fn delay2byte(&self, n: usize) -> &Delay2byte {
         #[allow(clippy::no_effect)]
         [(); 4][n];
         unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() }
@@ -262,7 +262,7 @@ impl RegisterBlock {
     #[doc = "Iterator for array of:"]
     #[doc = "0x30 - Delay2 Register by Byte"]
     #[inline(always)]
-    pub fn delay2byte0_iter(&self) -> impl Iterator<Item = &Delay2byte> {
+    pub fn delay2byte_iter(&self) -> impl Iterator<Item = &Delay2byte> {
         (0..4)
             .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() })
     }
@@ -312,14 +312,12 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`]
+#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`] module"]
-module"]
 #[doc(alias = "DATAIN")]
 pub type Datain = crate::Reg<datain::DatainSpec>;
 #[doc = "Data In Register"]
 pub mod datain;
-#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`]
+#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`] module"]
-module"]
 #[doc(alias = "DATAINBYTE")]
 pub type Datainbyte = crate::Reg<datainbyte::DatainbyteSpec>;
 #[doc = "Data In Register by Byte"]
@@ -328,14 +326,12 @@ pub use datain as datainraw;
 pub use datainbyte as datainrawbyte;
 pub use Datain as Datainraw;
 pub use Datainbyte as Datainrawbyte;
-#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`]
+#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`] module"]
-module"]
 #[doc(alias = "DATAOUT")]
 pub type Dataout = crate::Reg<dataout::DataoutSpec>;
 #[doc = "Data Out Register"]
 pub mod dataout;
-#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`]
+#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`] module"]
-module"]
 #[doc(alias = "DATAOUTBYTE")]
 pub type Dataoutbyte = crate::Reg<dataoutbyte::DataoutbyteSpec>;
 #[doc = "Data Out Register by Byte"]
@@ -356,14 +352,12 @@ pub use Dataoutbyte as Dataoutrawbyte;
 pub use Dataoutbyte as Setoutbyte;
 pub use Dataoutbyte as Clroutbyte;
 pub use Dataoutbyte as Togoutbyte;
-#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`]
+#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`] module"]
-module"]
 #[doc(alias = "DATAMASK")]
 pub type Datamask = crate::Reg<datamask::DatamaskSpec>;
 #[doc = "Data mask Register"]
 pub mod datamask;
-#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`]
+#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`] module"]
-module"]
 #[doc(alias = "DATAMASKBYTE")]
 pub type Datamaskbyte = crate::Reg<datamaskbyte::DatamaskbyteSpec>;
 #[doc = "Data Out Register by Byte"]
@@ -388,50 +382,42 @@ pub use Datamaskbyte as Pulsebyte;
 pub use Datamaskbyte as Pulsebasebyte;
 pub use Datamaskbyte as Delay1byte;
 pub use Datamaskbyte as Delay2byte;
-#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`]
+#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`] module"]
-module"]
 #[doc(alias = "IRQ_SEN")]
 pub type IrqSen = crate::Reg<irq_sen::IrqSenSpec>;
 #[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
 pub mod irq_sen;
-#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`]
+#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`] module"]
-module"]
 #[doc(alias = "IRQ_EDGE")]
 pub type IrqEdge = crate::Reg<irq_edge::IrqEdgeSpec>;
 #[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"]
 pub mod irq_edge;
-#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`]
+#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`] module"]
-module"]
 #[doc(alias = "IRQ_EVT")]
 pub type IrqEvt = crate::Reg<irq_evt::IrqEvtSpec>;
 #[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"]
 pub mod irq_evt;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
-module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
 #[doc = "Interrupt Enable Register"]
 pub mod irq_enb;
-#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
+#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] module"]
-module"]
 #[doc(alias = "IRQ_RAW")]
 pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>;
 #[doc = "Raw Interrupt Status"]
 pub mod irq_raw;
-#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
+#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] module"]
-module"]
 #[doc(alias = "IRQ_END")]
 pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>;
 #[doc = "Masked Interrupt Status"]
 pub mod irq_end;
-#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`]
+#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`] module"]
-module"]
 #[doc(alias = "EDGE_STATUS")]
 pub type EdgeStatus = crate::Reg<edge_status::EdgeStatusSpec>;
 #[doc = "Edge Status Register"]
 pub mod edge_status;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
-module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]

va108xx/src/porta/datain.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for DatainSpec {
 #[doc = "`read()` method returns [`datain::R`](R) reader structure"]
 impl crate::Readable for DatainSpec {}
 #[doc = "`reset()` method sets DATAIN to value 0"]
-impl crate::Resettable for DatainSpec {
+impl crate::Resettable for DatainSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/porta/datainbyte.rs

@@ -13,8 +13,5 @@ impl crate::RegisterSpec for DatainbyteSpec {
 }
 #[doc = "`read()` method returns [`datainbyte::R`](R) reader structure"]
 impl crate::Readable for DatainbyteSpec {}
-#[doc = "`reset()` method sets DATAINBYTE[%s]
+#[doc = "`reset()` method sets DATAINBYTE[%s] to value 0"]
-to value 0"]
+impl crate::Resettable for DatainbyteSpec {}
-impl crate::Resettable for DatainbyteSpec {
-    const RESET_VALUE: u8 = 0;
-}

va108xx/src/porta/datamask.rs

@@ -19,10 +19,6 @@ impl crate::Readable for DatamaskSpec {}
 #[doc = "`write(|w| ..)` method takes [`datamask::W`](W) writer structure"]
 impl crate::Writable for DatamaskSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets DATAMASK to value 0"]
-impl crate::Resettable for DatamaskSpec {
+impl crate::Resettable for DatamaskSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/porta/datamaskbyte.rs

@@ -19,11 +19,6 @@ impl crate::Readable for DatamaskbyteSpec {}
 #[doc = "`write(|w| ..)` method takes [`datamaskbyte::W`](W) writer structure"]
 impl crate::Writable for DatamaskbyteSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
-}
-#[doc = "`reset()` method sets DATAMASKBYTE[%s]
-to value 0"]
-impl crate::Resettable for DatamaskbyteSpec {
-    const RESET_VALUE: u8 = 0;
 }
+#[doc = "`reset()` method sets DATAMASKBYTE[%s] to value 0"]
+impl crate::Resettable for DatamaskbyteSpec {}

va108xx/src/porta/dataout.rs

@@ -15,10 +15,6 @@ impl crate::RegisterSpec for DataoutSpec {
 #[doc = "`write(|w| ..)` method takes [`dataout::W`](W) writer structure"]
 impl crate::Writable for DataoutSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets DATAOUT to value 0"]
-impl crate::Resettable for DataoutSpec {
+impl crate::Resettable for DataoutSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/porta/dataoutbyte.rs

@@ -15,11 +15,6 @@ impl crate::RegisterSpec for DataoutbyteSpec {
 #[doc = "`write(|w| ..)` method takes [`dataoutbyte::W`](W) writer structure"]
 impl crate::Writable for DataoutbyteSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
-}
-#[doc = "`reset()` method sets DATAOUTBYTE[%s]
-to value 0"]
-impl crate::Resettable for DataoutbyteSpec {
-    const RESET_VALUE: u8 = 0;
 }
+#[doc = "`reset()` method sets DATAOUTBYTE[%s] to value 0"]
+impl crate::Resettable for DataoutbyteSpec {}

va108xx/src/porta/edge_status.rs

@@ -19,10 +19,6 @@ impl crate::Readable for EdgeStatusSpec {}
 #[doc = "`write(|w| ..)` method takes [`edge_status::W`](W) writer structure"]
 impl crate::Writable for EdgeStatusSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets EDGE_STATUS to value 0"]
-impl crate::Resettable for EdgeStatusSpec {
+impl crate::Resettable for EdgeStatusSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/porta/irq_edge.rs

@@ -19,10 +19,6 @@ impl crate::Readable for IrqEdgeSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_edge::W`](W) writer structure"]
 impl crate::Writable for IrqEdgeSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_EDGE to value 0"]
-impl crate::Resettable for IrqEdgeSpec {
+impl crate::Resettable for IrqEdgeSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/porta/irq_enb.rs

@@ -19,10 +19,6 @@ impl crate::Readable for IrqEnbSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
 impl crate::Writable for IrqEnbSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_ENB to value 0"]
-impl crate::Resettable for IrqEnbSpec {
+impl crate::Resettable for IrqEnbSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/porta/irq_end.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for IrqEndSpec {
 #[doc = "`read()` method returns [`irq_end::R`](R) reader structure"]
 impl crate::Readable for IrqEndSpec {}
 #[doc = "`reset()` method sets IRQ_END to value 0"]
-impl crate::Resettable for IrqEndSpec {
+impl crate::Resettable for IrqEndSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/porta/irq_evt.rs

@@ -19,10 +19,6 @@ impl crate::Readable for IrqEvtSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_evt::W`](W) writer structure"]
 impl crate::Writable for IrqEvtSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_EVT to value 0"]
-impl crate::Resettable for IrqEvtSpec {
+impl crate::Resettable for IrqEvtSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/porta/irq_raw.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for IrqRawSpec {
 #[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"]
 impl crate::Readable for IrqRawSpec {}
 #[doc = "`reset()` method sets IRQ_RAW to value 0"]
-impl crate::Resettable for IrqRawSpec {
+impl crate::Resettable for IrqRawSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/porta/irq_sen.rs

@@ -19,10 +19,6 @@ impl crate::Readable for IrqSenSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_sen::W`](W) writer structure"]
 impl crate::Writable for IrqSenSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_SEN to value 0"]
-impl crate::Resettable for IrqSenSpec {
+impl crate::Resettable for IrqSenSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/spia.rs

@@ -89,38 +89,32 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
+#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] module"]
-module"]
 #[doc(alias = "CTRL0")]
 pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>;
 #[doc = "Control Register 0"]
 pub mod ctrl0;
-#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
+#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"]
-module"]
 #[doc(alias = "CTRL1")]
 pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>;
 #[doc = "Control Register 1"]
 pub mod ctrl1;
-#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
-module"]
 #[doc(alias = "DATA")]
 pub type Data = crate::Reg<data::DataSpec>;
 #[doc = "Data Input/Output"]
 pub mod data;
-#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
+#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
-module"]
 #[doc(alias = "STATUS")]
 pub type Status = crate::Reg<status::StatusSpec>;
 #[doc = "Status Register"]
 pub mod status;
-#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`]
+#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`] module"]
-module"]
 #[doc(alias = "CLKPRESCALE")]
 pub type Clkprescale = crate::Reg<clkprescale::ClkprescaleSpec>;
 #[doc = "Clock Pre Scale divide value"]
 pub mod clkprescale;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
-module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
 #[doc = "Interrupt Enable Register"]
@@ -131,32 +125,27 @@ pub use irq_enb as irq_clr;
 pub use IrqEnb as IrqRaw;
 pub use IrqEnb as IrqEnd;
 pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"]
-module"]
 #[doc(alias = "RXFIFOIRQTRG")]
 pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
 #[doc = "Rx FIFO IRQ Trigger Level"]
 pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"]
-module"]
 #[doc(alias = "TXFIFOIRQTRG")]
 pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
 #[doc = "Tx FIFO IRQ Trigger Level"]
 pub mod txfifoirqtrg;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"]
-module"]
 #[doc(alias = "FIFO_CLR")]
 pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
 #[doc = "Clear FIFO Register"]
 pub mod fifo_clr;
-#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"]
-module"]
 #[doc(alias = "STATE")]
 pub type State = crate::Reg<state::StateSpec>;
 #[doc = "Internal STATE of SPI Controller"]
 pub mod state;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
-module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]

va108xx/src/spia/clkprescale.rs

@@ -19,10 +19,6 @@ impl crate::Readable for ClkprescaleSpec {}
 #[doc = "`write(|w| ..)` method takes [`clkprescale::W`](W) writer structure"]
 impl crate::Writable for ClkprescaleSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CLKPRESCALE to value 0"]
-impl crate::Resettable for ClkprescaleSpec {
+impl crate::Resettable for ClkprescaleSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/spia/ctrl0.rs

@@ -43,22 +43,22 @@ impl R {
 impl W {
     #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
     #[inline(always)]
-    pub fn size(&mut self) -> SizeW<Ctrl0Spec> {
+    pub fn size(&mut self) -> SizeW<'_, Ctrl0Spec> {
         SizeW::new(self, 0)
     }
     #[doc = "Bit 6 - SPI Clock Polarity"]
     #[inline(always)]
-    pub fn spo(&mut self) -> SpoW<Ctrl0Spec> {
+    pub fn spo(&mut self) -> SpoW<'_, Ctrl0Spec> {
         SpoW::new(self, 6)
     }
     #[doc = "Bit 7 - SPI Clock Phase"]
     #[inline(always)]
-    pub fn sph(&mut self) -> SphW<Ctrl0Spec> {
+    pub fn sph(&mut self) -> SphW<'_, Ctrl0Spec> {
         SphW::new(self, 7)
     }
     #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
     #[inline(always)]
-    pub fn scrdv(&mut self) -> ScrdvW<Ctrl0Spec> {
+    pub fn scrdv(&mut self) -> ScrdvW<'_, Ctrl0Spec> {
         ScrdvW::new(self, 8)
     }
 }
@@ -72,10 +72,6 @@ impl crate::Readable for Ctrl0Spec {}
 #[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"]
 impl crate::Writable for Ctrl0Spec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CTRL0 to value 0"]
-impl crate::Resettable for Ctrl0Spec {
+impl crate::Resettable for Ctrl0Spec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/spia/ctrl1.rs

@@ -97,52 +97,52 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Loop Back"]
     #[inline(always)]
-    pub fn lbm(&mut self) -> LbmW<Ctrl1Spec> {
+    pub fn lbm(&mut self) -> LbmW<'_, Ctrl1Spec> {
         LbmW::new(self, 0)
     }
     #[doc = "Bit 1 - Enable"]
     #[inline(always)]
-    pub fn enable(&mut self) -> EnableW<Ctrl1Spec> {
+    pub fn enable(&mut self) -> EnableW<'_, Ctrl1Spec> {
         EnableW::new(self, 1)
     }
     #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"]
     #[inline(always)]
-    pub fn ms(&mut self) -> MsW<Ctrl1Spec> {
+    pub fn ms(&mut self) -> MsW<'_, Ctrl1Spec> {
         MsW::new(self, 2)
     }
     #[doc = "Bit 3 - Slave output Disable"]
     #[inline(always)]
-    pub fn sod(&mut self) -> SodW<Ctrl1Spec> {
+    pub fn sod(&mut self) -> SodW<'_, Ctrl1Spec> {
         SodW::new(self, 3)
     }
     #[doc = "Bits 4:6 - Slave Select"]
     #[inline(always)]
-    pub fn ss(&mut self) -> SsW<Ctrl1Spec> {
+    pub fn ss(&mut self) -> SsW<'_, Ctrl1Spec> {
         SsW::new(self, 4)
     }
     #[doc = "Bit 7 - Block Mode Enable"]
     #[inline(always)]
-    pub fn blockmode(&mut self) -> BlockmodeW<Ctrl1Spec> {
+    pub fn blockmode(&mut self) -> BlockmodeW<'_, Ctrl1Spec> {
         BlockmodeW::new(self, 7)
     }
     #[doc = "Bit 8 - Block Mode Start Status Enable"]
     #[inline(always)]
-    pub fn bmstart(&mut self) -> BmstartW<Ctrl1Spec> {
+    pub fn bmstart(&mut self) -> BmstartW<'_, Ctrl1Spec> {
         BmstartW::new(self, 8)
     }
     #[doc = "Bit 9 - Block Mode Stall Enable"]
     #[inline(always)]
-    pub fn bmstall(&mut self) -> BmstallW<Ctrl1Spec> {
+    pub fn bmstall(&mut self) -> BmstallW<'_, Ctrl1Spec> {
         BmstallW::new(self, 9)
     }
     #[doc = "Bit 10 - Master Delayed Capture Enable"]
     #[inline(always)]
-    pub fn mdlycap(&mut self) -> MdlycapW<Ctrl1Spec> {
+    pub fn mdlycap(&mut self) -> MdlycapW<'_, Ctrl1Spec> {
         MdlycapW::new(self, 10)
     }
     #[doc = "Bit 11 - Master Tx Pause Enable"]
     #[inline(always)]
-    pub fn mtxpause(&mut self) -> MtxpauseW<Ctrl1Spec> {
+    pub fn mtxpause(&mut self) -> MtxpauseW<'_, Ctrl1Spec> {
         MtxpauseW::new(self, 11)
     }
 }
@@ -156,10 +156,6 @@ impl crate::Readable for Ctrl1Spec {}
 #[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"]
 impl crate::Writable for Ctrl1Spec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CTRL1 to value 0"]
-impl crate::Resettable for Ctrl1Spec {
+impl crate::Resettable for Ctrl1Spec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/spia/data.rs

@@ -19,10 +19,6 @@ impl crate::Readable for DataSpec {}
 #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
 impl crate::Writable for DataSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets DATA to value 0"]
-impl crate::Resettable for DataSpec {
+impl crate::Resettable for DataSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/spia/fifo_clr.rs

@@ -7,12 +7,12 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
     #[doc = "Bit 0 - Clear Rx FIFO"]
     #[inline(always)]
-    pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
+    pub fn rxfifo(&mut self) -> RxfifoW<'_, FifoClrSpec> {
         RxfifoW::new(self, 0)
     }
     #[doc = "Bit 1 - Clear Tx FIFO"]
     #[inline(always)]
-    pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
+    pub fn txfifo(&mut self) -> TxfifoW<'_, FifoClrSpec> {
         TxfifoW::new(self, 1)
     }
 }
@@ -24,10 +24,6 @@ impl crate::RegisterSpec for FifoClrSpec {
 #[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"]
 impl crate::Writable for FifoClrSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets FIFO_CLR to value 0"]
-impl crate::Resettable for FifoClrSpec {
+impl crate::Resettable for FifoClrSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/spia/irq_enb.rs

@@ -43,22 +43,22 @@ impl R {
 impl W {
     #[doc = "Bit 0 - RX Overrun"]
     #[inline(always)]
-    pub fn rorim(&mut self) -> RorimW<IrqEnbSpec> {
+    pub fn rorim(&mut self) -> RorimW<'_, IrqEnbSpec> {
         RorimW::new(self, 0)
     }
     #[doc = "Bit 1 - RX Timeout"]
     #[inline(always)]
-    pub fn rtim(&mut self) -> RtimW<IrqEnbSpec> {
+    pub fn rtim(&mut self) -> RtimW<'_, IrqEnbSpec> {
         RtimW::new(self, 1)
     }
     #[doc = "Bit 2 - RX Fifo is at least half full"]
     #[inline(always)]
-    pub fn rxim(&mut self) -> RximW<IrqEnbSpec> {
+    pub fn rxim(&mut self) -> RximW<'_, IrqEnbSpec> {
         RximW::new(self, 2)
     }
     #[doc = "Bit 3 - TX Fifo is at least half empty"]
     #[inline(always)]
-    pub fn txim(&mut self) -> TximW<IrqEnbSpec> {
+    pub fn txim(&mut self) -> TximW<'_, IrqEnbSpec> {
         TximW::new(self, 3)
     }
 }
@@ -72,10 +72,6 @@ impl crate::Readable for IrqEnbSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
 impl crate::Writable for IrqEnbSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_ENB to value 0"]
-impl crate::Resettable for IrqEnbSpec {
+impl crate::Resettable for IrqEnbSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/spia/rxfifoirqtrg.rs

@@ -19,10 +19,6 @@ impl crate::Readable for RxfifoirqtrgSpec {}
 #[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"]
 impl crate::Writable for RxfifoirqtrgSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"]
-impl crate::Resettable for RxfifoirqtrgSpec {
+impl crate::Resettable for RxfifoirqtrgSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/spia/state.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for StateSpec {
 #[doc = "`read()` method returns [`state::R`](R) reader structure"]
 impl crate::Readable for StateSpec {}
 #[doc = "`reset()` method sets STATE to value 0"]
-impl crate::Resettable for StateSpec {
+impl crate::Resettable for StateSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/spia/status.rs

@@ -66,6 +66,4 @@ impl crate::RegisterSpec for StatusSpec {
 #[doc = "`read()` method returns [`status::R`](R) reader structure"]
 impl crate::Readable for StatusSpec {}
 #[doc = "`reset()` method sets STATUS to value 0"]
-impl crate::Resettable for StatusSpec {
+impl crate::Resettable for StatusSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/spia/txfifoirqtrg.rs

@@ -19,10 +19,6 @@ impl crate::Readable for TxfifoirqtrgSpec {}
 #[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"]
 impl crate::Writable for TxfifoirqtrgSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"]
-impl crate::Resettable for TxfifoirqtrgSpec {
+impl crate::Resettable for TxfifoirqtrgSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig.rs

@@ -234,8 +234,7 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`]
+#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`] module"]
-module"]
 #[doc(alias = "RST_STAT")]
 pub type RstStat = crate::Reg<rst_stat::RstStatSpec>;
 #[doc = "System Reset Status"]
@@ -244,28 +243,24 @@ pub use rst_stat as rst_cntl_rom;
 pub use rst_stat as rst_cntl_ram;
 pub use RstStat as RstCntlRom;
 pub use RstStat as RstCntlRam;
-#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`]
+#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`] module"]
-module"]
 #[doc(alias = "ROM_PROT")]
 pub type RomProt = crate::Reg<rom_prot::RomProtSpec>;
 #[doc = "ROM Protection Configuration"]
 pub mod rom_prot;
-#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`]
+#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`] module"]
-module"]
 #[doc(alias = "ROM_SCRUB")]
 pub type RomScrub = crate::Reg<rom_scrub::RomScrubSpec>;
 #[doc = "ROM Scrub Period Configuration"]
 pub mod rom_scrub;
 pub use rom_scrub as ram_scrub;
 pub use RomScrub as RamScrub;
-#[doc = "ROM_TRAP_ADDR (rw) register accessor: ROM Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_addr`]
+#[doc = "ROM_TRAP_ADDR (rw) register accessor: ROM Trap Address\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_addr`] module"]
-module"]
 #[doc(alias = "ROM_TRAP_ADDR")]
 pub type RomTrapAddr = crate::Reg<rom_trap_addr::RomTrapAddrSpec>;
 #[doc = "ROM Trap Address"]
 pub mod rom_trap_addr;
-#[doc = "ROM_TRAP_SYND (rw) register accessor: ROM Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`]
+#[doc = "ROM_TRAP_SYND (rw) register accessor: ROM Trap Syndrome\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_trap_synd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`] module"]
-module"]
 #[doc(alias = "ROM_TRAP_SYND")]
 pub type RomTrapSynd = crate::Reg<rom_trap_synd::RomTrapSyndSpec>;
 #[doc = "ROM Trap Syndrome"]
@@ -274,8 +269,7 @@ pub use rom_trap_addr as ram_trap_addr;
 pub use rom_trap_synd as ram_trap_synd;
 pub use RomTrapAddr as RamTrapAddr;
 pub use RomTrapSynd as RamTrapSynd;
-#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
-module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
 #[doc = "Enable EDAC Error Interrupt Register"]
@@ -286,8 +280,7 @@ pub use irq_enb as irq_clr;
 pub use IrqEnb as IrqRaw;
 pub use IrqEnb as IrqEnd;
 pub use IrqEnb as IrqClr;
-#[doc = "RAM_SBE (rw) register accessor: Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sbe`]
+#[doc = "RAM_SBE (rw) register accessor: Count of RAM EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_sbe`] module"]
-module"]
 #[doc(alias = "RAM_SBE")]
 pub type RamSbe = crate::Reg<ram_sbe::RamSbeSpec>;
 #[doc = "Count of RAM EDAC Single Bit Errors"]
@@ -298,80 +291,67 @@ pub use ram_sbe as rom_mbe;
 pub use RamSbe as RamMbe;
 pub use RamSbe as RomSbe;
 pub use RamSbe as RomMbe;
-#[doc = "IOCONFIG_CLKDIV0 (r) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv0`]
+#[doc = "IOCONFIG_CLKDIV0 (r) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv0`] module"]
-module"]
 #[doc(alias = "IOCONFIG_CLKDIV0")]
 pub type IoconfigClkdiv0 = crate::Reg<ioconfig_clkdiv0::IoconfigClkdiv0Spec>;
 #[doc = "IO Configuration Clock Divider Register"]
 pub mod ioconfig_clkdiv0;
-#[doc = "IOCONFIG_CLKDIV (rw) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv`]
+#[doc = "IOCONFIG_CLKDIV (rw) register accessor: IO Configuration Clock Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ioconfig_clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ioconfig_clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ioconfig_clkdiv`] module"]
-module"]
 #[doc(alias = "IOCONFIG_CLKDIV")]
 pub type IoconfigClkdiv = crate::Reg<ioconfig_clkdiv::IoconfigClkdivSpec>;
 #[doc = "IO Configuration Clock Divider Register"]
 pub mod ioconfig_clkdiv;
-#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`]
+#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`] module"]
-module"]
 #[doc(alias = "ROM_RETRIES")]
 pub type RomRetries = crate::Reg<rom_retries::RomRetriesSpec>;
 #[doc = "ROM BOOT Retry count"]
 pub mod rom_retries;
-#[doc = "REFRESH_CONFIG (rw) register accessor: Register Refresh Control\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config`]
+#[doc = "REFRESH_CONFIG (rw) register accessor: Register Refresh Control\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config`] module"]
-module"]
 #[doc(alias = "REFRESH_CONFIG")]
 pub type RefreshConfig = crate::Reg<refresh_config::RefreshConfigSpec>;
 #[doc = "Register Refresh Control"]
 pub mod refresh_config;
-#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`]
+#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`] module"]
-module"]
 #[doc(alias = "TIM_RESET")]
 pub type TimReset = crate::Reg<tim_reset::TimResetSpec>;
 #[doc = "TIM Reset Control"]
 pub mod tim_reset;
-#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`]
+#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`] module"]
-module"]
 #[doc(alias = "TIM_CLK_ENABLE")]
 pub type TimClkEnable = crate::Reg<tim_clk_enable::TimClkEnableSpec>;
 #[doc = "TIM Enable Control"]
 pub mod tim_clk_enable;
-#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`]
+#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`] module"]
-module"]
 #[doc(alias = "PERIPHERAL_RESET")]
 pub type PeripheralReset = crate::Reg<peripheral_reset::PeripheralResetSpec>;
 #[doc = "Peripheral Reset Control"]
 pub mod peripheral_reset;
-#[doc = "PERIPHERAL_CLK_ENABLE (rw) register accessor: Peripheral Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_clk_enable`]
+#[doc = "PERIPHERAL_CLK_ENABLE (rw) register accessor: Peripheral Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_clk_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_clk_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_clk_enable`] module"]
-module"]
 #[doc(alias = "PERIPHERAL_CLK_ENABLE")]
 pub type PeripheralClkEnable = crate::Reg<peripheral_clk_enable::PeripheralClkEnableSpec>;
 #[doc = "Peripheral Enable Control"]
 pub mod peripheral_clk_enable;
-#[doc = "LOCKUP_RESET (rw) register accessor: Lockup Reset Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lockup_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockup_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lockup_reset`]
+#[doc = "LOCKUP_RESET (rw) register accessor: Lockup Reset Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`lockup_reset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lockup_reset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lockup_reset`] module"]
-module"]
 #[doc(alias = "LOCKUP_RESET")]
 pub type LockupReset = crate::Reg<lockup_reset::LockupResetSpec>;
 #[doc = "Lockup Reset Configuration"]
 pub mod lockup_reset;
-#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`]
+#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`] module"]
-module"]
 #[doc(alias = "EF_CONFIG")]
 pub type EfConfig = crate::Reg<ef_config::EfConfigSpec>;
 #[doc = "EFuse Config Register"]
 pub mod ef_config;
-#[doc = "EF_ID (r) register accessor: EFuse ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id`]
+#[doc = "EF_ID (r) register accessor: EFuse ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id`] module"]
-module"]
 #[doc(alias = "EF_ID")]
 pub type EfId = crate::Reg<ef_id::EfIdSpec>;
 #[doc = "EFuse ID Register"]
 pub mod ef_id;
-#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`]
+#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`] module"]
-module"]
 #[doc(alias = "PROCID")]
 pub type Procid = crate::Reg<procid::ProcidSpec>;
 #[doc = "Processor ID Register"]
 pub mod procid;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
-module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]

va108xx/src/sysconfig/ef_config.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for EfConfigSpec {
 #[doc = "`read()` method returns [`ef_config::R`](R) reader structure"]
 impl crate::Readable for EfConfigSpec {}
 #[doc = "`reset()` method sets EF_CONFIG to value 0"]
-impl crate::Resettable for EfConfigSpec {
+impl crate::Resettable for EfConfigSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/ef_id.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for EfIdSpec {
 #[doc = "`read()` method returns [`ef_id::R`](R) reader structure"]
 impl crate::Readable for EfIdSpec {}
 #[doc = "`reset()` method sets EF_ID to value 0"]
-impl crate::Resettable for EfIdSpec {
+impl crate::Resettable for EfIdSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/ioconfig_clkdiv.rs

@@ -19,10 +19,6 @@ impl crate::Readable for IoconfigClkdivSpec {}
 #[doc = "`write(|w| ..)` method takes [`ioconfig_clkdiv::W`](W) writer structure"]
 impl crate::Writable for IoconfigClkdivSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IOCONFIG_CLKDIV%s to value 0"]
-impl crate::Resettable for IoconfigClkdivSpec {
+impl crate::Resettable for IoconfigClkdivSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/ioconfig_clkdiv0.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for IoconfigClkdiv0Spec {
 #[doc = "`read()` method returns [`ioconfig_clkdiv0::R`](R) reader structure"]
 impl crate::Readable for IoconfigClkdiv0Spec {}
 #[doc = "`reset()` method sets IOCONFIG_CLKDIV0 to value 0"]
-impl crate::Resettable for IoconfigClkdiv0Spec {
+impl crate::Resettable for IoconfigClkdiv0Spec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/irq_enb.rs

@@ -43,22 +43,22 @@ impl R {
 impl W {
     #[doc = "Bit 0 - RAM Single Bit Interrupt"]
     #[inline(always)]
-    pub fn ramsbe(&mut self) -> RamsbeW<IrqEnbSpec> {
+    pub fn ramsbe(&mut self) -> RamsbeW<'_, IrqEnbSpec> {
         RamsbeW::new(self, 0)
     }
     #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
     #[inline(always)]
-    pub fn rammbe(&mut self) -> RammbeW<IrqEnbSpec> {
+    pub fn rammbe(&mut self) -> RammbeW<'_, IrqEnbSpec> {
         RammbeW::new(self, 1)
     }
     #[doc = "Bit 2 - ROM Single Bit Interrupt"]
     #[inline(always)]
-    pub fn romsbe(&mut self) -> RomsbeW<IrqEnbSpec> {
+    pub fn romsbe(&mut self) -> RomsbeW<'_, IrqEnbSpec> {
         RomsbeW::new(self, 2)
     }
     #[doc = "Bit 3 - ROM Multi Bit Interrupt"]
     #[inline(always)]
-    pub fn rommbe(&mut self) -> RommbeW<IrqEnbSpec> {
+    pub fn rommbe(&mut self) -> RommbeW<'_, IrqEnbSpec> {
         RommbeW::new(self, 3)
     }
 }
@@ -72,10 +72,6 @@ impl crate::Readable for IrqEnbSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
 impl crate::Writable for IrqEnbSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_ENB to value 0"]
-impl crate::Resettable for IrqEnbSpec {
+impl crate::Resettable for IrqEnbSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/lockup_reset.rs

@@ -16,7 +16,7 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Lockup Reset Enable Bit"]
     #[inline(always)]
-    pub fn lren(&mut self) -> LrenW<LockupResetSpec> {
+    pub fn lren(&mut self) -> LrenW<'_, LockupResetSpec> {
         LrenW::new(self, 0)
     }
 }
@@ -30,8 +30,6 @@ impl crate::Readable for LockupResetSpec {}
 #[doc = "`write(|w| ..)` method takes [`lockup_reset::W`](W) writer structure"]
 impl crate::Writable for LockupResetSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets LOCKUP_RESET to value 0x01"]
 impl crate::Resettable for LockupResetSpec {

va108xx/src/sysconfig/peripheral_clk_enable.rs

@@ -10,47 +10,33 @@ pub type PortaW<'a, REG> = crate::BitWriter<'a, REG>;
 pub type PortbR = crate::BitReader;
 #[doc = "Field `PORTB` writer - Enable PORTB clock"]
 pub type PortbW<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `SPI_0` reader - Enable SPI\\[0\\]
+#[doc = "Field `SPI_0` reader - Enable SPI\\[0\\] clock"]
-clock"]
 pub type Spi0R = crate::BitReader;
-#[doc = "Field `SPI_0` writer - Enable SPI\\[0\\]
+#[doc = "Field `SPI_0` writer - Enable SPI\\[0\\] clock"]
-clock"]
 pub type Spi0W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `SPI_1` reader - Enable SPI\\[1\\]
+#[doc = "Field `SPI_1` reader - Enable SPI\\[1\\] clock"]
-clock"]
 pub type Spi1R = crate::BitReader;
-#[doc = "Field `SPI_1` writer - Enable SPI\\[1\\]
+#[doc = "Field `SPI_1` writer - Enable SPI\\[1\\] clock"]
-clock"]
 pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `SPI_2` reader - Enable SPI\\[2\\]
+#[doc = "Field `SPI_2` reader - Enable SPI\\[2\\] clock"]
-clock"]
 pub type Spi2R = crate::BitReader;
-#[doc = "Field `SPI_2` writer - Enable SPI\\[2\\]
+#[doc = "Field `SPI_2` writer - Enable SPI\\[2\\] clock"]
-clock"]
 pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `UART_0` reader - Enable UART\\[0\\]
+#[doc = "Field `UART_0` reader - Enable UART\\[0\\] clock"]
-clock"]
 pub type Uart0R = crate::BitReader;
-#[doc = "Field `UART_0` writer - Enable UART\\[0\\]
+#[doc = "Field `UART_0` writer - Enable UART\\[0\\] clock"]
-clock"]
 pub type Uart0W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `UART_1` reader - Enable UART\\[1\\]
+#[doc = "Field `UART_1` reader - Enable UART\\[1\\] clock"]
-clock"]
 pub type Uart1R = crate::BitReader;
-#[doc = "Field `UART_1` writer - Enable UART\\[1\\]
+#[doc = "Field `UART_1` writer - Enable UART\\[1\\] clock"]
-clock"]
 pub type Uart1W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `I2C_0` reader - Enable I2C\\[0\\]
+#[doc = "Field `I2C_0` reader - Enable I2C\\[0\\] clock"]
-clock"]
 pub type I2c0R = crate::BitReader;
-#[doc = "Field `I2C_0` writer - Enable I2C\\[0\\]
+#[doc = "Field `I2C_0` writer - Enable I2C\\[0\\] clock"]
-clock"]
 pub type I2c0W<'a, REG> = crate::BitWriter<'a, REG>;
-#[doc = "Field `I2C_1` reader - Enable I2C\\[1\\]
+#[doc = "Field `I2C_1` reader - Enable I2C\\[1\\] clock"]
-clock"]
 pub type I2c1R = crate::BitReader;
-#[doc = "Field `I2C_1` writer - Enable I2C\\[1\\]
+#[doc = "Field `I2C_1` writer - Enable I2C\\[1\\] clock"]
-clock"]
 pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>;
 #[doc = "Field `IRQSEL` reader - Enable IRQ selector clock"]
 pub type IrqselR = crate::BitReader;
@@ -79,44 +65,37 @@ impl R {
     pub fn portb(&self) -> PortbR {
         PortbR::new(((self.bits >> 1) & 1) != 0)
     }
-    #[doc = "Bit 4 - Enable SPI\\[0\\]
+    #[doc = "Bit 4 - Enable SPI\\[0\\] clock"]
-clock"]
     #[inline(always)]
     pub fn spi_0(&self) -> Spi0R {
         Spi0R::new(((self.bits >> 4) & 1) != 0)
     }
-    #[doc = "Bit 5 - Enable SPI\\[1\\]
+    #[doc = "Bit 5 - Enable SPI\\[1\\] clock"]
-clock"]
     #[inline(always)]
     pub fn spi_1(&self) -> Spi1R {
         Spi1R::new(((self.bits >> 5) & 1) != 0)
     }
-    #[doc = "Bit 6 - Enable SPI\\[2\\]
+    #[doc = "Bit 6 - Enable SPI\\[2\\] clock"]
-clock"]
     #[inline(always)]
     pub fn spi_2(&self) -> Spi2R {
         Spi2R::new(((self.bits >> 6) & 1) != 0)
     }
-    #[doc = "Bit 8 - Enable UART\\[0\\]
+    #[doc = "Bit 8 - Enable UART\\[0\\] clock"]
-clock"]
     #[inline(always)]
     pub fn uart_0(&self) -> Uart0R {
         Uart0R::new(((self.bits >> 8) & 1) != 0)
     }
-    #[doc = "Bit 9 - Enable UART\\[1\\]
+    #[doc = "Bit 9 - Enable UART\\[1\\] clock"]
-clock"]
     #[inline(always)]
     pub fn uart_1(&self) -> Uart1R {
         Uart1R::new(((self.bits >> 9) & 1) != 0)
     }
-    #[doc = "Bit 16 - Enable I2C\\[0\\]
+    #[doc = "Bit 16 - Enable I2C\\[0\\] clock"]
-clock"]
     #[inline(always)]
     pub fn i2c_0(&self) -> I2c0R {
         I2c0R::new(((self.bits >> 16) & 1) != 0)
     }
-    #[doc = "Bit 17 - Enable I2C\\[1\\]
+    #[doc = "Bit 17 - Enable I2C\\[1\\] clock"]
-clock"]
     #[inline(always)]
     pub fn i2c_1(&self) -> I2c1R {
         I2c1R::new(((self.bits >> 17) & 1) != 0)
@@ -145,74 +124,67 @@ clock"]
 impl W {
     #[doc = "Bit 0 - Enable PORTA clock"]
     #[inline(always)]
-    pub fn porta(&mut self) -> PortaW<PeripheralClkEnableSpec> {
+    pub fn porta(&mut self) -> PortaW<'_, PeripheralClkEnableSpec> {
         PortaW::new(self, 0)
     }
     #[doc = "Bit 1 - Enable PORTB clock"]
     #[inline(always)]
-    pub fn portb(&mut self) -> PortbW<PeripheralClkEnableSpec> {
+    pub fn portb(&mut self) -> PortbW<'_, PeripheralClkEnableSpec> {
         PortbW::new(self, 1)
     }
-    #[doc = "Bit 4 - Enable SPI\\[0\\]
+    #[doc = "Bit 4 - Enable SPI\\[0\\] clock"]
-clock"]
     #[inline(always)]
-    pub fn spi_0(&mut self) -> Spi0W<PeripheralClkEnableSpec> {
+    pub fn spi_0(&mut self) -> Spi0W<'_, PeripheralClkEnableSpec> {
         Spi0W::new(self, 4)
     }
-    #[doc = "Bit 5 - Enable SPI\\[1\\]
+    #[doc = "Bit 5 - Enable SPI\\[1\\] clock"]
-clock"]
     #[inline(always)]
-    pub fn spi_1(&mut self) -> Spi1W<PeripheralClkEnableSpec> {
+    pub fn spi_1(&mut self) -> Spi1W<'_, PeripheralClkEnableSpec> {
         Spi1W::new(self, 5)
     }
-    #[doc = "Bit 6 - Enable SPI\\[2\\]
+    #[doc = "Bit 6 - Enable SPI\\[2\\] clock"]
-clock"]
     #[inline(always)]
-    pub fn spi_2(&mut self) -> Spi2W<PeripheralClkEnableSpec> {
+    pub fn spi_2(&mut self) -> Spi2W<'_, PeripheralClkEnableSpec> {
         Spi2W::new(self, 6)
     }
-    #[doc = "Bit 8 - Enable UART\\[0\\]
+    #[doc = "Bit 8 - Enable UART\\[0\\] clock"]
-clock"]
     #[inline(always)]
-    pub fn uart_0(&mut self) -> Uart0W<PeripheralClkEnableSpec> {
+    pub fn uart_0(&mut self) -> Uart0W<'_, PeripheralClkEnableSpec> {
         Uart0W::new(self, 8)
     }
-    #[doc = "Bit 9 - Enable UART\\[1\\]
+    #[doc = "Bit 9 - Enable UART\\[1\\] clock"]
-clock"]
     #[inline(always)]
-    pub fn uart_1(&mut self) -> Uart1W<PeripheralClkEnableSpec> {
+    pub fn uart_1(&mut self) -> Uart1W<'_, PeripheralClkEnableSpec> {
         Uart1W::new(self, 9)
     }
-    #[doc = "Bit 16 - Enable I2C\\[0\\]
+    #[doc = "Bit 16 - Enable I2C\\[0\\] clock"]
-clock"]
     #[inline(always)]
-    pub fn i2c_0(&mut self) -> I2c0W<PeripheralClkEnableSpec> {
+    pub fn i2c_0(&mut self) -> I2c0W<'_, PeripheralClkEnableSpec> {
         I2c0W::new(self, 16)
     }
-    #[doc = "Bit 17 - Enable I2C\\[1\\]
+    #[doc = "Bit 17 - Enable I2C\\[1\\] clock"]
-clock"]
     #[inline(always)]
-    pub fn i2c_1(&mut self) -> I2c1W<PeripheralClkEnableSpec> {
+    pub fn i2c_1(&mut self) -> I2c1W<'_, PeripheralClkEnableSpec> {
         I2c1W::new(self, 17)
     }
     #[doc = "Bit 21 - Enable IRQ selector clock"]
     #[inline(always)]
-    pub fn irqsel(&mut self) -> IrqselW<PeripheralClkEnableSpec> {
+    pub fn irqsel(&mut self) -> IrqselW<'_, PeripheralClkEnableSpec> {
         IrqselW::new(self, 21)
     }
     #[doc = "Bit 22 - Enable IO Configuration block clock"]
     #[inline(always)]
-    pub fn ioconfig(&mut self) -> IoconfigW<PeripheralClkEnableSpec> {
+    pub fn ioconfig(&mut self) -> IoconfigW<'_, PeripheralClkEnableSpec> {
         IoconfigW::new(self, 22)
     }
     #[doc = "Bit 23 - Enable utility clock"]
     #[inline(always)]
-    pub fn utility(&mut self) -> UtilityW<PeripheralClkEnableSpec> {
+    pub fn utility(&mut self) -> UtilityW<'_, PeripheralClkEnableSpec> {
         UtilityW::new(self, 23)
     }
     #[doc = "Bit 24 - Enable GPIO clock"]
     #[inline(always)]
-    pub fn gpio(&mut self) -> GpioW<PeripheralClkEnableSpec> {
+    pub fn gpio(&mut self) -> GpioW<'_, PeripheralClkEnableSpec> {
         GpioW::new(self, 24)
     }
 }
@@ -226,10 +198,6 @@ impl crate::Readable for PeripheralClkEnableSpec {}
 #[doc = "`write(|w| ..)` method takes [`peripheral_clk_enable::W`](W) writer structure"]
 impl crate::Writable for PeripheralClkEnableSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets PERIPHERAL_CLK_ENABLE to value 0"]
-impl crate::Resettable for PeripheralClkEnableSpec {
+impl crate::Resettable for PeripheralClkEnableSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/peripheral_reset.rs

@@ -124,67 +124,67 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Reset PORTA"]
     #[inline(always)]
-    pub fn porta(&mut self) -> PortaW<PeripheralResetSpec> {
+    pub fn porta(&mut self) -> PortaW<'_, PeripheralResetSpec> {
         PortaW::new(self, 0)
     }
     #[doc = "Bit 1 - Reset PORTB"]
     #[inline(always)]
-    pub fn portb(&mut self) -> PortbW<PeripheralResetSpec> {
+    pub fn portb(&mut self) -> PortbW<'_, PeripheralResetSpec> {
         PortbW::new(self, 1)
     }
     #[doc = "Bit 4 - Reset SPI\\[0\\]"]
     #[inline(always)]
-    pub fn spi_0(&mut self) -> Spi0W<PeripheralResetSpec> {
+    pub fn spi_0(&mut self) -> Spi0W<'_, PeripheralResetSpec> {
         Spi0W::new(self, 4)
     }
     #[doc = "Bit 5 - Reset SPI\\[1\\]"]
     #[inline(always)]
-    pub fn spi_1(&mut self) -> Spi1W<PeripheralResetSpec> {
+    pub fn spi_1(&mut self) -> Spi1W<'_, PeripheralResetSpec> {
         Spi1W::new(self, 5)
     }
     #[doc = "Bit 6 - Reset SPI\\[2\\]"]
     #[inline(always)]
-    pub fn spi_2(&mut self) -> Spi2W<PeripheralResetSpec> {
+    pub fn spi_2(&mut self) -> Spi2W<'_, PeripheralResetSpec> {
         Spi2W::new(self, 6)
     }
     #[doc = "Bit 8 - Reset UART\\[0\\]"]
     #[inline(always)]
-    pub fn uart_0(&mut self) -> Uart0W<PeripheralResetSpec> {
+    pub fn uart_0(&mut self) -> Uart0W<'_, PeripheralResetSpec> {
         Uart0W::new(self, 8)
     }
     #[doc = "Bit 9 - Reset UART\\[1\\]"]
     #[inline(always)]
-    pub fn uart_1(&mut self) -> Uart1W<PeripheralResetSpec> {
+    pub fn uart_1(&mut self) -> Uart1W<'_, PeripheralResetSpec> {
         Uart1W::new(self, 9)
     }
     #[doc = "Bit 16 - Reset I2C\\[0\\]"]
     #[inline(always)]
-    pub fn i2c_0(&mut self) -> I2c0W<PeripheralResetSpec> {
+    pub fn i2c_0(&mut self) -> I2c0W<'_, PeripheralResetSpec> {
         I2c0W::new(self, 16)
     }
     #[doc = "Bit 17 - Reset I2C\\[1\\]"]
     #[inline(always)]
-    pub fn i2c_1(&mut self) -> I2c1W<PeripheralResetSpec> {
+    pub fn i2c_1(&mut self) -> I2c1W<'_, PeripheralResetSpec> {
         I2c1W::new(self, 17)
     }
     #[doc = "Bit 21 - Reset IRQ selector"]
     #[inline(always)]
-    pub fn irqsel(&mut self) -> IrqselW<PeripheralResetSpec> {
+    pub fn irqsel(&mut self) -> IrqselW<'_, PeripheralResetSpec> {
         IrqselW::new(self, 21)
     }
     #[doc = "Bit 22 - Reset IO Configuration block"]
     #[inline(always)]
-    pub fn ioconfig(&mut self) -> IoconfigW<PeripheralResetSpec> {
+    pub fn ioconfig(&mut self) -> IoconfigW<'_, PeripheralResetSpec> {
         IoconfigW::new(self, 22)
     }
     #[doc = "Bit 23 - Reset Utility Block"]
     #[inline(always)]
-    pub fn utility(&mut self) -> UtilityW<PeripheralResetSpec> {
+    pub fn utility(&mut self) -> UtilityW<'_, PeripheralResetSpec> {
         UtilityW::new(self, 23)
     }
     #[doc = "Bit 24 - Reset GPIO"]
     #[inline(always)]
-    pub fn gpio(&mut self) -> GpioW<PeripheralResetSpec> {
+    pub fn gpio(&mut self) -> GpioW<'_, PeripheralResetSpec> {
         GpioW::new(self, 24)
     }
 }
@@ -198,8 +198,6 @@ impl crate::Readable for PeripheralResetSpec {}
 #[doc = "`write(|w| ..)` method takes [`peripheral_reset::W`](W) writer structure"]
 impl crate::Writable for PeripheralResetSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets PERIPHERAL_RESET to value 0xffff_ffff"]
 impl crate::Resettable for PeripheralResetSpec {

va108xx/src/sysconfig/ram_sbe.rs

@@ -19,10 +19,6 @@ impl crate::Readable for RamSbeSpec {}
 #[doc = "`write(|w| ..)` method takes [`ram_sbe::W`](W) writer structure"]
 impl crate::Writable for RamSbeSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets RAM_SBE to value 0"]
-impl crate::Resettable for RamSbeSpec {
+impl crate::Resettable for RamSbeSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/refresh_config.rs

@@ -19,10 +19,6 @@ impl crate::Readable for RefreshConfigSpec {}
 #[doc = "`write(|w| ..)` method takes [`refresh_config::W`](W) writer structure"]
 impl crate::Writable for RefreshConfigSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets REFRESH_CONFIG to value 0"]
-impl crate::Resettable for RefreshConfigSpec {
+impl crate::Resettable for RefreshConfigSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/rom_prot.rs

@@ -16,7 +16,7 @@ impl R {
 impl W {
     #[doc = "Bit 0 - ROM Write Enable Bit"]
     #[inline(always)]
-    pub fn wren(&mut self) -> WrenW<RomProtSpec> {
+    pub fn wren(&mut self) -> WrenW<'_, RomProtSpec> {
         WrenW::new(self, 0)
     }
 }
@@ -30,8 +30,6 @@ impl crate::Readable for RomProtSpec {}
 #[doc = "`write(|w| ..)` method takes [`rom_prot::W`](W) writer structure"]
 impl crate::Writable for RomProtSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets ROM_PROT to value 0x01"]
 impl crate::Resettable for RomProtSpec {

va108xx/src/sysconfig/rom_retries.rs

@@ -14,6 +14,4 @@ impl crate::RegisterSpec for RomRetriesSpec {
 #[doc = "`read()` method returns [`rom_retries::R`](R) reader structure"]
 impl crate::Readable for RomRetriesSpec {}
 #[doc = "`reset()` method sets ROM_RETRIES to value 0"]
-impl crate::Resettable for RomRetriesSpec {
+impl crate::Resettable for RomRetriesSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/rom_scrub.rs

@@ -18,12 +18,12 @@ impl R {
 impl W {
     #[doc = "Bits 0:23 - Counter divide value"]
     #[inline(always)]
-    pub fn value(&mut self) -> ValueW<RomScrubSpec> {
+    pub fn value(&mut self) -> ValueW<'_, RomScrubSpec> {
         ValueW::new(self, 0)
     }
     #[doc = "Bit 31 - Reset Counter"]
     #[inline(always)]
-    pub fn reset(&mut self) -> ResetW<RomScrubSpec> {
+    pub fn reset(&mut self) -> ResetW<'_, RomScrubSpec> {
         ResetW::new(self, 31)
     }
 }
@@ -37,10 +37,7 @@ impl crate::Readable for RomScrubSpec {}
 #[doc = "`write(|w| ..)` method takes [`rom_scrub::W`](W) writer structure"]
 impl crate::Writable for RomScrubSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0000;
 }
 #[doc = "`reset()` method sets ROM_SCRUB to value 0"]
-impl crate::Resettable for RomScrubSpec {
+impl crate::Resettable for RomScrubSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/rom_trap_addr.rs

@@ -25,12 +25,12 @@ impl R {
 impl W {
     #[doc = "Bits 2:15 - Trap Address Match Bits"]
     #[inline(always)]
-    pub fn addr(&mut self) -> AddrW<RomTrapAddrSpec> {
+    pub fn addr(&mut self) -> AddrW<'_, RomTrapAddrSpec> {
         AddrW::new(self, 2)
     }
     #[doc = "Bit 31 - Trap Enable Bit"]
     #[inline(always)]
-    pub fn enable(&mut self) -> EnableW<RomTrapAddrSpec> {
+    pub fn enable(&mut self) -> EnableW<'_, RomTrapAddrSpec> {
         EnableW::new(self, 31)
     }
 }
@@ -44,10 +44,6 @@ impl crate::Readable for RomTrapAddrSpec {}
 #[doc = "`write(|w| ..)` method takes [`rom_trap_addr::W`](W) writer structure"]
 impl crate::Writable for RomTrapAddrSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets ROM_TRAP_ADDR to value 0"]
-impl crate::Resettable for RomTrapAddrSpec {
+impl crate::Resettable for RomTrapAddrSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/rom_trap_synd.rs

@@ -16,7 +16,7 @@ impl R {
 impl W {
     #[doc = "Bits 0:19 - Trap Syndrom Bits"]
     #[inline(always)]
-    pub fn synd(&mut self) -> SyndW<RomTrapSyndSpec> {
+    pub fn synd(&mut self) -> SyndW<'_, RomTrapSyndSpec> {
         SyndW::new(self, 0)
     }
 }
@@ -30,10 +30,6 @@ impl crate::Readable for RomTrapSyndSpec {}
 #[doc = "`write(|w| ..)` method takes [`rom_trap_synd::W`](W) writer structure"]
 impl crate::Writable for RomTrapSyndSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets ROM_TRAP_SYND to value 0"]
-impl crate::Resettable for RomTrapSyndSpec {
+impl crate::Resettable for RomTrapSyndSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/rst_stat.rs

@@ -61,32 +61,32 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Power On Reset Status"]
     #[inline(always)]
-    pub fn por(&mut self) -> PorW<RstStatSpec> {
+    pub fn por(&mut self) -> PorW<'_, RstStatSpec> {
         PorW::new(self, 0)
     }
     #[doc = "Bit 1 - External Reset Status"]
     #[inline(always)]
-    pub fn extrst(&mut self) -> ExtrstW<RstStatSpec> {
+    pub fn extrst(&mut self) -> ExtrstW<'_, RstStatSpec> {
         ExtrstW::new(self, 1)
     }
     #[doc = "Bit 2 - SYSRESETREQ Reset Status"]
     #[inline(always)]
-    pub fn sysrstreq(&mut self) -> SysrstreqW<RstStatSpec> {
+    pub fn sysrstreq(&mut self) -> SysrstreqW<'_, RstStatSpec> {
         SysrstreqW::new(self, 2)
     }
     #[doc = "Bit 3 - LOOKUP Reset Status"]
     #[inline(always)]
-    pub fn lookup(&mut self) -> LookupW<RstStatSpec> {
+    pub fn lookup(&mut self) -> LookupW<'_, RstStatSpec> {
         LookupW::new(self, 3)
     }
     #[doc = "Bit 4 - WATCHDOG Reset Status"]
     #[inline(always)]
-    pub fn watchdog(&mut self) -> WatchdogW<RstStatSpec> {
+    pub fn watchdog(&mut self) -> WatchdogW<'_, RstStatSpec> {
         WatchdogW::new(self, 4)
     }
     #[doc = "Bit 5 - Memory Error Reset Status"]
     #[inline(always)]
-    pub fn memerr(&mut self) -> MemerrW<RstStatSpec> {
+    pub fn memerr(&mut self) -> MemerrW<'_, RstStatSpec> {
         MemerrW::new(self, 5)
     }
 }
@@ -100,8 +100,6 @@ impl crate::Readable for RstStatSpec {}
 #[doc = "`write(|w| ..)` method takes [`rst_stat::W`](W) writer structure"]
 impl crate::Writable for RstStatSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets RST_STAT to value 0x01"]
 impl crate::Resettable for RstStatSpec {

va108xx/src/sysconfig/tim_clk_enable.rs

@@ -19,10 +19,6 @@ impl crate::Readable for TimClkEnableSpec {}
 #[doc = "`write(|w| ..)` method takes [`tim_clk_enable::W`](W) writer structure"]
 impl crate::Writable for TimClkEnableSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets TIM_CLK_ENABLE to value 0"]
-impl crate::Resettable for TimClkEnableSpec {
+impl crate::Resettable for TimClkEnableSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/sysconfig/tim_reset.rs

@@ -19,8 +19,6 @@ impl crate::Readable for TimResetSpec {}
 #[doc = "`write(|w| ..)` method takes [`tim_reset::W`](W) writer structure"]
 impl crate::Writable for TimResetSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets TIM_RESET to value 0xffff_ffff"]
 impl crate::Resettable for TimResetSpec {

va108xx/src/tim0.rs

@@ -76,38 +76,32 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
-module"]
 #[doc(alias = "CTRL")]
 pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
 #[doc = "Control Register"]
 pub mod ctrl;
-#[doc = "RST_VALUE (rw) register accessor: The value that counter start from after reaching 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_value`]
+#[doc = "RST_VALUE (rw) register accessor: The value that counter start from after reaching 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_value`] module"]
-module"]
 #[doc(alias = "RST_VALUE")]
 pub type RstValue = crate::Reg<rst_value::RstValueSpec>;
 #[doc = "The value that counter start from after reaching 0."]
 pub mod rst_value;
-#[doc = "CNT_VALUE (rw) register accessor: The current value of the counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt_value`]
+#[doc = "CNT_VALUE (rw) register accessor: The current value of the counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt_value`] module"]
-module"]
 #[doc(alias = "CNT_VALUE")]
 pub type CntValue = crate::Reg<cnt_value::CntValueSpec>;
 #[doc = "The current value of the counter"]
 pub mod cnt_value;
-#[doc = "ENABLE (rw) register accessor: Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`]
+#[doc = "ENABLE (rw) register accessor: Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"]
-module"]
 #[doc(alias = "ENABLE")]
 pub type Enable = crate::Reg<enable::EnableSpec>;
 #[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register"]
 pub mod enable;
-#[doc = "CSD_CTRL (rw) register accessor: The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::Reg::read) this register and get [`csd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csd_ctrl`]
+#[doc = "CSD_CTRL (rw) register accessor: The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::Reg::read) this register and get [`csd_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csd_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csd_ctrl`] module"]
-module"]
 #[doc(alias = "CSD_CTRL")]
 pub type CsdCtrl = crate::Reg<csd_ctrl::CsdCtrlSpec>;
 #[doc = "The Cascade Control Register. Controls the counter external enable signals"]
 pub mod csd_ctrl;
-#[doc = "CASCADE0 (rw) register accessor: Cascade Enable Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`cascade0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cascade0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cascade0`]
+#[doc = "CASCADE0 (rw) register accessor: Cascade Enable Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`cascade0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cascade0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cascade0`] module"]
-module"]
 #[doc(alias = "CASCADE0")]
 pub type Cascade0 = crate::Reg<cascade0::Cascade0Spec>;
 #[doc = "Cascade Enable Selection"]
@@ -116,26 +110,22 @@ pub use cascade0 as cascade1;
 pub use cascade0 as cascade2;
 pub use Cascade0 as Cascade1;
 pub use Cascade0 as Cascade2;
-#[doc = "PWM_VALUE (rw) register accessor: The Pulse Width Modulation Value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_value`]
+#[doc = "PWM_VALUE (rw) register accessor: The Pulse Width Modulation Value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_value`] module"]
-module"]
 #[doc(alias = "PWM_VALUE")]
 pub type PwmValue = crate::Reg<pwm_value::PwmValueSpec>;
 #[doc = "The Pulse Width Modulation Value"]
 pub mod pwm_value;
-#[doc = "PWMA_VALUE (rw) register accessor: The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::Reg::read) this register and get [`pwma_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwma_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwma_value`]
+#[doc = "PWMA_VALUE (rw) register accessor: The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::Reg::read) this register and get [`pwma_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwma_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwma_value`] module"]
-module"]
 #[doc(alias = "PWMA_VALUE")]
 pub type PwmaValue = crate::Reg<pwma_value::PwmaValueSpec>;
 #[doc = "The Pulse Width Modulation ValueA"]
 pub mod pwma_value;
-#[doc = "PWMB_VALUE (rw) register accessor: The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmb_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmb_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmb_value`]
+#[doc = "PWMB_VALUE (rw) register accessor: The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmb_value::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmb_value::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmb_value`] module"]
-module"]
 #[doc(alias = "PWMB_VALUE")]
 pub type PwmbValue = crate::Reg<pwmb_value::PwmbValueSpec>;
 #[doc = "The Pulse Width Modulation ValueB"]
 pub mod pwmb_value;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
-module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]

va108xx/src/tim0/cascade0.rs

@@ -16,7 +16,7 @@ impl R {
 impl W {
     #[doc = "Bits 0:7 - Cascade Selection"]
     #[inline(always)]
-    pub fn cassel(&mut self) -> CasselW<Cascade0Spec> {
+    pub fn cassel(&mut self) -> CasselW<'_, Cascade0Spec> {
         CasselW::new(self, 0)
     }
 }
@@ -30,10 +30,6 @@ impl crate::Readable for Cascade0Spec {}
 #[doc = "`write(|w| ..)` method takes [`cascade0::W`](W) writer structure"]
 impl crate::Writable for Cascade0Spec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CASCADE0 to value 0"]
-impl crate::Resettable for Cascade0Spec {
+impl crate::Resettable for Cascade0Spec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/tim0/cnt_value.rs

@@ -19,10 +19,6 @@ impl crate::Readable for CntValueSpec {}
 #[doc = "`write(|w| ..)` method takes [`cnt_value::W`](W) writer structure"]
 impl crate::Writable for CntValueSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CNT_VALUE to value 0"]
-impl crate::Resettable for CntValueSpec {
+impl crate::Resettable for CntValueSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/tim0/csd_ctrl.rs

@@ -106,57 +106,57 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Cascade 0 Enable"]
     #[inline(always)]
-    pub fn csden0(&mut self) -> Csden0W<CsdCtrlSpec> {
+    pub fn csden0(&mut self) -> Csden0W<'_, CsdCtrlSpec> {
         Csden0W::new(self, 0)
     }
     #[doc = "Bit 1 - Cascade 0 Invert"]
     #[inline(always)]
-    pub fn csdinv0(&mut self) -> Csdinv0W<CsdCtrlSpec> {
+    pub fn csdinv0(&mut self) -> Csdinv0W<'_, CsdCtrlSpec> {
         Csdinv0W::new(self, 1)
     }
     #[doc = "Bit 2 - Cascade 1 Enable"]
     #[inline(always)]
-    pub fn csden1(&mut self) -> Csden1W<CsdCtrlSpec> {
+    pub fn csden1(&mut self) -> Csden1W<'_, CsdCtrlSpec> {
         Csden1W::new(self, 2)
     }
     #[doc = "Bit 3 - Cascade 1 Invert"]
     #[inline(always)]
-    pub fn csdinv1(&mut self) -> Csdinv1W<CsdCtrlSpec> {
+    pub fn csdinv1(&mut self) -> Csdinv1W<'_, CsdCtrlSpec> {
         Csdinv1W::new(self, 3)
     }
     #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"]
     #[inline(always)]
-    pub fn dcasop(&mut self) -> DcasopW<CsdCtrlSpec> {
+    pub fn dcasop(&mut self) -> DcasopW<'_, CsdCtrlSpec> {
         DcasopW::new(self, 4)
     }
     #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"]
     #[inline(always)]
-    pub fn csdtrg0(&mut self) -> Csdtrg0W<CsdCtrlSpec> {
+    pub fn csdtrg0(&mut self) -> Csdtrg0W<'_, CsdCtrlSpec> {
         Csdtrg0W::new(self, 6)
     }
     #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"]
     #[inline(always)]
-    pub fn csdtrg1(&mut self) -> Csdtrg1W<CsdCtrlSpec> {
+    pub fn csdtrg1(&mut self) -> Csdtrg1W<'_, CsdCtrlSpec> {
         Csdtrg1W::new(self, 7)
     }
     #[doc = "Bit 8 - Cascade 2 Enable"]
     #[inline(always)]
-    pub fn csden2(&mut self) -> Csden2W<CsdCtrlSpec> {
+    pub fn csden2(&mut self) -> Csden2W<'_, CsdCtrlSpec> {
         Csden2W::new(self, 8)
     }
     #[doc = "Bit 9 - Cascade 2 Invert"]
     #[inline(always)]
-    pub fn csdinv2(&mut self) -> Csdinv2W<CsdCtrlSpec> {
+    pub fn csdinv2(&mut self) -> Csdinv2W<'_, CsdCtrlSpec> {
         Csdinv2W::new(self, 9)
     }
     #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
     #[inline(always)]
-    pub fn csdtrg2(&mut self) -> Csdtrg2W<CsdCtrlSpec> {
+    pub fn csdtrg2(&mut self) -> Csdtrg2W<'_, CsdCtrlSpec> {
         Csdtrg2W::new(self, 10)
     }
     #[doc = "Bit 11 - Cascade 2 test mode"]
     #[inline(always)]
-    pub fn csdxxx2(&mut self) -> Csdxxx2W<CsdCtrlSpec> {
+    pub fn csdxxx2(&mut self) -> Csdxxx2W<'_, CsdCtrlSpec> {
         Csdxxx2W::new(self, 11)
     }
 }
@@ -170,10 +170,6 @@ impl crate::Readable for CsdCtrlSpec {}
 #[doc = "`write(|w| ..)` method takes [`csd_ctrl::W`](W) writer structure"]
 impl crate::Writable for CsdCtrlSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CSD_CTRL to value 0"]
-impl crate::Resettable for CsdCtrlSpec {
+impl crate::Resettable for CsdCtrlSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/tim0/ctrl.rs

@@ -199,37 +199,37 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Counter Enable"]
     #[inline(always)]
-    pub fn enable(&mut self) -> EnableW<CtrlSpec> {
+    pub fn enable(&mut self) -> EnableW<'_, CtrlSpec> {
         EnableW::new(self, 0)
     }
     #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
     #[inline(always)]
-    pub fn auto_disable(&mut self) -> AutoDisableW<CtrlSpec> {
+    pub fn auto_disable(&mut self) -> AutoDisableW<'_, CtrlSpec> {
         AutoDisableW::new(self, 2)
     }
     #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
     #[inline(always)]
-    pub fn auto_deactivate(&mut self) -> AutoDeactivateW<CtrlSpec> {
+    pub fn auto_deactivate(&mut self) -> AutoDeactivateW<'_, CtrlSpec> {
         AutoDeactivateW::new(self, 3)
     }
     #[doc = "Bit 4 - Interrupt Enable"]
     #[inline(always)]
-    pub fn irq_enb(&mut self) -> IrqEnbW<CtrlSpec> {
+    pub fn irq_enb(&mut self) -> IrqEnbW<'_, CtrlSpec> {
         IrqEnbW::new(self, 4)
     }
     #[doc = "Bits 5:7 - Counter Status Selection"]
     #[inline(always)]
-    pub fn status_sel(&mut self) -> StatusSelW<CtrlSpec> {
+    pub fn status_sel(&mut self) -> StatusSelW<'_, CtrlSpec> {
         StatusSelW::new(self, 5)
     }
     #[doc = "Bit 8 - Invert the Output Status"]
     #[inline(always)]
-    pub fn status_inv(&mut self) -> StatusInvW<CtrlSpec> {
+    pub fn status_inv(&mut self) -> StatusInvW<'_, CtrlSpec> {
         StatusInvW::new(self, 8)
     }
     #[doc = "Bit 9 - Stop Request"]
     #[inline(always)]
-    pub fn req_stop(&mut self) -> ReqStopW<CtrlSpec> {
+    pub fn req_stop(&mut self) -> ReqStopW<'_, CtrlSpec> {
         ReqStopW::new(self, 9)
     }
 }
@@ -243,10 +243,6 @@ impl crate::Readable for CtrlSpec {}
 #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
 impl crate::Writable for CtrlSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CTRL to value 0"]
-impl crate::Resettable for CtrlSpec {
+impl crate::Resettable for CtrlSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/tim0/enable.rs

@@ -16,7 +16,7 @@ impl R {
 impl W {
     #[doc = "Bit 0 - Counter Enable"]
     #[inline(always)]
-    pub fn enable(&mut self) -> EnableW<EnableSpec> {
+    pub fn enable(&mut self) -> EnableW<'_, EnableSpec> {
         EnableW::new(self, 0)
     }
 }
@@ -30,10 +30,6 @@ impl crate::Readable for EnableSpec {}
 #[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"]
 impl crate::Writable for EnableSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets ENABLE to value 0"]
-impl crate::Resettable for EnableSpec {
+impl crate::Resettable for EnableSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/tim0/pwm_value.rs

@@ -19,10 +19,6 @@ impl crate::Readable for PwmValueSpec {}
 #[doc = "`write(|w| ..)` method takes [`pwm_value::W`](W) writer structure"]
 impl crate::Writable for PwmValueSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets PWM_VALUE to value 0"]
-impl crate::Resettable for PwmValueSpec {
+impl crate::Resettable for PwmValueSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/tim0/pwma_value.rs

@@ -19,10 +19,6 @@ impl crate::Readable for PwmaValueSpec {}
 #[doc = "`write(|w| ..)` method takes [`pwma_value::W`](W) writer structure"]
 impl crate::Writable for PwmaValueSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets PWMA_VALUE to value 0"]
-impl crate::Resettable for PwmaValueSpec {
+impl crate::Resettable for PwmaValueSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/tim0/pwmb_value.rs

@@ -19,10 +19,6 @@ impl crate::Readable for PwmbValueSpec {}
 #[doc = "`write(|w| ..)` method takes [`pwmb_value::W`](W) writer structure"]
 impl crate::Writable for PwmbValueSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets PWMB_VALUE to value 0"]
-impl crate::Resettable for PwmbValueSpec {
+impl crate::Resettable for PwmbValueSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/tim0/rst_value.rs

@@ -19,10 +19,6 @@ impl crate::Readable for RstValueSpec {}
 #[doc = "`write(|w| ..)` method takes [`rst_value::W`](W) writer structure"]
 impl crate::Writable for RstValueSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets RST_VALUE to value 0"]
-impl crate::Resettable for RstValueSpec {
+impl crate::Resettable for RstValueSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/uarta.rs

@@ -119,68 +119,57 @@ impl RegisterBlock {
         &self.perid
     }
 }
-#[doc = "DATA (rw) register accessor: Data In/Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
+#[doc = "DATA (rw) register accessor: Data In/Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
-module"]
 #[doc(alias = "DATA")]
 pub type Data = crate::Reg<data::DataSpec>;
 #[doc = "Data In/Out Register"]
 pub mod data;
-#[doc = "ENABLE (rw) register accessor: Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`]
+#[doc = "ENABLE (rw) register accessor: Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] module"]
-module"]
 #[doc(alias = "ENABLE")]
 pub type Enable = crate::Reg<enable::EnableSpec>;
 #[doc = "Enable Register"]
 pub mod enable;
-#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
-module"]
 #[doc(alias = "CTRL")]
 pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
 #[doc = "Control Register"]
 pub mod ctrl;
-#[doc = "CLKSCALE (rw) register accessor: Clock Scale Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
+#[doc = "CLKSCALE (rw) register accessor: Clock Scale Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] module"]
-module"]
 #[doc(alias = "CLKSCALE")]
 pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
 #[doc = "Clock Scale Register"]
 pub mod clkscale;
-#[doc = "RXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxstatus`]
+#[doc = "RXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxstatus`] module"]
-module"]
 #[doc(alias = "RXSTATUS")]
 pub type Rxstatus = crate::Reg<rxstatus::RxstatusSpec>;
 #[doc = "Status Register"]
 pub mod rxstatus;
-#[doc = "TXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txstatus`]
+#[doc = "TXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txstatus`] module"]
-module"]
 #[doc(alias = "TXSTATUS")]
 pub type Txstatus = crate::Reg<txstatus::TxstatusSpec>;
 #[doc = "Status Register"]
 pub mod txstatus;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"]
-module"]
 #[doc(alias = "FIFO_CLR")]
 pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
 #[doc = "Clear FIFO Register"]
 pub mod fifo_clr;
-#[doc = "TXBREAK (w) register accessor: Break Transmit Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbreak::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbreak`]
+#[doc = "TXBREAK (w) register accessor: Break Transmit Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbreak::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbreak`] module"]
-module"]
 #[doc(alias = "TXBREAK")]
 pub type Txbreak = crate::Reg<txbreak::TxbreakSpec>;
 #[doc = "Break Transmit Register"]
 pub mod txbreak;
-#[doc = "ADDR9 (rw) register accessor: Address9 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9`]
+#[doc = "ADDR9 (rw) register accessor: Address9 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9`] module"]
-module"]
 #[doc(alias = "ADDR9")]
 pub type Addr9 = crate::Reg<addr9::Addr9Spec>;
 #[doc = "Address9 Register"]
 pub mod addr9;
-#[doc = "ADDR9MASK (rw) register accessor: Address9 Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9mask`]
+#[doc = "ADDR9MASK (rw) register accessor: Address9 Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9mask`] module"]
-module"]
 #[doc(alias = "ADDR9MASK")]
 pub type Addr9mask = crate::Reg<addr9mask::Addr9maskSpec>;
 #[doc = "Address9 Mask Register"]
 pub mod addr9mask;
-#[doc = "IRQ_ENB (rw) register accessor: IRQ Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
+#[doc = "IRQ_ENB (rw) register accessor: IRQ Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
-module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
 #[doc = "IRQ Enable Register"]
@@ -191,32 +180,27 @@ pub use irq_enb as irq_clr;
 pub use IrqEnb as IrqRaw;
 pub use IrqEnb as IrqEnd;
 pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"]
-module"]
 #[doc(alias = "RXFIFOIRQTRG")]
 pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
 #[doc = "Rx FIFO IRQ Trigger Level"]
 pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"]
-module"]
 #[doc(alias = "TXFIFOIRQTRG")]
 pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
 #[doc = "Tx FIFO IRQ Trigger Level"]
 pub mod txfifoirqtrg;
-#[doc = "RXFIFORTSTRG (rw) register accessor: Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifortstrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifortstrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifortstrg`]
+#[doc = "RXFIFORTSTRG (rw) register accessor: Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifortstrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifortstrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifortstrg`] module"]
-module"]
 #[doc(alias = "RXFIFORTSTRG")]
 pub type Rxfifortstrg = crate::Reg<rxfifortstrg::RxfifortstrgSpec>;
 #[doc = "Rx FIFO RTS Trigger Level"]
 pub mod rxfifortstrg;
-#[doc = "STATE (r) register accessor: Internal STATE of UART Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
+#[doc = "STATE (r) register accessor: Internal STATE of UART Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"]
-module"]
 #[doc(alias = "STATE")]
 pub type State = crate::Reg<state::StateSpec>;
 #[doc = "Internal STATE of UART Controller"]
 pub mod state;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
-module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]

va108xx/src/uarta/addr9.rs

@@ -19,10 +19,6 @@ impl crate::Readable for Addr9Spec {}
 #[doc = "`write(|w| ..)` method takes [`addr9::W`](W) writer structure"]
 impl crate::Writable for Addr9Spec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets ADDR9 to value 0"]
-impl crate::Resettable for Addr9Spec {
+impl crate::Resettable for Addr9Spec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/uarta/addr9mask.rs

@@ -19,10 +19,6 @@ impl crate::Readable for Addr9maskSpec {}
 #[doc = "`write(|w| ..)` method takes [`addr9mask::W`](W) writer structure"]
 impl crate::Writable for Addr9maskSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets ADDR9MASK to value 0"]
-impl crate::Resettable for Addr9maskSpec {
+impl crate::Resettable for Addr9maskSpec {}
-    const RESET_VALUE: u32 = 0;
-}

va108xx/src/uarta/clkscale.rs

@@ -27,17 +27,17 @@ impl R {
 impl W {
     #[doc = "Bits 0:5 - Fractional Divide (64ths)"]
     #[inline(always)]
-    pub fn frac(&mut self) -> FracW<ClkscaleSpec> {
+    pub fn frac(&mut self) -> FracW<'_, ClkscaleSpec> {
         FracW::new(self, 0)
     }
     #[doc = "Bits 6:23 - Integer Divide"]
     #[inline(always)]
-    pub fn int(&mut self) -> IntW<ClkscaleSpec> {
+    pub fn int(&mut self) -> IntW<'_, ClkscaleSpec> {
         IntW::new(self, 6)
     }
     #[doc = "Bit 31 - Reset Baud Counter"]
     #[inline(always)]
-    pub fn reset(&mut self) -> ResetW<ClkscaleSpec> {
+    pub fn reset(&mut self) -> ResetW<'_, ClkscaleSpec> {
         ResetW::new(self, 31)
     }
 }
@@ -51,10 +51,6 @@ impl crate::Readable for ClkscaleSpec {}
 #[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"]
 impl crate::Writable for ClkscaleSpec {
     type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CLKSCALE to value 0"]
-impl crate::Resettable for ClkscaleSpec {
+impl crate::Resettable for ClkscaleSpec {}
-    const RESET_VALUE: u32 = 0;
-}