Robin Mueller
1825cc1cdb
Changed: - Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) which is mostly re-exported in this crate. - All HAL API constructors now have a more consistent argument order: PAC structures and resource management structures first, then clock configuration, then any other configuration. - Overhaul and simplification of several HAL APIs. The system configuration and IRQ router peripheral instance generally does not need to be passed to HAL API anymore. - All HAL drivers are now type erased. The constructors will still expect and consume the PAC singleton component for resource management purposes, but are not cached anymore. - Refactoring of GPIO library to be more inline with embassy GPIO API. Added: - I2C clock timeout feature support.
109 lines
3.4 KiB
Rust
109 lines
3.4 KiB
Rust
//! MS and Second counter implemented using the TIM0 and TIM1 peripheral
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#![no_main]
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#![no_std]
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use cortex_m_rt::entry;
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use embedded_hal::delay::DelayNs;
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// Import panic provider.
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use panic_probe as _;
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// Import logger.
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use defmt_rtt as _;
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use portable_atomic::AtomicU32;
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use va108xx_hal::{
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clock::{get_sys_clock, set_sys_clock},
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pac::{self, interrupt},
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prelude::*,
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time::Hertz,
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timer::{CountdownTimer, InterruptConfig},
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};
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#[allow(dead_code)]
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enum LibType {
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Pac,
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Hal,
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}
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static MS_COUNTER: AtomicU32 = AtomicU32::new(0);
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static SEC_COUNTER: AtomicU32 = AtomicU32::new(0);
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#[entry]
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fn main() -> ! {
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let dp = pac::Peripherals::take().unwrap();
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let mut delay = CountdownTimer::new(dp.tim2, 50.MHz());
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let mut last_ms = 0;
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defmt::info!("-- Vorago system ticks using timers --");
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set_sys_clock(50.MHz());
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let lib_type = LibType::Hal;
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match lib_type {
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LibType::Pac => {
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unsafe {
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dp.sysconfig
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.peripheral_clk_enable()
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.modify(|_, w| w.irqsel().set_bit());
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dp.sysconfig
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.tim_clk_enable()
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.modify(|r, w| w.bits(r.bits() | (1 << 0) | (1 << 1)));
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dp.irqsel.tim0(0).write(|w| w.bits(0x00));
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dp.irqsel.tim0(1).write(|w| w.bits(0x01));
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}
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let sys_clk: Hertz = 50.MHz();
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let cnt_ms = sys_clk.raw() / 1000 - 1;
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let cnt_sec = sys_clk.raw() - 1;
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unsafe {
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dp.tim0.cnt_value().write(|w| w.bits(cnt_ms));
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dp.tim0.rst_value().write(|w| w.bits(cnt_ms));
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dp.tim0.ctrl().write(|w| {
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w.enable().set_bit();
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w.irq_enb().set_bit()
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});
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dp.tim1.cnt_value().write(|w| w.bits(cnt_sec));
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dp.tim1.rst_value().write(|w| w.bits(cnt_sec));
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dp.tim1.ctrl().write(|w| {
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w.enable().set_bit();
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w.irq_enb().set_bit()
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});
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unmask_irqs();
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}
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}
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LibType::Hal => {
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let mut ms_timer = CountdownTimer::new(dp.tim0, get_sys_clock().unwrap());
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ms_timer.enable_interrupt(InterruptConfig::new(interrupt::OC0, true, true));
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ms_timer.start(1.kHz());
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let mut second_timer = CountdownTimer::new(dp.tim1, get_sys_clock().unwrap());
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second_timer.enable_interrupt(InterruptConfig::new(interrupt::OC1, true, true));
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second_timer.start(1.Hz());
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}
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}
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loop {
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let current_ms = MS_COUNTER.load(portable_atomic::Ordering::Relaxed);
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if current_ms - last_ms >= 1000 {
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// To prevent drift.
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last_ms += 1000;
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defmt::info!("MS counter: {}", current_ms);
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let second = SEC_COUNTER.load(portable_atomic::Ordering::Relaxed);
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defmt::info!("Second counter: {}", second);
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}
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delay.delay_ms(50);
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}
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}
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fn unmask_irqs() {
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unsafe {
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cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0);
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cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC1);
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}
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}
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#[interrupt]
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#[allow(non_snake_case)]
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fn OC0() {
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MS_COUNTER.fetch_add(1, portable_atomic::Ordering::Relaxed);
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}
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#[interrupt]
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#[allow(non_snake_case)]
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fn OC1() {
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SEC_COUNTER.fetch_add(1, portable_atomic::Ordering::Relaxed);
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}
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