Changed: - Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) which is mostly re-exported in this crate. - All HAL API constructors now have a more consistent argument order: PAC structures and resource management structures first, then clock configuration, then any other configuration. - Overhaul and simplification of several HAL APIs. The system configuration and IRQ router peripheral instance generally does not need to be passed to HAL API anymore. - All HAL drivers are now type erased. The constructors will still expect and consume the PAC singleton component for resource management purposes, but are not cached anymore. - Refactoring of GPIO library to be more inline with embassy GPIO API. Added: - I2C clock timeout feature support.
67 lines
2.0 KiB
Rust
67 lines
2.0 KiB
Rust
//! ADXL343 accelerometer example
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//!
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//! Please note that the default REB1 board is not populated with the ADXL343BCCZ-RL7.
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//! To use this example, this chip needs to be soldered onto the board.
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#![no_main]
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#![no_std]
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use cortex_m_rt::entry;
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use embedded_hal::delay::DelayNs;
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use embedded_hal::spi::{SpiBus, MODE_3};
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use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use va108xx_hal::gpio::{Output, PinState};
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use va108xx_hal::pins::PinsA;
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use va108xx_hal::spi::{configure_pin_as_hw_cs_pin, SpiClkConfig};
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use va108xx_hal::timer::CountdownTimer;
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use va108xx_hal::{
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pac,
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prelude::*,
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spi::{Spi, SpiConfig},
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};
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const READ_MASK: u8 = 1 << 7;
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const _MULTI_BYTE_MASK: u8 = 1 << 6;
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const DEVID_REG: u8 = 0x00;
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const POWER_CTL_REG: u8 = 0x2D;
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const PWR_MEASUREMENT_MODE_MASK: u8 = 1 << 3;
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#[entry]
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fn main() -> ! {
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rtt_init_print!();
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rprintln!("-- Vorago Accelerometer Example --");
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let dp = pac::Peripherals::take().unwrap();
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let pinsa = PinsA::new(dp.porta);
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let mut delay = CountdownTimer::new(dp.tim0, 50.MHz());
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let (sck, mosi, miso) = (pinsa.pa20, pinsa.pa19, pinsa.pa18);
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let cs_pin = pinsa.pa16;
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let hw_cs_id = configure_pin_as_hw_cs_pin(cs_pin);
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// Need to set the ADC chip select low
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Output::new(pinsa.pa17, PinState::Low);
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let spi_cfg = SpiConfig::default()
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.clk_cfg(
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SpiClkConfig::from_clk(50.MHz(), 1.MHz()).expect("creating SPI clock config failed"),
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)
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.mode(MODE_3)
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.slave_output_disable(true);
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let mut spi = Spi::new(dp.spib, (sck, miso, mosi), spi_cfg).unwrap();
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spi.cfg_hw_cs(hw_cs_id);
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let mut tx_rx_buf: [u8; 3] = [0; 3];
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tx_rx_buf[0] = READ_MASK | DEVID_REG;
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spi.transfer_in_place(&mut tx_rx_buf[0..2])
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.expect("Reading DEVID register failed");
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rprintln!("DEVID register: {}", tx_rx_buf[1]);
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tx_rx_buf[0] = POWER_CTL_REG;
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tx_rx_buf[1] = PWR_MEASUREMENT_MODE_MASK;
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spi.write(&tx_rx_buf[0..2])
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.expect("Enabling measurement mode failed");
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loop {
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delay.delay_ms(500);
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}
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}
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