Robin Mueller
58934e293f
Changed: - Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) which is mostly re-exported in this crate. - All HAL API constructors now have a more consistent argument order: PAC structures and resource management structures first, then clock configuration, then any other configuration. - Overhaul and simplification of several HAL APIs. The system configuration and IRQ router peripheral instance generally does not need to be passed to HAL API anymore. - All HAL drivers are now type erased. The constructors will still expect and consume the PAC singleton component for resource management purposes, but are not cached anymore. - Refactoring of GPIO library to be more inline with embassy GPIO API. Added: - I2C clock timeout feature support.
58 lines
1.9 KiB
Rust
58 lines
1.9 KiB
Rust
//! Example application which interfaces with the boot EEPROM.
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#![no_main]
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#![no_std]
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use cortex_m_rt::entry;
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use embedded_hal::delay::DelayNs;
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use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use va108xx_hal::{pac, spi::SpiClkConfig, time::Hertz, timer::CountdownTimer};
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use vorago_reb1::m95m01::{M95M01, PAGE_SIZE};
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const CLOCK_FREQ: Hertz = Hertz::from_raw(50_000_000);
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#[entry]
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fn main() -> ! {
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rtt_init_print!();
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rprintln!("-- VA108XX REB1 NVM example --");
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let dp = pac::Peripherals::take().unwrap();
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let mut delay = CountdownTimer::new(dp.tim0, CLOCK_FREQ);
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let clk_config = SpiClkConfig::new(2, 4);
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let mut nvm = M95M01::new(dp.spic, clk_config);
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let status_reg = nvm.read_status_reg().expect("reading status reg failed");
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if status_reg.zero_segment().value() == 0b111 {
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panic!("status register unexpected values");
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}
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let mut orig_content: [u8; 512] = [0; 512];
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let mut read_buf: [u8; 512] = [0; 512];
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let mut write_buf: [u8; 512] = [0; 512];
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for (idx, val) in write_buf.iter_mut().enumerate() {
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*val = ((idx as u16) % (u8::MAX as u16 + 1)) as u8;
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}
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nvm.read(0, &mut orig_content).unwrap();
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nvm.write_page(0, 0, &[1, 2, 3, 4]).unwrap();
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nvm.read(0, &mut read_buf[0..4]).unwrap();
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// Read the whole content. Write will internally be split across two page bounaries.
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nvm.write(0, &write_buf).unwrap();
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// Memory can be read in one go.
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nvm.read(0, &mut read_buf).unwrap();
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assert_eq!(&read_buf, &write_buf);
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assert!(nvm.verify(0, &write_buf).unwrap());
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read_buf.fill(0);
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// Write along page boundary
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nvm.write(PAGE_SIZE - 2, &write_buf[0..8]).unwrap();
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nvm.read(PAGE_SIZE - 2, &mut read_buf[0..8]).unwrap();
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assert_eq!(&read_buf[0..8], &write_buf[0..8]);
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assert!(nvm.verify(PAGE_SIZE - 2, &write_buf[0..8]).unwrap());
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nvm.write(0, &orig_content).unwrap();
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loop {
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delay.delay_ms(500);
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}
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}
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