250 lines
9.7 KiB
Rust
250 lines
9.7 KiB
Rust
#[doc = "Register `S0_IRQ_ENB` reader"]
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pub type R = crate::R<S0IrqEnbSpec>;
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#[doc = "Register `S0_IRQ_ENB` writer"]
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pub type W = crate::W<S0IrqEnbSpec>;
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#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"]
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pub type CompletedR = crate::BitReader;
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#[doc = "Field `COMPLETED` writer - Controller Complted a Transaction"]
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pub type CompletedW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `IDLE` reader - Controller is Idle"]
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pub type IdleR = crate::BitReader;
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#[doc = "Field `IDLE` writer - Controller is Idle"]
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pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `WAITING` reader - Controller is Waiting"]
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pub type WaitingR = crate::BitReader;
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#[doc = "Field `WAITING` writer - Controller is Waiting"]
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pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"]
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pub type TxstalledR = crate::BitReader;
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#[doc = "Field `TXSTALLED` writer - Controller is Tx Stalled"]
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pub type TxstalledW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"]
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pub type RxstalledR = crate::BitReader;
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#[doc = "Field `RXSTALLED` writer - Controller is Rx Stalled"]
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pub type RxstalledW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"]
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pub type AddressmatchR = crate::BitReader;
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#[doc = "Field `ADDRESSMATCH` writer - I2C Address Match"]
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pub type AddressmatchW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
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pub type NackdataR = crate::BitReader;
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#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
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pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"]
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pub type RxdatafirstR = crate::BitReader;
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#[doc = "Field `RXDATAFIRST` writer - Pending Data is first Byte following Address"]
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pub type RxdatafirstW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `I2C_START` reader - I2C Start Condition"]
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pub type I2cStartR = crate::BitReader;
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#[doc = "Field `I2C_START` writer - I2C Start Condition"]
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pub type I2cStartW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"]
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pub type I2cStopR = crate::BitReader;
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#[doc = "Field `I2C_STOP` writer - I2C Stop Condition"]
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pub type I2cStopW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"]
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pub type TxunderflowR = crate::BitReader;
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#[doc = "Field `TXUNDERFLOW` writer - TX FIFO Underflowed"]
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pub type TxunderflowW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"]
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pub type RxoverflowR = crate::BitReader;
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#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"]
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pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `TXREADY` reader - TX FIFO Ready"]
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pub type TxreadyR = crate::BitReader;
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#[doc = "Field `TXREADY` writer - TX FIFO Ready"]
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pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `RXREADY` reader - RX FIFO Ready"]
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pub type RxreadyR = crate::BitReader;
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#[doc = "Field `RXREADY` writer - RX FIFO Ready"]
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pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"]
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pub type TxemptyR = crate::BitReader;
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#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"]
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pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `RXFULL` reader - RX FIFO Full"]
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pub type RxfullR = crate::BitReader;
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#[doc = "Field `RXFULL` writer - RX FIFO Full"]
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pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - Controller Complted a Transaction"]
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#[inline(always)]
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pub fn completed(&self) -> CompletedR {
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CompletedR::new((self.bits & 1) != 0)
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}
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#[doc = "Bit 1 - Controller is Idle"]
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#[inline(always)]
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pub fn idle(&self) -> IdleR {
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IdleR::new(((self.bits >> 1) & 1) != 0)
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}
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#[doc = "Bit 2 - Controller is Waiting"]
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#[inline(always)]
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pub fn waiting(&self) -> WaitingR {
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WaitingR::new(((self.bits >> 2) & 1) != 0)
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}
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#[doc = "Bit 3 - Controller is Tx Stalled"]
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#[inline(always)]
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pub fn txstalled(&self) -> TxstalledR {
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TxstalledR::new(((self.bits >> 3) & 1) != 0)
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}
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#[doc = "Bit 4 - Controller is Rx Stalled"]
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#[inline(always)]
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pub fn rxstalled(&self) -> RxstalledR {
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RxstalledR::new(((self.bits >> 4) & 1) != 0)
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}
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#[doc = "Bit 5 - I2C Address Match"]
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#[inline(always)]
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pub fn addressmatch(&self) -> AddressmatchR {
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AddressmatchR::new(((self.bits >> 5) & 1) != 0)
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}
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#[doc = "Bit 6 - I2C Data was not Acknowledged"]
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#[inline(always)]
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pub fn nackdata(&self) -> NackdataR {
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NackdataR::new(((self.bits >> 6) & 1) != 0)
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}
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#[doc = "Bit 7 - Pending Data is first Byte following Address"]
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#[inline(always)]
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pub fn rxdatafirst(&self) -> RxdatafirstR {
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RxdatafirstR::new(((self.bits >> 7) & 1) != 0)
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}
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#[doc = "Bit 8 - I2C Start Condition"]
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#[inline(always)]
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pub fn i2c_start(&self) -> I2cStartR {
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I2cStartR::new(((self.bits >> 8) & 1) != 0)
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}
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#[doc = "Bit 9 - I2C Stop Condition"]
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#[inline(always)]
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pub fn i2c_stop(&self) -> I2cStopR {
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I2cStopR::new(((self.bits >> 9) & 1) != 0)
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}
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#[doc = "Bit 10 - TX FIFO Underflowed"]
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#[inline(always)]
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pub fn txunderflow(&self) -> TxunderflowR {
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TxunderflowR::new(((self.bits >> 10) & 1) != 0)
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}
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#[doc = "Bit 11 - TX FIFO Overflowed"]
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#[inline(always)]
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pub fn rxoverflow(&self) -> RxoverflowR {
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RxoverflowR::new(((self.bits >> 11) & 1) != 0)
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}
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#[doc = "Bit 12 - TX FIFO Ready"]
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#[inline(always)]
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pub fn txready(&self) -> TxreadyR {
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TxreadyR::new(((self.bits >> 12) & 1) != 0)
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}
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#[doc = "Bit 13 - RX FIFO Ready"]
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#[inline(always)]
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pub fn rxready(&self) -> RxreadyR {
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RxreadyR::new(((self.bits >> 13) & 1) != 0)
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}
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#[doc = "Bit 14 - TX FIFO Empty"]
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#[inline(always)]
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pub fn txempty(&self) -> TxemptyR {
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TxemptyR::new(((self.bits >> 14) & 1) != 0)
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}
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#[doc = "Bit 15 - RX FIFO Full"]
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#[inline(always)]
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pub fn rxfull(&self) -> RxfullR {
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RxfullR::new(((self.bits >> 15) & 1) != 0)
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}
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}
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impl W {
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#[doc = "Bit 0 - Controller Complted a Transaction"]
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#[inline(always)]
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pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> {
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CompletedW::new(self, 0)
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}
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#[doc = "Bit 1 - Controller is Idle"]
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#[inline(always)]
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pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> {
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IdleW::new(self, 1)
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}
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#[doc = "Bit 2 - Controller is Waiting"]
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#[inline(always)]
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pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> {
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WaitingW::new(self, 2)
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}
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#[doc = "Bit 3 - Controller is Tx Stalled"]
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#[inline(always)]
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pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> {
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TxstalledW::new(self, 3)
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}
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#[doc = "Bit 4 - Controller is Rx Stalled"]
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#[inline(always)]
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pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> {
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RxstalledW::new(self, 4)
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}
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#[doc = "Bit 5 - I2C Address Match"]
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#[inline(always)]
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pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> {
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AddressmatchW::new(self, 5)
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}
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#[doc = "Bit 6 - I2C Data was not Acknowledged"]
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#[inline(always)]
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pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> {
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NackdataW::new(self, 6)
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}
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#[doc = "Bit 7 - Pending Data is first Byte following Address"]
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#[inline(always)]
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pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> {
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RxdatafirstW::new(self, 7)
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}
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#[doc = "Bit 8 - I2C Start Condition"]
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#[inline(always)]
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pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> {
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I2cStartW::new(self, 8)
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}
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#[doc = "Bit 9 - I2C Stop Condition"]
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#[inline(always)]
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pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> {
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I2cStopW::new(self, 9)
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}
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#[doc = "Bit 10 - TX FIFO Underflowed"]
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#[inline(always)]
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pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> {
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TxunderflowW::new(self, 10)
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}
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#[doc = "Bit 11 - TX FIFO Overflowed"]
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#[inline(always)]
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pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> {
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RxoverflowW::new(self, 11)
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}
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#[doc = "Bit 12 - TX FIFO Ready"]
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#[inline(always)]
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pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> {
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TxreadyW::new(self, 12)
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}
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#[doc = "Bit 13 - RX FIFO Ready"]
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#[inline(always)]
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pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> {
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RxreadyW::new(self, 13)
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}
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#[doc = "Bit 14 - TX FIFO Empty"]
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#[inline(always)]
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pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> {
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TxemptyW::new(self, 14)
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}
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#[doc = "Bit 15 - RX FIFO Full"]
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#[inline(always)]
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pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> {
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RxfullW::new(self, 15)
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}
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}
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#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct S0IrqEnbSpec;
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impl crate::RegisterSpec for S0IrqEnbSpec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`s0_irq_enb::R`](R) reader structure"]
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impl crate::Readable for S0IrqEnbSpec {}
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#[doc = "`write(|w| ..)` method takes [`s0_irq_enb::W`](W) writer structure"]
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impl crate::Writable for S0IrqEnbSpec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets S0_IRQ_ENB to value 0"]
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impl crate::Resettable for S0IrqEnbSpec {
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const RESET_VALUE: u32 = 0;
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}
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