53 lines
1.8 KiB
Rust
53 lines
1.8 KiB
Rust
//! # API for clock related functionality
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//!
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//! This also includes functionality to enable the peripheral clocks
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use crate::time::Hertz;
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use cortex_m::interrupt::{self, Mutex};
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use once_cell::unsync::OnceCell;
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pub use vorago_shared_periphs::gpio::FilterClkSel;
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pub use vorago_shared_periphs::sysconfig::{disable_peripheral_clock, enable_peripheral_clock};
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static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
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/// The Vorago in powered by an external clock which might have different frequencies.
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/// The clock can be set here so it can be used by other software components as well.
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/// The clock can be set exactly once
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pub fn set_sys_clock(freq: impl Into<Hertz>) {
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interrupt::free(|cs| {
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SYS_CLOCK.borrow(cs).set(freq.into()).ok();
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})
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}
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/// Returns the configured system clock
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pub fn get_sys_clock() -> Option<Hertz> {
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interrupt::free(|cs| SYS_CLOCK.borrow(cs).get().copied())
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}
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pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClkSel, div: u32) {
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match clk_sel {
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FilterClkSel::SysClk => (),
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FilterClkSel::Clk1 => {
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syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) });
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}
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FilterClkSel::Clk2 => {
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syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) });
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}
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FilterClkSel::Clk3 => {
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syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) });
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}
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FilterClkSel::Clk4 => {
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syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) });
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}
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FilterClkSel::Clk5 => {
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syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) });
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}
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FilterClkSel::Clk6 => {
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syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) });
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}
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FilterClkSel::Clk7 => {
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syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) });
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}
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}
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}
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