222 lines
7.6 KiB
Rust
222 lines
7.6 KiB
Rust
#[repr(C)]
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#[doc = "Register block"]
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pub struct RegisterBlock {
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porta0: [Porta; 32],
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portb0: [Portb; 32],
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tim0: [Tim; 32],
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uart0: [Uart; 4],
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spi0: [Spi; 4],
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i2c_ms0: [I2cMs; 4],
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i2c_sl0: [I2cSl; 4],
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int_ram_sbe: IntRamSbe,
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int_ram_mbe: IntRamMbe,
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int_rom_sbe: IntRomSbe,
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int_rom_mbe: IntRomMbe,
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txev: Txev,
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_reserved12: [u8; 0x062c],
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irqs0: [Irqs; 32],
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_reserved13: [u8; 0x68],
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edbgrq: Edbgrq,
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mereset: Mereset,
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watchdog: Watchdog,
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rxev: Rxev,
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nmi: Nmi,
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_reserved18: [u8; 0x0700],
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perid: Perid,
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}
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impl RegisterBlock {
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#[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn porta0(&self, n: usize) -> &Porta {
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&self.porta0[n]
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}
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#[doc = "Iterator for array of:"]
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#[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
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#[inline(always)]
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pub fn porta0_iter(&self) -> impl Iterator<Item = &Porta> {
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self.porta0.iter()
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}
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#[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn portb0(&self, n: usize) -> &Portb {
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&self.portb0[n]
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}
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#[doc = "Iterator for array of:"]
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#[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
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#[inline(always)]
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pub fn portb0_iter(&self) -> impl Iterator<Item = &Portb> {
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self.portb0.iter()
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}
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#[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn tim0(&self, n: usize) -> &Tim {
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&self.tim0[n]
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}
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#[doc = "Iterator for array of:"]
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#[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
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#[inline(always)]
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pub fn tim0_iter(&self) -> impl Iterator<Item = &Tim> {
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self.tim0.iter()
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}
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#[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn uart0(&self, n: usize) -> &Uart {
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&self.uart0[n]
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}
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#[doc = "Iterator for array of:"]
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#[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
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#[inline(always)]
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pub fn uart0_iter(&self) -> impl Iterator<Item = &Uart> {
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self.uart0.iter()
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}
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#[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn spi0(&self, n: usize) -> &Spi {
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&self.spi0[n]
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}
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#[doc = "Iterator for array of:"]
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#[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
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#[inline(always)]
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pub fn spi0_iter(&self) -> impl Iterator<Item = &Spi> {
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self.spi0.iter()
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}
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#[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn i2c_ms0(&self, n: usize) -> &I2cMs {
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&self.i2c_ms0[n]
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}
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#[doc = "Iterator for array of:"]
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#[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
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#[inline(always)]
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pub fn i2c_ms0_iter(&self) -> impl Iterator<Item = &I2cMs> {
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self.i2c_ms0.iter()
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}
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#[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn i2c_sl0(&self, n: usize) -> &I2cSl {
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&self.i2c_sl0[n]
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}
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#[doc = "Iterator for array of:"]
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#[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
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#[inline(always)]
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pub fn i2c_sl0_iter(&self) -> impl Iterator<Item = &I2cSl> {
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self.i2c_sl0.iter()
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}
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#[doc = "0x1c0 - Internal Memory RAM SBE Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn int_ram_sbe(&self) -> &IntRamSbe {
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&self.int_ram_sbe
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}
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#[doc = "0x1c4 - Internal Memory RAM MBE Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn int_ram_mbe(&self) -> &IntRamMbe {
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&self.int_ram_mbe
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}
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#[doc = "0x1c8 - Internal Memory ROM SBE Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn int_rom_sbe(&self) -> &IntRomSbe {
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&self.int_rom_sbe
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}
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#[doc = "0x1cc - Internal Memory ROM MBE Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn int_rom_mbe(&self) -> &IntRomMbe {
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&self.int_rom_mbe
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}
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#[doc = "0x1d0 - Processor TXEV Interrupt Redirect Selection"]
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#[inline(always)]
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pub const fn txev(&self) -> &Txev {
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&self.txev
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}
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#[doc = "0x800..0x880 - Interrupt Status Register"]
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#[inline(always)]
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pub const fn irqs0(&self, n: usize) -> &Irqs {
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&self.irqs0[n]
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}
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#[doc = "Iterator for array of:"]
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#[doc = "0x800..0x880 - Interrupt Status Register"]
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#[inline(always)]
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pub fn irqs0_iter(&self) -> impl Iterator<Item = &Irqs> {
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self.irqs0.iter()
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}
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#[doc = "0x8e8 - EDBGRQ Status Register"]
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#[inline(always)]
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pub const fn edbgrq(&self) -> &Edbgrq {
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&self.edbgrq
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}
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#[doc = "0x8ec - MERESET Status Register"]
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#[inline(always)]
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pub const fn mereset(&self) -> &Mereset {
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&self.mereset
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}
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#[doc = "0x8f0 - WATCHDOG Status Register"]
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#[inline(always)]
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pub const fn watchdog(&self) -> &Watchdog {
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&self.watchdog
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}
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#[doc = "0x8f4 - RXEV Status Register"]
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#[inline(always)]
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pub const fn rxev(&self) -> &Rxev {
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&self.rxev
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}
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#[doc = "0x8f8 - NMI Status Register"]
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#[inline(always)]
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pub const fn nmi(&self) -> &Nmi {
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&self.nmi
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}
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#[doc = "0xffc - Peripheral ID Register"]
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#[inline(always)]
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pub const fn perid(&self) -> &Perid {
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&self.perid
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}
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}
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#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`]
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module"]
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#[doc(alias = "INT_RAM_SBE")]
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pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>;
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#[doc = "Internal Memory RAM SBE Interrupt Redirect Selection"]
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pub mod int_ram_sbe;
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pub use int_ram_sbe as porta;
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pub use int_ram_sbe as portb;
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pub use int_ram_sbe as tim;
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pub use int_ram_sbe as uart;
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pub use int_ram_sbe as spi;
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pub use int_ram_sbe as i2c_ms;
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pub use int_ram_sbe as i2c_sl;
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pub use int_ram_sbe as int_ram_mbe;
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pub use int_ram_sbe as int_rom_sbe;
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pub use int_ram_sbe as int_rom_mbe;
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pub use int_ram_sbe as txev;
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pub use IntRamSbe as Porta;
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pub use IntRamSbe as Portb;
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pub use IntRamSbe as Tim;
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pub use IntRamSbe as Uart;
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pub use IntRamSbe as Spi;
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pub use IntRamSbe as I2cMs;
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pub use IntRamSbe as I2cSl;
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pub use IntRamSbe as IntRamMbe;
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pub use IntRamSbe as IntRomSbe;
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pub use IntRamSbe as IntRomMbe;
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pub use IntRamSbe as Txev;
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#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`]
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module"]
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#[doc(alias = "NMI")]
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pub type Nmi = crate::Reg<nmi::NmiSpec>;
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#[doc = "NMI Status Register"]
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pub mod nmi;
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pub use nmi as rxev;
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pub use nmi as watchdog;
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pub use nmi as mereset;
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pub use nmi as edbgrq;
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pub use nmi as irqs;
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pub use Nmi as Rxev;
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pub use Nmi as Watchdog;
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pub use Nmi as Mereset;
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pub use Nmi as Edbgrq;
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pub use Nmi as Irqs;
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#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
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module"]
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#[doc(alias = "PERID")]
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pub type Perid = crate::Reg<perid::PeridSpec>;
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#[doc = "Peripheral ID Register"]
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pub mod perid;
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