110 lines
3.6 KiB
Rust
110 lines
3.6 KiB
Rust
//! Simple Cascade example
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//!
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//! A timer will be periodically started which starts another timer via the cascade feature.
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//! This timer will then start another timer with the cascade feature as well.
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#![no_main]
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#![no_std]
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#![allow(non_snake_case)]
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use cortex_m_rt::entry;
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use embedded_hal::delay::DelayNs;
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// Import panic provider.
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use panic_probe as _;
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// Import logger.
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use defmt_rtt as _;
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use va108xx_hal::{
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pac::{self, interrupt},
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prelude::*,
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timer::{CascadeControl, CascadeSelect, CascadeSource, CountdownTimer, InterruptConfig},
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};
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#[entry]
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fn main() -> ! {
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defmt::println!("-- VA108xx Cascade example application--");
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let dp = pac::Peripherals::take().unwrap();
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let mut delay = CountdownTimer::new(50.MHz(), dp.tim0);
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// Will be started periodically to trigger a cascade
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let mut cascade_triggerer = CountdownTimer::new(50.MHz(), dp.tim3);
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cascade_triggerer.auto_disable(true);
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cascade_triggerer.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC1, true, false));
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cascade_triggerer.enable();
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// First target for cascade
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let mut cascade_target_1 = CountdownTimer::new(50.MHz(), dp.tim4);
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cascade_target_1.auto_deactivate(true);
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cascade_target_1
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.cascade_source(CascadeSelect::Csd0, CascadeSource::Tim(3))
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.unwrap();
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let mut csd_cfg = CascadeControl {
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enable_src_0: true,
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trigger_mode_0: true,
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..Default::default()
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};
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cascade_target_1.cascade_control(csd_cfg);
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// Normally it should already be sufficient to activate IRQ in the CTRL
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// register but a full interrupt is use here to display print output when
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// the timer expires
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cascade_target_1.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC2, true, false));
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// The counter will only activate when the cascade signal is coming in so
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// it is okay to call start here to set the reset value
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cascade_target_1.start(1.Hz());
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// Activated by first cascade target
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let mut cascade_target_2 = CountdownTimer::new(50.MHz(), dp.tim5);
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cascade_target_2.auto_deactivate(true);
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// Set TIM4 as cascade source
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cascade_target_2
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.cascade_source(CascadeSelect::Csd1, CascadeSource::Tim(4))
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.unwrap();
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csd_cfg = CascadeControl::default();
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csd_cfg.enable_src_1 = true;
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// Use trigger mode here
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csd_cfg.trigger_mode_1 = true;
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cascade_target_2.cascade_control(csd_cfg);
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// Normally it should already be sufficient to activate IRQ in the CTRL
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// register but a full interrupt is use here to display print output when
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// the timer expires
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cascade_target_2.enable_interrupt(InterruptConfig::new(pac::Interrupt::OC3, true, false));
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// The counter will only activate when the cascade signal is coming in so
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// it is okay to call start here to set the reset value
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cascade_target_2.start(1.Hz());
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// Unpend all IRQs
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unsafe {
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cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0);
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cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC1);
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cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC2);
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cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC3);
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}
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loop {
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defmt::info!("-- Triggering cascade in 0.5 seconds --");
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cascade_triggerer.start(2.Hz());
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delay.delay_ms(5000);
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}
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}
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#[interrupt]
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fn OC1() {
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static mut IDX: u32 = 0;
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defmt::info!("{}: Cascade trigger timed out", &IDX);
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*IDX += 1;
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}
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#[interrupt]
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fn OC2() {
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static mut IDX: u32 = 0;
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defmt::info!("{}: First cascade target timed out", &IDX);
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*IDX += 1;
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}
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#[interrupt]
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fn OC3() {
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static mut IDX: u32 = 0;
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defmt::info!("{}: Second cascade target timed out", &IDX);
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*IDX += 1;
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}
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