613 lines
19 KiB
Rust
613 lines
19 KiB
Rust
//! # Type-erased, value-level module for GPIO pins
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//!
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//! Although the type-level API is generally preferred, it is not suitable in
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//! all cases. Because each pin is represented by a distinct type, it is not
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//! possible to store multiple pins in a homogeneous data structure. The
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//! value-level API solves this problem by erasing the type information and
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//! tracking the pin at run-time.
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//!
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//! Value-level pins are represented by the [`DynPin`] type. [`DynPin`] has two
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//! fields, `id` and `mode` with types [`DynPinId`] and [`DynPinMode`]
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//! respectively. The implementation of these types closely mirrors the
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//! type-level API.
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//!
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//! Instances of [`DynPin`] cannot be created directly. Rather, they must be
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//! created from their type-level equivalents using [`From`]/[`Into`].
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//!
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//! ```
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//! // Move a pin out of the Pins struct and convert to a DynPin
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//! let pa0: DynPin = pins.pa0.into();
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//! ```
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//!
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//! Conversions between pin modes use a value-level version of the type-level
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//! API.
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//!
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//! ```
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//! // Use one of the literal function names
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//! pa0.into_floating_input();
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//! // Use a method and a DynPinMode variant
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//! pa0.into_mode(DYN_FLOATING_INPUT);
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//! ```
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//!
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//! Because the pin state cannot be tracked at compile-time, many [`DynPin`]
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//! operations become fallible. Run-time checks are inserted to ensure that
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//! users don't try to, for example, set the output level of an input pin.
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//!
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//! Users may try to convert value-level pins back to their type-level
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//! equivalents. However, this option is fallible, because the compiler cannot
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//! guarantee the pin has the correct ID or is in the correct mode at
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//! compile-time. Use [TryFrom]/[TryInto] for this conversion.
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//!
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//! ```
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//! // Convert to a `DynPin`
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//! let pa0: DynPin = pins.pa0.into();
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//! // Change pin mode
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//! pa0.into_floating_input();
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//! // Convert back to a `Pin`
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//! let pa0: Pin<PA0, FloatingInput> = pa0.try_into().unwrap();
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//! ```
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//!
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//! # Embedded HAL traits
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//!
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//! This module implements all of the embedded HAL GPIO traits for [`DynPin`].
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//! However, whereas the type-level API uses
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//! `Error = core::convert::Infallible`, the value-level API can return a real
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//! error. If the [`DynPin`] is not in the correct [`DynPinMode`] for the
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//! operation, the trait functions will return
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//! [InvalidPinTypeError].
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use super::{
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pin::{FilterType, InterruptEdge, InterruptLevel, Pin, PinId, PinMode, PinState},
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reg::RegisterInterface,
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InputDynPinAsync,
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};
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use crate::{clock::FilterClkSel, enable_interrupt, pac, FunSel, IrqCfg};
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//==================================================================================================
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// DynPinMode configurations
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//==================================================================================================
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/// Value-level `enum` for disabled configurations
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#[derive(PartialEq, Eq, Clone, Copy)]
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pub enum DynDisabled {
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Floating,
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PullDown,
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PullUp,
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}
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/// Value-level `enum` for input configurations
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#[derive(Debug, PartialEq, Eq, Clone, Copy)]
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pub enum DynInput {
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Floating,
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PullDown,
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PullUp,
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}
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/// Value-level `enum` for output configurations
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#[derive(Debug, PartialEq, Eq, Clone, Copy)]
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pub enum DynOutput {
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PushPull,
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OpenDrain,
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ReadablePushPull,
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ReadableOpenDrain,
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}
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pub type DynAlternate = FunSel;
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//==============================================================================
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// Error
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//==============================================================================
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/// GPIO error type
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///
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/// [`DynPin`]s are not tracked and verified at compile-time, so run-time
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/// operations are fallible. This `enum` represents the corresponding errors.
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#[derive(Debug, PartialEq, Eq, thiserror::Error)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[error("Invalid pin type for operation: {0:?}")]
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pub struct InvalidPinTypeError(pub DynPinMode);
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impl embedded_hal::digital::Error for InvalidPinTypeError {
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fn kind(&self) -> embedded_hal::digital::ErrorKind {
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embedded_hal::digital::ErrorKind::Other
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}
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}
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//==================================================================================================
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// DynPinMode
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//==================================================================================================
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/// Value-level `enum` representing pin modes
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#[derive(Debug, PartialEq, Eq, Clone, Copy)]
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pub enum DynPinMode {
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Input(DynInput),
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Output(DynOutput),
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Alternate(DynAlternate),
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}
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/// Value-level variant of [`DynPinMode`] for floating input mode
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pub const DYN_FLOATING_INPUT: DynPinMode = DynPinMode::Input(DynInput::Floating);
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/// Value-level variant of [`DynPinMode`] for pull-down input mode
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pub const DYN_PULL_DOWN_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullDown);
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/// Value-level variant of [`DynPinMode`] for pull-up input mode
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pub const DYN_PULL_UP_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullUp);
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/// Value-level variant of [`DynPinMode`] for push-pull output mode
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pub const DYN_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::PushPull);
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/// Value-level variant of [`DynPinMode`] for open-drain output mode
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pub const DYN_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::OpenDrain);
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/// Value-level variant of [`DynPinMode`] for readable push-pull output mode
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pub const DYN_RD_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadablePushPull);
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/// Value-level variant of [`DynPinMode`] for readable opendrain output mode
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pub const DYN_RD_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadableOpenDrain);
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/// Value-level variant of [`DynPinMode`] for function select 1
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pub const DYN_ALT_FUNC_1: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel1);
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/// Value-level variant of [`DynPinMode`] for function select 2
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pub const DYN_ALT_FUNC_2: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel2);
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/// Value-level variant of [`DynPinMode`] for function select 3
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pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel3);
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//==================================================================================================
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// DynGroup & DynPinId
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//==================================================================================================
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/// Value-level `enum` for pin groups
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#[derive(PartialEq, Eq, Clone, Copy)]
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pub enum DynGroup {
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A,
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B,
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}
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/// Value-level `struct` representing pin IDs
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#[derive(PartialEq, Eq, Clone, Copy)]
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pub struct DynPinId {
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pub group: DynGroup,
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pub num: u8,
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}
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//==================================================================================================
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// DynRegisters
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//==================================================================================================
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/// Provide a safe register interface for [`DynPin`]s
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///
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/// This `struct` takes ownership of a [`DynPinId`] and provides an API to
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/// access the corresponding regsiters.
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pub(crate) struct DynRegisters(DynPinId);
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// [`DynRegisters`] takes ownership of the [`DynPinId`], and [`DynPin`]
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// guarantees that each pin is a singleton, so this implementation is safe.
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unsafe impl RegisterInterface for DynRegisters {
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#[inline]
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fn id(&self) -> DynPinId {
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self.0
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}
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}
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impl DynRegisters {
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/// Create a new instance of [`DynRegisters`]
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///
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/// # Safety
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///
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/// Users must never create two simultaneous instances of this `struct` with
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/// the same [`DynPinId`]
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#[inline]
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unsafe fn new(id: DynPinId) -> Self {
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DynRegisters(id)
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}
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}
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//==================================================================================================
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// DynPin
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//==================================================================================================
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/// A value-level pin, parameterized by [`DynPinId`] and [`DynPinMode`]
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///
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/// This type acts as a type-erased version of [`Pin`]. Every pin is represented
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/// by the same type, and pins are tracked and distinguished at run-time.
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pub struct DynPin {
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pub(crate) regs: DynRegisters,
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mode: DynPinMode,
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}
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impl DynPin {
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/// Create a new [`DynPin`]
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///
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/// # Safety
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///
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/// Each [`DynPin`] must be a singleton. For a given [`DynPinId`], there
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/// must be at most one corresponding [`DynPin`] in existence at any given
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/// time. Violating this requirement is `unsafe`.
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#[inline]
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pub(crate) unsafe fn new(id: DynPinId, mode: DynPinMode) -> Self {
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DynPin {
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regs: DynRegisters::new(id),
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mode,
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}
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}
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/// Return a copy of the pin ID
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#[inline]
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pub fn id(&self) -> DynPinId {
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self.regs.0
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}
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/// Return a copy of the pin mode
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#[inline]
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pub fn mode(&self) -> DynPinMode {
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self.mode
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}
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/// Convert the pin to the requested [`DynPinMode`]
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#[inline]
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pub fn into_mode(&mut self, mode: DynPinMode) {
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// Only modify registers if we are actually changing pin mode
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if mode != self.mode {
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self.regs.change_mode(mode);
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self.mode = mode;
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}
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}
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#[inline]
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pub fn is_input_pin(&self) -> bool {
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matches!(self.mode, DynPinMode::Input(_))
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}
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#[inline]
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pub fn into_funsel_1(&mut self) {
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self.into_mode(DYN_ALT_FUNC_1);
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}
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#[inline]
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pub fn into_funsel_2(&mut self) {
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self.into_mode(DYN_ALT_FUNC_2);
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}
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#[inline]
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pub fn into_funsel_3(&mut self) {
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self.into_mode(DYN_ALT_FUNC_3);
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}
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/// Configure the pin to operate as a floating input
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#[inline]
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pub fn into_floating_input(&mut self) {
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self.into_mode(DYN_FLOATING_INPUT);
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}
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/// Configure the pin to operate as a pulled down input
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#[inline]
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pub fn into_pull_down_input(&mut self) {
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self.into_mode(DYN_PULL_DOWN_INPUT);
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}
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/// Configure the pin to operate as a pulled up input
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#[inline]
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pub fn into_pull_up_input(&mut self) {
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self.into_mode(DYN_PULL_UP_INPUT);
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}
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/// Configure the pin to operate as a push-pull output
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#[inline]
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pub fn into_push_pull_output(&mut self) {
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self.into_mode(DYN_PUSH_PULL_OUTPUT);
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}
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/// Configure the pin to operate as a push-pull output
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#[inline]
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pub fn into_open_drain_output(&mut self) {
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self.into_mode(DYN_OPEN_DRAIN_OUTPUT);
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}
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/// Configure the pin to operate as a push-pull output
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#[inline]
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pub fn into_readable_push_pull_output(&mut self) {
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self.into_mode(DYN_RD_PUSH_PULL_OUTPUT);
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}
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/// Configure the pin to operate as a push-pull output
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#[inline]
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pub fn into_readable_open_drain_output(&mut self) {
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self.into_mode(DYN_RD_OPEN_DRAIN_OUTPUT);
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}
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#[inline]
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pub fn datamask(&self) -> bool {
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self.regs.datamask()
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}
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#[inline]
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pub fn clear_datamask(&mut self) {
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self.regs.clear_datamask();
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}
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#[inline]
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pub fn set_datamask(&mut self) {
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self.regs.set_datamask();
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}
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#[inline]
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pub fn is_high_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
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self.regs.read_pin_masked()
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}
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#[inline]
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pub fn is_low_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
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self.regs.read_pin_masked().map(|v| !v)
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}
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#[inline]
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pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
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self.regs.write_pin_masked(true)
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}
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#[inline]
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pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
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self.regs.write_pin_masked(false)
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}
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#[inline]
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pub fn edge_has_occurred(&mut self) -> bool {
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self.regs.edge_has_occurred()
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}
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pub(crate) fn irq_enb(
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&mut self,
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irq_cfg: crate::IrqCfg,
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syscfg: Option<&mut va108xx::Sysconfig>,
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irqsel: Option<&mut va108xx::Irqsel>,
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) {
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if let Some(syscfg) = syscfg {
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crate::clock::enable_peripheral_clock(syscfg, crate::clock::PeripheralClocks::Irqsel);
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}
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self.regs.enable_irq();
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if let Some(irqsel) = irqsel {
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if irq_cfg.route {
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match self.regs.id().group {
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// Set the correct interrupt number in the IRQSEL register
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DynGroup::A => {
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irqsel
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.porta0(self.regs.id().num as usize)
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.write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
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}
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DynGroup::B => {
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irqsel
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.portb0(self.regs.id().num as usize)
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.write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
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}
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}
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}
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}
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if irq_cfg.enable {
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unsafe { enable_interrupt(irq_cfg.irq) };
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}
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}
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/// See p.53 of the programmers guide for more information.
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/// Possible delays in clock cycles:
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/// - Delay 1: 1
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/// - Delay 2: 2
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/// - Delay 1 + Delay 2: 3
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#[inline]
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pub fn delay(self, delay_1: bool, delay_2: bool) -> Result<Self, InvalidPinTypeError> {
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match self.mode {
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DynPinMode::Output(_) => {
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self.regs.delay(delay_1, delay_2);
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Ok(self)
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}
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_ => Err(InvalidPinTypeError(self.mode)),
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}
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}
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/// See p.52 of the programmers guide for more information.
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/// When configured for pulse mode, a given pin will set the non-default state for exactly
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/// one clock cycle before returning to the configured default state
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#[inline]
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pub fn pulse_mode(
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&mut self,
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enable: bool,
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default_state: PinState,
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) -> Result<(), InvalidPinTypeError> {
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match self.mode {
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DynPinMode::Output(_) => {
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self.regs.pulse_mode(enable, default_state);
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Ok(())
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}
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_ => Err(InvalidPinTypeError(self.mode)),
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}
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}
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/// See p.37 and p.38 of the programmers guide for more information.
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#[inline]
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pub fn filter_type(
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&mut self,
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filter: FilterType,
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clksel: FilterClkSel,
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) -> Result<(), InvalidPinTypeError> {
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match self.mode {
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DynPinMode::Input(_) => {
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self.regs.filter_type(filter, clksel);
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Ok(())
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}
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_ => Err(InvalidPinTypeError(self.mode)),
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}
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}
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#[inline]
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pub fn interrupt_edge(
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&mut self,
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edge_type: InterruptEdge,
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irq_cfg: IrqCfg,
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syscfg: Option<&mut pac::Sysconfig>,
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irqsel: Option<&mut pac::Irqsel>,
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) -> Result<(), InvalidPinTypeError> {
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match self.mode {
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DynPinMode::Input(_) | DynPinMode::Output(_) => {
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self.regs.interrupt_edge(edge_type);
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self.irq_enb(irq_cfg, syscfg, irqsel);
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Ok(())
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}
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_ => Err(InvalidPinTypeError(self.mode)),
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}
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}
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#[inline]
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pub fn interrupt_level(
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&mut self,
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level_type: InterruptLevel,
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irq_cfg: IrqCfg,
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syscfg: Option<&mut pac::Sysconfig>,
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irqsel: Option<&mut pac::Irqsel>,
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) -> Result<(), InvalidPinTypeError> {
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match self.mode {
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DynPinMode::Input(_) | DynPinMode::Output(_) => {
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self.regs.interrupt_level(level_type);
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self.irq_enb(irq_cfg, syscfg, irqsel);
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Ok(())
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}
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_ => Err(InvalidPinTypeError(self.mode)),
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}
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}
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#[inline]
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pub fn toggle_with_toggle_reg(&mut self) -> Result<(), InvalidPinTypeError> {
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match self.mode {
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DynPinMode::Output(_) => {
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self.regs.toggle();
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Ok(())
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}
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_ => Err(InvalidPinTypeError(self.mode)),
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}
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}
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#[inline]
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fn _read(&self) -> Result<bool, InvalidPinTypeError> {
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match self.mode {
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DynPinMode::Input(_) | DYN_RD_OPEN_DRAIN_OUTPUT | DYN_RD_PUSH_PULL_OUTPUT => {
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Ok(self.regs.read_pin())
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}
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_ => Err(InvalidPinTypeError(self.mode)),
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}
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}
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#[inline]
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fn _write(&mut self, bit: bool) -> Result<(), InvalidPinTypeError> {
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match self.mode {
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DynPinMode::Output(_) => {
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self.regs.write_pin(bit);
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Ok(())
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}
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_ => Err(InvalidPinTypeError(self.mode)),
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}
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}
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#[inline]
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fn _is_low(&self) -> Result<bool, InvalidPinTypeError> {
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self._read().map(|v| !v)
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}
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#[inline]
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fn _is_high(&self) -> Result<bool, InvalidPinTypeError> {
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self._read()
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}
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#[inline]
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fn _set_low(&mut self) -> Result<(), InvalidPinTypeError> {
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self._write(false)
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}
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#[inline]
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|
fn _set_high(&mut self) -> Result<(), InvalidPinTypeError> {
|
|
self._write(true)
|
|
}
|
|
|
|
/// Try to recreate a type-level [`Pin`] from a value-level [`DynPin`]
|
|
///
|
|
/// There is no way for the compiler to know if the conversion will be
|
|
/// successful at compile-time. We must verify the conversion at run-time
|
|
/// or refuse to perform it.
|
|
#[inline]
|
|
pub fn upgrade<I: PinId, M: PinMode>(self) -> Result<Pin<I, M>, InvalidPinTypeError> {
|
|
if self.regs.0 == I::DYN && self.mode == M::DYN {
|
|
// The `DynPin` is consumed, so it is safe to replace it with the
|
|
// corresponding `Pin`
|
|
return Ok(unsafe { Pin::new() });
|
|
}
|
|
Err(InvalidPinTypeError(self.mode))
|
|
}
|
|
|
|
/// Convert the pin into an async pin. The pin can be converted back by calling
|
|
/// [InputDynPinAsync::release]
|
|
pub fn into_async_input(
|
|
self,
|
|
irq: crate::pac::Interrupt,
|
|
) -> Result<InputDynPinAsync, InvalidPinTypeError> {
|
|
InputDynPinAsync::new(self, irq)
|
|
}
|
|
}
|
|
|
|
//==================================================================================================
|
|
// Convert between Pin and DynPin
|
|
//==================================================================================================
|
|
|
|
impl<I: PinId, M: PinMode> From<Pin<I, M>> for DynPin {
|
|
/// Erase the type-level information in a [`Pin`] and return a value-level
|
|
/// [`DynPin`]
|
|
#[inline]
|
|
fn from(pin: Pin<I, M>) -> Self {
|
|
pin.downgrade()
|
|
}
|
|
}
|
|
|
|
impl<I: PinId, M: PinMode> TryFrom<DynPin> for Pin<I, M> {
|
|
type Error = InvalidPinTypeError;
|
|
|
|
/// Try to recreate a type-level [`Pin`] from a value-level [`DynPin`]
|
|
///
|
|
/// There is no way for the compiler to know if the conversion will be
|
|
/// successful at compile-time. We must verify the conversion at run-time
|
|
/// or refuse to perform it.
|
|
#[inline]
|
|
fn try_from(pin: DynPin) -> Result<Self, Self::Error> {
|
|
pin.upgrade()
|
|
}
|
|
}
|
|
|
|
//==================================================================================================
|
|
// Embedded HAL traits
|
|
//==================================================================================================
|
|
|
|
impl embedded_hal::digital::ErrorType for DynPin {
|
|
type Error = InvalidPinTypeError;
|
|
}
|
|
|
|
impl embedded_hal::digital::OutputPin for DynPin {
|
|
#[inline]
|
|
fn set_high(&mut self) -> Result<(), Self::Error> {
|
|
self._set_high()
|
|
}
|
|
#[inline]
|
|
fn set_low(&mut self) -> Result<(), Self::Error> {
|
|
self._set_low()
|
|
}
|
|
}
|
|
|
|
impl embedded_hal::digital::InputPin for DynPin {
|
|
#[inline]
|
|
fn is_high(&mut self) -> Result<bool, Self::Error> {
|
|
self._is_high()
|
|
}
|
|
#[inline]
|
|
fn is_low(&mut self) -> Result<bool, Self::Error> {
|
|
self._is_low()
|
|
}
|
|
}
|
|
|
|
impl embedded_hal::digital::StatefulOutputPin for DynPin {
|
|
#[inline]
|
|
fn is_set_high(&mut self) -> Result<bool, Self::Error> {
|
|
self._is_high()
|
|
}
|
|
|
|
#[inline]
|
|
fn is_set_low(&mut self) -> Result<bool, Self::Error> {
|
|
self._is_low()
|
|
}
|
|
}
|