From d9784284a843f20f31b581ea2d5dd2ba79566ca6 Mon Sep 17 00:00:00 2001
From: Robin Mueller <robin.mueller.m@gmail.com>
Date: Sat, 6 Nov 2021 01:37:29 +0100
Subject: [PATCH 1/5] added crates IO badge

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index b1c9030..8bd0bb7 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
-
+[![Crates.io](https://img.shields.io/crates/v/va108xx)](https://crates.io/crates/va108xx)
 [![build](https://github.com/robamu-org/va108xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/robamu-org/va108xx-rs/actions/workflows/ci.yml)
 [![docs.rs](https://img.shields.io/docsrs/va108xx)](https://docs.rs/va108xx)
 

From 20ab6733d7d8e5a68b4ff58b72b78b48217d90fc Mon Sep 17 00:00:00 2001
From: Robin Mueller <robin.mueller.m@gmail.com>
Date: Mon, 8 Nov 2021 23:52:41 +0100
Subject: [PATCH 2/5] cross-compile now in CI

---
 .github/workflows/ci.yml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 8362357..5a9dad0 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -12,10 +12,13 @@ jobs:
         with:
           profile: minimal
           toolchain: stable
+          target: thumbv6m-none-eabi
           override: true
       - uses: actions-rs/cargo@v1
         with:
+          use-cross: true
           command: check
+          args: --target thumbv6m-none-eabi
 
   fmt:
     name: Rustfmt
@@ -42,12 +45,14 @@ jobs:
         with:
           profile: minimal
           toolchain: stable
+          target: thumbv6m-none-eabi
           override: true
       - run: rustup component add clippy
       - uses: actions-rs/cargo@v1
         with:
+          use-cross: true
           command: clippy
-          args: -- -D warnings
+          args: --target thumbv6m-none-eabi -- -D warnings
 
   ci:
       if: ${{ success() }}

From d37aad6b1c3a7c4bf6141c9761b7e3d279997499 Mon Sep 17 00:00:00 2001
From: Robin Mueller <robin.mueller.m@gmail.com>
Date: Tue, 9 Nov 2021 11:29:28 +0100
Subject: [PATCH 3/5] updated rust edition to 2021

---
 Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Cargo.toml b/Cargo.toml
index b273b85..23b0364 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -2,7 +2,7 @@
 name = "va108xx"
 version = "0.1.0"
 authors = ["Robin Mueller <robin.mueller.m@gmail.com>"]
-edition = "2018"
+edition = "2021"
 description = "PAC for the Vorago VA108xx family of microcontrollers"
 homepage = "https://github.com/robamu-org/va108xx-rs"
 repository = "https://github.com/robamu-org/va108xx-rs"

From 8c28367a33b12659df701057d001bb82ec9f2ea0 Mon Sep 17 00:00:00 2001
From: Robin Mueller <robin.mueller.m@gmail.com>
Date: Tue, 9 Nov 2021 18:11:56 +0100
Subject: [PATCH 4/5] Important fix: Use bitmask everywhere now

This PAC was generated using a patched version of svd2rust with
commit hash 43be074d21132c3a76780816010df592a3603874

It includes bugfix https://github.com/rust-embedded/svd2rust/pull/549
---
 CHANGELOG.md                           | 6 ++++++
 src/i2ca/clkscale.rs                   | 4 ++--
 src/i2ca/ctrl.rs                       | 4 ++--
 src/i2ca/fifo_clr.rs                   | 2 +-
 src/i2ca/irq_clr.rs                    | 2 +-
 src/i2ca/irq_enb.rs                    | 4 ++--
 src/i2ca/irq_end.rs                    | 2 +-
 src/i2ca/irq_raw.rs                    | 2 +-
 src/i2ca/s0_ctrl.rs                    | 4 ++--
 src/i2ca/s0_fifo_clr.rs                | 2 +-
 src/i2ca/s0_irq_clr.rs                 | 2 +-
 src/i2ca/s0_irq_enb.rs                 | 4 ++--
 src/i2ca/s0_irq_end.rs                 | 2 +-
 src/i2ca/s0_irq_raw.rs                 | 2 +-
 src/i2ca/s0_status.rs                  | 2 +-
 src/ioconfig/porta.rs                  | 4 ++--
 src/ioconfig/portb.rs                  | 4 ++--
 src/irqsel/edbgrq.rs                   | 2 +-
 src/irqsel/irqs.rs                     | 2 +-
 src/irqsel/mereset.rs                  | 2 +-
 src/irqsel/nmi.rs                      | 2 +-
 src/irqsel/rxev.rs                     | 2 +-
 src/irqsel/watchdog.rs                 | 2 +-
 src/lib.rs                             | 2 +-
 src/spia/ctrl0.rs                      | 4 ++--
 src/spia/ctrl1.rs                      | 4 ++--
 src/spia/fifo_clr.rs                   | 2 +-
 src/spia/irq_clr.rs                    | 2 +-
 src/spia/irq_enb.rs                    | 4 ++--
 src/spia/irq_end.rs                    | 2 +-
 src/spia/irq_raw.rs                    | 2 +-
 src/spia/status.rs                     | 2 +-
 src/sysconfig/irq_clr.rs               | 2 +-
 src/sysconfig/irq_enb.rs               | 4 ++--
 src/sysconfig/irq_end.rs               | 2 +-
 src/sysconfig/irq_raw.rs               | 2 +-
 src/sysconfig/lockup_reset.rs          | 4 ++--
 src/sysconfig/peripheral_clk_enable.rs | 4 ++--
 src/sysconfig/ram_scrub.rs             | 4 ++--
 src/sysconfig/ram_trap_synd.rs         | 4 ++--
 src/sysconfig/rom_prot.rs              | 4 ++--
 src/sysconfig/rom_scrub.rs             | 4 ++--
 src/sysconfig/rom_trap_synd.rs         | 4 ++--
 src/sysconfig/rst_cntl_ram.rs          | 4 ++--
 src/sysconfig/rst_cntl_rom.rs          | 4 ++--
 src/sysconfig/rst_stat.rs              | 4 ++--
 src/tim0/cascade0.rs                   | 4 ++--
 src/tim0/cascade1.rs                   | 4 ++--
 src/tim0/cascade2.rs                   | 4 ++--
 src/tim0/csd_ctrl.rs                   | 4 ++--
 src/tim0/ctrl.rs                       | 4 ++--
 src/tim0/enable.rs                     | 4 ++--
 src/uarta/clkscale.rs                  | 4 ++--
 src/uarta/ctrl.rs                      | 4 ++--
 src/uarta/enable.rs                    | 4 ++--
 src/uarta/fifo_clr.rs                  | 2 +-
 src/uarta/irq_clr.rs                   | 2 +-
 src/uarta/irq_enb.rs                   | 4 ++--
 src/uarta/irq_end.rs                   | 2 +-
 src/uarta/irq_raw.rs                   | 2 +-
 src/uarta/rxstatus.rs                  | 2 +-
 src/uarta/txstatus.rs                  | 2 +-
 62 files changed, 98 insertions(+), 92 deletions(-)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 3c282bd..51017b4 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -12,6 +12,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Relicensed under dual Apache-2.0 / MIT license
 
+### Fixed
+
+- Generated with patched version of `svd2rust`: See 
+  https://github.com/rust-embedded/svd2rust/pull/549 for more details.
+  Some bitmasks were missing from register reader definitions.
+
 ### Changed
 
 - SVD file handling improved and new fields added for the peripheral
diff --git a/src/i2ca/clkscale.rs b/src/i2ca/clkscale.rs
index 9ca7451..5b221e4 100644
--- a/src/i2ca/clkscale.rs
+++ b/src/i2ca/clkscale.rs
@@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x7fff_ffff) | (value as u32 & 0x7fff_ffff);
         self.w
     }
 }
@@ -102,7 +102,7 @@ impl R {
     #[doc = "Bits 0:30 - Enable FastMode"]
     #[inline(always)]
     pub fn value(&self) -> VALUE_R {
-        VALUE_R::new(self.bits as u32)
+        VALUE_R::new((self.bits & 0x7fff_ffff) as u32)
     }
     #[doc = "Bit 31 - Enable FastMode"]
     #[inline(always)]
diff --git a/src/i2ca/ctrl.rs b/src/i2ca/ctrl.rs
index 436694c..0c6cbb1 100644
--- a/src/i2ca/ctrl.rs
+++ b/src/i2ca/ctrl.rs
@@ -67,7 +67,7 @@ impl<'a> CLKENABLED_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -371,7 +371,7 @@ impl R {
     #[doc = "Bit 0 - I2C CLK Enabled"]
     #[inline(always)]
     pub fn clkenabled(&self) -> CLKENABLED_R {
-        CLKENABLED_R::new(self.bits != 0)
+        CLKENABLED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - I2C Activated"]
     #[inline(always)]
diff --git a/src/i2ca/fifo_clr.rs b/src/i2ca/fifo_clr.rs
index bb47c33..3d95fdd 100644
--- a/src/i2ca/fifo_clr.rs
+++ b/src/i2ca/fifo_clr.rs
@@ -37,7 +37,7 @@ impl<'a> RXFIFO_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
diff --git a/src/i2ca/irq_clr.rs b/src/i2ca/irq_clr.rs
index 7f58643..fad92d0 100644
--- a/src/i2ca/irq_clr.rs
+++ b/src/i2ca/irq_clr.rs
@@ -37,7 +37,7 @@ impl<'a> I2CIDLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
diff --git a/src/i2ca/irq_enb.rs b/src/i2ca/irq_enb.rs
index 71869da..eab46a4 100644
--- a/src/i2ca/irq_enb.rs
+++ b/src/i2ca/irq_enb.rs
@@ -67,7 +67,7 @@ impl<'a> I2CIDLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -556,7 +556,7 @@ impl R {
     #[doc = "Bit 0 - I2C Bus is Idle"]
     #[inline(always)]
     pub fn i2cidle(&self) -> I2CIDLE_R {
-        I2CIDLE_R::new(self.bits != 0)
+        I2CIDLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
diff --git a/src/i2ca/irq_end.rs b/src/i2ca/irq_end.rs
index 59f0056..6a0ac28 100644
--- a/src/i2ca/irq_end.rs
+++ b/src/i2ca/irq_end.rs
@@ -227,7 +227,7 @@ impl R {
     #[doc = "Bit 0 - I2C Bus is Idle"]
     #[inline(always)]
     pub fn i2cidle(&self) -> I2CIDLE_R {
-        I2CIDLE_R::new(self.bits != 0)
+        I2CIDLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
diff --git a/src/i2ca/irq_raw.rs b/src/i2ca/irq_raw.rs
index e953587..e164ea0 100644
--- a/src/i2ca/irq_raw.rs
+++ b/src/i2ca/irq_raw.rs
@@ -227,7 +227,7 @@ impl R {
     #[doc = "Bit 0 - I2C Bus is Idle"]
     #[inline(always)]
     pub fn i2cidle(&self) -> I2CIDLE_R {
-        I2CIDLE_R::new(self.bits != 0)
+        I2CIDLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
diff --git a/src/i2ca/s0_ctrl.rs b/src/i2ca/s0_ctrl.rs
index 0e326d2..9cb3965 100644
--- a/src/i2ca/s0_ctrl.rs
+++ b/src/i2ca/s0_ctrl.rs
@@ -67,7 +67,7 @@ impl<'a> CLKENABLED_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -223,7 +223,7 @@ impl R {
     #[doc = "Bit 0 - I2C Enabled"]
     #[inline(always)]
     pub fn clkenabled(&self) -> CLKENABLED_R {
-        CLKENABLED_R::new(self.bits != 0)
+        CLKENABLED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - I2C Activated"]
     #[inline(always)]
diff --git a/src/i2ca/s0_fifo_clr.rs b/src/i2ca/s0_fifo_clr.rs
index a224609..f9cc956 100644
--- a/src/i2ca/s0_fifo_clr.rs
+++ b/src/i2ca/s0_fifo_clr.rs
@@ -37,7 +37,7 @@ impl<'a> RXFIFO_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
diff --git a/src/i2ca/s0_irq_clr.rs b/src/i2ca/s0_irq_clr.rs
index 07e3c44..0024cd9 100644
--- a/src/i2ca/s0_irq_clr.rs
+++ b/src/i2ca/s0_irq_clr.rs
@@ -37,7 +37,7 @@ impl<'a> COMPLETED_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
diff --git a/src/i2ca/s0_irq_enb.rs b/src/i2ca/s0_irq_enb.rs
index 6291b6f..bd93ee9 100644
--- a/src/i2ca/s0_irq_enb.rs
+++ b/src/i2ca/s0_irq_enb.rs
@@ -67,7 +67,7 @@ impl<'a> COMPLETED_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -630,7 +630,7 @@ impl R {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
     pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
diff --git a/src/i2ca/s0_irq_end.rs b/src/i2ca/s0_irq_end.rs
index bbfd158..56d29fe 100644
--- a/src/i2ca/s0_irq_end.rs
+++ b/src/i2ca/s0_irq_end.rs
@@ -257,7 +257,7 @@ impl R {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
     pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
diff --git a/src/i2ca/s0_irq_raw.rs b/src/i2ca/s0_irq_raw.rs
index 9279c3d..601b3b1 100644
--- a/src/i2ca/s0_irq_raw.rs
+++ b/src/i2ca/s0_irq_raw.rs
@@ -257,7 +257,7 @@ impl R {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
     pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
diff --git a/src/i2ca/s0_status.rs b/src/i2ca/s0_status.rs
index fe08adf..9324f04 100644
--- a/src/i2ca/s0_status.rs
+++ b/src/i2ca/s0_status.rs
@@ -272,7 +272,7 @@ impl R {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
     pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]
diff --git a/src/ioconfig/porta.rs b/src/ioconfig/porta.rs
index 36e2ca1..13d1444 100644
--- a/src/ioconfig/porta.rs
+++ b/src/ioconfig/porta.rs
@@ -158,7 +158,7 @@ impl<'a> FLTTYPE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
         self.w
     }
 }
@@ -516,7 +516,7 @@ impl R {
     #[doc = "Bits 0:2 - Input Filter Selectoin"]
     #[inline(always)]
     pub fn flttype(&self) -> FLTTYPE_R {
-        FLTTYPE_R::new(self.bits as u8)
+        FLTTYPE_R::new((self.bits & 0x07) as u8)
     }
     #[doc = "Bits 3:5 - Input Filter Clock Selection"]
     #[inline(always)]
diff --git a/src/ioconfig/portb.rs b/src/ioconfig/portb.rs
index a712260..7dc1a05 100644
--- a/src/ioconfig/portb.rs
+++ b/src/ioconfig/portb.rs
@@ -158,7 +158,7 @@ impl<'a> FLTTYPE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
         self.w
     }
 }
@@ -516,7 +516,7 @@ impl R {
     #[doc = "Bits 0:2 - Input Filter Selectoin"]
     #[inline(always)]
     pub fn flttype(&self) -> FLTTYPE_R {
-        FLTTYPE_R::new(self.bits as u8)
+        FLTTYPE_R::new((self.bits & 0x07) as u8)
     }
     #[doc = "Bits 3:5 - Input Filter Clock Selection"]
     #[inline(always)]
diff --git a/src/irqsel/edbgrq.rs b/src/irqsel/edbgrq.rs
index 632d784..9f25404 100644
--- a/src/irqsel/edbgrq.rs
+++ b/src/irqsel/edbgrq.rs
@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "EDBGRQ Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [edbgrq](index.html) module"]
diff --git a/src/irqsel/irqs.rs b/src/irqsel/irqs.rs
index fff2422..bce8e72 100644
--- a/src/irqsel/irqs.rs
+++ b/src/irqsel/irqs.rs
@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irqs](index.html) module"]
diff --git a/src/irqsel/mereset.rs b/src/irqsel/mereset.rs
index 631df61..6a07356 100644
--- a/src/irqsel/mereset.rs
+++ b/src/irqsel/mereset.rs
@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "MERESET Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mereset](index.html) module"]
diff --git a/src/irqsel/nmi.rs b/src/irqsel/nmi.rs
index 486bf39..e9bcbb0 100644
--- a/src/irqsel/nmi.rs
+++ b/src/irqsel/nmi.rs
@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "NMI Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmi](index.html) module"]
diff --git a/src/irqsel/rxev.rs b/src/irqsel/rxev.rs
index 831276d..9829290 100644
--- a/src/irqsel/rxev.rs
+++ b/src/irqsel/rxev.rs
@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "RXEV Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxev](index.html) module"]
diff --git a/src/irqsel/watchdog.rs b/src/irqsel/watchdog.rs
index 074dbf3..4510f29 100644
--- a/src/irqsel/watchdog.rs
+++ b/src/irqsel/watchdog.rs
@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "WATCHDOG Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [watchdog](index.html) module"]
diff --git a/src/lib.rs b/src/lib.rs
index 1483a16..8b837c9 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (58c0bb6 2021-11-02))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
+#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (43be074 2021-11-09))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
 svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![deny(const_err)]
 #![deny(dead_code)]
diff --git a/src/spia/ctrl0.rs b/src/spia/ctrl0.rs
index 3df7089..143e388 100644
--- a/src/spia/ctrl0.rs
+++ b/src/spia/ctrl0.rs
@@ -57,7 +57,7 @@ impl<'a> SIZE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
         self.w
     }
 }
@@ -166,7 +166,7 @@ impl R {
     #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
     #[inline(always)]
     pub fn size(&self) -> SIZE_R {
-        SIZE_R::new(self.bits as u8)
+        SIZE_R::new((self.bits & 0x0f) as u8)
     }
     #[doc = "Bit 6 - SPI Clock Polarity"]
     #[inline(always)]
diff --git a/src/spia/ctrl1.rs b/src/spia/ctrl1.rs
index e987556..fca0c46 100644
--- a/src/spia/ctrl1.rs
+++ b/src/spia/ctrl1.rs
@@ -67,7 +67,7 @@ impl<'a> LBM_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -398,7 +398,7 @@ impl R {
     #[doc = "Bit 0 - Loop Back"]
     #[inline(always)]
     pub fn lbm(&self) -> LBM_R {
-        LBM_R::new(self.bits != 0)
+        LBM_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Enable"]
     #[inline(always)]
diff --git a/src/spia/fifo_clr.rs b/src/spia/fifo_clr.rs
index bb47c33..3d95fdd 100644
--- a/src/spia/fifo_clr.rs
+++ b/src/spia/fifo_clr.rs
@@ -37,7 +37,7 @@ impl<'a> RXFIFO_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
diff --git a/src/spia/irq_clr.rs b/src/spia/irq_clr.rs
index 3126d39..14ca32b 100644
--- a/src/spia/irq_clr.rs
+++ b/src/spia/irq_clr.rs
@@ -37,7 +37,7 @@ impl<'a> RORIM_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
diff --git a/src/spia/irq_enb.rs b/src/spia/irq_enb.rs
index 724b53c..ebe47c6 100644
--- a/src/spia/irq_enb.rs
+++ b/src/spia/irq_enb.rs
@@ -67,7 +67,7 @@ impl<'a> RORIM_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -186,7 +186,7 @@ impl R {
     #[doc = "Bit 0 - RX Overrun"]
     #[inline(always)]
     pub fn rorim(&self) -> RORIM_R {
-        RORIM_R::new(self.bits != 0)
+        RORIM_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Timeout"]
     #[inline(always)]
diff --git a/src/spia/irq_end.rs b/src/spia/irq_end.rs
index 9213a93..22b34dc 100644
--- a/src/spia/irq_end.rs
+++ b/src/spia/irq_end.rs
@@ -77,7 +77,7 @@ impl R {
     #[doc = "Bit 0 - RX Overrun"]
     #[inline(always)]
     pub fn rorim(&self) -> RORIM_R {
-        RORIM_R::new(self.bits != 0)
+        RORIM_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Timeout"]
     #[inline(always)]
diff --git a/src/spia/irq_raw.rs b/src/spia/irq_raw.rs
index 5647cf2..bc608c7 100644
--- a/src/spia/irq_raw.rs
+++ b/src/spia/irq_raw.rs
@@ -77,7 +77,7 @@ impl R {
     #[doc = "Bit 0 - RX Overrun"]
     #[inline(always)]
     pub fn rorim(&self) -> RORIM_R {
-        RORIM_R::new(self.bits != 0)
+        RORIM_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Timeout"]
     #[inline(always)]
diff --git a/src/spia/status.rs b/src/spia/status.rs
index d82ce22..916b025 100644
--- a/src/spia/status.rs
+++ b/src/spia/status.rs
@@ -137,7 +137,7 @@ impl R {
     #[doc = "Bit 0 - Transmit FIFO empty"]
     #[inline(always)]
     pub fn tfe(&self) -> TFE_R {
-        TFE_R::new(self.bits != 0)
+        TFE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Transmit FIFO not full"]
     #[inline(always)]
diff --git a/src/sysconfig/irq_clr.rs b/src/sysconfig/irq_clr.rs
index b0b643b..974a8c1 100644
--- a/src/sysconfig/irq_clr.rs
+++ b/src/sysconfig/irq_clr.rs
@@ -37,7 +37,7 @@ impl<'a> RAMSBE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
diff --git a/src/sysconfig/irq_enb.rs b/src/sysconfig/irq_enb.rs
index 6512dbd..f100096 100644
--- a/src/sysconfig/irq_enb.rs
+++ b/src/sysconfig/irq_enb.rs
@@ -67,7 +67,7 @@ impl<'a> RAMSBE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -186,7 +186,7 @@ impl R {
     #[doc = "Bit 0 - RAM Single Bit Interrupt"]
     #[inline(always)]
     pub fn ramsbe(&self) -> RAMSBE_R {
-        RAMSBE_R::new(self.bits != 0)
+        RAMSBE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
     #[inline(always)]
diff --git a/src/sysconfig/irq_end.rs b/src/sysconfig/irq_end.rs
index 45825ea..b25f553 100644
--- a/src/sysconfig/irq_end.rs
+++ b/src/sysconfig/irq_end.rs
@@ -77,7 +77,7 @@ impl R {
     #[doc = "Bit 0 - RAM Single Bit Interrupt"]
     #[inline(always)]
     pub fn ramsbe(&self) -> RAMSBE_R {
-        RAMSBE_R::new(self.bits != 0)
+        RAMSBE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
     #[inline(always)]
diff --git a/src/sysconfig/irq_raw.rs b/src/sysconfig/irq_raw.rs
index 0f04bfb..84498a4 100644
--- a/src/sysconfig/irq_raw.rs
+++ b/src/sysconfig/irq_raw.rs
@@ -77,7 +77,7 @@ impl R {
     #[doc = "Bit 0 - RAM Single Bit Interrupt"]
     #[inline(always)]
     pub fn ramsbe(&self) -> RAMSBE_R {
-        RAMSBE_R::new(self.bits != 0)
+        RAMSBE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
     #[inline(always)]
diff --git a/src/sysconfig/lockup_reset.rs b/src/sysconfig/lockup_reset.rs
index 78fb1d9..e714a27 100644
--- a/src/sysconfig/lockup_reset.rs
+++ b/src/sysconfig/lockup_reset.rs
@@ -67,7 +67,7 @@ impl<'a> LREN_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -75,7 +75,7 @@ impl R {
     #[doc = "Bit 0 - Lockup Reset Enable Bit"]
     #[inline(always)]
     pub fn lren(&self) -> LREN_R {
-        LREN_R::new(self.bits != 0)
+        LREN_R::new((self.bits & 0x01) != 0)
     }
 }
 impl W {
diff --git a/src/sysconfig/peripheral_clk_enable.rs b/src/sysconfig/peripheral_clk_enable.rs
index 70d3ef7..edef104 100644
--- a/src/sysconfig/peripheral_clk_enable.rs
+++ b/src/sysconfig/peripheral_clk_enable.rs
@@ -67,7 +67,7 @@ impl<'a> PORTA_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -533,7 +533,7 @@ impl R {
     #[doc = "Bit 0 - Enable PORTA clock"]
     #[inline(always)]
     pub fn porta(&self) -> PORTA_R {
-        PORTA_R::new(self.bits != 0)
+        PORTA_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Enable PORTB clock"]
     #[inline(always)]
diff --git a/src/sysconfig/ram_scrub.rs b/src/sysconfig/ram_scrub.rs
index 69558df..de2aa4e 100644
--- a/src/sysconfig/ram_scrub.rs
+++ b/src/sysconfig/ram_scrub.rs
@@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
         self.w
     }
 }
@@ -87,7 +87,7 @@ impl R {
     #[doc = "Bits 0:23 - Counter divide value"]
     #[inline(always)]
     pub fn value(&self) -> VALUE_R {
-        VALUE_R::new(self.bits as u32)
+        VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
     }
 }
 impl W {
diff --git a/src/sysconfig/ram_trap_synd.rs b/src/sysconfig/ram_trap_synd.rs
index d19b6ca..1a30ccf 100644
--- a/src/sysconfig/ram_trap_synd.rs
+++ b/src/sysconfig/ram_trap_synd.rs
@@ -57,7 +57,7 @@ impl<'a> SYND_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x000f_ffff) | (value as u32 & 0x000f_ffff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:19 - Trap Syndrom Bits"]
     #[inline(always)]
     pub fn synd(&self) -> SYND_R {
-        SYND_R::new(self.bits as u32)
+        SYND_R::new((self.bits & 0x000f_ffff) as u32)
     }
 }
 impl W {
diff --git a/src/sysconfig/rom_prot.rs b/src/sysconfig/rom_prot.rs
index 5f9399b..2f20c63 100644
--- a/src/sysconfig/rom_prot.rs
+++ b/src/sysconfig/rom_prot.rs
@@ -67,7 +67,7 @@ impl<'a> WREN_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -75,7 +75,7 @@ impl R {
     #[doc = "Bit 0 - ROM Write Enable Bit"]
     #[inline(always)]
     pub fn wren(&self) -> WREN_R {
-        WREN_R::new(self.bits != 0)
+        WREN_R::new((self.bits & 0x01) != 0)
     }
 }
 impl W {
diff --git a/src/sysconfig/rom_scrub.rs b/src/sysconfig/rom_scrub.rs
index 8085a4c..ba17dbb 100644
--- a/src/sysconfig/rom_scrub.rs
+++ b/src/sysconfig/rom_scrub.rs
@@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
         self.w
     }
 }
@@ -87,7 +87,7 @@ impl R {
     #[doc = "Bits 0:23 - Counter divide value"]
     #[inline(always)]
     pub fn value(&self) -> VALUE_R {
-        VALUE_R::new(self.bits as u32)
+        VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
     }
 }
 impl W {
diff --git a/src/sysconfig/rom_trap_synd.rs b/src/sysconfig/rom_trap_synd.rs
index 00bd9b2..b2ed1f6 100644
--- a/src/sysconfig/rom_trap_synd.rs
+++ b/src/sysconfig/rom_trap_synd.rs
@@ -57,7 +57,7 @@ impl<'a> SYND_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x000f_ffff) | (value as u32 & 0x000f_ffff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:19 - Trap Syndrom Bits"]
     #[inline(always)]
     pub fn synd(&self) -> SYND_R {
-        SYND_R::new(self.bits as u32)
+        SYND_R::new((self.bits & 0x000f_ffff) as u32)
     }
 }
 impl W {
diff --git a/src/sysconfig/rst_cntl_ram.rs b/src/sysconfig/rst_cntl_ram.rs
index ba0e8f1..e11112f 100644
--- a/src/sysconfig/rst_cntl_ram.rs
+++ b/src/sysconfig/rst_cntl_ram.rs
@@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -260,7 +260,7 @@ impl R {
     #[doc = "Bit 0 - Power On Reset Status"]
     #[inline(always)]
     pub fn por(&self) -> POR_R {
-        POR_R::new(self.bits != 0)
+        POR_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - External Reset Status"]
     #[inline(always)]
diff --git a/src/sysconfig/rst_cntl_rom.rs b/src/sysconfig/rst_cntl_rom.rs
index aaeafca..de2b996 100644
--- a/src/sysconfig/rst_cntl_rom.rs
+++ b/src/sysconfig/rst_cntl_rom.rs
@@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -260,7 +260,7 @@ impl R {
     #[doc = "Bit 0 - Power On Reset Status"]
     #[inline(always)]
     pub fn por(&self) -> POR_R {
-        POR_R::new(self.bits != 0)
+        POR_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - External Reset Status"]
     #[inline(always)]
diff --git a/src/sysconfig/rst_stat.rs b/src/sysconfig/rst_stat.rs
index 7cb7867..4352754 100644
--- a/src/sysconfig/rst_stat.rs
+++ b/src/sysconfig/rst_stat.rs
@@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -260,7 +260,7 @@ impl R {
     #[doc = "Bit 0 - Power On Reset Status"]
     #[inline(always)]
     pub fn por(&self) -> POR_R {
-        POR_R::new(self.bits != 0)
+        POR_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - External Reset Status"]
     #[inline(always)]
diff --git a/src/tim0/cascade0.rs b/src/tim0/cascade0.rs
index 42bfd26..b3a8955 100644
--- a/src/tim0/cascade0.rs
+++ b/src/tim0/cascade0.rs
@@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:7 - Cascade Selection"]
     #[inline(always)]
     pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
     }
 }
 impl W {
diff --git a/src/tim0/cascade1.rs b/src/tim0/cascade1.rs
index ab69f94..6a962c0 100644
--- a/src/tim0/cascade1.rs
+++ b/src/tim0/cascade1.rs
@@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:7 - Cascade Selection"]
     #[inline(always)]
     pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
     }
 }
 impl W {
diff --git a/src/tim0/cascade2.rs b/src/tim0/cascade2.rs
index 6800103..905d693 100644
--- a/src/tim0/cascade2.rs
+++ b/src/tim0/cascade2.rs
@@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:7 - Cascade Selection"]
     #[inline(always)]
     pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
     }
 }
 impl W {
diff --git a/src/tim0/csd_ctrl.rs b/src/tim0/csd_ctrl.rs
index 40f1d15..5d3c665 100644
--- a/src/tim0/csd_ctrl.rs
+++ b/src/tim0/csd_ctrl.rs
@@ -67,7 +67,7 @@ impl<'a> CSDEN0_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -408,7 +408,7 @@ impl R {
     #[doc = "Bit 0 - Cascade 0 Enable"]
     #[inline(always)]
     pub fn csden0(&self) -> CSDEN0_R {
-        CSDEN0_R::new(self.bits != 0)
+        CSDEN0_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Cascade 0 Invert"]
     #[inline(always)]
diff --git a/src/tim0/ctrl.rs b/src/tim0/ctrl.rs
index c542692..1d7f569 100644
--- a/src/tim0/ctrl.rs
+++ b/src/tim0/ctrl.rs
@@ -67,7 +67,7 @@ impl<'a> ENABLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -416,7 +416,7 @@ impl R {
     #[doc = "Bit 0 - Counter Enable"]
     #[inline(always)]
     pub fn enable(&self) -> ENABLE_R {
-        ENABLE_R::new(self.bits != 0)
+        ENABLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Counter Active"]
     #[inline(always)]
diff --git a/src/tim0/enable.rs b/src/tim0/enable.rs
index 4cb0670..90b8636 100644
--- a/src/tim0/enable.rs
+++ b/src/tim0/enable.rs
@@ -67,7 +67,7 @@ impl<'a> ENABLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -75,7 +75,7 @@ impl R {
     #[doc = "Bit 0 - Counter Enable"]
     #[inline(always)]
     pub fn enable(&self) -> ENABLE_R {
-        ENABLE_R::new(self.bits != 0)
+        ENABLE_R::new((self.bits & 0x01) != 0)
     }
 }
 impl W {
diff --git a/src/uarta/clkscale.rs b/src/uarta/clkscale.rs
index 2198f41..40fa684 100644
--- a/src/uarta/clkscale.rs
+++ b/src/uarta/clkscale.rs
@@ -57,7 +57,7 @@ impl<'a> FRAC_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f);
         self.w
     }
 }
@@ -114,7 +114,7 @@ impl R {
     #[doc = "Bits 0:5 - Fractional Divide (64ths)"]
     #[inline(always)]
     pub fn frac(&self) -> FRAC_R {
-        FRAC_R::new(self.bits as u8)
+        FRAC_R::new((self.bits & 0x3f) as u8)
     }
     #[doc = "Bits 6:23 - Integer Divide"]
     #[inline(always)]
diff --git a/src/uarta/ctrl.rs b/src/uarta/ctrl.rs
index d013682..f5663f9 100644
--- a/src/uarta/ctrl.rs
+++ b/src/uarta/ctrl.rs
@@ -67,7 +67,7 @@ impl<'a> PAREN_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -435,7 +435,7 @@ impl R {
     #[doc = "Bit 0 - Parity Enable"]
     #[inline(always)]
     pub fn paren(&self) -> PAREN_R {
-        PAREN_R::new(self.bits != 0)
+        PAREN_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Parity Even/Odd(1/0)"]
     #[inline(always)]
diff --git a/src/uarta/enable.rs b/src/uarta/enable.rs
index 3f47815..5584706 100644
--- a/src/uarta/enable.rs
+++ b/src/uarta/enable.rs
@@ -67,7 +67,7 @@ impl<'a> RXENABLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -112,7 +112,7 @@ impl R {
     #[doc = "Bit 0 - Rx Enable"]
     #[inline(always)]
     pub fn rxenable(&self) -> RXENABLE_R {
-        RXENABLE_R::new(self.bits != 0)
+        RXENABLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Tx Enable"]
     #[inline(always)]
diff --git a/src/uarta/fifo_clr.rs b/src/uarta/fifo_clr.rs
index 1dc692f..8729ac9 100644
--- a/src/uarta/fifo_clr.rs
+++ b/src/uarta/fifo_clr.rs
@@ -37,7 +37,7 @@ impl<'a> RXSTS_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
diff --git a/src/uarta/irq_clr.rs b/src/uarta/irq_clr.rs
index c0ad3ff..451b609 100644
--- a/src/uarta/irq_clr.rs
+++ b/src/uarta/irq_clr.rs
@@ -37,7 +37,7 @@ impl<'a> IRQ_RX_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
diff --git a/src/uarta/irq_enb.rs b/src/uarta/irq_enb.rs
index 8666902..93f50e1 100644
--- a/src/uarta/irq_enb.rs
+++ b/src/uarta/irq_enb.rs
@@ -67,7 +67,7 @@ impl<'a> IRQ_RX_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -297,7 +297,7 @@ impl R {
     #[doc = "Bit 0 - RX Interrupt"]
     #[inline(always)]
     pub fn irq_rx(&self) -> IRQ_RX_R {
-        IRQ_RX_R::new(self.bits != 0)
+        IRQ_RX_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Status Interrupt"]
     #[inline(always)]
diff --git a/src/uarta/irq_end.rs b/src/uarta/irq_end.rs
index 3154193..b2eb6c8 100644
--- a/src/uarta/irq_end.rs
+++ b/src/uarta/irq_end.rs
@@ -122,7 +122,7 @@ impl R {
     #[doc = "Bit 0 - RX Interrupt"]
     #[inline(always)]
     pub fn irq_rx(&self) -> IRQ_RX_R {
-        IRQ_RX_R::new(self.bits != 0)
+        IRQ_RX_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Status Interrupt"]
     #[inline(always)]
diff --git a/src/uarta/irq_raw.rs b/src/uarta/irq_raw.rs
index 7c5a64f..ba40050 100644
--- a/src/uarta/irq_raw.rs
+++ b/src/uarta/irq_raw.rs
@@ -122,7 +122,7 @@ impl R {
     #[doc = "Bit 0 - RX Interrupt"]
     #[inline(always)]
     pub fn irq_rx(&self) -> IRQ_RX_R {
-        IRQ_RX_R::new(self.bits != 0)
+        IRQ_RX_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Status Interrupt"]
     #[inline(always)]
diff --git a/src/uarta/rxstatus.rs b/src/uarta/rxstatus.rs
index 75ba388..779d361 100644
--- a/src/uarta/rxstatus.rs
+++ b/src/uarta/rxstatus.rs
@@ -182,7 +182,7 @@ impl R {
     #[doc = "Bit 0 - Read Data Available"]
     #[inline(always)]
     pub fn rdavl(&self) -> RDAVL_R {
-        RDAVL_R::new(self.bits != 0)
+        RDAVL_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Read Fifo NOT Full"]
     #[inline(always)]
diff --git a/src/uarta/txstatus.rs b/src/uarta/txstatus.rs
index 7ee9615..e96e737 100644
--- a/src/uarta/txstatus.rs
+++ b/src/uarta/txstatus.rs
@@ -92,7 +92,7 @@ impl R {
     #[doc = "Bit 0 - Write Fifo NOT Full"]
     #[inline(always)]
     pub fn wrrdy(&self) -> WRRDY_R {
-        WRRDY_R::new(self.bits != 0)
+        WRRDY_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Write Fifo Full"]
     #[inline(always)]

From 25d0ec677adc40d9ef58d1467ff2c778bfb74470 Mon Sep 17 00:00:00 2001
From: Robin Mueller <robin.mueller.m@gmail.com>
Date: Tue, 9 Nov 2021 18:16:08 +0100
Subject: [PATCH 5/5] bumped revision for bugfix

---
 Cargo.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Cargo.toml b/Cargo.toml
index 23b0364..a6fb322 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "va108xx"
-version = "0.1.0"
+version = "0.1.1"
 authors = ["Robin Mueller <robin.mueller.m@gmail.com>"]
 edition = "2021"
 description = "PAC for the Vorago VA108xx family of microcontrollers"