From cba43bc22172553582e95c302be2cd266ddfc8ab Mon Sep 17 00:00:00 2001
From: Robin Mueller <muellerr@irs.uni-stuttgart.de>
Date: Mon, 6 Dec 2021 00:03:28 +0100
Subject: [PATCH] added missing cascade field

---
 src/tim0/csd_ctrl.rs         | 47 ++++++++++++++++++++++++++++++++++++
 svd/va108xx-base.svd.patched |  3 ++-
 svd/va108xx-patch.yml        |  9 +++++++
 3 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/src/tim0/csd_ctrl.rs b/src/tim0/csd_ctrl.rs
index 5d3c665..d09433c 100644
--- a/src/tim0/csd_ctrl.rs
+++ b/src/tim0/csd_ctrl.rs
@@ -404,6 +404,43 @@ impl<'a> CSDXXX2_W<'a> {
         self.w
     }
 }
+#[doc = "Field `CSDTRG2` reader - Cascade 2 Enabled as Trigger"]
+pub struct CSDTRG2_R(crate::FieldReader<bool, bool>);
+impl CSDTRG2_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CSDTRG2_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CSDTRG2_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CSDTRG2` writer - Cascade 2 Enabled as Trigger"]
+pub struct CSDTRG2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CSDTRG2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
+        self.w
+    }
+}
 impl R {
     #[doc = "Bit 0 - Cascade 0 Enable"]
     #[inline(always)]
@@ -455,6 +492,11 @@ impl R {
     pub fn csdxxx2(&self) -> CSDXXX2_R {
         CSDXXX2_R::new(((self.bits >> 11) & 0x01) != 0)
     }
+    #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
+    #[inline(always)]
+    pub fn csdtrg2(&self) -> CSDTRG2_R {
+        CSDTRG2_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
 }
 impl W {
     #[doc = "Bit 0 - Cascade 0 Enable"]
@@ -507,6 +549,11 @@ impl W {
     pub fn csdxxx2(&mut self) -> CSDXXX2_W {
         CSDXXX2_W { w: self }
     }
+    #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
+    #[inline(always)]
+    pub fn csdtrg2(&mut self) -> CSDTRG2_W {
+        CSDTRG2_W { w: self }
+    }
     #[doc = "Writes raw bits to the register."]
     #[inline(always)]
     pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
diff --git a/svd/va108xx-base.svd.patched b/svd/va108xx-base.svd.patched
index 969f177..31e3ecd 100644
--- a/svd/va108xx-base.svd.patched
+++ b/svd/va108xx-base.svd.patched
@@ -1296,7 +1296,8 @@
               <description>Cascade 2 test  mode</description>
               <bitRange>[11:11]</bitRange>
             </field>
-          </fields>
+          <field><name>CSDTRG2</name><description>Cascade 2 Enabled as Trigger</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field>
+            </fields>
         </register>
         <register>
           <name>CASCADE0</name>
diff --git a/svd/va108xx-patch.yml b/svd/va108xx-patch.yml
index 6bd4d0c..cafcacb 100644
--- a/svd/va108xx-patch.yml
+++ b/svd/va108xx-patch.yml
@@ -126,3 +126,12 @@ I2CA:
         description: Controller is Idle
         bitOffset: 1
         bitWidth: 1
+
+# All TIMs are derived from TIM0
+TIM0:
+  CSD_CTRL:
+    _add:
+      CSDTRG2:
+        description: Cascade 2 Enabled as Trigger
+        bitOffset: 10
+        bitWidth: 1
-- 
2.43.0