VORAGO TECHNOLOGIES SST va108xx M0 1.1 ARM 32-bit Cortex-M0 Microcontroller based device, CPU clock up to 50MHz VORAGO Technologies \n \n ----------------------------------------------------------------------------\n Copyright (c) 2013-2016 VORAGO Technologies\n \n BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND BY ALL THE TERMS\n AND CONDITIONS OF THE VORAGO TECHNOLOGIES END USER LICENSE AGREEMENT. \n \n THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n VORAGO TECHNOLOGIES SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE\n FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n CM0 r0p0 little false false 2 false system_VA108xx VOR_ 83232 read-write0x000000000xFFFFFFFF SYSCONFIG 1.0 System Configuration Peripheral 0x40000000 0 0x00001000 registers RST_STAT System Reset Status 0x000 read-write 0x00000001 POR Power On Reset Status [0:0] EXTRST External Reset Status [1:1] SYSRSTREQ SYSRESETREQ Reset Status [2:2] LOOKUP LOOKUP Reset Status [3:3] WATCHDOG WATCHDOG Reset Status [4:4] MEMERR Memory Error Reset Status [5:5] RST_CNTL_ROM ROM Reset Control 0x004 0x0000001F RST_CNTL_RAM RAM Reset Control 0x008 0x0000001F ROM_PROT ROM Protection Configuration 0x00C 0x00000001 WREN ROM Write Enable Bit [0:0] ROM_SCRUB ROM Scrub Period Configuration 0x010 read-write 0x00000000 VALUE Counter divide value [23:0] RESET Reset Counter [31:31] write-only oneToClear RAM_SCRUB RAM Scrub Period Configuration 0x014 ROM_TRAP_ADDR ROM Trap Address 0x018 0x00000000 ADDR Trap Address Match Bits [15:2] ENABLE Trap Enable Bit [31:31] ROM_TRAP_SYND ROM Trap Syndrome 0x01C 0x00000000 SYND Trap Syndrom Bits [19:0] RAM_TRAP_ADDR RAM Trap Address 0x020 RAM_TRAP_SYND RAM Trap Syndrome 0x024 IRQ_ENB Enable EDAC Error Interrupt Register 0x028 read-write 0x00000000 RAMSBE RAM Single Bit Interrupt [0:0] RAMMBE RAM Multi Bit Interrupt [1:1] ROMSBE ROM Single Bit Interrupt [2:2] ROMMBE ROM Multi Bit Interrupt [3:3] IRQ_RAW Raw EDAC Error Interrupt Status 0x02C read-only 0x00000000 IRQ_END Enabled EDAC Error Interrupt Status 0x030 read-only 0x00000000 IRQ_CLR Clear EDAC Error Interrupt Status 0x034 write-only 0x00000000 oneToClear RAM_SBE Count of RAM EDAC Single Bit Errors 0x038 0x00000000 RAM_MBE Count of RAM EDAC Multi Bit Errors 0x03C ROM_SBE Count of ROM EDAC Single Bit Errors 0x040 ROM_MBE Count of ROM EDAC Multi Bit Errors 0x044 IOCONFIG_CLKDIV0 IO Configuration Clock Divider Register 0x048 read-only 0x00000000 7 4 1-7 IOCONFIG_CLKDIV%s IO Configuration Clock Divider Register 0x04C 0x00000000 ROM_RETRIES ROM BOOT Retry count 0x068 read-only 0x00000000 REFRESH_CONFIG Register Refresh Control 0x06C 0x00000000 TIM_RESET TIM Reset Control 0x070 0xFFFFFFFF TIM_CLK_ENABLE TIM Enable Control 0x074 0x00000000 PERIPHERAL_RESET Peripheral Reset Control 0x078 0xFFFFFFFF PERIPHERAL_CLK_ENABLE Peripheral Enable Control 0x07C 0x00000000 PORTAEnable PORTA clock01 PORTBEnable PORTB clock11 SPI_0Enable SPI[0] clock41 SPI_1Enable SPI[1] clock51 SPI_2Enable SPI[2] clock61 UART_0Enable UART[0] clock81 UART_1Enable UART[1] clock91 I2C_0Enable I2C[0] clock161 I2C_1Enable I2C[1] clock171 IRQSELEnable IRQ selector clock211 IOCONFIGEnable IO Configuration block clock221 UTILITYEnable utility clock231 GPIOEnable GPIO clock241 LOCKUP_RESET Lockup Reset Configuration 0x080 0x00000001 LREN Lockup Reset Enable Bit [0:0] EF_CONFIG EFuse Config Register 0xff0 read-only 0x00000000 EF_ID EFuse ID Register 0xff4 read-only 0x00000000 PROCID Processor ID Register 0xff8 read-only 0x040017e3 PERID Peripheral ID Register 0xffc read-only 0x008007e1 IRQSEL 1.0 Interrupt Selector Peripheral 0x40001000 0 0x00001000 registers OC0 0 OC1 1 OC2 2 OC3 3 OC4 4 OC5 5 OC6 6 OC7 7 OC8 8 OC9 9 OC10 10 OC11 11 OC12 12 OC13 13 OC14 14 OC15 15 OC16 16 OC17 17 OC18 18 OC19 19 OC20 20 OC21 21 OC22 22 OC23 23 OC24 24 OC25 25 OC26 26 OC27 27 OC28 28 OC29 29 OC30 30 OC31 31 INT_RAM_SBE Internal Memory RAM SBE Interrupt Redirect Selection 0x01C0 read-write 0xFFFFFFFF 32 4 PORTA[%s] PORTA Interrupt Redirect Selection 0x000 32 4 PORTB[%s] PORTB Interrupt Redirect Selection 0x080 32 4 TIM[%s] TIM Interrupt Redirect Selection 0x100 4 4 UART[%s] UART Interrupt Redirect Selection 0x180 4 4 SPI[%s] SPI Interrupt Redirect Selection 0x190 4 4 I2C_MS[%s] Master I2C Interrupt Redirect Selection 0x01a0 4 4 I2C_SL[%s] Slave I2C Interrupt Redirect Selection 0x01B0 INT_RAM_MBE Internal Memory RAM MBE Interrupt Redirect Selection 0x01C4 INT_ROM_SBE Internal Memory ROM SBE Interrupt Redirect Selection 0x01C8 INT_ROM_MBE Internal Memory ROM MBE Interrupt Redirect Selection 0x01CC TXEV Processor TXEV Interrupt Redirect Selection 0x01D0 NMI NMI Status Register 0x8f8 read-only 0x00000000 ACTIVE Active [0:0] RXEV RXEV Status Register 0x8f4 WATCHDOG WATCHDOG Status Register 0x8f0 MERESET MERESET Status Register 0x8ec EDBGRQ EDBGRQ Status Register 0x8e8 32 4 IRQS[%s] Interrupt Status Register 0x800 PERID Peripheral ID Register 0xffc 32 read-only 0x008007e1 IOCONFIG 1.0 IO Pin Configuration Peripheral 0x40002000 0 0x00001000 registers 32 4 PORTA[%s] PORTA Pin Configuration Register 0x000 0x00000000 FLTTYPE Input Filter Selectoin [2:0] SYNC Synchronize to system clock 0 DIRECT Direct input, no synchronization 1 FILTER1 Require 2 samples to have the same value 2 FILTER2 Require 3 samples to have the same value 3 FILTER3 Require 4 samples to have the same value 4 FILTER4 Require 5 samples to have the same value 5 FLTCLK Input Filter Clock Selection [5:3] INVINP Input Invert Selection [6:6] IEWO Input Enable While Output enabled [7:7] OPENDRN Output Open Drain Mode [8:8] INVOUT Output Invert Selection [9:9] PLEVEL Internal Pull up/down level [10:10] PEN Enable Internal Pull up/down [11:11] PWOA Enable Pull when output active [12:12] FUNSEL Pin Function Selection [15:13] IODIS IO Pin Disable [16:16] PORTB[%s] PORTB Pin Configuration Register 0x0080 0x00000800 PERID Peripheral ID Register 0xffc read-only 0x008207e1 UTILITY 1.0 Utility Peripheral 0x40003000 0 0x00001000 registers SYND_DATA0 Synd Data 0 Register 0x000 0x00000000 SYND_DATA1 Synd Data 1 Register 0x004 0x00000000 SYND_SYND Synd Parity Register 0x008 0x00000000 SYND_ENC_32 Synd 32 bit Encoded Syndrome 0x00c read-only 0x00000000 SYND_CHECK_32_DATA Synd 32 bit Corrected Data 0x010 read-only 0x00000000 SYND_CHECK_32_SYND Synd 32 bit Corrected Syndrome and Status 0x014 read-only 0x00000000 SYND_ENC_64 Synd 64 bit Encoded Syndrome 0x018 read-only 0x00000000 SYND_CHECK_64_DATA0 Synd 64 bit Corrected Data 0 0x01c read-only 0x00000000 SYND_CHECK_64_DATA1 Synd 64 bit Corrected Data 1 0x020 read-only 0x00000000 SYND_CHECK_64_SYND Synd 64 bit Corrected Parity and Status 0x024 read-only 0x00000000 SYND_ENC_32_52 Synd 32/52 bit Encoded Syndrome 0x028 read-only 0x00000000 SYND_CHECK_32_52_DATA Synd 32/52 bit Corrected Data 0x02c read-only 0x00000000 SYND_CHECK_32_52_SYND Synd 32/52 bit Corrected Syndrome and Status 0x030 read-only 0x00000000 PERID Peripheral ID Register 0xffc read-only 0x008207e1 PORTA 1.0 GPIO Peripheral GPIO 0x50000000 0 0x00001000 registers DATAIN Data In Register 0x000 read-only 0x0000000 4 1 DATAINBYTE[%s] Data In Register by Byte DATAIN 0x000 8 read-only 0x0000000 DATAINRAW Data In Raw Register 0x004 0x0000000 DATAINRAWBYTE[%s] Data In Raw Register by Byte DATAINRAW 0x004 0x0000000 DATAOUT Data Out Register 0x008 write-only 0x0000000 4 1 DATAOUTBYTE[%s] Data Out Register by Byte DATAOUT 0x008 8 write-only 0x0000000 DATAOUTRAW Data Out Register 0x00c 0x0000000 DATAOUTRAWBYTE[%s] Data Out Register by Byte DATAOUTRAW 0x00c 0x0000000 SETOUT Set Out Register 0x010 0x0000000 SETOUTBYTE[%s] Set Out Register by Byte SETOUT 0x010 0x0000000 CLROUT Clear Out Register 0x014 0x0000000 CLROUTBYTE[%s] Clear Out Register by Byte CLROUT 0x014 0x0000000 TOGOUT Toggle Out Register 0x018 0x0000000 TOGOUTBYTE[%s] Toggle Out Register by Byte TOGOUT 0x018 0x0000000 DATAMASK Data mask Register 0x01c 0x0000000 4 1 DATAMASKBYTE[%s] Data Out Register by Byte DATAMASK 0x01c 8 0x0000000 DIR Direction Register (1:Output, 0:Input) 0x020 0x0000000 DIRBYTE[%s] Direction Register by Byte DIR 0x020 0x0000000 PULSE Pulse Mode Register 0x024 0x0000000 PULSEBYTE[%s] Pulse Mode Register by Byte PULSE 0x024 0x0000000 PULSEBASE Pulse Base Value Register 0x028 0x0000000 PULSEBASEBYTE[%s] Pulse Base Mode Register by Byte PULSEBASE 0x028 0x0000000 DELAY1 Delay1 Register 0x02c 0x0000000 DELAY1BYTE[%s] Delay1 Register by Byte DELAY1 0x02c 0x0000000 DELAY2 Delay2 Register 0x030 32 read-write 0x0000000 DELAY2BYTE[%s] Delay2 Register by Byte DELAY2 0x030 0x0000000 IRQ_SEN Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive) 0x034 0x0000000 IRQ_EDGE Interrupt Both Edge Register (1:Both Edges, 0:Single Edge) 0x038 0x0000000 IRQ_EVT Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) 0x03c 0x0000000 IRQ_ENB Interrupt Enable Register 0x040 0x0000000 IRQ_RAW Raw Interrupt Status 0x044 read-only 0x0000000 IRQ_END Masked Interrupt Status 0x048 read-only 0x0000000 EDGE_STATUS Edge Status Register 0x04c read-write 0x00000000 PERID Peripheral ID Register 0xffc 32 read-only 0x001007e1 PORTB 0x50001000 TIM0 1.0 Timer/Counter Peripheral Timer_Counter 0x40020000 0 0x00001000 registers CTRL Control Register 0x000 read-write ENABLE Counter Enable [0:0] ACTIVE Counter Active [1:1] read-only AUTO_DISABLE Auto Disables the counter (set ENABLE to 0) when the count reaches 0 [2:2] AUTO_DEACTIVATE Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0 [3:3] IRQ_ENB Interrupt Enable [4:4] STATUS_SEL Counter Status Selection [7:5] DONE Single cycle pulse when the counter reaches 0 0 ACTIVE Returns the counter ACTIVE bit 1 TOGGLE Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output. 2 PWMA Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE 3 PWMB Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE 4 ENABLED Returns the counter ENABLED bit 5 PWMA_ACTIVE Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0 6 STATUS_INV Invert the Output Status [8:8] REQ_STOP Stop Request [9:9] RST_VALUE The value that counter start from after reaching 0. 0x004 CNT_VALUE The current value of the counter 0x008 ENABLE Alternate access to the Counter ENABLE bit in the CTRL Register 0x00c ENABLE Counter Enable [0:0] CSD_CTRL The Cascade Control Register. Controls the counter external enable signals 0x010 CSDEN0 Cascade 0 Enable [0:0] CSDINV0 Cascade 0 Invert [1:1] CSDEN1 Cascade 1 Enable [2:2] CSDINV1 Cascade 1 Invert [3:3] DCASOP Dual Cascade Operation (0:AND, 1:OR) [4:4] CSDTRG0 Cascade 0 Enabled as Trigger [6:6] CSDTRG1 Cascade 1 Enabled as Trigger [7:7] CSDEN2 Cascade 2 Enable [8:8] CSDINV2 Cascade 2 Invert [9:9] CSDXXX2 Cascade 2 test mode [11:11] CASCADE0 Cascade Enable Selection 0x014 CASSEL Cascade Selection [7:0] CASCADE1 Cascade Enable Selection 0x018 CASCADE2 Cascade Enable Selection 0x01c PWM_VALUE The Pulse Width Modulation Value 0x020 PWMA_VALUE The Pulse Width Modulation ValueA PWM_VALUE 0x020 PWMB_VALUE The Pulse Width Modulation ValueB 0x024 PERID Peripheral ID Register 0xffc read-only 0x001107e1 TIM1 0x40021000 TIM2 0x40022000 TIM3 0x40023000 TIM4 0x40024000 TIM5 0x40025000 TIM6 0x40026000 TIM7 0x40027000 TIM8 0x40028000 TIM9 0x40029000 TIM10 0x4002a000 TIM11 0x4002b000 TIM12 0x4002c000 TIM13 0x4002d000 TIM14 0x4002e000 TIM15 0x4002f000 TIM16 0x40030000 TIM17 0x40031000 TIM18 0x40032000 TIM19 0x40033000 TIM20 0x40034000 TIM21 0x40035000 TIM22 0x40036000 TIM23 0x40037000 UARTA 1.0 UART Peripheral UART 0x40040000 0 0x00001000 registers DATA Data In/Out Register 0x000 0x0000000 ENABLE Enable Register 0x004 0x0000000 RXENABLE Rx Enable [0:0] TXENABLE Tx Enable [1:1] CTRL Control Register 0x008 0x0000000 PAREN Parity Enable [0:0] PAREVEN Parity Even/Odd(1/0) [1:1] PARSTK Parity Sticky [2:2] STOPBITS Stop Bits 1/2(0/1) [3:3] WORDSIZE Word Size in Bits 5/6/7/8(00/01/10/11) [5:4] LOOPBACK Loopback Enable [6:6] LOOPBACKBLK Loopback Block [7:7] AUTOCTS Enable Auto CTS mode [8:8] DEFRTS Default RTSn value [9:9] AUTORTS Enable Auto RTS mode [10:10] BAUD8 Enable BAUD8 mode [11:11] CLKSCALE Clock Scale Register 0x00c 0x0000000 FRAC Fractional Divide (64ths) [5:0] INT Integer Divide [23:6] RESET Reset Baud Counter [31:31] write-only RXSTATUS Status Register 0x010 read-only 0x0000000 RDAVL Read Data Available [0:0] RDNFULL Read Fifo NOT Full [1:1] RXBUSY RX Busy Receiving [2:2] RXTO RX Receive Timeout [3:3] RXOVR Read Fifo Overflow [4:4] RXFRM RX Framing Error [5:5] RXPAR RX Parity Error [6:6] RXBRK RX Break Error [7:7] RXBUSYBRK RX Busy Receiving Break [8:8] RXADDR9 Address Match for 9 bit mode [9:9] RXRTSN RX RTSn Output Value [15:15] TXSTATUS Status Register 0x014 read-only 0x0000000 WRRDY Write Fifo NOT Full [0:0] WRBUSY Write Fifo Full [1:1] TXBUSY TX Busy Transmitting [2:2] WRLOST Write Data Lost (Fifo Overflow) [3:3] TXCTSN TX CTSn Input Value [15:15] FIFO_CLR Clear FIFO Register 0x018 write-only 0x0000000 RXSTS Clear Rx Status [0:0] TXSTS Clear Tx Status [1:1] RXFIFO Clear Rx FIFO [2:2] TXFIFO Clear Tx FIFO [3:3] TXBREAK Break Transmit Register 0x01c write-only 0x0000000 ADDR9 Address9 Register 0x020 read-write 0x0000000 ADDR9MASK Address9 Mask Register 0x024 read-write 0x0000000 IRQ_ENB IRQ Enable Register 0x028 read-write 0x0000000 IRQ_RX RX Interrupt [0:0] IRQ_RX_STATUS RX Status Interrupt [1:1] IRQ_RX_TO RX Timeout Interrupt [2:2] IRQ_TX TX Interrupt [4:4] IRQ_TX_STATUS TX Status Interrupt [5:5] IRQ_TX_EMPTY TX Empty Interrupt [6:6] IRQ_TX_CTS TX CTS Change Interrupt [7:7] IRQ_RAW IRQ Raw Status Register 0x02c read-only 0x0000000 IRQ_END IRQ Enabled Status Register 0x030 read-only 0x0000000 IRQ_CLR IRQ Clear Status Register 0x034 write-only 0x0000000 RXFIFOIRQTRG Rx FIFO IRQ Trigger Level 0x038 TXFIFOIRQTRG Tx FIFO IRQ Trigger Level 0x03c RXFIFORTSTRG Rx FIFO RTS Trigger Level 0x040 STATE Internal STATE of UART Controller 0x044 32 read-only PERID Peripheral ID Register 0xffc read-only 0x001207e1 UARTB 0x40041000 SPIA 1.0 SPI Peripheral SPI 0x40050000 0 0x00001000 registers CTRL0 Control Register 0 0x000 0x0000000 SIZE Data Size(0x3=>4, 0xf=>16) [3:0] SPO SPI Clock Polarity [6:6] SPH SPI Clock Phase [7:7] SCRDV Serial Clock Rate divide+1 value [15:8] CTRL1 Control Register 1 0x004 0x0000000 LBM Loop Back [0:0] ENABLE Enable [1:1] MS Master/Slave (0:Master, 1:Slave) [2:2] SOD Slave output Disable [3:3] SS Slave Select [6:4] BLOCKMODE Block Mode Enable [7:7] BMSTART Block Mode Start Status Enable [8:8] BMSTALL Block Mode Stall Enable [9:9] MDLYCAP Master Delayed Capture Enable [10:10] MTXPAUSE Master Tx Pause Enable [11:11] DATA Data Input/Output 0x008 STATUS Status Register 0x00C read-only 0x0000000 TFE Transmit FIFO empty [0:0] TNF Transmit FIFO not full [1:1] RNE Receive FIFO not empty [2:2] RFF Receive FIFO Full [3:3] BUSY Busy [4:4] RXDATAFIRST Pending Data is first Byte in BLOCKMODE [5:5] RXTRIGGER RX FIFO Above Trigger Level [6:6] TXTRIGGER TX FIFO Below Trigger Level [7:7] CLKPRESCALE Clock Pre Scale divide value 0x010 IRQ_ENB Interrupt Enable Register 0x014 read-write 0x0000000 RORIM RX Overrun [0:0] RTIM RX Timeout [1:1] RXIM RX Fifo is at least half full [2:2] TXIM TX Fifo is at least half empty [3:3] IRQ_RAW Raw Interrupt Status Register 0x018 read-only IRQ_END Enabled Interrupt Status Register 0x01C read-only IRQ_CLR Clear Interrupt Status Register 0x020 write-only oneToClear RXFIFOIRQTRG Rx FIFO IRQ Trigger Level 0x024 TXFIFOIRQTRG Tx FIFO IRQ Trigger Level 0x028 FIFO_CLR Clear FIFO Register 0x02c write-only RXFIFO Clear Rx FIFO [0:0] TXFIFO Clear Tx FIFO [1:1] STATE Internal STATE of SPI Controller 0x030 read-only PERID Peripheral ID Register 0xffc read-only 0x001207e1 SPIB 0x40051000 SPIC 0x40052000 I2CA 1.0 I2C Peripheral I2C 0x40060000 0 0x00001000 registers CTRL Control Register 0x000 0x0000000 CLKENABLED I2C CLK Enabled [0:0] ENABLED I2C Activated [1:1] ENABLE I2C Active [2:2] TXFEMD TX FIFIO Empty Mode [3:3] RXFFMD RX FIFO Full Mode [4:4] ALGFILTER Enable Input Analog Glitch Filter [5:5] DLGFILTER Enable Input Digital Glitch Filter [6:6] LOOPBACK Enable LoopBack Mode [8:8] TMCONFIGENB Enable Timing Config Register [9:9] CLKSCALE Clock Scale divide value 0x004 VALUE Enable FastMode [30:0] FASTMODE Enable FastMode [31:31] WORDS Word Count value 0x008 ADDRESS I2C Address value 0x00c DATA Data Input/Output 0x010 CMD Command Register 0x014 STATUS I2C Controller Status Register 0x018 WAITING Controller is Waiting [2:2] STALLED Controller is Stalled [3:3] ARBLOST I2C Arbitration was lost [4:4] NACKADDR I2C Address was not Acknowledged [5:5] NACKDATA I2C Data was not Acknowledged [6:6] RXNEMPTY RX FIFO is Not Empty [8:8] RXFULL RX FIFO is Full [9:9] RXTRIGGER RX FIFO Above Trigger Level [11:11] TXEMPTY TX FIFO is Empty [12:12] TXNFULL TX FIFO is Full [13:13] TXTRIGGER TX FIFO Below Trigger Level [15:15] RAW_SDA I2C Raw SDA value [30:30] RAW_SCL I2C Raw SCL value [31:31] STATE Internal STATE of I2C Master Controller 0x01c read-only TXCOUNT TX Count Register 0x020 read-only RXCOUNT RX Count Register 0x024 read-only IRQ_ENB Interrupt Enable Register 0x028 read-write 0x0000000 I2CIDLE I2C Bus is Idle [0:0] IDLE Controller is Idle [1:1] WAITING Controller is Waiting [2:2] STALLED Controller is Stalled [3:3] ARBLOST I2C Arbitration was lost [4:4] NACKADDR I2C Address was not Acknowledged [5:5] NACKDATA I2C Data was not Acknowledged [6:6] CLKLOTO I2C Clock Low Timeout [7:7] TXOVERFLOW TX FIFO Overflowed [10:10] RXOVERFLOW TX FIFO Overflowed [11:11] TXREADY TX FIFO Ready [12:12] RXREADY RX FIFO Ready [13:13] TXEMPTY TX FIFO Empty [14:14] RXFULL RX FIFO Full [15:15] IRQ_RAW Raw Interrupt Status Register 0x02c read-only IRQ_END Enabled Interrupt Status Register 0x030 read-only IRQ_CLR Clear Interrupt Status Register 0x034 write-only oneToClear RXFIFOIRQTRG Rx FIFO IRQ Trigger Level 0x038 TXFIFOIRQTRG Tx FIFO IRQ Trigger Level 0x03c FIFO_CLR Clear FIFO Register 0x040 write-only RXFIFO Clear Rx FIFO [0:0] TXFIFO Clear Tx FIFO [1:1] TMCONFIG Timing Config Register 0x044 CLKTOLIMIT Clock Low Timeout Limit Register 0x048 S0_CTRL Slave Control Register 0x100 0x0000000 CLKENABLED I2C Enabled [0:0] ENABLED I2C Activated [1:1] ENABLE I2C Active [2:2] TXFEMD TX FIFIO Empty Mode [3:3] RXFFMD RX FIFO Full Mode [4:4] S0_MAXWORDS Slave MaxWords Register 0x104 S0_ADDRESS Slave I2C Address Value 0x108 S0_ADDRESSMASK Slave I2C Address Mask value 0x10c S0_DATA Slave Data Input/Output 0x110 S0_LASTADDRESS Slave I2C Last Address value 0x114 read-only S0_STATUS Slave I2C Controller Status Register 0x118 read-only 0x0000000 COMPLETED Controller Complted a Transaction [0:0] IDLE Controller is Idle [1:1] WAITING Controller is Waiting [2:2] TXSTALLED Controller is Tx Stalled [3:3] RXSTALLED Controller is Rx Stalled [4:4] ADDRESSMATCH I2C Address Match [5:5] NACKDATA I2C Data was not Acknowledged [6:6] RXDATAFIRST Pending Data is first Byte following Address [7:7] RXNEMPTY RX FIFO is Not Empty [8:8] RXFULL RX FIFO is Full [9:9] RXTRIGGER RX FIFO Above Trigger Level [11:11] TXEMPTY TX FIFO is Empty [12:12] TXNFULL TX FIFO is Full [13:13] TXTRIGGER TX FIFO Below Trigger Level [15:15] RAW_BUSY I2C Raw Busy value [29:29] RAW_SDA I2C Raw SDA value [30:30] RAW_SCL I2C Raw SCL value [31:31] S0_STATE Internal STATE of I2C Slave Controller 0x11c read-only S0_TXCOUNT Slave TX Count Register 0x120 read-only S0_RXCOUNT Slave RX Count Register 0x124 read-only S0_IRQ_ENB Slave Interrupt Enable Register 0x128 read-write 0x0000000 COMPLETED Controller Complted a Transaction [0:0] IDLE Controller is Idle [1:1] WAITING Controller is Waiting [2:2] TXSTALLED Controller is Tx Stalled [3:3] RXSTALLED Controller is Rx Stalled [4:4] ADDRESSMATCH I2C Address Match [5:5] NACKDATA I2C Data was not Acknowledged [6:6] RXDATAFIRST Pending Data is first Byte following Address [7:7] I2C_START I2C Start Condition [8:8] I2C_STOP I2C Stop Condition [9:9] TXUNDERFLOW TX FIFO Underflowed [10:10] RXOVERFLOW TX FIFO Overflowed [11:11] TXREADY TX FIFO Ready [12:12] RXREADY RX FIFO Ready [13:13] TXEMPTY TX FIFO Empty [14:14] RXFULL RX FIFO Full [15:15] S0_IRQ_RAW Slave Raw Interrupt Status Register 0x12c read-only S0_IRQ_END Slave Enabled Interrupt Status Register 0x130 read-only S0_IRQ_CLR Slave Clear Interrupt Status Register 0x134 write-only oneToClear S0_RXFIFOIRQTRG Slave Rx FIFO IRQ Trigger Level 0x138 S0_TXFIFOIRQTRG Slave Tx FIFO IRQ Trigger Level 0x13c S0_FIFO_CLR Slave Clear FIFO Register 0x140 write-only RXFIFO Clear Rx FIFO [0:0] TXFIFO Clear Tx FIFO [1:1] S0_ADDRESSB Slave I2C Address B Value 0x144 S0_ADDRESSMASKB Slave I2C Address B Mask value 0x148 PERID Peripheral ID Register 0xffc read-only 0x001407e1 I2CB 0x40061000