#[doc = "Register `IRQ_CLR` writer"] pub struct W(crate::W); impl core::ops::Deref for W { type Target = crate::W; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl From> for W { #[inline(always)] fn from(writer: crate::W) -> Self { W(writer) } } #[doc = "Field `RORIM` writer - RX Overrun"] pub struct RORIM_W<'a> { w: &'a mut W, } impl<'a> RORIM_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01); self.w } } #[doc = "Field `RTIM` writer - RX Timeout"] pub struct RTIM_W<'a> { w: &'a mut W, } impl<'a> RTIM_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1); self.w } } #[doc = "Field `RXIM` writer - RX Fifo is at least half full"] pub struct RXIM_W<'a> { w: &'a mut W, } impl<'a> RXIM_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2); self.w } } #[doc = "Field `TXIM` writer - TX Fifo is at least half empty"] pub struct TXIM_W<'a> { w: &'a mut W, } impl<'a> TXIM_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3); self.w } } impl W { #[doc = "Bit 0 - RX Overrun"] #[inline(always)] pub fn rorim(&mut self) -> RORIM_W { RORIM_W { w: self } } #[doc = "Bit 1 - RX Timeout"] #[inline(always)] pub fn rtim(&mut self) -> RTIM_W { RTIM_W { w: self } } #[doc = "Bit 2 - RX Fifo is at least half full"] #[inline(always)] pub fn rxim(&mut self) -> RXIM_W { RXIM_W { w: self } } #[doc = "Bit 3 - TX Fifo is at least half empty"] #[inline(always)] pub fn txim(&mut self) -> TXIM_W { TXIM_W { w: self } } #[doc = "Writes raw bits to the register."] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "Clear Interrupt Status Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"] pub struct IRQ_CLR_SPEC; impl crate::RegisterSpec for IRQ_CLR_SPEC { type Ux = u32; } #[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"] impl crate::Writable for IRQ_CLR_SPEC { type Writer = W; } #[doc = "`reset()` method sets IRQ_CLR to value 0"] impl crate::Resettable for IRQ_CLR_SPEC { #[inline(always)] fn reset_value() -> Self::Ux { 0 } }