67 lines
2.0 KiB
Rust
67 lines
2.0 KiB
Rust
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use crate::{enable_interrupt, pac};
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#[inline(always)]
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pub fn enable_rom_scrub(syscfg: &mut pac::Sysconfig, counter_reset: u16) {
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syscfg
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.rom_scrub()
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.write(|w| unsafe { w.bits(counter_reset as u32) })
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}
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#[inline(always)]
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pub fn enable_ram0_scrub(syscfg: &mut pac::Sysconfig, counter_reset: u16) {
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syscfg
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.ram0_scrub()
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.write(|w| unsafe { w.bits(counter_reset as u32) })
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}
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#[inline(always)]
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pub fn enable_ram1_scrub(syscfg: &mut pac::Sysconfig, counter_reset: u16) {
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syscfg
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.ram1_scrub()
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.write(|w| unsafe { w.bits(counter_reset as u32) })
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}
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/// This function enables the SBE related interrupts. The user should also provide a
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/// `EDAC_SBE` ISR and use [clear_sbe_irq] inside that ISR at the very least.
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#[inline(always)]
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pub fn enable_sbe_irq() {
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unsafe {
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enable_interrupt(pac::Interrupt::EDAC_SBE);
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}
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}
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/// This function enables the SBE related interrupts. The user should also provide a
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/// `EDAC_MBE` ISR and use [clear_mbe_irq] inside that ISR at the very least.
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#[inline(always)]
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pub fn enable_mbe_irq() {
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unsafe {
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enable_interrupt(pac::Interrupt::EDAC_MBE);
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}
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}
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/// This function should be called in the user provided `EDAC_SBE` interrupt-service routine
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/// to clear the SBE related interrupts.
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#[inline(always)]
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pub fn clear_sbe_irq() {
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// Safety: This function only clears SBE related IRQs
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let syscfg = unsafe { pac::Sysconfig::steal() };
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syscfg.irq_clr().write(|w| {
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w.romsbe().set_bit();
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w.ram0sbe().set_bit();
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w.ram1sbe().set_bit()
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});
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}
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/// This function should be called in the user provided `EDAC_MBE` interrupt-service routine
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/// to clear the MBE related interrupts.
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#[inline(always)]
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pub fn clear_mbe_irq() {
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// Safety: This function only clears SBE related IRQs
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let syscfg = unsafe { pac::Sysconfig::steal() };
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syscfg.irq_clr().write(|w| {
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w.rommbe().set_bit();
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w.ram0mbe().set_bit();
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w.ram1mbe().set_bit()
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});
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}
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