140 lines
7.7 KiB
Rust
140 lines
7.7 KiB
Rust
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#[repr(C)]
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#[doc = "Register block"]
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pub struct RegisterBlock {
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ctrl0: Ctrl0,
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ctrl1: Ctrl1,
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fifo_data: FifoData,
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status: Status,
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irq_enb: IrqEnb,
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irq_raw: IrqRaw,
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irq_end: IrqEnd,
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irq_clr: IrqClr,
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txfifoirqtrg: Txfifoirqtrg,
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fifo_clr: FifoClr,
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_reserved10: [u8; 0x07d4],
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perid: Perid,
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}
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impl RegisterBlock {
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#[doc = "0x00 - Control Register 0"]
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#[inline(always)]
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pub const fn ctrl0(&self) -> &Ctrl0 {
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&self.ctrl0
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}
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#[doc = "0x04 - Control Register 1"]
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#[inline(always)]
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pub const fn ctrl1(&self) -> &Ctrl1 {
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&self.ctrl1
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}
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#[doc = "0x08 - FIFO data"]
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#[inline(always)]
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pub const fn fifo_data(&self) -> &FifoData {
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&self.fifo_data
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}
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#[doc = "0x0c - Status"]
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#[inline(always)]
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pub const fn status(&self) -> &Status {
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&self.status
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}
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#[doc = "0x10 - Interrupt Enable"]
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#[inline(always)]
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pub const fn irq_enb(&self) -> &IrqEnb {
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&self.irq_enb
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}
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#[doc = "0x14 - Raw Interrupt Status"]
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#[inline(always)]
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pub const fn irq_raw(&self) -> &IrqRaw {
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&self.irq_raw
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}
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#[doc = "0x18 - Enabled Interrupt Status"]
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#[inline(always)]
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pub const fn irq_end(&self) -> &IrqEnd {
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&self.irq_end
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}
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#[doc = "0x1c - Clear Interrupt"]
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#[inline(always)]
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pub const fn irq_clr(&self) -> &IrqClr {
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&self.irq_clr
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}
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#[doc = "0x20 - Receive FIFO Interrupt Trigger Value"]
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#[inline(always)]
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pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg {
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&self.txfifoirqtrg
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}
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#[doc = "0x24 - FIFO Clear"]
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#[inline(always)]
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pub const fn fifo_clr(&self) -> &FifoClr {
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&self.fifo_clr
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}
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#[doc = "0x7fc - Peripheral ID Register"]
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#[inline(always)]
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pub const fn perid(&self) -> &Perid {
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&self.perid
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}
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}
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#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
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module"]
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#[doc(alias = "CTRL0")]
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pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>;
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#[doc = "Control Register 0"]
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pub mod ctrl0;
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#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
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module"]
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#[doc(alias = "CTRL1")]
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pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>;
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#[doc = "Control Register 1"]
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pub mod ctrl1;
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#[doc = "FIFO_DATA (rw) register accessor: FIFO data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_data`]
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module"]
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#[doc(alias = "FIFO_DATA")]
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pub type FifoData = crate::Reg<fifo_data::FifoDataSpec>;
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#[doc = "FIFO data"]
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pub mod fifo_data;
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#[doc = "STATUS (r) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
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module"]
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#[doc(alias = "STATUS")]
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pub type Status = crate::Reg<status::StatusSpec>;
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#[doc = "Status"]
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pub mod status;
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#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
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module"]
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#[doc(alias = "IRQ_ENB")]
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pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
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#[doc = "Interrupt Enable"]
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pub mod irq_enb;
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#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
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module"]
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#[doc(alias = "IRQ_RAW")]
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pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>;
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#[doc = "Raw Interrupt Status"]
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pub mod irq_raw;
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#[doc = "IRQ_END (r) register accessor: Enabled Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
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module"]
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#[doc(alias = "IRQ_END")]
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pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>;
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#[doc = "Enabled Interrupt Status"]
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pub mod irq_end;
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#[doc = "IRQ_CLR (w) register accessor: Clear Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_clr`]
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module"]
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#[doc(alias = "IRQ_CLR")]
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pub type IrqClr = crate::Reg<irq_clr::IrqClrSpec>;
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#[doc = "Clear Interrupt"]
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pub mod irq_clr;
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#[doc = "TXFIFOIRQTRG (rw) register accessor: Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
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module"]
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#[doc(alias = "TXFIFOIRQTRG")]
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pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
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#[doc = "Receive FIFO Interrupt Trigger Value"]
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pub mod txfifoirqtrg;
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#[doc = "FIFO_CLR (rw) register accessor: FIFO Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
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module"]
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#[doc(alias = "FIFO_CLR")]
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pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
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#[doc = "FIFO Clear"]
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pub mod fifo_clr;
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#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
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module"]
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#[doc(alias = "PERID")]
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pub type Perid = crate::Reg<perid::PeridSpec>;
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#[doc = "Peripheral ID Register"]
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pub mod perid;
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