# This is a combination of 17 commits.

# This is the 1st commit message:

init commit

# This is the commit message #2:

smaller fixes for config files

# This is the commit message #3:

update VA416xx flash script file

# This is the commit message #4:

completed UART HAL, added first example

# This is the commit message #5:

UART, WDT and CLKGEN

# This is the commit message #6:

smaller workspace file tweaks

# This is the commit message #7:

SPI peripheral implementation

# This is the commit message #8:

update VS Code files

# This is the commit message #9:

update JLink files

# This is the commit message #10:

update VS Code files

# This is the commit message #11:

timer, PWM and I2C module

# This is the commit message #12:

Add CI

# This is the commit message #13:

update docs

# This is the commit message #14:

updates for documentation

# This is the commit message #15:

update CI as well

# This is the commit message #16:

add docs for setting up binary crate

# This is the commit message #17:

add additional memory section

vorago-peb1/memory.x

@@ -0,0 +1,14 @@
+MEMORY
+{
+	FLASH : ORIGIN = 0x00000000, LENGTH = 256K
+	/* RAM is a mandatory region. This RAM refers to the SRAM_0 */
+	RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K
+	SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* This is where the call stack will be allocated. */
+/* The stack is of the full descending type. */
+/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */
+/* SRAM_0 can be used for all busses: Instruction, Data and System */
+/* SRAM_1 only supports the system bus */
+_stack_start = ORIGIN(RAM) + LENGTH(RAM);