some more improvements
This commit is contained in:
parent
d3deb8a467
commit
01341edc91
@ -88,25 +88,25 @@ bitfield::bitfield! {
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u32;
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u32;
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pub raw, set_raw: 31,0;
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pub raw, set_raw: 31,0;
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u8;
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u8;
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dst_inc, set_dst_inc: 31, 30;
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pub dst_inc, set_dst_inc: 31, 30;
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u8;
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u8;
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dst_size, set_dst_size: 29, 28;
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pub dst_size, set_dst_size: 29, 28;
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u8;
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u8;
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src_inc, set_src_inc: 27, 26;
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pub src_inc, set_src_inc: 27, 26;
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u8;
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u8;
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src_size, set_src_size: 25, 24;
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pub src_size, set_src_size: 25, 24;
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u8;
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u8;
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dest_prot_ctrl, set_dest_prot_ctrl: 23, 21;
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pub dest_prot_ctrl, set_dest_prot_ctrl: 23, 21;
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u8;
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u8;
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src_prot_ctrl, set_src_prot_ctrl: 20, 18;
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pub src_prot_ctrl, set_src_prot_ctrl: 20, 18;
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u8;
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u8;
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r_power, set_r_power: 17, 14;
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pub r_power, set_r_power: 17, 14;
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u16;
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u16;
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n_minus_1, set_n_minus_1: 13, 4;
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pub n_minus_1, set_n_minus_1: 13, 4;
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bool;
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bool;
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next_useburst, set_next_useburst: 3;
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pub next_useburst, set_next_useburst: 3;
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u8;
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u8;
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cycle_ctrl, set_cycle_ctr: 2, 0;
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pub cycle_ctrl, set_cycle_ctr: 2, 0;
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}
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}
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#[repr(C)]
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#[repr(C)]
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@ -183,7 +183,7 @@ pub struct DmaCfg {
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}
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}
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pub struct DmaChannel {
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pub struct DmaChannel {
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idx: u8,
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channel: u8,
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done_interrupt: pac::Interrupt,
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done_interrupt: pac::Interrupt,
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active_interrupt: pac::Interrupt,
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active_interrupt: pac::Interrupt,
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pub dma: pac::Dma,
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pub dma: pac::Dma,
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@ -192,30 +192,35 @@ pub struct DmaChannel {
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}
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}
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impl DmaChannel {
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impl DmaChannel {
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#[inline(always)]
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pub fn channel(&self) -> u8 {
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self.channel
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}
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#[inline(always)]
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#[inline(always)]
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pub fn enable(&mut self) {
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pub fn enable(&mut self) {
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self.dma
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self.dma
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.chnl_enable_set()
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.chnl_enable_set()
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.write(|w| unsafe { w.bits(1 << self.idx) });
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.write(|w| unsafe { w.bits(1 << self.channel) });
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}
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}
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#[inline(always)]
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#[inline(always)]
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pub fn is_enabled(&mut self) -> bool {
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pub fn is_enabled(&mut self) -> bool {
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((self.dma.chnl_enable_set().read().bits() >> self.idx) & 0b1) != 0
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((self.dma.chnl_enable_set().read().bits() >> self.channel) & 0b1) != 0
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}
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}
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#[inline(always)]
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#[inline(always)]
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pub fn disable(&mut self) {
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pub fn disable(&mut self) {
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self.dma
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self.dma
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.chnl_enable_clr()
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.chnl_enable_clr()
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.write(|w| unsafe { w.bits(1 << self.idx) });
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.write(|w| unsafe { w.bits(1 << self.channel) });
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}
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}
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#[inline(always)]
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#[inline(always)]
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pub fn trigger_with_sw_request(&mut self) {
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pub fn trigger_with_sw_request(&mut self) {
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self.dma
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self.dma
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.chnl_sw_request()
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.chnl_sw_request()
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.write(|w| unsafe { w.bits(1 << self.idx) });
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.write(|w| unsafe { w.bits(1 << self.channel) });
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}
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}
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#[inline(always)]
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#[inline(always)]
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@ -227,14 +232,14 @@ impl DmaChannel {
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pub fn select_primary_structure(&self) {
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pub fn select_primary_structure(&self) {
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self.dma
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self.dma
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.chnl_pri_alt_clr()
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.chnl_pri_alt_clr()
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.write(|w| unsafe { w.bits(1 << self.idx) });
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.write(|w| unsafe { w.bits(1 << self.channel) });
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}
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}
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#[inline(always)]
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#[inline(always)]
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pub fn select_alternate_structure(&self) {
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pub fn select_alternate_structure(&self) {
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self.dma
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self.dma
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.chnl_pri_alt_set()
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.chnl_pri_alt_set()
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.write(|w| unsafe { w.bits(1 << self.idx) });
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.write(|w| unsafe { w.bits(1 << self.channel) });
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}
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}
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/// Enables the DMA_DONE interrupt for the DMA channel.
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/// Enables the DMA_DONE interrupt for the DMA channel.
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@ -258,7 +263,8 @@ impl DmaChannel {
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/// Prepares a 8-bit DMA transfer from memory to memory.
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/// Prepares a 8-bit DMA transfer from memory to memory.
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///
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///
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/// This function does not enable the DMA channel and interrupts and only prepares
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/// This function does not enable the DMA channel and interrupts and only prepares
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/// the DMA control block parameters for the transfer.
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/// the DMA control block parameters for the transfer. It configures the primary channel control
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/// structure to perform the transfer.
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///
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///
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/// You can use [Self::enable], [Self::enable_done_interrupt], [Self::enable_active_interrupt]
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/// You can use [Self::enable], [Self::enable_done_interrupt], [Self::enable_active_interrupt]
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/// to finish the transfer preparation and then use [Self::trigger_with_sw_request] to
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/// to finish the transfer preparation and then use [Self::trigger_with_sw_request] to
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@ -286,7 +292,8 @@ impl DmaChannel {
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/// Prepares a 16-bit DMA transfer from memory to memory.
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/// Prepares a 16-bit DMA transfer from memory to memory.
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///
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///
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/// This function does not enable the DMA channel and interrupts and only prepares
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/// This function does not enable the DMA channel and interrupts and only prepares
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/// the DMA control block parameters for the transfer.
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/// the DMA control block parameters for the transfer. It configures the primary channel control
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/// structure to perform the transfer.
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///
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///
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/// You can use [Self::enable], [Self::enable_done_interrupt], [Self::enable_active_interrupt]
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/// You can use [Self::enable], [Self::enable_done_interrupt], [Self::enable_active_interrupt]
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/// to finish the transfer preparation and then use [Self::trigger_with_sw_request] to
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/// to finish the transfer preparation and then use [Self::trigger_with_sw_request] to
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@ -314,7 +321,8 @@ impl DmaChannel {
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/// Prepares a 32-bit DMA transfer from memory to memory.
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/// Prepares a 32-bit DMA transfer from memory to memory.
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///
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///
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/// This function does not enable the DMA channel and interrupts and only prepares
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/// This function does not enable the DMA channel and interrupts and only prepares
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/// the DMA control block parameters for the transfer.
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/// the DMA control block parameters for the transfer. It configures the primary channel control
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/// structure to perform the transfer.
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///
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///
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/// You can use [Self::enable], [Self::enable_done_interrupt], [Self::enable_active_interrupt]
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/// You can use [Self::enable], [Self::enable_done_interrupt], [Self::enable_active_interrupt]
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/// to finish the transfer preparation and then use [Self::trigger_with_sw_request] to
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/// to finish the transfer preparation and then use [Self::trigger_with_sw_request] to
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@ -373,6 +381,7 @@ impl DmaChannel {
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self.ch_ctrl_pri.cfg.set_dst_inc(addr_incr as u8);
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self.ch_ctrl_pri.cfg.set_dst_inc(addr_incr as u8);
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self.ch_ctrl_pri.cfg.set_n_minus_1(n_minus_one as u16);
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self.ch_ctrl_pri.cfg.set_n_minus_1(n_minus_one as u16);
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self.ch_ctrl_pri.cfg.set_r_power(RPower::Every4 as u8);
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self.ch_ctrl_pri.cfg.set_r_power(RPower::Every4 as u8);
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self.select_primary_structure();
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}
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}
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}
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}
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@ -427,7 +436,7 @@ impl Dma {
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// Safety: The DMA channel API only operates on its respective channels.
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// Safety: The DMA channel API only operates on its respective channels.
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(
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(
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DmaChannel {
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DmaChannel {
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idx: 0,
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channel: 0,
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done_interrupt: pac::Interrupt::DMA_DONE0,
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done_interrupt: pac::Interrupt::DMA_DONE0,
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active_interrupt: pac::Interrupt::DMA_ACTIVE0,
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active_interrupt: pac::Interrupt::DMA_ACTIVE0,
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dma: unsafe { pac::Dma::steal() },
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dma: unsafe { pac::Dma::steal() },
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@ -435,7 +444,7 @@ impl Dma {
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ch_ctrl_alt: unsafe { &mut (*self.ctrl_block).alt[0] },
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ch_ctrl_alt: unsafe { &mut (*self.ctrl_block).alt[0] },
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},
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},
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DmaChannel {
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DmaChannel {
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idx: 1,
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channel: 1,
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done_interrupt: pac::Interrupt::DMA_DONE1,
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done_interrupt: pac::Interrupt::DMA_DONE1,
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active_interrupt: pac::Interrupt::DMA_ACTIVE1,
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active_interrupt: pac::Interrupt::DMA_ACTIVE1,
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dma: unsafe { pac::Dma::steal() },
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dma: unsafe { pac::Dma::steal() },
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@ -443,7 +452,7 @@ impl Dma {
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ch_ctrl_alt: unsafe { &mut (*self.ctrl_block).alt[1] },
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ch_ctrl_alt: unsafe { &mut (*self.ctrl_block).alt[1] },
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},
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},
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DmaChannel {
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DmaChannel {
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idx: 2,
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channel: 2,
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done_interrupt: pac::Interrupt::DMA_DONE2,
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done_interrupt: pac::Interrupt::DMA_DONE2,
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active_interrupt: pac::Interrupt::DMA_ACTIVE2,
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active_interrupt: pac::Interrupt::DMA_ACTIVE2,
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dma: unsafe { pac::Dma::steal() },
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dma: unsafe { pac::Dma::steal() },
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@ -451,7 +460,7 @@ impl Dma {
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ch_ctrl_alt: unsafe { &mut (*self.ctrl_block).alt[2] },
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ch_ctrl_alt: unsafe { &mut (*self.ctrl_block).alt[2] },
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},
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},
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DmaChannel {
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DmaChannel {
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idx: 3,
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channel: 3,
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done_interrupt: pac::Interrupt::DMA_DONE3,
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done_interrupt: pac::Interrupt::DMA_DONE3,
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active_interrupt: pac::Interrupt::DMA_ACTIVE3,
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active_interrupt: pac::Interrupt::DMA_ACTIVE3,
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dma: unsafe { pac::Dma::steal() },
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dma: unsafe { pac::Dma::steal() },
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