Async GPIO implementation
This commit is contained in:
@ -68,46 +68,19 @@
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//! # Embedded HAL traits
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//!
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//! This module implements all of the embedded HAL GPIO traits for each [`Pin`]
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//! in the corresponding [`PinMode`]s, namely: [`InputPin`], [`OutputPin`],
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//! and [`StatefulOutputPin`].
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//! in the corresponding [`PinMode`]s, namely: [embedded_hal::digital::InputPin],
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//! [embedded_hal::digital::OutputPin] and [embedded_hal::digital::StatefulOutputPin].
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use core::{convert::Infallible, marker::PhantomData, mem::transmute};
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pub use crate::clock::FilterClkSel;
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use crate::typelevel::Sealed;
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use embedded_hal::digital::{ErrorType, InputPin, OutputPin, StatefulOutputPin};
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use va416xx::{Porta, Portb, Portc, Portd, Porte, Portf, Portg};
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use va416xx::{self as pac, Porta, Portb, Portc, Portd, Porte, Portf, Portg};
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use super::{
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reg::RegisterInterface, DynAlternate, DynGroup, DynInput, DynOutput, DynPin, DynPinId,
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DynPinMode,
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DynAlternate, DynInput, DynOutput, DynPin, DynPinId, DynPinMode, InputPinAsync, InterruptEdge,
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InterruptLevel, PinState, Port, PortGDoesNotSupportAsyncError,
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};
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//==================================================================================================
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// Errors and Definitions
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//==================================================================================================
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum InterruptEdge {
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HighToLow,
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LowToHigh,
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BothEdges,
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}
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum InterruptLevel {
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Low = 0,
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High = 1,
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}
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum PinState {
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Low = 0,
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High = 1,
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}
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//==================================================================================================
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// Input configuration
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//==================================================================================================
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@ -296,10 +269,11 @@ impl<C: AlternateConfig> PinMode for Alternate<C> {
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pub trait PinId: Sealed {
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/// Corresponding [DynPinId]
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const DYN: DynPinId;
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const IRQ: Option<pac::Interrupt>;
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}
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macro_rules! pin_id {
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($Group:ident, $Id:ident, $NUM:literal $(, $meta: meta)?) => {
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($Port:ident, $Id:ident, $NUM:literal, $Irq:expr, $(, $meta: meta)?) => {
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// Need paste macro to use ident in doc attribute
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paste::paste! {
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$(#[$meta])?
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@ -311,10 +285,8 @@ macro_rules! pin_id {
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$(#[$meta])?
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impl PinId for $Id {
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const DYN: DynPinId = DynPinId {
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group: DynGroup::$Group,
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num: $NUM,
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};
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const DYN: DynPinId = DynPinId::new(Port::$Port, $NUM);
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const IRQ: Option<pac::Interrupt> = $Irq;
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}
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}
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};
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@ -340,7 +312,7 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
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/// at most one corresponding [`Pin`] in existence at any given time.
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/// Violating this requirement is `unsafe`.
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#[inline]
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pub(crate) unsafe fn new() -> Pin<I, M> {
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pub(crate) const unsafe fn new() -> Pin<I, M> {
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Pin {
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inner: DynPin::new(I::DYN, M::DYN),
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mode: PhantomData,
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@ -348,35 +320,40 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
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}
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#[inline]
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pub fn id(&self) -> DynPinId {
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pub const fn id(&self) -> DynPinId {
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self.inner.id()
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}
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#[inline(always)]
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pub const fn irq_id(&self) -> Option<pac::Interrupt> {
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I::IRQ
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}
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/// Convert the pin to the requested [`PinMode`]
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#[inline]
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pub fn into_mode<N: PinMode>(mut self) -> Pin<I, N> {
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// Only modify registers if we are actually changing pin mode
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// This check should compile away
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if N::DYN != M::DYN {
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self.inner.regs.change_mode(N::DYN);
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self.inner.change_mode(N::DYN);
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}
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// Safe because we drop the existing Pin
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unsafe { Pin::new() }
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}
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/// Configure the pin for function select 1. See Programmer Guide p.40 for the function table
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/// Configure the pin for function select 1. See Programmer Guide p. 286 for the function table
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#[inline]
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pub fn into_funsel_1(self) -> Pin<I, AltFunc1> {
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self.into_mode()
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}
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/// Configure the pin for function select 2. See Programmer Guide p.40 for the function table
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/// Configure the pin for function select 2. See Programmer Guide p. 286 for the function table
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#[inline]
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pub fn into_funsel_2(self) -> Pin<I, AltFunc2> {
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self.into_mode()
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}
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/// Configure the pin for function select 3. See Programmer Guide p.40 for the function table
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/// Configure the pin for function select 3. See Programmer Guide p. 286 for the function table
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#[inline]
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pub fn into_funsel_3(self) -> Pin<I, AltFunc3> {
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self.into_mode()
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@ -418,6 +395,16 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
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self.into_mode()
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}
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#[inline]
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pub fn is_low(&self) -> bool {
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!self.inner.read_pin()
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}
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#[inline]
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pub fn is_high(&self) -> bool {
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self.inner.read_pin()
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}
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#[inline]
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pub fn datamask(&self) -> bool {
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self.inner.datamask()
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@ -443,43 +430,41 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
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self.inner.is_low_masked()
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}
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#[inline]
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pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
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self.inner.set_high_masked()
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}
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#[inline]
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pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
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self.inner.set_low_masked()
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}
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#[inline]
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pub fn downgrade(self) -> DynPin {
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self.inner
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}
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fn irq_enb(&mut self) {
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self.inner.irq_enb();
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// Those only serve for the embedded HAL implementations which have different mutability.
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#[inline]
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fn is_low_mut(&mut self) -> bool {
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self.is_low()
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}
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#[inline]
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pub(crate) fn _set_high(&mut self) {
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self.inner.regs.write_pin(true)
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fn is_high_mut(&mut self) -> bool {
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self.is_high()
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}
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#[inline]
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pub(crate) fn _set_low(&mut self) {
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self.inner.regs.write_pin(false)
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pub fn enable_interrupt(&mut self) {
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self.inner.enable_interrupt();
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}
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#[inline]
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pub(crate) fn _is_low(&self) -> bool {
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!self.inner.regs.read_pin()
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pub fn disable_interrupt(&mut self) {
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self.inner.disable_interrupt();
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}
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#[inline]
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pub(crate) fn _is_high(&self) -> bool {
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self.inner.regs.read_pin()
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/// Configure the pin for an edge interrupt but does not enable the interrupt.
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pub fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) {
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self.inner.configure_edge_interrupt(edge_type).unwrap();
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}
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/// Configure the pin for a level interrupt but does not enable the interrupt.
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pub fn configure_level_interrupt(&mut self, level_type: InterruptLevel) {
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self.inner.configure_level_interrupt(level_type).unwrap();
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}
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}
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@ -571,56 +556,61 @@ impl<P: AnyPin> AsMut<P> for SpecificPin<P> {
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//==================================================================================================
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impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
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pub fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) {
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self.inner.regs.configure_edge_interrupt(edge_type);
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self.irq_enb();
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}
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pub fn configure_interrupt_level(&mut self, level_type: InterruptLevel) {
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self.inner.regs.configure_level_interrupt(level_type);
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self.irq_enb();
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/// Convert the pin into an async pin. The pin can be converted back by calling
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/// [InputPinAsync::release]
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pub fn into_async_input(self) -> Result<InputPinAsync<I, C>, PortGDoesNotSupportAsyncError> {
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InputPinAsync::new(self)
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}
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}
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impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
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/// See p.53 of the programmers guide for more information.
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#[inline]
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pub fn set_high(&mut self) {
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self.inner.write_pin(true)
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}
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#[inline]
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pub fn set_low(&mut self) {
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self.inner.write_pin(false)
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}
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#[inline]
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pub fn toggle(&mut self) {
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self.inner.toggle().unwrap()
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}
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#[inline]
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pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
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self.inner.set_high_masked()
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}
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#[inline]
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pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
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self.inner.set_low_masked()
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}
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/// Possible delays in clock cycles:
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/// - Delay 1: 1
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/// - Delay 2: 2
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/// - Delay 1 + Delay 2: 3
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#[inline]
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pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool) {
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self.inner.regs.configure_delay(delay_1, delay_2);
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self.inner.configure_delay(delay_1, delay_2).unwrap();
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}
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#[inline]
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pub fn toggle_with_toggle_reg(&mut self) {
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self.inner.regs.toggle()
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}
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/// See p.52 of the programmers guide for more information.
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/// When configured for pulse mode, a given pin will set the non-default state for exactly
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/// one clock cycle before returning to the configured default state
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pub fn configure_pulse_mode(&mut self, enable: bool, default_state: PinState) {
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self.inner.regs.configure_pulse_mode(enable, default_state);
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}
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pub fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) {
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self.inner.regs.configure_edge_interrupt(edge_type);
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self.irq_enb();
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}
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pub fn configure_level_interrupt(&mut self, level_type: InterruptLevel) {
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self.inner.regs.configure_level_interrupt(level_type);
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self.irq_enb();
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self.inner
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.configure_pulse_mode(enable, default_state)
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.unwrap();
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}
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}
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impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
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/// See p.37 and p.38 of the programmers guide for more information.
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#[inline]
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pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
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self.inner.regs.configure_filter_type(filter, clksel);
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self.inner.configure_filter_type(filter, clksel).unwrap();
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}
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}
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@ -628,7 +618,7 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
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// Embedded HAL traits
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//==================================================================================================
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impl<I, M> ErrorType for Pin<I, M>
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impl<I, M> embedded_hal::digital::ErrorType for Pin<I, M>
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where
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I: PinId,
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M: PinMode,
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@ -636,63 +626,69 @@ where
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type Error = Infallible;
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}
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impl<I: PinId, C: OutputConfig> OutputPin for Pin<I, Output<C>> {
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impl<I: PinId, C: OutputConfig> embedded_hal::digital::OutputPin for Pin<I, Output<C>> {
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#[inline]
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fn set_high(&mut self) -> Result<(), Self::Error> {
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self._set_high();
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self.set_high();
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Ok(())
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}
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#[inline]
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fn set_low(&mut self) -> Result<(), Self::Error> {
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self._set_low();
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self.set_low();
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Ok(())
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}
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}
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impl<I, C> InputPin for Pin<I, Input<C>>
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impl<I, C> embedded_hal::digital::InputPin for Pin<I, Input<C>>
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where
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I: PinId,
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C: InputConfig,
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{
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#[inline]
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fn is_high(&mut self) -> Result<bool, Self::Error> {
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Ok(self._is_high())
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Ok(self.is_high_mut())
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}
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#[inline]
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fn is_low(&mut self) -> Result<bool, Self::Error> {
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Ok(self._is_low())
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Ok(self.is_low_mut())
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}
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}
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impl<I, C> StatefulOutputPin for Pin<I, Output<C>>
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impl<I, C> embedded_hal::digital::StatefulOutputPin for Pin<I, Output<C>>
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where
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I: PinId,
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C: OutputConfig + ReadableOutput,
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{
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#[inline]
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fn is_set_high(&mut self) -> Result<bool, Self::Error> {
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Ok(self._is_high())
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Ok(self.is_high())
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}
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#[inline]
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fn is_set_low(&mut self) -> Result<bool, Self::Error> {
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Ok(self._is_low())
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Ok(self.is_low())
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}
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#[inline]
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fn toggle(&mut self) -> Result<(), Self::Error> {
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self.toggle();
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Ok(())
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}
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}
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impl<I, C> InputPin for Pin<I, Output<C>>
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impl<I, C> embedded_hal::digital::InputPin for Pin<I, Output<C>>
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where
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I: PinId,
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C: OutputConfig + ReadableOutput,
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{
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#[inline]
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fn is_high(&mut self) -> Result<bool, Self::Error> {
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Ok(self._is_high())
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Ok(self.is_high_mut())
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}
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#[inline]
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fn is_low(&mut self) -> Result<bool, Self::Error> {
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Ok(self._is_low())
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Ok(self.is_low_mut())
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}
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}
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@ -754,18 +750,31 @@ macro_rules! pins {
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}
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}
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macro_rules! declare_pins_with_irq {
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(
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$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal $(, $meta:meta)?)),+]
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) => {
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pins!($Port, $PinsName, $($Id $(, $meta)?)+,);
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$(
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paste::paste! {
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pin_id!($Group, $Id, $NUM, Some(pac::Interrupt::[<$Port:upper $NUM>]), $(, $meta)?);
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}
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)+
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}
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}
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macro_rules! declare_pins {
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(
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$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal $(, $meta:meta)?)),+]
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) => {
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pins!($Port, $PinsName, $($Id $(, $meta)?)+,);
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$(
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pin_id!($Group, $Id, $NUM $(, $meta)?);
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pin_id!($Group, $Id, $NUM, None, $(, $meta)?);
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)+
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}
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}
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declare_pins!(
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declare_pins_with_irq!(
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A,
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PinsA,
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Porta,
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@ -789,7 +798,7 @@ declare_pins!(
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]
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);
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declare_pins!(
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declare_pins_with_irq!(
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B,
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PinsB,
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Portb,
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@ -813,7 +822,7 @@ declare_pins!(
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]
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);
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declare_pins!(
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declare_pins_with_irq!(
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C,
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PinsC,
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Portc,
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@ -837,7 +846,7 @@ declare_pins!(
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]
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);
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declare_pins!(
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declare_pins_with_irq!(
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D,
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PinsD,
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Portd,
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@ -861,7 +870,7 @@ declare_pins!(
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]
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);
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declare_pins!(
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declare_pins_with_irq!(
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E,
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PinsE,
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Porte,
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@ -885,7 +894,7 @@ declare_pins!(
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]
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);
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declare_pins!(
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declare_pins_with_irq!(
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F,
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PinsF,
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Portf,
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Block a user