Updated GPIO impl
This commit is contained in:
@ -78,7 +78,8 @@ use embedded_hal::digital::{ErrorType, InputPin, OutputPin, StatefulOutputPin};
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use va416xx::{Porta, Portb, Portc, Portd, Porte, Portf, Portg};
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use super::{
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reg::RegisterInterface, DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode,
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reg::RegisterInterface, DynAlternate, DynGroup, DynInput, DynOutput, DynPin, DynPinId,
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DynPinMode,
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};
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//==================================================================================================
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@ -86,6 +87,7 @@ use super::{
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//==================================================================================================
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum InterruptEdge {
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HighToLow,
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LowToHigh,
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@ -93,12 +95,14 @@ pub enum InterruptEdge {
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}
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum InterruptLevel {
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Low = 0,
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High = 1,
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}
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum PinState {
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Low = 0,
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High = 1,
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@ -321,9 +325,10 @@ macro_rules! pin_id {
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//==================================================================================================
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/// A type-level GPIO pin, parameterized by [`PinId`] and [`PinMode`] types
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#[derive(Debug)]
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pub struct Pin<I: PinId, M: PinMode> {
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pub(in crate::gpio) regs: Registers<I>,
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mode: PhantomData<M>,
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inner: DynPin,
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mode: PhantomData<(I, M)>,
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}
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impl<I: PinId, M: PinMode> Pin<I, M> {
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@ -337,18 +342,23 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
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#[inline]
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pub(crate) unsafe fn new() -> Pin<I, M> {
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Pin {
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regs: Registers::new(),
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inner: DynPin::new(I::DYN, M::DYN),
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mode: PhantomData,
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}
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}
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#[inline]
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pub fn id(&self) -> DynPinId {
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self.inner.id()
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}
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/// Convert the pin to the requested [`PinMode`]
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#[inline]
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pub fn into_mode<N: PinMode>(mut self) -> Pin<I, N> {
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// Only modify registers if we are actually changing pin mode
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// This check should compile away
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if N::DYN != M::DYN {
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self.regs.change_mode::<N>();
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self.inner.regs.change_mode(N::DYN);
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}
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// Safe because we drop the existing Pin
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unsafe { Pin::new() }
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@ -408,26 +418,68 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
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self.into_mode()
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}
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common_reg_if_functions!();
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#[inline]
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pub fn datamask(&self) -> bool {
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self.inner.datamask()
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}
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#[inline]
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pub fn clear_datamask(&mut self) {
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self.inner.clear_datamask()
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}
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#[inline]
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pub fn set_datamask(&mut self) {
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self.inner.set_datamask()
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}
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#[inline]
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pub fn is_high_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
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self.inner.is_high_masked()
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}
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#[inline]
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pub fn is_low_masked(&self) -> Result<bool, crate::gpio::IsMaskedError> {
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self.inner.is_low_masked()
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}
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#[inline]
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pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
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self.inner.set_high_masked()
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}
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#[inline]
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pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> {
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self.inner.set_low_masked()
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}
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#[inline]
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pub fn downgrade(self) -> DynPin {
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self.inner
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}
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fn irq_enb(&mut self) {
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self.inner.irq_enb();
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}
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#[inline]
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pub(crate) fn _set_high(&mut self) {
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self.regs.write_pin(true)
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self.inner.regs.write_pin(true)
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}
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#[inline]
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pub(crate) fn _set_low(&mut self) {
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self.regs.write_pin(false)
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self.inner.regs.write_pin(false)
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}
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#[inline]
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pub(crate) fn _is_low(&self) -> bool {
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!self.regs.read_pin()
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!self.inner.regs.read_pin()
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}
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#[inline]
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pub(crate) fn _is_high(&self) -> bool {
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self.regs.read_pin()
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self.inner.regs.read_pin()
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}
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}
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@ -519,16 +571,14 @@ impl<P: AnyPin> AsMut<P> for SpecificPin<P> {
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//==================================================================================================
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impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
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pub fn interrupt_edge(mut self, edge_type: InterruptEdge) -> Self {
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self.regs.interrupt_edge(edge_type);
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pub fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) {
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self.inner.regs.configure_edge_interrupt(edge_type);
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self.irq_enb();
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self
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}
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pub fn interrupt_level(mut self, level_type: InterruptLevel) -> Self {
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self.regs.interrupt_level(level_type);
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pub fn configure_interrupt_level(&mut self, level_type: InterruptLevel) {
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self.inner.regs.configure_level_interrupt(level_type);
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self.irq_enb();
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self
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}
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}
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@ -539,38 +589,38 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
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/// - Delay 2: 2
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/// - Delay 1 + Delay 2: 3
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#[inline]
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pub fn delay(self, delay_1: bool, delay_2: bool) -> Self {
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self.regs.delay(delay_1, delay_2);
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self
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pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool) {
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self.inner.regs.configure_delay(delay_1, delay_2);
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}
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#[inline]
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pub fn toggle_with_toggle_reg(&mut self) {
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self.inner.regs.toggle()
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}
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/// See p.52 of the programmers guide for more information.
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/// When configured for pulse mode, a given pin will set the non-default state for exactly
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/// one clock cycle before returning to the configured default state
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pub fn pulse_mode(self, enable: bool, default_state: PinState) -> Self {
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self.regs.pulse_mode(enable, default_state);
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self
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pub fn configure_pulse_mode(&mut self, enable: bool, default_state: PinState) {
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self.inner.regs.configure_pulse_mode(enable, default_state);
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}
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pub fn interrupt_edge(mut self, edge_type: InterruptEdge) -> Self {
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self.regs.interrupt_edge(edge_type);
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pub fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) {
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self.inner.regs.configure_edge_interrupt(edge_type);
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self.irq_enb();
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self
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}
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pub fn interrupt_level(mut self, level_type: InterruptLevel) -> Self {
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self.regs.interrupt_level(level_type);
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pub fn configure_level_interrupt(&mut self, level_type: InterruptLevel) {
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self.inner.regs.configure_level_interrupt(level_type);
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self.irq_enb();
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self
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}
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}
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impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
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/// See p.37 and p.38 of the programmers guide for more information.
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#[inline]
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pub fn filter_type(self, filter: FilterType, clksel: FilterClkSel) -> Self {
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self.regs.filter_type(filter, clksel);
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self
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pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
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self.inner.regs.configure_filter_type(filter, clksel);
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}
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}
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@ -646,47 +696,6 @@ where
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}
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}
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//==================================================================================================
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// Registers
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//==================================================================================================
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/// Provide a safe register interface for [`Pin`]s
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///
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/// This `struct` takes ownership of a [`PinId`] and provides an API to
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/// access the corresponding registers.
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pub(in crate::gpio) struct Registers<I: PinId> {
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id: PhantomData<I>,
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}
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// [`Registers`] takes ownership of the [`PinId`], and [`Pin`] guarantees that
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// each pin is a singleton, so this implementation is safe.
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unsafe impl<I: PinId> RegisterInterface for Registers<I> {
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#[inline]
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fn id(&self) -> DynPinId {
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I::DYN
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}
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}
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impl<I: PinId> Registers<I> {
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/// Create a new instance of [`Registers`]
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///
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/// # Safety
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///
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/// Users must never create two simultaneous instances of this `struct` with
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/// the same [`PinId`]
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#[inline]
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unsafe fn new() -> Self {
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Registers { id: PhantomData }
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}
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/// Provide a type-level equivalent for the
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/// [`RegisterInterface::change_mode`] method.
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#[inline]
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pub(in crate::gpio) fn change_mode<M: PinMode>(&mut self) {
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RegisterInterface::change_mode(self, M::DYN);
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}
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}
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//==================================================================================================
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// Pin definitions
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//==================================================================================================
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@ -745,8 +754,6 @@ macro_rules! pins {
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}
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}
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//$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal $(, $meta:meta)?)),+]
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//$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal, $meta: meta),)+]
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macro_rules! declare_pins {
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(
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$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal $(, $meta:meta)?)),+]
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