more cleaning

examples/simple/examples/pwm.rs

@@ -14,7 +14,7 @@ use simple_examples::peb1;
 use va416xx_hal::{
     clock::ClockConfigurator,
     pac,
-    pins::{PinsA, PinsG},
+    pins::PinsG,
     prelude::*,
     pwm::{get_duty_from_percent, PwmA, PwmB, PwmPin},
     timer::CountdownTimer,

va416xx-embassy/Cargo.toml

@@ -11,7 +11,7 @@ keywords = ["no-std", "hal", "cortex-m", "vorago", "va416xx"]
 categories = ["aerospace", "embedded", "no-std", "hardware-support"]
 
 [dependencies]
-vorago-shared-periphs = { git = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs.git", features = ["vor4x"] }
+vorago-shared-periphs = { path = "../../vorago-shared-periphs", features = ["vor4x"] }
 va416xx-hal = { path = "../va416xx-hal" }
 
 [features]

va416xx-hal/Cargo.toml

@@ -12,34 +12,24 @@ categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
 cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
-critical-section = "1"
-nb = "1"
-paste = "1"
-embedded-hal-nb = "1"
-embedded-hal-async = "1"
-embedded-hal = "1"
-embedded-io = "0.6"
-embedded-io-async = "0.6"
-num_enum = { version = "0.7", default-features = false }
-typenum = "1"
-bitflags = "2"
-bitfield = { version = ">=0.17, <=0.18"}
-fugit = "0.3"
-delegate = ">=0.12, <=0.13"
-heapless = "0.8"
-void = { version = "1", default-features = false }
-thiserror = { version = "2", default-features = false }
-portable-atomic = "1"
-embassy-sync = "0.6"
-vorago-shared-periphs = { git = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs.git", features = ["vor4x"] }
 va416xx = { version = "0.4", features = ["critical-section"], default-features = false }
+vorago-shared-periphs = { path = "../../vorago-shared-periphs", features = ["vor4x"] }
+
+nb = "1"
+embedded-hal = "1"
+num_enum = { version = "0.7", default-features = false }
+bitflags = "2"
+bitbybit = "1.3"
+arbitrary-int = "1.3"
+fugit = "0.3"
+thiserror = { version = "2", default-features = false }
 
 defmt = { version = "0.3", optional = true }
 
 [features]
 default = ["rt", "revb"]
 rt = ["va416xx/rt"]
-defmt = ["dep:defmt", "fugit/defmt", "embedded-hal/defmt-03", "vorago-shared-periphs/defmt"]
+defmt = ["dep:defmt", "fugit/defmt", "vorago-shared-periphs/defmt"]
 
 va41630 = ["device-selected"]
 va41620 = ["device-selected"]

va416xx-hal/src/dma.rs

@@ -3,6 +3,7 @@
 //! ## Examples
 //!
 //! - [Simple DMA example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/dma.rs)
+use arbitrary_int::{u10, u3};
 use vorago_shared_periphs::{
     enable_peripheral_clock, reset_peripheral_for_cycles, PeripheralSelect,
 };
@@ -15,9 +16,10 @@ const BASE_PTR_ADDR_MASK: u32 = 0b1111111;
 /// DMA cycle control values.
 ///
 /// Refer to chapter 6.3.1 and 6.6.3 of the datasheet for more details.
-#[repr(u8)]
+#[bitbybit::bitenum(u3, exhaustive = true)]
-#[derive(Debug, Clone, Copy)]
+#[derive(Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[repr(u8)]
 pub enum CycleControl {
     /// Indicates that the data structure is invalid.
     Stop = 0b000,
@@ -42,7 +44,8 @@ pub enum CycleControl {
     PeriphScatterGatherAlternate = 0b111,
 }
 
-#[derive(Debug, Clone, Copy)]
+#[bitbybit::bitenum(u2, exhaustive = true)]
+#[derive(Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum AddrIncrement {
     Byte = 0b00,
@@ -51,7 +54,8 @@ pub enum AddrIncrement {
     None = 0b11,
 }
 
-#[derive(Debug, Clone, Copy)]
+#[bitbybit::bitenum(u2, exhaustive = false)]
+#[derive(Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum DataSize {
     Byte = 0b00,
@@ -60,7 +64,8 @@ pub enum DataSize {
 }
 
 /// This configuration controls how many DMA transfers can occur before the controller arbitrates.
-#[derive(Debug, Clone, Copy)]
+#[bitbybit::bitenum(u4, exhaustive = true)]
+#[derive(Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum RPower {
     EachTransfer = 0b0000,
@@ -73,8 +78,12 @@ pub enum RPower {
     Every128 = 0b0111,
     Every256 = 0b1000,
     Every512 = 0b1001,
-    Every1024Min = 0b1010,
+    Every1024 = 0b1010,
-    Every1024 = 0b1111,
+    Every1024Alt0 = 0b1011,
+    Every1024Alt1 = 0b1100,
+    Every1024Alt2 = 0b1101,
+    Every1024Alt3 = 0b1110,
+    Every1024Alt4 = 0b1111,
 }
 
 #[derive(Debug, PartialEq, Eq, thiserror::Error)]
@@ -82,6 +91,7 @@ pub enum RPower {
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct InvalidCtrlBlockAddrError;
 
+/*
 bitfield::bitfield! {
     #[repr(transparent)]
     #[derive(Clone, Copy)]
@@ -111,6 +121,33 @@ bitfield::bitfield! {
     u8;
     pub cycle_ctrl, set_cycle_ctr: 2, 0;
 }
+*/
+
+#[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct ChannelConfig {
+    #[bits(30..=31, rw)]
+    dst_inc: AddrIncrement,
+    #[bits(28..=29, rw)]
+    dst_size: Option<DataSize>,
+    #[bits(26..=27, rw)]
+    src_inc: AddrIncrement,
+    #[bits(24..=25, rw)]
+    src_size: Option<DataSize>,
+    #[bits(21..=23, rw)]
+    dest_prot_ctrl: u3,
+    #[bits(18..=20, rw)]
+    src_prot_ctrl: u3,
+    #[bits(14..=17, rw)]
+    r_power: RPower,
+    #[bits(4..=13, rw)]
+    n_minus_1: u10,
+    #[bit(3, rw)]
+    next_useburst: bool,
+    #[bits(0..=2, rw)]
+    cycle_ctrl: CycleControl,
+}
 
 #[repr(C)]
 #[derive(Debug, Copy, Clone)]
@@ -127,7 +164,7 @@ impl DmaChannelControl {
         Self {
             src_end_ptr: 0,
             dest_end_ptr: 0,
-            cfg: ChannelConfig(0),
+            cfg: ChannelConfig::new_with_raw_value(0),
             padding: 0,
         }
     }
@@ -428,20 +465,18 @@ impl DmaChannel {
             return Err(DmaTransferInitError::TransferSizeTooLarge(source.len()));
         }
         let len = source.len() - 1;
-        self.ch_ctrl_pri.cfg.set_raw(0);
+        self.ch_ctrl_pri.cfg = ChannelConfig::new_with_raw_value(0);
         self.ch_ctrl_pri.src_end_ptr = (source.as_ptr() as u32)
             .checked_add(len as u32)
             .ok_or(DmaTransferInitError::AddrOverflow)?;
         self.ch_ctrl_pri.dest_end_ptr = dest as u32;
-        self.ch_ctrl_pri
+        self.ch_ctrl_pri.cfg.set_cycle_ctrl(CycleControl::Basic);
-            .cfg
+        self.ch_ctrl_pri.cfg.set_src_size(DataSize::Byte);
-            .set_cycle_ctr(CycleControl::Basic as u8);
+        self.ch_ctrl_pri.cfg.set_src_inc(AddrIncrement::Byte);
-        self.ch_ctrl_pri.cfg.set_src_size(DataSize::Byte as u8);
+        self.ch_ctrl_pri.cfg.set_dst_size(DataSize::Byte);
-        self.ch_ctrl_pri.cfg.set_src_inc(AddrIncrement::Byte as u8);
+        self.ch_ctrl_pri.cfg.set_dst_inc(AddrIncrement::None);
-        self.ch_ctrl_pri.cfg.set_dst_size(DataSize::Byte as u8);
+        self.ch_ctrl_pri.cfg.set_n_minus_1(u10::new(len as u16));
-        self.ch_ctrl_pri.cfg.set_dst_inc(AddrIncrement::None as u8);
+        self.ch_ctrl_pri.cfg.set_r_power(RPower::Every8);
-        self.ch_ctrl_pri.cfg.set_n_minus_1(len as u16);
-        self.ch_ctrl_pri.cfg.set_r_power(RPower::Every8 as u8);
         self.select_primary_structure();
         Ok(())
     }
@@ -470,16 +505,18 @@ impl DmaChannel {
         data_size: DataSize,
         addr_incr: AddrIncrement,
     ) {
-        self.ch_ctrl_pri.cfg.set_raw(0);
+        self.ch_ctrl_pri.cfg = ChannelConfig::new_with_raw_value(0);
         self.ch_ctrl_pri.src_end_ptr = src_end_ptr;
         self.ch_ctrl_pri.dest_end_ptr = dest_end_ptr;
-        self.ch_ctrl_pri.cfg.set_cycle_ctr(CycleControl::Auto as u8);
+        self.ch_ctrl_pri.cfg.set_cycle_ctrl(CycleControl::Auto);
-        self.ch_ctrl_pri.cfg.set_src_size(data_size as u8);
+        self.ch_ctrl_pri.cfg.set_src_size(data_size);
-        self.ch_ctrl_pri.cfg.set_src_inc(addr_incr as u8);
+        self.ch_ctrl_pri.cfg.set_src_inc(addr_incr);
-        self.ch_ctrl_pri.cfg.set_dst_size(data_size as u8);
+        self.ch_ctrl_pri.cfg.set_dst_size(data_size);
-        self.ch_ctrl_pri.cfg.set_dst_inc(addr_incr as u8);
+        self.ch_ctrl_pri.cfg.set_dst_inc(addr_incr);
-        self.ch_ctrl_pri.cfg.set_n_minus_1(n_minus_one as u16);
+        self.ch_ctrl_pri
-        self.ch_ctrl_pri.cfg.set_r_power(RPower::Every4 as u8);
+            .cfg
+            .set_n_minus_1(u10::new(n_minus_one as u16));
+        self.ch_ctrl_pri.cfg.set_r_power(RPower::Every4);
         self.select_primary_structure();
     }
 }

vorago-peb1/Cargo.toml

@@ -11,15 +11,11 @@ keywords = ["no-std", "peb1", "cortex-m", "vorago", "va416xx"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-cortex-m = "0.7"
+va416xx-hal = { version = ">=0.3, <=0.5", path = "../va416xx-hal", features = ["va41630"] }
-cortex-m-rt = "0.7"
 embedded-hal = "1"
 lis2dh12 = { version = "0.7", features = ["out_f32"] }
 
-va416xx-hal = { version = ">=0.3, <=0.5", path = "../va416xx-hal", features = ["va41630"] }
-
 [features]
-rt = ["va416xx-hal/rt"]
 
 [package.metadata.docs.rs]
 all-features = true