rust/va416xx-rs
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regenerate PAC, va416xx v0.3.0

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This commit is contained in:
Robin Müller
2025-02-13 15:58:05 +01:00
parent 0c040515fe
commit 2c9ca004ce
517 changed files with 1376 additions and 2392 deletions
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6
va416xx/src/adc/irq_clr.rs
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@ -11,30 +11,26 @@ pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Clears the FIFO overflow interrupt status. Always reads 0"]
#[inline(always)]
#[must_use]
pub fn fifo_oflow(&mut self) -> FifoOflowW<IrqClrSpec> {
FifoOflowW::new(self, 0)
}
#[doc = "Bit 1 - Clears the FIFO underflow interrupt status. Always reads 0"]
#[inline(always)]
#[must_use]
pub fn fifo_uflow(&mut self) -> FifoUflowW<IrqClrSpec> {
FifoUflowW::new(self, 1)
}
#[doc = "Bit 2 - Clears the ADC done interrupt status. Always reads 0"]
#[inline(always)]
#[must_use]
pub fn adc_done(&mut self) -> AdcDoneW<IrqClrSpec> {
AdcDoneW::new(self, 2)
}
#[doc = "Bit 3 - Clears the trigger error interrupt status. Always reads 0"]
#[inline(always)]
#[must_use]
pub fn trig_error(&mut self) -> TrigErrorW<IrqClrSpec> {
TrigErrorW::new(self, 3)
}
}
#[doc = "Clear Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Clear Interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqClrSpec;
impl crate::RegisterSpec for IrqClrSpec {
type Ux = u32;