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regenerate PAC, va416xx v0.3.0

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This commit is contained in:
Robin Müller
2025-02-13 15:58:05 +01:00
parent 0c040515fe
commit 2c9ca004ce
517 changed files with 1376 additions and 2392 deletions
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4
va416xx/src/can0/cien.rs
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@ -25,18 +25,16 @@ impl R {
impl W {
#[doc = "Bits 0:14 - Buffer Interrupt Enable\\[14:0\\]"]
#[inline(always)]
#[must_use]
pub fn ien(&mut self) -> IenW<CienSpec> {
IenW::new(self, 0)
}
#[doc = "Bit 15 - Error Interrupt Enable"]
#[inline(always)]
#[must_use]
pub fn eien(&mut self) -> EienW<CienSpec> {
EienW::new(self, 15)
}
}
#[doc = "CAN Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cien::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cien::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "CAN Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CienSpec;
impl crate::RegisterSpec for CienSpec {
type Ux = u32;