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regenerate PAC, va416xx v0.3.0

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This commit is contained in:
Robin Müller
2025-02-13 15:58:05 +01:00
parent 0c040515fe
commit 2c9ca004ce
517 changed files with 1376 additions and 2392 deletions
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3
va416xx/src/irq_router/adcsel.rs
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@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:4 - ADC trigger source selection value"]
#[inline(always)]
#[must_use]
pub fn adcsel(&mut self) -> AdcselW<AdcselSpec> {
AdcselW::new(self, 0)
}
}
#[doc = "Interrupt select for ADC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcsel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Interrupt select for ADC\n\nYou can [`read`](crate::Reg::read) this register and get [`adcsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adcsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AdcselSpec;
impl crate::RegisterSpec for AdcselSpec {
type Ux = u32;

3
va416xx/src/irq_router/dacsel0.rs
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@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:4 - DAC trigger source selection value"]
#[inline(always)]
#[must_use]
pub fn dacsel(&mut self) -> DacselW<Dacsel0Spec> {
DacselW::new(self, 0)
}
}
#[doc = "Interrupt select for DAC0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dacsel0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dacsel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Interrupt select for DAC0\n\nYou can [`read`](crate::Reg::read) this register and get [`dacsel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dacsel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dacsel0Spec;
impl crate::RegisterSpec for Dacsel0Spec {
type Ux = u32;

3
va416xx/src/irq_router/dacsel1.rs
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@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:4 - DAC trigger source selection value"]
#[inline(always)]
#[must_use]
pub fn dacsel(&mut self) -> DacselW<Dacsel1Spec> {
DacselW::new(self, 0)
}
}
#[doc = "Interrupt select for DAC1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dacsel1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dacsel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Interrupt select for DAC1\n\nYou can [`read`](crate::Reg::read) this register and get [`dacsel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dacsel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dacsel1Spec;
impl crate::RegisterSpec for Dacsel1Spec {
type Ux = u32;

3
va416xx/src/irq_router/dmasel0.rs
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@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:6 - DMA trigger source selection value"]
#[inline(always)]
#[must_use]
pub fn dmasel(&mut self) -> DmaselW<Dmasel0Spec> {
DmaselW::new(self, 0)
}
}
#[doc = "Interrupt select for DMA channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Interrupt select for DMA channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmasel0Spec;
impl crate::RegisterSpec for Dmasel0Spec {
type Ux = u32;

3
va416xx/src/irq_router/dmasel1.rs
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@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:6 - DMA trigger source selection value"]
#[inline(always)]
#[must_use]
pub fn dmasel(&mut self) -> DmaselW<Dmasel1Spec> {
DmaselW::new(self, 0)
}
}
#[doc = "Interrupt select for DMA channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Interrupt select for DMA channel 1\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmasel1Spec;
impl crate::RegisterSpec for Dmasel1Spec {
type Ux = u32;

3
va416xx/src/irq_router/dmasel2.rs
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@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:6 - DMA trigger source selection value"]
#[inline(always)]
#[must_use]
pub fn dmasel(&mut self) -> DmaselW<Dmasel2Spec> {
DmaselW::new(self, 0)
}
}
#[doc = "Interrupt select for DMA channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Interrupt select for DMA channel 2\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmasel2Spec;
impl crate::RegisterSpec for Dmasel2Spec {
type Ux = u32;

3
va416xx/src/irq_router/dmasel3.rs
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@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:6 - DMA trigger source selection value"]
#[inline(always)]
#[must_use]
pub fn dmasel(&mut self) -> DmaselW<Dmasel3Spec> {
DmaselW::new(self, 0)
}
}
#[doc = "Interrupt select for DMA channel 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Interrupt select for DMA channel 3\n\nYou can [`read`](crate::Reg::read) this register and get [`dmasel3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmasel3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dmasel3Spec;
impl crate::RegisterSpec for Dmasel3Spec {
type Ux = u32;

3
va416xx/src/irq_router/dmattsel.rs
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@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:3 - DMA trigger type selection value"]
#[inline(always)]
#[must_use]
pub fn dmattsel(&mut self) -> DmattselW<DmattselSpec> {
DmattselW::new(self, 0)
}
}
#[doc = "Trigger select for the DMA channels\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmattsel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmattsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Trigger select for the DMA channels\n\nYou can [`read`](crate::Reg::read) this register and get [`dmattsel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmattsel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DmattselSpec;
impl crate::RegisterSpec for DmattselSpec {
type Ux = u32;

2
va416xx/src/irq_router/irq_out0.rs
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@ -9,7 +9,7 @@ impl R {
IrqOut0R::new(self.bits)
}
}
#[doc = "DEBUG IRQ_OUT\\[31:0\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "DEBUG IRQ_OUT\\[31:0\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqOut0Spec;
impl crate::RegisterSpec for IrqOut0Spec {
type Ux = u32;

2
va416xx/src/irq_router/irq_out1.rs
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@ -9,7 +9,7 @@ impl R {
IrqOut1R::new(self.bits)
}
}
#[doc = "DEBUG IRQ_OUT\\[63:32\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "DEBUG IRQ_OUT\\[63:32\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqOut1Spec;
impl crate::RegisterSpec for IrqOut1Spec {
type Ux = u32;

2
va416xx/src/irq_router/irq_out2.rs
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@ -9,7 +9,7 @@ impl R {
IrqOut2R::new(self.bits)
}
}
#[doc = "DEBUG IRQ_OUT\\[95:64\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "DEBUG IRQ_OUT\\[95:64\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqOut2Spec;
impl crate::RegisterSpec for IrqOut2Spec {
type Ux = u32;

2
va416xx/src/irq_router/irq_out3.rs
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@ -9,7 +9,7 @@ impl R {
IrqOut3R::new(self.bits)
}
}
#[doc = "DEBUG IRQ_OUT\\[127:96\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "DEBUG IRQ_OUT\\[127:96\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqOut3Spec;
impl crate::RegisterSpec for IrqOut3Spec {
type Ux = u32;

2
va416xx/src/irq_router/irq_out4.rs
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@ -9,7 +9,7 @@ impl R {
IrqOut4R::new(self.bits)
}
}
#[doc = "DEBUG IRQ_OUT\\[159:128\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "DEBUG IRQ_OUT\\[159:128\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqOut4Spec;
impl crate::RegisterSpec for IrqOut4Spec {
type Ux = u32;

2
va416xx/src/irq_router/irq_out5.rs
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@ -9,7 +9,7 @@ impl R {
IrqOut5R::new(self.bits & 0x000f_ffff)
}
}
#[doc = "DEBUG IRQ_OUT\\[179:160\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "DEBUG IRQ_OUT\\[179:160\\]\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_out5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqOut5Spec;
impl crate::RegisterSpec for IrqOut5Spec {
type Ux = u32;

2
va416xx/src/irq_router/perid.rs
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@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;