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regenerate PAC, va416xx v0.3.0

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This commit is contained in:
Robin Müller
2025-02-13 15:58:05 +01:00
parent 0c040515fe
commit 2c9ca004ce
517 changed files with 1376 additions and 2392 deletions
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2
va416xx/src/sysconfig/adc_cal.rs
View File

@ -9,7 +9,7 @@ impl R {
AdcCalR::new((self.bits & 0x1f) as u8)
}
}
#[doc = "ADC Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "ADC Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`adc_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AdcCalSpec;
impl crate::RegisterSpec for AdcCalSpec {
type Ux = u32;

16
va416xx/src/sysconfig/analog_cntl.rs
View File

@ -133,90 +133,76 @@ impl R {
impl W {
#[doc = "Bit 0 - Test Mode"]
#[inline(always)]
#[must_use]
pub fn tmosc(&mut self) -> TmoscW<AnalogCntlSpec> {
TmoscW::new(self, 0)
}
#[doc = "Bit 1 - Test Mode"]
#[inline(always)]
#[must_use]
pub fn tmpokdis(&mut self) -> TmpokdisW<AnalogCntlSpec> {
TmpokdisW::new(self, 1)
}
#[doc = "Bit 2 - Test Mode"]
#[inline(always)]
#[must_use]
pub fn tm_adcmux_n(&mut self) -> TmAdcmuxNW<AnalogCntlSpec> {
TmAdcmuxNW::new(self, 2)
}
#[doc = "Bit 3 - Test Mode"]
#[inline(always)]
#[must_use]
pub fn tm_adcmux_p(&mut self) -> TmAdcmuxPW<AnalogCntlSpec> {
TmAdcmuxPW::new(self, 3)
}
#[doc = "Bit 4 - Test Mode"]
#[inline(always)]
#[must_use]
pub fn tmratio(&mut self) -> TmratioW<AnalogCntlSpec> {
TmratioW::new(self, 4)
}
#[doc = "Bits 5:6 - Test Mode"]
#[inline(always)]
#[must_use]
pub fn tmatomux(&mut self) -> TmatomuxW<AnalogCntlSpec> {
TmatomuxW::new(self, 5)
}
#[doc = "Bits 9:12 - Number of clocks for sample time"]
#[inline(always)]
#[must_use]
pub fn adc_stest(&mut self) -> AdcStestW<AnalogCntlSpec> {
AdcStestW::new(self, 9)
}
#[doc = "Bit 14 - Enable normal test clock"]
#[inline(always)]
#[must_use]
pub fn rclk_pos_en(&mut self) -> RclkPosEnW<AnalogCntlSpec> {
RclkPosEnW::new(self, 14)
}
#[doc = "Bit 15 - Enable inverted test clock"]
#[inline(always)]
#[must_use]
pub fn rclk_neg_en(&mut self) -> RclkNegEnW<AnalogCntlSpec> {
RclkNegEnW::new(self, 15)
}
#[doc = "Bit 16 - Enable normal APB2CLK for test output"]
#[inline(always)]
#[must_use]
pub fn apb2clk_pos_en(&mut self) -> Apb2clkPosEnW<AnalogCntlSpec> {
Apb2clkPosEnW::new(self, 16)
}
#[doc = "Bit 17 - Enable inverted APB2CLK for test output"]
#[inline(always)]
#[must_use]
pub fn apb2clk_neg_en(&mut self) -> Apb2clkNegEnW<AnalogCntlSpec> {
Apb2clkNegEnW::new(self, 17)
}
#[doc = "Bit 18 - Enables pull down on analog pads"]
#[inline(always)]
#[must_use]
pub fn tm_analog_pd_en(&mut self) -> TmAnalogPdEnW<AnalogCntlSpec> {
TmAnalogPdEnW::new(self, 18)
}
#[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"]
#[inline(always)]
#[must_use]
pub fn jmp2boot(&mut self) -> Jmp2bootW<AnalogCntlSpec> {
Jmp2bootW::new(self, 19)
}
#[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"]
#[inline(always)]
#[must_use]
pub fn skipboot(&mut self) -> SkipbootW<AnalogCntlSpec> {
SkipbootW::new(self, 20)
}
}
#[doc = "Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`analog_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`analog_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Analog Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`analog_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`analog_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AnalogCntlSpec;
impl crate::RegisterSpec for AnalogCntlSpec {
type Ux = u32;

2
va416xx/src/sysconfig/areg_cal.rs
View File

@ -9,7 +9,7 @@ impl R {
AregCalR::new((self.bits & 0x01ff) as u16)
}
}
#[doc = "Analog LDO Regulator Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`areg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Analog LDO Regulator Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`areg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AregCalSpec;
impl crate::RegisterSpec for AregCalSpec {
type Ux = u32;

2
va416xx/src/sysconfig/bg_cal.rs
View File

@ -9,7 +9,7 @@ impl R {
BgCalR::new((self.bits & 7) as u8)
}
}
#[doc = "Bandgap Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Bandgap Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`bg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BgCalSpec;
impl crate::RegisterSpec for BgCalSpec {
type Ux = u32;

2
va416xx/src/sysconfig/dac0_cal.rs
View File

@ -9,7 +9,7 @@ impl R {
Dac0CalR::new((self.bits & 0x1f) as u8)
}
}
#[doc = "DAC0 Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac0_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "DAC0 Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dac0_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dac0CalSpec;
impl crate::RegisterSpec for Dac0CalSpec {
type Ux = u32;

2
va416xx/src/sysconfig/dac1_cal.rs
View File

@ -9,7 +9,7 @@ impl R {
Dac1CalR::new((self.bits & 0x1f) as u8)
}
}
#[doc = "DAC1 Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac1_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "DAC1 Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dac1_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Dac1CalSpec;
impl crate::RegisterSpec for Dac1CalSpec {
type Ux = u32;

2
va416xx/src/sysconfig/dreg_cal.rs
View File

@ -9,7 +9,7 @@ impl R {
DregCalR::new((self.bits & 0x01ff) as u16)
}
}
#[doc = "Digital LDO Regulator Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dreg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Digital LDO Regulator Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`dreg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DregCalSpec;
impl crate::RegisterSpec for DregCalSpec {
type Ux = u32;

8
va416xx/src/sysconfig/ebi_cfg0.rs
View File

@ -61,42 +61,36 @@ impl R {
impl W {
#[doc = "Bits 0:7 - Lower bound address for CEN0"]
#[inline(always)]
#[must_use]
pub fn addrlow0(&mut self) -> Addrlow0W<EbiCfg0Spec> {
Addrlow0W::new(self, 0)
}
#[doc = "Bits 8:15 - Upper bound address for CEN0"]
#[inline(always)]
#[must_use]
pub fn addrhigh0(&mut self) -> Addrhigh0W<EbiCfg0Spec> {
Addrhigh0W::new(self, 8)
}
#[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"]
#[inline(always)]
#[must_use]
pub fn cfgreadcycle(&mut self) -> CfgreadcycleW<EbiCfg0Spec> {
CfgreadcycleW::new(self, 16)
}
#[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"]
#[inline(always)]
#[must_use]
pub fn cfgwritecycle(&mut self) -> CfgwritecycleW<EbiCfg0Spec> {
CfgwritecycleW::new(self, 19)
}
#[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"]
#[inline(always)]
#[must_use]
pub fn cfgturnaroundcycle(&mut self) -> CfgturnaroundcycleW<EbiCfg0Spec> {
CfgturnaroundcycleW::new(self, 22)
}
#[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"]
#[inline(always)]
#[must_use]
pub fn cfgsize(&mut self) -> CfgsizeW<EbiCfg0Spec> {
CfgsizeW::new(self, 25)
}
}
#[doc = "EBI Config Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ebi_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ebi_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "EBI Config Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ebi_cfg0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ebi_cfg0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EbiCfg0Spec;
impl crate::RegisterSpec for EbiCfg0Spec {
type Ux = u32;

2
va416xx/src/sysconfig/ef_config.rs
View File

@ -79,7 +79,7 @@ impl R {
WmR::new(((self.bits >> 28) & 1) != 0)
}
}
#[doc = "EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "EFuse Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EfConfigSpec;
impl crate::RegisterSpec for EfConfigSpec {
type Ux = u32;

2
va416xx/src/sysconfig/ef_id0.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "EFuse ID0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "EFuse ID0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EfId0Spec;
impl crate::RegisterSpec for EfId0Spec {
type Ux = u32;

2
va416xx/src/sysconfig/ef_id1.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "EFuse ID1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "EFuse ID1 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ef_id1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EfId1Spec;
impl crate::RegisterSpec for EfId1Spec {
type Ux = u32;

2
va416xx/src/sysconfig/hbo_cal.rs
View File

@ -16,7 +16,7 @@ impl R {
OscCalR::new(((self.bits >> 3) & 1) != 0)
}
}
#[doc = "Heart Beat OSC Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hbo_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Heart Beat OSC Calibration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`hbo_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct HboCalSpec;
impl crate::RegisterSpec for HboCalSpec {
type Ux = u32;

8
va416xx/src/sysconfig/irq_enb.rs
View File

@ -61,42 +61,36 @@ impl R {
impl W {
#[doc = "Bit 0 - ROM Multi Bit Interrupt"]
#[inline(always)]
#[must_use]
pub fn rommbe(&mut self) -> RommbeW<IrqEnbSpec> {
RommbeW::new(self, 0)
}
#[doc = "Bit 1 - ROM Single Bit Interrupt"]
#[inline(always)]
#[must_use]
pub fn romsbe(&mut self) -> RomsbeW<IrqEnbSpec> {
RomsbeW::new(self, 1)
}
#[doc = "Bit 2 - RAM0 Multi Bit Interrupt"]
#[inline(always)]
#[must_use]
pub fn ram0mbe(&mut self) -> Ram0mbeW<IrqEnbSpec> {
Ram0mbeW::new(self, 2)
}
#[doc = "Bit 3 - RAM0 Single Bit Interrupt"]
#[inline(always)]
#[must_use]
pub fn ram0sbe(&mut self) -> Ram0sbeW<IrqEnbSpec> {
Ram0sbeW::new(self, 3)
}
#[doc = "Bit 4 - RAM1 Multi Bit Interrupt"]
#[inline(always)]
#[must_use]
pub fn ram1mbe(&mut self) -> Ram1mbeW<IrqEnbSpec> {
Ram1mbeW::new(self, 4)
}
#[doc = "Bit 5 - RAM1 Single Bit Interrupt"]
#[inline(always)]
#[must_use]
pub fn ram1sbe(&mut self) -> Ram1sbeW<IrqEnbSpec> {
Ram1sbeW::new(self, 5)
}
}
#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32;

2
va416xx/src/sysconfig/perid.rs
View File

@ -23,7 +23,7 @@ impl R {
PeripheralVerR::new(((self.bits >> 24) & 0xff) as u8)
}
}
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;

33
va416xx/src/sysconfig/peripheral_reset.rs
View File

@ -286,192 +286,161 @@ impl R {
impl W {
#[doc = "Bit 0 - Resetn of SPI0"]
#[inline(always)]
#[must_use]
pub fn spi0(&mut self) -> Spi0W<PeripheralResetSpec> {
Spi0W::new(self, 0)
}
#[doc = "Bit 1 - Resetn of SPI1"]
#[inline(always)]
#[must_use]
pub fn spi1(&mut self) -> Spi1W<PeripheralResetSpec> {
Spi1W::new(self, 1)
}
#[doc = "Bit 2 - Resetn of SPI2"]
#[inline(always)]
#[must_use]
pub fn spi2(&mut self) -> Spi2W<PeripheralResetSpec> {
Spi2W::new(self, 2)
}
#[doc = "Bit 3 - Resetn of SPI3"]
#[inline(always)]
#[must_use]
pub fn spi3(&mut self) -> Spi3W<PeripheralResetSpec> {
Spi3W::new(self, 3)
}
#[doc = "Bit 4 - Resetn of UART0"]
#[inline(always)]
#[must_use]
pub fn uart0(&mut self) -> Uart0W<PeripheralResetSpec> {
Uart0W::new(self, 4)
}
#[doc = "Bit 5 - Resetn of UART1"]
#[inline(always)]
#[must_use]
pub fn uart1(&mut self) -> Uart1W<PeripheralResetSpec> {
Uart1W::new(self, 5)
}
#[doc = "Bit 6 - Resetn of UART2"]
#[inline(always)]
#[must_use]
pub fn uart2(&mut self) -> Uart2W<PeripheralResetSpec> {
Uart2W::new(self, 6)
}
#[doc = "Bit 7 - Resetn of I2C0"]
#[inline(always)]
#[must_use]
pub fn i2c0(&mut self) -> I2c0W<PeripheralResetSpec> {
I2c0W::new(self, 7)
}
#[doc = "Bit 8 - Resetn of I2C1"]
#[inline(always)]
#[must_use]
pub fn i2c1(&mut self) -> I2c1W<PeripheralResetSpec> {
I2c1W::new(self, 8)
}
#[doc = "Bit 9 - Resetn of I2C2"]
#[inline(always)]
#[must_use]
pub fn i2c2(&mut self) -> I2c2W<PeripheralResetSpec> {
I2c2W::new(self, 9)
}
#[doc = "Bit 10 - Resetn of CAN0"]
#[inline(always)]
#[must_use]
pub fn can0(&mut self) -> Can0W<PeripheralResetSpec> {
Can0W::new(self, 10)
}
#[doc = "Bit 11 - Resetn of CAN1"]
#[inline(always)]
#[must_use]
pub fn can1(&mut self) -> Can1W<PeripheralResetSpec> {
Can1W::new(self, 11)
}
#[doc = "Bit 12 - Resetn of TRNG"]
#[inline(always)]
#[must_use]
pub fn trng(&mut self) -> TrngW<PeripheralResetSpec> {
TrngW::new(self, 12)
}
#[doc = "Bit 13 - Resetn of ADC"]
#[inline(always)]
#[must_use]
pub fn adc(&mut self) -> AdcW<PeripheralResetSpec> {
AdcW::new(self, 13)
}
#[doc = "Bit 14 - Resetn of DAC"]
#[inline(always)]
#[must_use]
pub fn dac(&mut self) -> DacW<PeripheralResetSpec> {
DacW::new(self, 14)
}
#[doc = "Bit 15 - Resetn of DMA"]
#[inline(always)]
#[must_use]
pub fn dma(&mut self) -> DmaW<PeripheralResetSpec> {
DmaW::new(self, 15)
}
#[doc = "Bit 16 - Resetn of EBI"]
#[inline(always)]
#[must_use]
pub fn ebi(&mut self) -> EbiW<PeripheralResetSpec> {
EbiW::new(self, 16)
}
#[doc = "Bit 17 - Resetn of Ethernet"]
#[inline(always)]
#[must_use]
pub fn eth(&mut self) -> EthW<PeripheralResetSpec> {
EthW::new(self, 17)
}
#[doc = "Bit 18 - Resetn of SpaceWire"]
#[inline(always)]
#[must_use]
pub fn spw(&mut self) -> SpwW<PeripheralResetSpec> {
SpwW::new(self, 18)
}
#[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"]
#[inline(always)]
#[must_use]
pub fn clkgen(&mut self) -> ClkgenW<PeripheralResetSpec> {
ClkgenW::new(self, 19)
}
#[doc = "Bit 20 - Resetn of IRQ Router"]
#[inline(always)]
#[must_use]
pub fn irq(&mut self) -> IrqW<PeripheralResetSpec> {
IrqW::new(self, 20)
}
#[doc = "Bit 21 - Resetn of IO CONFIG"]
#[inline(always)]
#[must_use]
pub fn ioconfig(&mut self) -> IoconfigW<PeripheralResetSpec> {
IoconfigW::new(self, 21)
}
#[doc = "Bit 22 - Resetn of UTILITY peripheral"]
#[inline(always)]
#[must_use]
pub fn utility(&mut self) -> UtilityW<PeripheralResetSpec> {
UtilityW::new(self, 22)
}
#[doc = "Bit 23 - Resetn of WDOG"]
#[inline(always)]
#[must_use]
pub fn wdog(&mut self) -> WdogW<PeripheralResetSpec> {
WdogW::new(self, 23)
}
#[doc = "Bit 24 - Resetn of PORTA"]
#[inline(always)]
#[must_use]
pub fn porta(&mut self) -> PortaW<PeripheralResetSpec> {
PortaW::new(self, 24)
}
#[doc = "Bit 25 - Resetn of PORTB"]
#[inline(always)]
#[must_use]
pub fn portb(&mut self) -> PortbW<PeripheralResetSpec> {
PortbW::new(self, 25)
}
#[doc = "Bit 26 - Resetn of PORTC"]
#[inline(always)]
#[must_use]
pub fn portc(&mut self) -> PortcW<PeripheralResetSpec> {
PortcW::new(self, 26)
}
#[doc = "Bit 27 - Resetn of PORTD"]
#[inline(always)]
#[must_use]
pub fn portd(&mut self) -> PortdW<PeripheralResetSpec> {
PortdW::new(self, 27)
}
#[doc = "Bit 28 - Resetn of PORTE"]
#[inline(always)]
#[must_use]
pub fn porte(&mut self) -> PorteW<PeripheralResetSpec> {
PorteW::new(self, 28)
}
#[doc = "Bit 29 - Resetn of PORTF"]
#[inline(always)]
#[must_use]
pub fn portf(&mut self) -> PortfW<PeripheralResetSpec> {
PortfW::new(self, 29)
}
#[doc = "Bit 30 - Resetn of PORTG"]
#[inline(always)]
#[must_use]
pub fn portg(&mut self) -> PortgW<PeripheralResetSpec> {
PortgW::new(self, 30)
}
}
#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`peripheral_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeripheralResetSpec;
impl crate::RegisterSpec for PeripheralResetSpec {
type Ux = u32;

3
va416xx/src/sysconfig/pmu_ctrl.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:1 - Select the POK detect level"]
#[inline(always)]
#[must_use]
pub fn lvl_slct(&mut self) -> LvlSlctW<PmuCtrlSpec> {
LvlSlctW::new(self, 0)
}
}
#[doc = "PMU Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "PMU Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pmu_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmu_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PmuCtrlSpec;
impl crate::RegisterSpec for PmuCtrlSpec {
type Ux = u32;

2
va416xx/src/sysconfig/procid.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "Processor ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`procid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Processor ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`procid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ProcidSpec;
impl crate::RegisterSpec for ProcidSpec {
type Ux = u32;

3
va416xx/src/sysconfig/ram0_mbe.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:15 - RAM0 Multi Bit Errors"]
#[inline(always)]
#[must_use]
pub fn count(&mut self) -> CountW<Ram0MbeSpec> {
CountW::new(self, 0)
}
}
#[doc = "Count of RAM0 EDAC Multi Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram0_mbe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram0_mbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Count of RAM0 EDAC Multi Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram0_mbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram0_mbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ram0MbeSpec;
impl crate::RegisterSpec for Ram0MbeSpec {
type Ux = u32;

3
va416xx/src/sysconfig/ram0_sbe.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"]
#[inline(always)]
#[must_use]
pub fn count(&mut self) -> CountW<Ram0SbeSpec> {
CountW::new(self, 0)
}
}
#[doc = "Count of RAM0 EDAC Single Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram0_sbe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram0_sbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Count of RAM0 EDAC Single Bit Errors\n\nYou can [`read`](crate::Reg::read) this register and get [`ram0_sbe::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram0_sbe::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Ram0SbeSpec;
impl crate::RegisterSpec for Ram0SbeSpec {
type Ux = u32;

4
va416xx/src/sysconfig/refresh_config_h.rs
View File

@ -25,18 +25,16 @@ impl R {
impl W {
#[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
#[inline(always)]
#[must_use]
pub fn divcount(&mut self) -> DivcountW<RefreshConfigHSpec> {
DivcountW::new(self, 0)
}
#[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."]
#[inline(always)]
#[must_use]
pub fn testmode(&mut self) -> TestmodeW<RefreshConfigHSpec> {
TestmodeW::new(self, 30)
}
}
#[doc = "Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config_h::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config_h::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config_h::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config_h::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RefreshConfigHSpec;
impl crate::RegisterSpec for RefreshConfigHSpec {
type Ux = u32;

3
va416xx/src/sysconfig/refresh_config_l.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"]
#[inline(always)]
#[must_use]
pub fn divcount(&mut self) -> DivcountW<RefreshConfigLSpec> {
DivcountW::new(self, 0)
}
}
#[doc = "Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config_l::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config_l::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::Reg::read) this register and get [`refresh_config_l::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`refresh_config_l::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RefreshConfigLSpec;
impl crate::RegisterSpec for RefreshConfigLSpec {
type Ux = u32;

3
va416xx/src/sysconfig/rom_prot.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bit 0 - ROM Write Enable Bit"]
#[inline(always)]
#[must_use]
pub fn wren(&mut self) -> WrenW<RomProtSpec> {
WrenW::new(self, 0)
}
}
#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_prot::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_prot::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomProtSpec;
impl crate::RegisterSpec for RomProtSpec {
type Ux = u32;

2
va416xx/src/sysconfig/rom_retries.rs
View File

@ -9,7 +9,7 @@ impl R {
CountR::new((self.bits & 0xff) as u8)
}
}
#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_retries::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_retries::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomRetriesSpec;
impl crate::RegisterSpec for RomRetriesSpec {
type Ux = u32;

4
va416xx/src/sysconfig/rom_scrub.rs
View File

@ -18,18 +18,16 @@ impl R {
impl W {
#[doc = "Bits 0:23 - Counter divide value"]
#[inline(always)]
#[must_use]
pub fn value(&mut self) -> ValueW<RomScrubSpec> {
ValueW::new(self, 0)
}
#[doc = "Bit 31 - Reset Counter"]
#[inline(always)]
#[must_use]
pub fn reset(&mut self) -> ResetW<RomScrubSpec> {
ResetW::new(self, 31)
}
}
#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_scrub::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_scrub::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RomScrubSpec;
impl crate::RegisterSpec for RomScrubSpec {
type Ux = u32;

7
va416xx/src/sysconfig/rst_stat.rs
View File

@ -59,36 +59,31 @@ impl R {
impl W {
#[doc = "Bit 0 - Power On Reset Status"]
#[inline(always)]
#[must_use]
pub fn por(&mut self) -> PorW<RstStatSpec> {
PorW::new(self, 0)
}
#[doc = "Bit 1 - External Reset Status"]
#[inline(always)]
#[must_use]
pub fn extrst(&mut self) -> ExtrstW<RstStatSpec> {
ExtrstW::new(self, 1)
}
#[doc = "Bit 2 - SYSRESETREQ Reset Status"]
#[inline(always)]
#[must_use]
pub fn sysrstreq(&mut self) -> SysrstreqW<RstStatSpec> {
SysrstreqW::new(self, 2)
}
#[doc = "Bit 3 - LOOKUP Reset Status"]
#[inline(always)]
#[must_use]
pub fn lookup(&mut self) -> LookupW<RstStatSpec> {
LookupW::new(self, 3)
}
#[doc = "Bit 4 - WATCHDOG Reset Status"]
#[inline(always)]
#[must_use]
pub fn watchdog(&mut self) -> WatchdogW<RstStatSpec> {
WatchdogW::new(self, 4)
}
}
#[doc = "System Reset Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "System Reset Status\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstStatSpec;
impl crate::RegisterSpec for RstStatSpec {
type Ux = u32;

5
va416xx/src/sysconfig/spw_m4_ctrl.rs
View File

@ -34,24 +34,21 @@ impl R {
impl W {
#[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"]
#[inline(always)]
#[must_use]
pub fn reg_wr_key(&mut self) -> RegWrKeyW<SpwM4CtrlSpec> {
RegWrKeyW::new(self, 0)
}
#[doc = "Bit 16 - SPW pad enable"]
#[inline(always)]
#[must_use]
pub fn spw_pad_en(&mut self) -> SpwPadEnW<SpwM4CtrlSpec> {
SpwPadEnW::new(self, 16)
}
#[doc = "Bit 17 - Lockup reset enable"]
#[inline(always)]
#[must_use]
pub fn lren(&mut self) -> LrenW<SpwM4CtrlSpec> {
LrenW::new(self, 17)
}
}
#[doc = "SPW M4 control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spw_m4_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spw_m4_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "SPW M4 control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spw_m4_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spw_m4_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SpwM4CtrlSpec;
impl crate::RegisterSpec for SpwM4CtrlSpec {
type Ux = u32;

3
va416xx/src/sysconfig/sw_clkdiv10.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"]
#[inline(always)]
#[must_use]
pub fn sw_clkdiv10(&mut self) -> SwClkdiv10W<SwClkdiv10Spec> {
SwClkdiv10W::new(self, 0)
}
}
#[doc = "Initial SpW Clock Divider Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_clkdiv10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_clkdiv10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Initial SpW Clock Divider Value\n\nYou can [`read`](crate::Reg::read) this register and get [`sw_clkdiv10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sw_clkdiv10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SwClkdiv10Spec;
impl crate::RegisterSpec for SwClkdiv10Spec {
type Ux = u32;

3
va416xx/src/sysconfig/tim_clk_enable.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:23 - Clock enable of a given TIMER"]
#[inline(always)]
#[must_use]
pub fn timers(&mut self) -> TimersW<TimClkEnableSpec> {
TimersW::new(self, 0)
}
}
#[doc = "TIM Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_clk_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "TIM Enable Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_clk_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TimClkEnableSpec;
impl crate::RegisterSpec for TimClkEnableSpec {
type Ux = u32;

3
va416xx/src/sysconfig/tim_reset.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:23 - Reset of a given TIMER"]
#[inline(always)]
#[must_use]
pub fn tim_reset(&mut self) -> TimResetW<TimResetSpec> {
TimResetW::new(self, 0)
}
}
#[doc = "TIM Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "TIM Reset Control\n\nYou can [`read`](crate::Reg::read) this register and get [`tim_reset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TimResetSpec;
impl crate::RegisterSpec for TimResetSpec {
type Ux = u32;

4
va416xx/src/sysconfig/wakeup_cnt.rs
View File

@ -25,18 +25,16 @@ impl R {
impl W {
#[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"]
#[inline(always)]
#[must_use]
pub fn wkup_cnt(&mut self) -> WkupCntW<WakeupCntSpec> {
WkupCntW::new(self, 0)
}
#[doc = "Bit 3 - Launch SLP mode in analog block"]
#[inline(always)]
#[must_use]
pub fn cntstrt(&mut self) -> CntstrtW<WakeupCntSpec> {
CntstrtW::new(self, 3)
}
}
#[doc = "Wakeup Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Wakeup Control\n\nYou can [`read`](crate::Reg::read) this register and get [`wakeup_cnt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wakeup_cnt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WakeupCntSpec;
impl crate::RegisterSpec for WakeupCntSpec {
type Ux = u32;