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regenerate PAC, va416xx v0.3.0

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This commit is contained in:
Robin Müller
2025-02-13 15:58:05 +01:00
parent 0c040515fe
commit 2c9ca004ce
517 changed files with 1376 additions and 2392 deletions
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2
va416xx/src/uart0/addr9.rs
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@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Address9 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Address9 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Addr9Spec;
impl crate::RegisterSpec for Addr9Spec {
type Ux = u32;

2
va416xx/src/uart0/addr9mask.rs
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@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Address9 Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Address9 Mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`addr9mask::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr9mask::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Addr9maskSpec;
impl crate::RegisterSpec for Addr9maskSpec {
type Ux = u32;

5
va416xx/src/uart0/clkscale.rs
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@ -27,24 +27,21 @@ impl R {
impl W {
#[doc = "Bits 0:5 - Fractional Divide (64ths)"]
#[inline(always)]
#[must_use]
pub fn frac(&mut self) -> FracW<ClkscaleSpec> {
FracW::new(self, 0)
}
#[doc = "Bits 6:23 - Integer Divide"]
#[inline(always)]
#[must_use]
pub fn int(&mut self) -> IntW<ClkscaleSpec> {
IntW::new(self, 6)
}
#[doc = "Bit 31 - Reset Baud Counter"]
#[inline(always)]
#[must_use]
pub fn reset(&mut self) -> ResetW<ClkscaleSpec> {
ResetW::new(self, 31)
}
}
#[doc = "Clock Scale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Clock Scale Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ClkscaleSpec;
impl crate::RegisterSpec for ClkscaleSpec {
type Ux = u32;

13
va416xx/src/uart0/ctrl.rs
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@ -106,72 +106,61 @@ impl R {
impl W {
#[doc = "Bit 0 - Parity Enable"]
#[inline(always)]
#[must_use]
pub fn paren(&mut self) -> ParenW<CtrlSpec> {
ParenW::new(self, 0)
}
#[doc = "Bit 1 - Parity Even/Odd(1/0)"]
#[inline(always)]
#[must_use]
pub fn pareven(&mut self) -> ParevenW<CtrlSpec> {
ParevenW::new(self, 1)
}
#[doc = "Bit 2 - Parity Sticky"]
#[inline(always)]
#[must_use]
pub fn parstk(&mut self) -> ParstkW<CtrlSpec> {
ParstkW::new(self, 2)
}
#[doc = "Bit 3 - Stop Bits 1/2(0/1)"]
#[inline(always)]
#[must_use]
pub fn stopbits(&mut self) -> StopbitsW<CtrlSpec> {
StopbitsW::new(self, 3)
}
#[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"]
#[inline(always)]
#[must_use]
pub fn wordsize(&mut self) -> WordsizeW<CtrlSpec> {
WordsizeW::new(self, 4)
}
#[doc = "Bit 6 - Loopback Enable"]
#[inline(always)]
#[must_use]
pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
LoopbackW::new(self, 6)
}
#[doc = "Bit 7 - Loopback Block"]
#[inline(always)]
#[must_use]
pub fn loopbackblk(&mut self) -> LoopbackblkW<CtrlSpec> {
LoopbackblkW::new(self, 7)
}
#[doc = "Bit 8 - Enable Auto CTS mode"]
#[inline(always)]
#[must_use]
pub fn autocts(&mut self) -> AutoctsW<CtrlSpec> {
AutoctsW::new(self, 8)
}
#[doc = "Bit 9 - Default RTSn value"]
#[inline(always)]
#[must_use]
pub fn defrts(&mut self) -> DefrtsW<CtrlSpec> {
DefrtsW::new(self, 9)
}
#[doc = "Bit 10 - Enable Auto RTS mode"]
#[inline(always)]
#[must_use]
pub fn autorts(&mut self) -> AutortsW<CtrlSpec> {
AutortsW::new(self, 10)
}
#[doc = "Bit 11 - Enable BAUD8 mode"]
#[inline(always)]
#[must_use]
pub fn baud8(&mut self) -> Baud8W<CtrlSpec> {
Baud8W::new(self, 11)
}
}
#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec;
impl crate::RegisterSpec for CtrlSpec {
type Ux = u32;

2
va416xx/src/uart0/data.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Data In/Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Data In/Out Register\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DataSpec;
impl crate::RegisterSpec for DataSpec {
type Ux = u32;

4
va416xx/src/uart0/enable.rs
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@ -25,18 +25,16 @@ impl R {
impl W {
#[doc = "Bit 0 - Rx Enable"]
#[inline(always)]
#[must_use]
pub fn rxenable(&mut self) -> RxenableW<EnableSpec> {
RxenableW::new(self, 0)
}
#[doc = "Bit 1 - Tx Enable"]
#[inline(always)]
#[must_use]
pub fn txenable(&mut self) -> TxenableW<EnableSpec> {
TxenableW::new(self, 1)
}
}
#[doc = "Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EnableSpec;
impl crate::RegisterSpec for EnableSpec {
type Ux = u32;

4
va416xx/src/uart0/fifo_clr.rs
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@ -7,18 +7,16 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Clear Rx FIFO"]
#[inline(always)]
#[must_use]
pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
RxfifoW::new(self, 0)
}
#[doc = "Bit 1 - Clear Tx FIFO"]
#[inline(always)]
#[must_use]
pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
TxfifoW::new(self, 1)
}
}
#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoClrSpec;
impl crate::RegisterSpec for FifoClrSpec {
type Ux = u32;

9
va416xx/src/uart0/irq_enb.rs
View File

@ -70,48 +70,41 @@ impl R {
impl W {
#[doc = "Bit 0 - RX Interrupt"]
#[inline(always)]
#[must_use]
pub fn irq_rx(&mut self) -> IrqRxW<IrqEnbSpec> {
IrqRxW::new(self, 0)
}
#[doc = "Bit 1 - RX Status Interrupt"]
#[inline(always)]
#[must_use]
pub fn irq_rx_status(&mut self) -> IrqRxStatusW<IrqEnbSpec> {
IrqRxStatusW::new(self, 1)
}
#[doc = "Bit 2 - RX Timeout Interrupt"]
#[inline(always)]
#[must_use]
pub fn irq_rx_to(&mut self) -> IrqRxToW<IrqEnbSpec> {
IrqRxToW::new(self, 2)
}
#[doc = "Bit 4 - TX Interrupt"]
#[inline(always)]
#[must_use]
pub fn irq_tx(&mut self) -> IrqTxW<IrqEnbSpec> {
IrqTxW::new(self, 4)
}
#[doc = "Bit 5 - TX Status Interrupt"]
#[inline(always)]
#[must_use]
pub fn irq_tx_status(&mut self) -> IrqTxStatusW<IrqEnbSpec> {
IrqTxStatusW::new(self, 5)
}
#[doc = "Bit 6 - TX Empty Interrupt"]
#[inline(always)]
#[must_use]
pub fn irq_tx_empty(&mut self) -> IrqTxEmptyW<IrqEnbSpec> {
IrqTxEmptyW::new(self, 6)
}
#[doc = "Bit 7 - TX CTS Change Interrupt"]
#[inline(always)]
#[must_use]
pub fn irq_tx_cts(&mut self) -> IrqTxCtsW<IrqEnbSpec> {
IrqTxCtsW::new(self, 7)
}
}
#[doc = "IRQ Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "IRQ Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32;

2
va416xx/src/uart0/perid.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;

2
va416xx/src/uart0/rxfifoirqtrg.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxfifoirqtrgSpec;
impl crate::RegisterSpec for RxfifoirqtrgSpec {
type Ux = u32;

2
va416xx/src/uart0/rxfifortstrg.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifortstrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifortstrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifortstrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifortstrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxfifortstrgSpec;
impl crate::RegisterSpec for RxfifortstrgSpec {
type Ux = u32;

2
va416xx/src/uart0/rxstatus.rs
View File

@ -79,7 +79,7 @@ impl R {
RxrtsnR::new(((self.bits >> 15) & 1) != 0)
}
}
#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxstatusSpec;
impl crate::RegisterSpec for RxstatusSpec {
type Ux = u32;

2
va416xx/src/uart0/state.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "Internal STATE of UART Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Internal STATE of UART Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StateSpec;
impl crate::RegisterSpec for StateSpec {
type Ux = u32;

2
va416xx/src/uart0/txbreak.rs
View File

@ -6,7 +6,7 @@ impl core::fmt::Debug for crate::generic::Reg<TxbreakSpec> {
}
}
impl W {}
#[doc = "Break Transmit Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbreak::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Break Transmit Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbreak::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxbreakSpec;
impl crate::RegisterSpec for TxbreakSpec {
type Ux = u32;

2
va416xx/src/uart0/txfifoirqtrg.rs
View File

@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxfifoirqtrgSpec;
impl crate::RegisterSpec for TxfifoirqtrgSpec {
type Ux = u32;

2
va416xx/src/uart0/txstatus.rs
View File

@ -37,7 +37,7 @@ impl R {
TxctsnR::new(((self.bits >> 15) & 1) != 0)
}
}
#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TxstatusSpec;
impl crate::RegisterSpec for TxstatusSpec {
type Ux = u32;