somethings wrong

va416xx-hal/src/clock.rs

@@ -494,7 +494,7 @@ pub struct Clocks {
 
 impl Clocks {
     /// Returns the frequency of the HBO clock
-    pub fn hbo(&self) -> Hertz {
+    pub const fn hbo(&self) -> Hertz {
         HBO_FREQ
     }
 
@@ -504,23 +504,23 @@ impl Clocks {
     }
 
     /// Returns system clock divied by 2.
-    pub fn apb1(&self) -> Hertz {
+    pub const fn apb1(&self) -> Hertz {
         self.apb1
     }
 
     /// Returns system clock divied by 4.
-    pub fn apb2(&self) -> Hertz {
+    pub const fn apb2(&self) -> Hertz {
         self.apb2
     }
 
     /// Returns the system (core) frequency
-    pub fn sysclk(&self) -> Hertz {
+    pub const fn sysclk(&self) -> Hertz {
         self.sysclk
     }
 
     /// Returns the ADC clock frequency which has a separate divider.
     #[cfg(not(feature = "va41628"))]
-    pub fn adc_clk(&self) -> Hertz {
+    pub const fn adc_clk(&self) -> Hertz {
         self.adc_clk
     }
 }

va416xx-hal/src/timer.rs

@@ -169,6 +169,14 @@ macro_rules! tim_markers {
     };
 }
 
+pub const fn const_clock<Tim: ValidTim + ?Sized>(_: &Tim, clocks: &Clocks) -> Hertz {
+    if Tim::TIM_ID <= 15 {
+        clocks.apb1()
+    } else {
+        clocks.apb2()
+    }
+}
+
 tim_markers!(
     (pac::Tim0, 0, pac::Interrupt::TIM0),
     (pac::Tim1, 1, pac::Interrupt::TIM1),
@@ -328,14 +336,14 @@ valid_pin_and_tims!(
 ///
 /// Only the bit related to the corresponding TIM peripheral is modified
 #[inline]
-fn assert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) {
+pub fn assert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) {
     syscfg
         .tim_reset()
         .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << tim_id as u32)) })
 }
 
 #[inline]
-fn deassert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) {
+pub fn deassert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) {
     syscfg
         .tim_reset()
         .modify(|r, w| unsafe { w.bits(r.bits() | (1 << tim_id as u32)) })
@@ -481,7 +489,7 @@ pub struct CountdownTimer<TIM: ValidTim> {
 }
 
 #[inline]
-fn enable_tim_clk(syscfg: &mut pac::Sysconfig, idx: u8) {
+pub fn enable_tim_clk(syscfg: &mut pac::Sysconfig, idx: u8) {
     syscfg
         .tim_clk_enable()
         .modify(|r, w| unsafe { w.bits(r.bits() | (1 << idx)) });
@@ -581,6 +589,7 @@ impl<Tim: ValidTim> CountdownTimer<Tim> {
         self.curr_freq = timeout.into();
         self.rst_val = self.clock.raw() / self.curr_freq.raw();
         self.set_reload(self.rst_val);
+        // Decrementing counter, to set the reset value.
         self.set_count(0);
     }