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This commit is contained in:
parent
f8a1a56c41
commit
4a9d08663d
@ -1,5 +1,5 @@
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[package]
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name = "embassy"
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name = "embassy-example"
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version = "0.1.0"
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edition = "2021"
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@ -12,12 +12,17 @@ panic-rtt-target = { version = "0.1" }
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critical-section = "1"
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embassy-sync = { version = "0.6.0" }
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embassy-time = { version = "0.3.2", features = ["tick-hz-32_768"] }
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embassy-time = { version = "0.3.2", features = ["tick-hz-1_000"] }
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embassy-time-driver = { version = "0.1" }
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[dependencies.embassy-executor]
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version = "0.6.0"
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features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "integrated-timers"]
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features = [
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"arch-cortex-m",
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"executor-thread",
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"executor-interrupt",
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"integrated-timers",
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]
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[dependencies.va416xx-hal]
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path = "../../va416xx-hal"
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@ -2,21 +2,50 @@
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use core::{
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cell::Cell,
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mem, ptr,
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sync::atomic::{AtomicU32, AtomicU8, Ordering}, u32,
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sync::atomic::{AtomicU32, AtomicU8, Ordering},
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};
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use critical_section::CriticalSection;
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use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
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use embassy_sync::blocking_mutex::Mutex;
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use embassy_time_driver::{time_driver_impl, AlarmHandle, Driver};
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use va416xx_hal::pac;
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use embassy_time_driver::{time_driver_impl, AlarmHandle, Driver, TICK_HZ};
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use va416xx_hal::{
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clock::Clocks,
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enable_interrupt,
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pac::{self, interrupt},
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pwm::{assert_tim_reset, deassert_tim_reset, enable_tim_clk, ValidTim},
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};
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fn alarm_tim() -> &'static pac::tim0::RegisterBlock {
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unsafe { &*pac::Tim23::ptr() }
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pub type TimekeeperClk = pac::Tim15;
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pub type AlarmClk0 = pac::Tim14;
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pub type AlarmClk1 = pac::Tim13;
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pub type AlarmClk2 = pac::Tim12;
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/// This has to be called to initiate the time driver for embassy.
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pub fn init(
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syscfg: &mut pac::Sysconfig,
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timekeeper: TimekeeperClk,
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alarm: AlarmClk0,
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clocks: &Clocks,
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) {
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DRIVER.init(syscfg, timekeeper, alarm, clocks)
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}
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fn timekeeping_tim() -> &'static pac::tim0::RegisterBlock {
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unsafe { &*pac::Tim23::ptr() }
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const fn alarm_tim(idx: usize) -> &'static pac::tim0::RegisterBlock {
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// Safety: This is a memory-mapped peripheral.
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match idx {
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0 => unsafe { &*AlarmClk0::ptr() },
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1 => unsafe { &*AlarmClk1::ptr() },
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2 => unsafe { &*AlarmClk2::ptr() },
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_ => {
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panic!("invalid alarm timer index")
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}
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}
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}
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const fn timekeeping_tim() -> &'static pac::tim0::RegisterBlock {
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// Safety: This is a memory-mapped peripheral.
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unsafe { &*TimekeeperClk::ptr() }
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}
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struct AlarmState {
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@ -41,36 +70,92 @@ impl AlarmState {
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unsafe impl Send for AlarmState {}
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const ALARM_COUNT: usize = 1;
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// Margin value which is used when detecting whether an alarm should fire soon.
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const TIMER_MARGIN: u64 = 0xc000_0000;
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pub struct EmbassyVa416xxTimeDriver {
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pub struct TimerDriverEmbassy {
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periods: AtomicU32,
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alarm_count: AtomicU8,
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/// Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled.
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alarms: Mutex<CriticalSectionRawMutex, [AlarmState; ALARM_COUNT]>,
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}
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impl EmbassyVa416xxTimeDriver {
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impl TimerDriverEmbassy {
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fn init(
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&self,
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syscfg: &mut pac::Sysconfig,
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timekeeper: TimekeeperClk,
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alarm_tim: AlarmClk0,
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clocks: &Clocks,
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) {
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enable_tim_clk(syscfg, TimekeeperClk::TIM_ID);
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assert_tim_reset(syscfg, TimekeeperClk::TIM_ID);
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cortex_m::asm::nop();
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cortex_m::asm::nop();
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deassert_tim_reset(syscfg, TimekeeperClk::TIM_ID);
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let rst_value = TimekeeperClk::clock(clocks).raw() / TICK_HZ as u32 - 1;
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// Safety: We have a valid instance of the tim peripheral.
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timekeeper
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.rst_value()
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.write(|w| unsafe { w.bits(rst_value) });
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//timekeeper
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//.cnt_value()
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//.write(|w| unsafe { w.bits(rst_value) });
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// Switch on. Timekeeping should always be done.
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timekeeper.ctrl().modify(|_, w| {
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w.irq_enb().set_bit();
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w.enable().set_bit()
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});
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unsafe {
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enable_interrupt(TimekeeperClk::IRQ);
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}
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enable_tim_clk(syscfg, AlarmClk0::TIM_ID);
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assert_tim_reset(syscfg, AlarmClk0::TIM_ID);
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cortex_m::asm::nop();
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cortex_m::asm::nop();
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deassert_tim_reset(syscfg, AlarmClk0::TIM_ID);
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// Explicitely disable alarm timer until needed.
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alarm_tim.ctrl().modify(|_, w| {
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w.irq_enb().clear_bit();
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w.enable().clear_bit()
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});
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// Enable general interrupts. The IRQ enable of the peripheral remains cleared.
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unsafe {
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enable_interrupt(AlarmClk0::IRQ);
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}
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}
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fn on_interrupt_timekeeping(&self) {
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self.next_period();
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}
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fn on_interrupt_alarm(&self, idx: usize) {
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critical_section::with(|cs| {
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let alarm = &self.alarms.borrow(cs)[idx];
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let at = alarm.timestamp.get();
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let period = self.periods.load(Ordering::Relaxed);
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let t = (period as u64) << 32;
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if at < t + u32::MAX as u64 {
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//alarm_tim().
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// just enable it. `set_alarm` has already set the correct CC val.
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alarm_tim().ctrl().modify(|_, w| w.irq_enb().set_bit());
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}
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})
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critical_section::with(|cs| self.trigger_alarm(idx, cs))
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}
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fn next_period(&self) {
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self.periods.fetch_add(1, Ordering::Release);
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let period = self.periods.fetch_add(1, Ordering::AcqRel) + 1;
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critical_section::with(|cs| {
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for i in 0..ALARM_COUNT {
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let alarm = &self.alarms.borrow(cs)[i];
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let at = alarm.timestamp.get();
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let t = (period as u64) << 32;
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if at < t + TIMER_MARGIN {
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//let rst_val = alarm_tim(i).rst_value().read().bits();
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// alarm_tim(i).cnt_value()
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//alarm_tim(i)
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//.cnt_value()
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//.write(|w| unsafe { w.bits(rst_val) });
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alarm_tim(i).ctrl().modify(|_, w| {
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w.irq_enb().set_bit();
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w.enable().set_bit()
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});
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}
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}
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})
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}
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fn get_alarm<'a>(&'a self, cs: CriticalSection<'a>, alarm: AlarmHandle) -> &'a AlarmState {
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@ -80,8 +165,10 @@ impl EmbassyVa416xxTimeDriver {
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}
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fn trigger_alarm(&self, n: usize, cs: CriticalSection) {
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let r = alarm_tim();
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r.ctrl().modify(|_, w| w.irq_enb().clear_bit());
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alarm_tim(n).ctrl().modify(|_, w| {
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w.irq_enb().clear_bit();
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w.enable().clear_bit()
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});
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let alarm = &self.alarms.borrow(cs)[n];
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// Setting the maximum value disables the alarm.
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@ -97,7 +184,7 @@ impl EmbassyVa416xxTimeDriver {
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}
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}
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impl Driver for EmbassyVa416xxTimeDriver {
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impl Driver for TimerDriverEmbassy {
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fn now(&self) -> u64 {
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let mut period1: u32;
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let mut period2: u32;
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@ -107,9 +194,10 @@ impl Driver for EmbassyVa416xxTimeDriver {
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// no instructions can be reordered before the load.
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period1 = self.periods.load(Ordering::Acquire);
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counter_val = timekeeping_tim().cnt_value().read().bits();
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counter_val = timekeeping_tim().rst_value().read().bits()
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- timekeeping_tim().cnt_value().read().bits();
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period2 = self.periods.load(Ordering::Acquire);
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period2 = self.periods.load(Ordering::Relaxed);
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if period1 == period2 {
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break;
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}
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@ -145,48 +233,52 @@ impl Driver for EmbassyVa416xxTimeDriver {
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fn set_alarm(&self, alarm: embassy_time_driver::AlarmHandle, timestamp: u64) -> bool {
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critical_section::with(|cs| {
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let n = alarm.id() as _;
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let n = alarm.id();
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let alarm = self.get_alarm(cs, alarm);
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alarm.timestamp.set(timestamp);
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let r = alarm_tim();
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let alarm_tim = alarm_tim(n.into());
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let t = self.now();
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if timestamp <= t {
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r.ctrl().modify(|_, w| w.irq_enb().clear_bit());
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alarm_tim.ctrl().modify(|_, w| {
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w.irq_enb().clear_bit();
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w.enable().clear_bit()
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});
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alarm.timestamp.set(u64::MAX);
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return false;
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}
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// If it hasn't triggered yet, setup it in the compare channel.
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// If it hasn't triggered yet, setup the relevant reset value, regardless of whether
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// the interrupts are enabled or not. When they are enabled at a later point, the
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// right value is already set.
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// Write the CC value regardless of whether we're going to enable it now or not.
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// This way, when we enable it later, the right value is already set.
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// nrf52 docs say:
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// If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event.
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// To workaround this, we never write a timestamp smaller than N+3.
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// N+2 is not safe because rtc can tick from N to N+1 between calling now() and writing cc.
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//
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// It is impossible for rtc to tick more than once because
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// - this code takes less time than 1 tick
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// - it runs with interrupts disabled so nothing else can preempt it.
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// If the timestamp is in the next few ticks, add a bit of buffer to be sure the alarm
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// is not missed.
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//
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// This means that an alarm can be delayed for up to 2 ticks (from t+1 to t+3), but this is allowed
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// by the Alarm trait contract. What's not allowed is triggering alarms *before* their scheduled time,
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// and we don't do that here.
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let safe_timestamp = timestamp.max(t + 3);
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r.cc[n].write(|w| unsafe { w.bits(safe_timestamp as u32 & 0xFFFFFF) });
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alarm_tim
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.rst_value()
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.write(|w| unsafe { w.bits((safe_timestamp & u32::MAX as u64) as u32) });
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let diff = timestamp - t;
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if diff < 0xc00000 {
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r.intenset.write(|w| unsafe { w.bits(compare_n(n)) });
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if diff < TIMER_MARGIN {
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alarm_tim.ctrl().modify(|_, w| {
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w.irq_enb().set_bit();
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w.enable().set_bit()
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});
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} else {
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// If it's too far in the future, don't setup the compare channel yet.
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// It will be setup later by `next_period`.
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r.intenclr.write(|w| unsafe { w.bits(compare_n(n)) });
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// If it's too far in the future, don't enable timer yet.
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// It will be enabled later by `next_period`.
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alarm_tim.ctrl().modify(|_, w| {
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w.irq_enb().clear_bit();
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w.enable().clear_bit()
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});
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}
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true
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@ -195,8 +287,20 @@ impl Driver for EmbassyVa416xxTimeDriver {
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}
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time_driver_impl!(
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static DRIVER: EmbassyVa416xxTimeDriver = EmbassyVa416xxTimeDriver {
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static DRIVER: TimerDriverEmbassy = TimerDriverEmbassy {
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periods: AtomicU32::new(0),
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alarm_count: AtomicU8::new(0),
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alarms: Mutex::const_new(CriticalSectionRawMutex::new(), [AlarmState::new(); ALARM_COUNT])
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});
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#[interrupt]
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#[allow(non_snake_case)]
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fn TIM15() {
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DRIVER.on_interrupt_timekeeping()
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}
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#[interrupt]
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#[allow(non_snake_case)]
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fn TIM14() {
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DRIVER.on_interrupt_alarm(0)
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}
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|
@ -1,23 +1,36 @@
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#![no_std]
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#![no_main]
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use cortex_m::asm;
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use embassy_executor::Spawner;
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use embassy_time::Timer;
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use embedded_hal::digital::StatefulOutputPin;
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use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use va416xx_hal::{gpio::PinsG, pac};
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use va416xx_hal::{gpio::PinsG, pac, prelude::*, time::Hertz};
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const EXTCLK_FREQ: u32 = 40_000_000;
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// main is itself an async function.
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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rtt_init_print!();
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rprintln!("VA416xx RTT Demo");
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rprintln!("VA416xx Embassy Demo");
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let mut dp = pac::Peripherals::take().unwrap();
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// Initialize the systick interrupt & obtain the token to prove that we did
|
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// Use the external clock connected to XTAL_N.
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let clocks = dp
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.clkgen
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.constrain()
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.xtal_n_clk_with_src_freq(Hertz::from_raw(EXTCLK_FREQ))
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.freeze(&mut dp.sysconfig)
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.unwrap();
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embassy_example::init(&mut dp.sysconfig, dp.tim15, dp.tim14, &clocks);
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let portg = PinsG::new(&mut dp.sysconfig, dp.portg);
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let mut led = portg.pg5.into_readable_push_pull_output();
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loop {
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Timer::after_millis(200).await;
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Timer::after_millis(2000).await;
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led.toggle().ok();
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}
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||||
}
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|
@ -494,7 +494,7 @@ pub struct Clocks {
|
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|
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impl Clocks {
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/// Returns the frequency of the HBO clock
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pub fn hbo(&self) -> Hertz {
|
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pub const fn hbo(&self) -> Hertz {
|
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HBO_FREQ
|
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}
|
||||
|
||||
@ -504,23 +504,23 @@ impl Clocks {
|
||||
}
|
||||
|
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/// Returns system clock divied by 2.
|
||||
pub fn apb1(&self) -> Hertz {
|
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pub const fn apb1(&self) -> Hertz {
|
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self.apb1
|
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}
|
||||
|
||||
/// Returns system clock divied by 4.
|
||||
pub fn apb2(&self) -> Hertz {
|
||||
pub const fn apb2(&self) -> Hertz {
|
||||
self.apb2
|
||||
}
|
||||
|
||||
/// Returns the system (core) frequency
|
||||
pub fn sysclk(&self) -> Hertz {
|
||||
pub const fn sysclk(&self) -> Hertz {
|
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self.sysclk
|
||||
}
|
||||
|
||||
/// Returns the ADC clock frequency which has a separate divider.
|
||||
#[cfg(not(feature = "va41628"))]
|
||||
pub fn adc_clk(&self) -> Hertz {
|
||||
pub const fn adc_clk(&self) -> Hertz {
|
||||
self.adc_clk
|
||||
}
|
||||
}
|
||||
|
@ -169,6 +169,14 @@ macro_rules! tim_markers {
|
||||
};
|
||||
}
|
||||
|
||||
pub const fn const_clock<Tim: ValidTim + ?Sized>(_: &Tim, clocks: &Clocks) -> Hertz {
|
||||
if Tim::TIM_ID <= 15 {
|
||||
clocks.apb1()
|
||||
} else {
|
||||
clocks.apb2()
|
||||
}
|
||||
}
|
||||
|
||||
tim_markers!(
|
||||
(pac::Tim0, 0, pac::Interrupt::TIM0),
|
||||
(pac::Tim1, 1, pac::Interrupt::TIM1),
|
||||
@ -328,14 +336,14 @@ valid_pin_and_tims!(
|
||||
///
|
||||
/// Only the bit related to the corresponding TIM peripheral is modified
|
||||
#[inline]
|
||||
fn assert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) {
|
||||
pub fn assert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) {
|
||||
syscfg
|
||||
.tim_reset()
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << tim_id as u32)) })
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn deassert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) {
|
||||
pub fn deassert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) {
|
||||
syscfg
|
||||
.tim_reset()
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << tim_id as u32)) })
|
||||
@ -481,7 +489,7 @@ pub struct CountdownTimer<TIM: ValidTim> {
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn enable_tim_clk(syscfg: &mut pac::Sysconfig, idx: u8) {
|
||||
pub fn enable_tim_clk(syscfg: &mut pac::Sysconfig, idx: u8) {
|
||||
syscfg
|
||||
.tim_clk_enable()
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << idx)) });
|
||||
@ -581,6 +589,7 @@ impl<Tim: ValidTim> CountdownTimer<Tim> {
|
||||
self.curr_freq = timeout.into();
|
||||
self.rst_val = self.clock.raw() / self.curr_freq.raw();
|
||||
self.set_reload(self.rst_val);
|
||||
// Decrementing counter, to set the reset value.
|
||||
self.set_count(0);
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user