From 5d1740efeaf7a64fa10a56ecd8cca84c46b6c9e0 Mon Sep 17 00:00:00 2001 From: Robin Mueller Date: Tue, 7 Dec 2021 00:31:51 +0100 Subject: [PATCH] Init Commit Monorepo for Rust support of VA416XX family of radiation hardened MCUs --- .cargo/def-config.toml | 40 + .github/workflows/ci.yml | 52 + .gitignore | 16 + .gitmodules | 0 Cargo.toml | 26 + LICENSE-APACHE | 201 + NOTICE | 3 + README.md | 109 + automation/Dockerfile | 13 + automation/Jenkinsfile | 43 + examples/simple/Cargo.toml | 18 + examples/simple/examples/blinky-pac.rs | 33 + examples/simple/examples/blinky.rs | 24 + .../simple/examples/peb1-accelerometer.rs | 88 + examples/simple/examples/pwm.rs | 81 + examples/simple/examples/rtt-log.rs | 36 + examples/simple/examples/spi.rs | 96 + examples/simple/examples/timer-ticks.rs | 68 + examples/simple/examples/uart.rs | 57 + examples/simple/examples/wdt.rs | 79 + examples/simple/src/lib.rs | 11 + examples/simple/src/main.rs | 13 + jlink-gdb.sh | 5 + jlink/JLinkSettings.JLinkScript | 62 + jlink/jlink-reva.gdb | 13 + jlink/jlink.gdb | 10 + memory.x | 23 + scripts/VA416xx_Series.yaml | 100 + scripts/prep-flash.gdb | 8 + scripts/prep-flash.sh | 3 + va416xx-hal/.cargo/config.toml | 38 + va416xx-hal/.cargo/def-config.toml | 39 + va416xx-hal/.gitignore | 2 + va416xx-hal/Cargo.toml | 43 + va416xx-hal/LICENSE-APACHE | 201 + va416xx-hal/NOTICE | 3 + va416xx-hal/README.md | 67 + va416xx-hal/jlink-gdb.sh | 5 + va416xx-hal/jlink/JLinkSettings.JLinkScript | 77 + va416xx-hal/jlink/jlink-reva.gdb | 13 + va416xx-hal/jlink/jlink.gdb | 11 + va416xx-hal/memory.x | 14 + va416xx-hal/src/clock.rs | 537 + va416xx-hal/src/gpio/dynpin.rs | 453 + va416xx-hal/src/gpio/mod.rs | 82 + va416xx-hal/src/gpio/pin.rs | 911 ++ va416xx-hal/src/gpio/reg.rs | 387 + va416xx-hal/src/i2c.rs | 904 ++ va416xx-hal/src/lib.rs | 46 + va416xx-hal/src/prelude.rs | 4 + va416xx-hal/src/pwm.rs | 388 + va416xx-hal/src/spi.rs | 978 ++ va416xx-hal/src/time.rs | 26 + va416xx-hal/src/timer.rs | 801 + va416xx-hal/src/typelevel.rs | 155 + va416xx-hal/src/uart.rs | 1014 ++ va416xx-hal/src/wdt.rs | 118 + va416xx/.github/bors.toml | 2 + va416xx/.github/workflows/changelog.yml | 20 + va416xx/.github/workflows/ci.yml | 64 + va416xx/.gitignore | 2 + va416xx/CHANGELOG.md | 21 + va416xx/Cargo.toml | 29 + va416xx/LICENSE-APACHE | 201 + va416xx/NOTICE | 3 + va416xx/README.md | 58 + va416xx/automation/Dockerfile | 11 + va416xx/automation/Jenkinsfile | 39 + va416xx/build.rs | 17 + va416xx/device.x | 197 + va416xx/gen-helper.sh | 42 + va416xx/src/adc.rs | 127 + va416xx/src/adc/ctrl.rs | 115 + va416xx/src/adc/fifo_clr.rs | 31 + va416xx/src/adc/fifo_data.rs | 29 + va416xx/src/adc/irq_clr.rs | 51 + va416xx/src/adc/irq_enb.rs | 130 + va416xx/src/adc/irq_end.rs | 64 + va416xx/src/adc/irq_raw.rs | 64 + va416xx/src/adc/perid.rs | 18 + va416xx/src/adc/rxfifoirqtrg.rs | 40 + va416xx/src/adc/status.rs | 29 + va416xx/src/can0.rs | 1710 ++ va416xx/src/can0/bmskb.rs | 105 + va416xx/src/can0/bmskx.rs | 63 + va416xx/src/can0/canec.rs | 55 + va416xx/src/can0/cediag.rs | 130 + va416xx/src/can0/cgcr.rs | 205 + va416xx/src/can0/cicen.rs | 55 + va416xx/src/can0/ciclr.rs | 55 + va416xx/src/can0/cien.rs | 55 + va416xx/src/can0/cipnd.rs | 55 + va416xx/src/can0/cnstat_cmb0.rs | 70 + va416xx/src/can0/cnstat_cmb1.rs | 70 + va416xx/src/can0/cnstat_cmb10.rs | 70 + va416xx/src/can0/cnstat_cmb11.rs | 70 + va416xx/src/can0/cnstat_cmb12.rs | 70 + va416xx/src/can0/cnstat_cmb13.rs | 70 + va416xx/src/can0/cnstat_cmb14.rs | 70 + va416xx/src/can0/cnstat_cmb2.rs | 70 + va416xx/src/can0/cnstat_cmb3.rs | 70 + va416xx/src/can0/cnstat_cmb4.rs | 70 + va416xx/src/can0/cnstat_cmb5.rs | 70 + va416xx/src/can0/cnstat_cmb6.rs | 70 + va416xx/src/can0/cnstat_cmb7.rs | 70 + va416xx/src/can0/cnstat_cmb8.rs | 70 + va416xx/src/can0/cnstat_cmb9.rs | 70 + va416xx/src/can0/cnstat_hcmb.rs | 70 + va416xx/src/can0/cstpnd.rs | 70 + va416xx/src/can0/ctim.rs | 85 + va416xx/src/can0/ctmr.rs | 31 + va416xx/src/can0/data0_cmb0.rs | 55 + va416xx/src/can0/data0_cmb1.rs | 55 + va416xx/src/can0/data0_cmb10.rs | 55 + va416xx/src/can0/data0_cmb11.rs | 55 + va416xx/src/can0/data0_cmb12.rs | 55 + va416xx/src/can0/data0_cmb13.rs | 55 + va416xx/src/can0/data0_cmb14.rs | 55 + va416xx/src/can0/data0_cmb2.rs | 55 + va416xx/src/can0/data0_cmb3.rs | 55 + va416xx/src/can0/data0_cmb4.rs | 55 + va416xx/src/can0/data0_cmb5.rs | 55 + va416xx/src/can0/data0_cmb6.rs | 55 + va416xx/src/can0/data0_cmb7.rs | 55 + va416xx/src/can0/data0_cmb8.rs | 55 + va416xx/src/can0/data0_cmb9.rs | 55 + va416xx/src/can0/data0_hcmb.rs | 55 + va416xx/src/can0/data1_cmb0.rs | 55 + va416xx/src/can0/data1_cmb1.rs | 55 + va416xx/src/can0/data1_cmb10.rs | 55 + va416xx/src/can0/data1_cmb11.rs | 55 + va416xx/src/can0/data1_cmb12.rs | 55 + va416xx/src/can0/data1_cmb13.rs | 55 + va416xx/src/can0/data1_cmb14.rs | 55 + va416xx/src/can0/data1_cmb2.rs | 55 + va416xx/src/can0/data1_cmb3.rs | 55 + va416xx/src/can0/data1_cmb4.rs | 55 + va416xx/src/can0/data1_cmb5.rs | 55 + va416xx/src/can0/data1_cmb6.rs | 55 + va416xx/src/can0/data1_cmb7.rs | 55 + va416xx/src/can0/data1_cmb8.rs | 55 + va416xx/src/can0/data1_cmb9.rs | 55 + va416xx/src/can0/data1_hcmb.rs | 55 + va416xx/src/can0/data2_cmb0.rs | 55 + va416xx/src/can0/data2_cmb1.rs | 55 + va416xx/src/can0/data2_cmb10.rs | 55 + va416xx/src/can0/data2_cmb11.rs | 55 + va416xx/src/can0/data2_cmb12.rs | 55 + va416xx/src/can0/data2_cmb13.rs | 55 + va416xx/src/can0/data2_cmb14.rs | 55 + va416xx/src/can0/data2_cmb2.rs | 55 + va416xx/src/can0/data2_cmb3.rs | 55 + va416xx/src/can0/data2_cmb4.rs | 55 + va416xx/src/can0/data2_cmb5.rs | 55 + va416xx/src/can0/data2_cmb6.rs | 55 + va416xx/src/can0/data2_cmb7.rs | 55 + va416xx/src/can0/data2_cmb8.rs | 55 + va416xx/src/can0/data2_cmb9.rs | 55 + va416xx/src/can0/data2_hcmb.rs | 55 + va416xx/src/can0/data3_cmb0.rs | 55 + va416xx/src/can0/data3_cmb1.rs | 55 + va416xx/src/can0/data3_cmb10.rs | 55 + va416xx/src/can0/data3_cmb11.rs | 55 + va416xx/src/can0/data3_cmb12.rs | 55 + va416xx/src/can0/data3_cmb13.rs | 55 + va416xx/src/can0/data3_cmb14.rs | 55 + va416xx/src/can0/data3_cmb2.rs | 55 + va416xx/src/can0/data3_cmb3.rs | 55 + va416xx/src/can0/data3_cmb4.rs | 55 + va416xx/src/can0/data3_cmb5.rs | 55 + va416xx/src/can0/data3_cmb6.rs | 55 + va416xx/src/can0/data3_cmb7.rs | 55 + va416xx/src/can0/data3_cmb8.rs | 55 + va416xx/src/can0/data3_cmb9.rs | 55 + va416xx/src/can0/data3_hcmb.rs | 55 + va416xx/src/can0/gmskb.rs | 105 + va416xx/src/can0/gmskx.rs | 63 + va416xx/src/can0/id0_cmb0.rs | 40 + va416xx/src/can0/id0_cmb1.rs | 40 + va416xx/src/can0/id0_cmb10.rs | 40 + va416xx/src/can0/id0_cmb11.rs | 40 + va416xx/src/can0/id0_cmb12.rs | 40 + va416xx/src/can0/id0_cmb13.rs | 40 + va416xx/src/can0/id0_cmb14.rs | 40 + va416xx/src/can0/id0_cmb2.rs | 40 + va416xx/src/can0/id0_cmb3.rs | 40 + va416xx/src/can0/id0_cmb4.rs | 40 + va416xx/src/can0/id0_cmb5.rs | 40 + va416xx/src/can0/id0_cmb6.rs | 40 + va416xx/src/can0/id0_cmb7.rs | 40 + va416xx/src/can0/id0_cmb8.rs | 40 + va416xx/src/can0/id0_cmb9.rs | 40 + va416xx/src/can0/id0_hcmb.rs | 40 + va416xx/src/can0/id1_cmb0.rs | 40 + va416xx/src/can0/id1_cmb1.rs | 40 + va416xx/src/can0/id1_cmb10.rs | 40 + va416xx/src/can0/id1_cmb11.rs | 40 + va416xx/src/can0/id1_cmb12.rs | 40 + va416xx/src/can0/id1_cmb13.rs | 40 + va416xx/src/can0/id1_cmb14.rs | 40 + va416xx/src/can0/id1_cmb2.rs | 40 + va416xx/src/can0/id1_cmb3.rs | 40 + va416xx/src/can0/id1_cmb4.rs | 40 + va416xx/src/can0/id1_cmb5.rs | 40 + va416xx/src/can0/id1_cmb6.rs | 40 + va416xx/src/can0/id1_cmb7.rs | 40 + va416xx/src/can0/id1_cmb8.rs | 40 + va416xx/src/can0/id1_cmb9.rs | 40 + va416xx/src/can0/id1_hcmb.rs | 40 + va416xx/src/can0/tstp_cmb0.rs | 40 + va416xx/src/can0/tstp_cmb1.rs | 40 + va416xx/src/can0/tstp_cmb10.rs | 40 + va416xx/src/can0/tstp_cmb11.rs | 40 + va416xx/src/can0/tstp_cmb12.rs | 40 + va416xx/src/can0/tstp_cmb13.rs | 40 + va416xx/src/can0/tstp_cmb14.rs | 40 + va416xx/src/can0/tstp_cmb2.rs | 40 + va416xx/src/can0/tstp_cmb3.rs | 40 + va416xx/src/can0/tstp_cmb4.rs | 40 + va416xx/src/can0/tstp_cmb5.rs | 40 + va416xx/src/can0/tstp_cmb6.rs | 40 + va416xx/src/can0/tstp_cmb7.rs | 40 + va416xx/src/can0/tstp_cmb8.rs | 40 + va416xx/src/can0/tstp_cmb9.rs | 40 + va416xx/src/can0/tstp_hcmb.rs | 40 + va416xx/src/clkgen.rs | 42 + va416xx/src/clkgen/ctrl0.rs | 220 + va416xx/src/clkgen/ctrl1.rs | 115 + va416xx/src/clkgen/stat.rs | 43 + va416xx/src/dac0.rs | 139 + va416xx/src/dac0/ctrl0.rs | 55 + va416xx/src/dac0/ctrl1.rs | 55 + va416xx/src/dac0/fifo_clr.rs | 31 + va416xx/src/dac0/fifo_data.rs | 31 + va416xx/src/dac0/irq_clr.rs | 51 + va416xx/src/dac0/irq_enb.rs | 130 + va416xx/src/dac0/irq_end.rs | 64 + va416xx/src/dac0/irq_raw.rs | 64 + va416xx/src/dac0/perid.rs | 18 + va416xx/src/dac0/status.rs | 29 + va416xx/src/dac0/txfifoirqtrg.rs | 40 + va416xx/src/dma.rs | 434 + va416xx/src/dma/alt_ctrl_base_ptr.rs | 40 + va416xx/src/dma/cfg.rs | 35 + va416xx/src/dma/chnl_enable_clr.rs | 85 + va416xx/src/dma/chnl_enable_set.rs | 85 + va416xx/src/dma/chnl_pri_alt_clr.rs | 85 + va416xx/src/dma/chnl_pri_alt_set.rs | 85 + va416xx/src/dma/chnl_priority_clr.rs | 51 + va416xx/src/dma/chnl_priority_set.rs | 85 + va416xx/src/dma/chnl_req_mask_clr.rs | 85 + va416xx/src/dma/chnl_req_mask_set.rs | 85 + va416xx/src/dma/chnl_sw_request.rs | 51 + va416xx/src/dma/chnl_useburst_clr.rs | 85 + va416xx/src/dma/chnl_useburst_set.rs | 85 + va416xx/src/dma/ctrl_base_ptr.rs | 40 + va416xx/src/dma/dma_active_clr.rs | 85 + va416xx/src/dma/dma_active_set.rs | 85 + va416xx/src/dma/dma_done_clr.rs | 85 + va416xx/src/dma/dma_done_set.rs | 85 + va416xx/src/dma/dma_req_status.rs | 85 + va416xx/src/dma/dma_sreq_status.rs | 85 + va416xx/src/dma/err_clr.rs | 40 + va416xx/src/dma/err_set.rs | 31 + va416xx/src/dma/integration_cfg.rs | 40 + va416xx/src/dma/periph_id_0.rs | 40 + va416xx/src/dma/periph_id_1.rs | 29 + va416xx/src/dma/periph_id_2.rs | 70 + va416xx/src/dma/periph_id_3.rs | 40 + va416xx/src/dma/periph_id_4.rs | 55 + va416xx/src/dma/primecell_id_0.rs | 40 + va416xx/src/dma/primecell_id_1.rs | 40 + va416xx/src/dma/primecell_id_2.rs | 40 + va416xx/src/dma/primecell_id_3.rs | 40 + va416xx/src/dma/stall_status.rs | 31 + va416xx/src/dma/status.rs | 43 + va416xx/src/dma/waitonreq_status.rs | 43 + va416xx/src/eth.rs | 1157 ++ va416xx/src/eth/dma_ahb_status.rs | 40 + va416xx/src/eth/dma_bus_mode.rs | 235 + va416xx/src/eth/dma_curr_rx_bufr_addr.rs | 40 + va416xx/src/eth/dma_curr_rx_desc.rs | 40 + va416xx/src/eth/dma_curr_tx_bufr_addr.rs | 40 + va416xx/src/eth/dma_curr_tx_desc.rs | 40 + va416xx/src/eth/dma_intr_en.rs | 250 + va416xx/src/eth/dma_miss_over_counter.rs | 85 + va416xx/src/eth/dma_oper_mode.rs | 250 + va416xx/src/eth/dma_rx_desc_list_addr.rs | 40 + va416xx/src/eth/dma_rx_intr_wdog_timer.rs | 40 + va416xx/src/eth/dma_rx_poll_demand.rs | 40 + va416xx/src/eth/dma_status.rs | 155 + va416xx/src/eth/dma_tx_desc_list_addr.rs | 40 + va416xx/src/eth/dma_tx_poll_demand.rs | 40 + va416xx/src/eth/mac_addr_h.rs | 38 + va416xx/src/eth/mac_addr_l.rs | 31 + va416xx/src/eth/mac_config.rs | 310 + va416xx/src/eth/mac_debug.rs | 99 + va416xx/src/eth/mac_flow_ctrl.rs | 130 + va416xx/src/eth/mac_frame_fltr.rs | 220 + va416xx/src/eth/mac_gmii_addr.rs | 100 + va416xx/src/eth/mac_gmii_data.rs | 40 + va416xx/src/eth/mac_intr_mask.rs | 40 + va416xx/src/eth/mac_intr_stat.rs | 50 + va416xx/src/eth/mac_vlan_tag.rs | 85 + va416xx/src/eth/mac_wdog_to.rs | 55 + va416xx/src/eth/mmc_cntrl.rs | 130 + va416xx/src/eth/mmc_intr_mask_rx.rs | 415 + va416xx/src/eth/mmc_intr_mask_tx.rs | 415 + va416xx/src/eth/mmc_intr_rx.rs | 415 + va416xx/src/eth/mmc_intr_tx.rs | 415 + va416xx/src/eth/rx1024maxoct_gb.rs | 22 + va416xx/src/eth/rx128to255oct_gb.rs | 22 + va416xx/src/eth/rx256to511oct_gb.rs | 22 + va416xx/src/eth/rx512to1023oct_gb.rs | 22 + va416xx/src/eth/rx64octets_gb.rs | 22 + va416xx/src/eth/rx65to127oct_gb.rs | 22 + va416xx/src/eth/rxalignerror.rs | 22 + va416xx/src/eth/rxbcastframes_g.rs | 22 + va416xx/src/eth/rxcrcerror.rs | 22 + va416xx/src/eth/rxctrlframes_g.rs | 22 + va416xx/src/eth/rxfifooverflow.rs | 22 + va416xx/src/eth/rxframecount_gb.rs | 22 + va416xx/src/eth/rxjabbererror.rs | 22 + va416xx/src/eth/rxlengtherror.rs | 22 + va416xx/src/eth/rxmcastframes_g.rs | 22 + va416xx/src/eth/rxoctetcount_g.rs | 22 + va416xx/src/eth/rxoctetcount_gb.rs | 22 + va416xx/src/eth/rxoutrangetype.rs | 22 + va416xx/src/eth/rxoversize_g.rs | 22 + va416xx/src/eth/rxpauseframes.rs | 22 + va416xx/src/eth/rxrcverror.rs | 22 + va416xx/src/eth/rxrunterror.rs | 22 + va416xx/src/eth/rxucastframes_g.rs | 22 + va416xx/src/eth/rxundersize_g.rs | 22 + va416xx/src/eth/rxvlanframes_gb.rs | 22 + va416xx/src/eth/rxwdogerror.rs | 22 + va416xx/src/eth/subsec_inc.rs | 40 + va416xx/src/eth/systime_nanosec.rs | 22 + va416xx/src/eth/systime_nsecup.rs | 55 + va416xx/src/eth/systime_seconds.rs | 22 + va416xx/src/eth/systime_secsupdat.rs | 40 + va416xx/src/eth/target_time_nsec.rs | 55 + va416xx/src/eth/target_time_secs.rs | 40 + va416xx/src/eth/timestamp_ctrl.rs | 340 + va416xx/src/eth/timestampaddend.rs | 40 + va416xx/src/eth/tx1024maxoct_gb.rs | 22 + va416xx/src/eth/tx128to255oct_gb.rs | 22 + va416xx/src/eth/tx256to511oct_gb.rs | 22 + va416xx/src/eth/tx512to1023oct_gb.rs | 22 + va416xx/src/eth/tx64oct_gb.rs | 22 + va416xx/src/eth/tx65to127oct_gb.rs | 22 + va416xx/src/eth/txbcastframe_gb.rs | 22 + va416xx/src/eth/txbcastframes_g.rs | 22 + va416xx/src/eth/txcarriererror.rs | 22 + va416xx/src/eth/txdeferred.rs | 22 + va416xx/src/eth/txexcessdef.rs | 22 + va416xx/src/eth/txexesscol.rs | 22 + va416xx/src/eth/txframecount_g.rs | 22 + va416xx/src/eth/txframecount_gb.rs | 22 + va416xx/src/eth/txlanframes_g.rs | 22 + va416xx/src/eth/txlatecol.rs | 22 + va416xx/src/eth/txmcastframe_gb.rs | 22 + va416xx/src/eth/txmcastframes_g.rs | 22 + va416xx/src/eth/txmulticol_g.rs | 22 + va416xx/src/eth/txoctetcount_g.rs | 22 + va416xx/src/eth/txoctetcount_gb.rs | 22 + va416xx/src/eth/txoversize_g.rs | 22 + va416xx/src/eth/txpauseframes.rs | 22 + va416xx/src/eth/txsinglecol_g.rs | 22 + va416xx/src/eth/txucastframe_gb.rs | 22 + va416xx/src/eth/txundererr.rs | 22 + va416xx/src/eth/vlan_hashtable.rs | 40 + va416xx/src/eth/vlan_increplace.rs | 85 + va416xx/src/generic.rs | 618 + va416xx/src/generic/raw.rs | 93 + va416xx/src/i2c0.rs | 452 + va416xx/src/i2c0/address.rs | 27 + va416xx/src/i2c0/clkscale.rs | 55 + va416xx/src/i2c0/clktolimit.rs | 27 + va416xx/src/i2c0/cmd.rs | 27 + va416xx/src/i2c0/ctrl.rs | 160 + va416xx/src/i2c0/data.rs | 27 + va416xx/src/i2c0/fifo_clr.rs | 35 + va416xx/src/i2c0/irq_enb.rs | 235 + va416xx/src/i2c0/perid.rs | 18 + va416xx/src/i2c0/rxcount.rs | 18 + va416xx/src/i2c0/rxfifoirqtrg.rs | 27 + va416xx/src/i2c0/s0_address.rs | 70 + va416xx/src/i2c0/s0_addressb.rs | 70 + va416xx/src/i2c0/s0_addressmask.rs | 55 + va416xx/src/i2c0/s0_addressmaskb.rs | 55 + va416xx/src/i2c0/s0_ctrl.rs | 100 + va416xx/src/i2c0/s0_data.rs | 40 + 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vorago-peb1/jlink-gdb.sh create mode 100644 vorago-peb1/jlink/JLinkSettings.JLinkScript create mode 100644 vorago-peb1/jlink/jlink-reva.gdb create mode 100644 vorago-peb1/jlink/jlink.gdb create mode 100644 vorago-peb1/memory.x create mode 100644 vorago-peb1/src/lib.rs create mode 100644 vscode/.cortex-debug.peripherals.state.json create mode 100644 vscode/.cortex-debug.registers.state.json create mode 100644 vscode/extensions.json create mode 100644 vscode/launch.json create mode 100644 vscode/settings.json create mode 100644 vscode/tasks.json diff --git a/.cargo/def-config.toml b/.cargo/def-config.toml new file mode 100644 index 0000000..0445fd4 --- /dev/null +++ b/.cargo/def-config.toml @@ -0,0 +1,40 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +runner = "gdb-multiarch -q -x jlink/jlink.gdb" +# runner = "arm-none-eabi-gdb -q -x jlink/jlink-reva.gdb" +# runner = "gdb-multiarch -q -x jlink/jlink-reva.gdb" + +# Probe-rs is currently problematic, possibly because of the +# ROM protection? +# runner = "probe-rs run --chip-description-path ./scripts/VA416xx_Series.yaml" +# runner = ["probe-rs", "run", "--chip", "$CHIP", "--log-format", "{L} {s}"] + + +rustflags = [ + "-C", + "link-arg=-Tlink.x", + # "-C", + # "linker=flip-link", + # "-C", + # "link-arg=-Tdefmt.x", + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", + "link-arg=--nmagic", + # Can be useful for debugging. + # "-Clink-args=-Map=app.map" +] + +[build] +# (`thumbv6m-*` is compatible with all ARM Cortex-M chips but using the right +# target improves performance) +# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ +# target = "thumbv7m-none-eabi" # Cortex-M3 +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) +target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) + +[alias] +rb = "run --bin" +rrb = "run --release --bin" + +[env] +DEFMT_LOG = "info" diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml new file mode 100644 index 0000000..a2d1b1f --- /dev/null +++ b/.github/workflows/ci.yml @@ -0,0 +1,52 @@ +name: ci +on: [push, pull_request] + +jobs: + check: + name: Check build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + targets: "thumbv7em-none-eabihf" + - run: cargo check --target thumbv7em-none-eabihf --release + - run: cargo check --target thumbv7em-none-eabihf --examples --release + + test: + name: Run Tests + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + - name: Install nextest + uses: taiki-e/install-action@nextest + - run: cargo nextest run --all-features -p va416xx-hal + # I think we can skip those on an embedded crate.. + # - run: cargo test --doc -p va108xx-hal + + fmt: + name: Check formatting + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + - run: cargo fmt --all -- --check + + docs: + name: Check Documentation Build + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@nightly + - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc --all-features + + clippy: + name: Clippy + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: dtolnay/rust-toolchain@stable + with: + targets: "thumbv7em-none-eabihf" + - run: cargo clippy --target thumbv7em-none-eabihf -- -D warnings diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..4f9c3c0 --- /dev/null +++ b/.gitignore @@ -0,0 +1,16 @@ +# Generated by Cargo +# will have compiled files and executables +/target/ +/.vscode + +# Ignore user config +/.cargo/config.toml + +# Remove Cargo.lock from gitignore if creating an executable, leave it for libraries +# More information here https://doc.rust-lang.org/cargo/guide/cargo-toml-vs-cargo-lock.html +Cargo.lock + +# These are backup files generated by rustfmt +**/*.rs.bk + +/app.map diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..e69de29 diff --git a/Cargo.toml b/Cargo.toml new file mode 100644 index 0000000..d189036 --- /dev/null +++ b/Cargo.toml @@ -0,0 +1,26 @@ +[workspace] +resolver = "2" +members = [ + "examples/simple", + "va416xx", + "va416xx-hal", + "vorago-peb1" +] + +[profile.dev] +codegen-units = 1 +debug = 2 +debug-assertions = true # <- +incremental = false +opt-level = 'z' # <- +overflow-checks = true # <- + +# cargo build/run --release +[profile.release] +codegen-units = 1 +debug = 2 +debug-assertions = false # <- +incremental = false +lto = 'fat' +opt-level = 3 # <- +overflow-checks = false # <- diff --git a/LICENSE-APACHE b/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/NOTICE b/NOTICE new file mode 100644 index 0000000..f2f635d --- /dev/null +++ b/NOTICE @@ -0,0 +1,3 @@ +Workspace to develop Rust for the VA416xx devices + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 0000000..8c45d57 --- /dev/null +++ b/README.md @@ -0,0 +1,109 @@ +[![build](https://github.com/us-irs/va416xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va416xx-rs/actions/workflows/ci.yml) + +Vorago VA416xx Rust Support +========= + +This crate collection provided support to write Rust applications for the VA416XX family +of devices. + +## List of crates + +This workspace contains the following crates: + +- The [`va416xx`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx) + PAC crate containing basic low-level register definition +- The [`va416xx-hal`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx-hal) + HAL crate containing higher-level abstractions on top of the PAC register crate. +- The [`vorago-peb1`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/vorago-peb1) + BSP crate containing support for the PEB1 development board. + +It also contains the following helper crates: + +- The `examples` crates contains various example applications for the HAL and the PAC. + +## Using the `.cargo/config.toml` file + +Use the following command to have a starting `config.toml` file + +```sh +cp .cargo/def-config.toml .cargo/config.toml +``` + +You then can adapt the `config.toml` to your needs. For example, you can configure runners +to conveniently flash with `cargo run`. + +## Using the sample VS Code files + +Use the following command to have a starting configuration for VS Code: + +```sh +cp -rT vscode .vscode +``` + +You can then adapt the files in `.vscode` to your needs. + +## Flashing, running and debugging the software + +You can use CLI or VS Code for flashing, running and debugging. In any case, take +care of installing the pre-requisites first. + +### Pre-Requisites + +1. [SEGGER J-Link tools](https://www.segger.com/downloads/jlink/) installed +2. [gdb-multiarch](https://packages.debian.org/sid/gdb-multiarch) or similar + cross-architecture debugger installed. All commands here assume `gdb-multiarch`. + +### Using CLI + +You can build the blinky example application with the following command + +```sh +cargo build --example blinky +``` + +Start the GDB server first. The server needs to be started with a certain configuration and with +a JLink script to disable ROM protection. +For example, on Debian based system the following command can be used to do this (this command +is also run when running the `jlink-gdb.sh` script) + +```sh +JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \ + -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript +``` + +After this, you can flash and debug the application with the following command + +```sh +gdb-mutliarch -q -x jlink/jlink.gdb target/thumbv7em-none-eabihf/debug/examples/blinky +``` + +Please note that you can automate all steps except starting the GDB server by using a cargo +runner configuration, for example with the following lines in your `.cargo/config.toml` file: + +```toml +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +runner = "gdb-multiarch -q -x jlink/jlink.gdb" +``` + +After that, you can simply use `cargo run --example blinky` to flash the blinky +example. + +### Using VS Code + +Assuming a working debug connection to your VA108xx board, you can debug using VS Code with +the [`Cortex-Debug` plugin](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug). + +Some sample configuration files for VS code were provided and can be used by running +`cp -rT vscode .vscode` like specified above. After that, you can use `Run and Debug` +to automatically rebuild and flash your application. + +If you would like to use a custom GDB application, you can specify the gdb binary in the following +configuration variables in your `settings.json`: + +- `"cortex-debug.gdbPath"` +- `"cortex-debug.gdbPath.linux"` +- `"cortex-debug.gdbPath.windows"` +- `"cortex-debug.gdbPath.osx"` + +The provided VS Code configurations also provide an integrated RTT logger, which you can access +via the terminal at `RTT Ch:0 console`. diff --git a/automation/Dockerfile b/automation/Dockerfile new file mode 100644 index 0000000..48c8e1d --- /dev/null +++ b/automation/Dockerfile @@ -0,0 +1,13 @@ +# Run the following commands from root directory to build and run locally +# docker build -f automation/Dockerfile -t . +# docker run -it +FROM rust:latest +RUN apt-get update +RUN apt-get --yes upgrade +# tzdata is a dependency, won't install otherwise +ARG DEBIAN_FRONTEND=noninteractive + +RUN rustup install nightly && \ + rustup target add thumbv7em-none-eabihf && \ + rustup +nightly target add thumbv7em-none-eabihf && \ + rustup component add rustfmt clippy diff --git a/automation/Jenkinsfile b/automation/Jenkinsfile new file mode 100644 index 0000000..b2e6c5d --- /dev/null +++ b/automation/Jenkinsfile @@ -0,0 +1,43 @@ +pipeline { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + + stages { + stage('Rust Toolchain Info') { + steps { + sh 'rustc --version' + } + } + stage('Clippy') { + steps { + sh 'cargo clippy --target thumbv7em-none-eabihf' + } + } + stage('Rustfmt') { + steps { + sh 'cargo fmt' + } + } + stage('Docs') { + steps { + sh """ + RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc --all-features + """ + } + } + stage('Check') { + steps { + sh 'cargo check --target thumbv7em-none-eabihf' + } + } + stage('Check Examples') { + steps { + sh 'cargo check --target thumbv7em-none-eabihf --examples' + } + } + } +} diff --git a/examples/simple/Cargo.toml b/examples/simple/Cargo.toml new file mode 100644 index 0000000..130ca39 --- /dev/null +++ b/examples/simple/Cargo.toml @@ -0,0 +1,18 @@ +[package] +name = "simple_examples" +version = "0.1.0" +edition = "2021" + +[dependencies] +cortex-m-rt = "0.7" +va416xx-hal = { path = "../../va416xx-hal" } +panic-rtt-target = { version = "0.1.3" } +rtt-target = { version = "0.5" } +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +embedded-hal = "1" +embedded-hal-nb = "1" +nb = "1" +embedded-io = "0.6" +panic-halt = "0.2" +vorago-peb1 = { path = "../../vorago-peb1" } +accelerometer = "0.12" diff --git a/examples/simple/examples/blinky-pac.rs b/examples/simple/examples/blinky-pac.rs new file mode 100644 index 0000000..1f99f28 --- /dev/null +++ b/examples/simple/examples/blinky-pac.rs @@ -0,0 +1,33 @@ +//! Simple blinky example +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use panic_halt as _; +use va416xx_hal::pac; + +// Mask for the LED +const LED_PG5: u32 = 1 << 5; + +#[entry] +fn main() -> ! { + let dp = pac::Peripherals::take().unwrap(); + // Enable all peripheral clocks + dp.sysconfig + .peripheral_clk_enable() + .modify(|_, w| unsafe { w.bits(0xffffffff) }); + dp.portg.dir().modify(|_, w| unsafe { w.bits(LED_PG5) }); + dp.portg + .datamask() + .modify(|_, w| unsafe { w.bits(LED_PG5) }); + for _ in 0..10 { + dp.portg.clrout().write(|w| unsafe { w.bits(LED_PG5) }); + cortex_m::asm::delay(2_000_000); + dp.portg.setout().write(|w| unsafe { w.bits(LED_PG5) }); + cortex_m::asm::delay(2_000_000); + } + loop { + dp.portg.togout().write(|w| unsafe { w.bits(LED_PG5) }); + cortex_m::asm::delay(2_000_000); + } +} diff --git a/examples/simple/examples/blinky.rs b/examples/simple/examples/blinky.rs new file mode 100644 index 0000000..3056748 --- /dev/null +++ b/examples/simple/examples/blinky.rs @@ -0,0 +1,24 @@ +//! Simple blinky example using the HAL +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::digital::StatefulOutputPin; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va416xx_hal::{gpio::PinsG, pac}; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("VA416xx HAL blinky example"); + + let mut dp = pac::Peripherals::take().unwrap(); + let portg = PinsG::new(&mut dp.sysconfig, dp.portg); + let mut led = portg.pg5.into_readable_push_pull_output(); + //let mut delay = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM0); + loop { + cortex_m::asm::delay(2_000_000); + led.toggle().ok(); + } +} diff --git a/examples/simple/examples/peb1-accelerometer.rs b/examples/simple/examples/peb1-accelerometer.rs new file mode 100644 index 0000000..a9ed8bf --- /dev/null +++ b/examples/simple/examples/peb1-accelerometer.rs @@ -0,0 +1,88 @@ +//! Example code for the PEB1 development board accelerometer. +#![no_main] +#![no_std] + +use accelerometer::{Accelerometer, RawAccelerometer}; +use cortex_m_rt::entry; +use embedded_hal::delay::DelayNs; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use simple_examples::peb1; +use va416xx_hal::{ + i2c, + pac::{self}, + prelude::*, + pwm::CountdownTimer, +}; +use vorago_peb1::lis2dh12::{self, detect_i2c_addr, FullScale, Odr}; + +pub enum DisplayMode { + Raw, + Normalized, +} + +const DISPLAY_MODE: DisplayMode = DisplayMode::Normalized; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + let mut dp = pac::Peripherals::take().unwrap(); + rprintln!("-- Vorago PEB1 accelerometer example --"); + // Use the external clock connected to XTAL_N. + let clocks = dp + .clkgen + .constrain() + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze(&mut dp.sysconfig) + .unwrap(); + let mut i2c_master = i2c::I2cMaster::new( + dp.i2c0, + &mut dp.sysconfig, + i2c::MasterConfig::default(), + &clocks, + i2c::I2cSpeed::Regular100khz, + ) + .expect("creating I2C master failed"); + let mut delay_provider = CountdownTimer::new(&mut dp.sysconfig, dp.tim1, &clocks); + // Detect the I2C address of the accelerometer by scanning all possible values. + let slave_addr = detect_i2c_addr(&mut i2c_master).expect("detecting I2C address failed"); + // Create the accelerometer driver using the PEB1 BSP. + let mut accelerometer = vorago_peb1::accelerometer::new_with_i2cm(i2c_master, slave_addr) + .expect("creating accelerometer driver failed"); + let device_id = accelerometer.get_device_id().unwrap(); + accelerometer + .set_mode(lis2dh12::reg::Mode::Normal) + .expect("setting mode failed"); + accelerometer + .set_odr(Odr::Hz100) + .expect("setting ODR failed"); + accelerometer + .set_fs(FullScale::G4) + .expect("setting full scale failed"); + // This function also enabled BDU. + accelerometer + .enable_temp(true) + .expect("enabling temperature sensor failed"); + rprintln!("Device ID: 0x{:02X}", device_id); + // Start reading the accelerometer periodically. + loop { + let temperature = accelerometer + .get_temp_outf() + .expect("reading temperature failed"); + match DISPLAY_MODE { + DisplayMode::Normalized => { + let value = accelerometer + .accel_norm() + .expect("reading normalized accelerometer data failed"); + rprintln!("Accel Norm F32x3: {:.06?} | Temp {} °C", value, temperature); + } + DisplayMode::Raw => { + let value_raw = accelerometer + .accel_raw() + .expect("reading raw accelerometer data failed"); + rprintln!("Accel Raw F32x3: {:?} | Temp {} °C", value_raw, temperature); + } + } + delay_provider.delay_ms(100); + } +} diff --git a/examples/simple/examples/pwm.rs b/examples/simple/examples/pwm.rs new file mode 100644 index 0000000..922ae00 --- /dev/null +++ b/examples/simple/examples/pwm.rs @@ -0,0 +1,81 @@ +//! Simple PWM example +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::{delay::DelayNs, pwm::SetDutyCycle}; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use simple_examples::peb1; +use va416xx_hal::{ + gpio::PinsA, + pac, + prelude::*, + pwm::{self, get_duty_from_percent, CountdownTimer, PwmA, PwmB, ReducedPwmPin}, +}; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("-- VA108xx PWM example application--"); + let mut dp = pac::Peripherals::take().unwrap(); + + // Use the external clock connected to XTAL_N. + let clocks = dp + .clkgen + .constrain() + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze(&mut dp.sysconfig) + .unwrap(); + + let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta); + let mut pwm = pwm::PwmPin::new( + (pinsa.pa3.into_funsel_1(), dp.tim3), + &mut dp.sysconfig, + &clocks, + 10.Hz(), + ); + let mut delay_timer = CountdownTimer::new(&mut dp.sysconfig, dp.tim0, &clocks); + let mut current_duty_cycle = 0.0; + pwm.set_duty_cycle(get_duty_from_percent(current_duty_cycle)) + .unwrap(); + pwm.enable(); + + // Delete type information, increased code readibility for the rest of the code + let mut reduced_pin = ReducedPwmPin::from(pwm); + loop { + let mut counter = 0; + // Increase duty cycle continuously + while current_duty_cycle < 1.0 { + delay_timer.delay_ms(400); + current_duty_cycle += 0.02; + counter += 1; + if counter % 10 == 0 { + rprintln!("current duty cycle: {}", current_duty_cycle); + } + + reduced_pin + .set_duty_cycle(get_duty_from_percent(current_duty_cycle)) + .unwrap(); + } + + // Switch to PWMB and decrease the window with a high signal from 100 % to 0 % + // continously + current_duty_cycle = 0.0; + let mut upper_limit = 1.0; + let mut lower_limit = 0.0; + let mut pwmb: ReducedPwmPin = ReducedPwmPin::from(reduced_pin); + pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit)); + pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit)); + while lower_limit < 0.5 { + delay_timer.delay_ms(400); + lower_limit += 0.01; + upper_limit -= 0.01; + pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit)); + pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit)); + rprintln!("Lower limit: {}", pwmb.pwmb_lower_limit()); + rprintln!("Upper limit: {}", pwmb.pwmb_upper_limit()); + } + reduced_pin = ReducedPwmPin::::from(pwmb); + } +} diff --git a/examples/simple/examples/rtt-log.rs b/examples/simple/examples/rtt-log.rs new file mode 100644 index 0000000..8eb2475 --- /dev/null +++ b/examples/simple/examples/rtt-log.rs @@ -0,0 +1,36 @@ +// Code to test RTT logger functionality. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use va416xx_hal::pac; + +// Mask for the LED +const LED_PG5: u32 = 1 << 5; + +#[entry] +fn main() -> ! { + let dp = pac::Peripherals::take().unwrap(); + // Enable all peripheral clocks + dp.sysconfig + .peripheral_clk_enable() + .modify(|_, w| unsafe { w.bits(0xffffffff) }); + dp.portg.dir().modify(|_, w| unsafe { w.bits(LED_PG5) }); + dp.portg + .datamask() + .modify(|_, w| unsafe { w.bits(LED_PG5) }); + + rtt_init_print!(); + rprintln!("VA416xx RTT Demo"); + let mut counter = 0; + loop { + rprintln!("{}: Hello, world!", counter); + // Still toggle LED. If there are issues with the RTT log, the LED + // blinking ensures that the application is actually running. + dp.portg.togout().write(|w| unsafe { w.bits(LED_PG5) }); + counter += 1; + cortex_m::asm::delay(10_000_000); + } +} diff --git a/examples/simple/examples/spi.rs b/examples/simple/examples/spi.rs new file mode 100644 index 0000000..e9e5401 --- /dev/null +++ b/examples/simple/examples/spi.rs @@ -0,0 +1,96 @@ +//! SPI example application. +//! +//! If you do not use the loopback mode, MOSI and MISO need to be tied together on the board. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal::spi::{Mode, SpiBus, MODE_0}; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use simple_examples::peb1; +use va416xx_hal::spi::{Spi, TransferConfig}; +use va416xx_hal::{ + gpio::{PinsB, PinsC}, + pac, + prelude::*, + spi::SpiConfig, +}; + +#[derive(PartialEq, Debug)] +pub enum ExampleSelect { + // Enter loopback mode. It is not necessary to tie MOSI/MISO together for this + Loopback, + // Send a test buffer and print everything received. You need to tie together MOSI/MISO in this + // mode. + TestBuffer, +} + +const EXAMPLE_SEL: ExampleSelect = ExampleSelect::Loopback; +const SPI_SPEED_KHZ: u32 = 1000; +const SPI_MODE: Mode = MODE_0; +const BLOCKMODE: bool = true; +const FILL_WORD: u8 = 0x0f; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("-- VA108xx SPI example application--"); + let cp = cortex_m::Peripherals::take().unwrap(); + let mut dp = pac::Peripherals::take().unwrap(); + // Use the external clock connected to XTAL_N. + let clocks = dp + .clkgen + .constrain() + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze(&mut dp.sysconfig) + .unwrap(); + let mut delay_sysclk = cortex_m::delay::Delay::new(cp.SYST, clocks.apb0().raw()); + + let pins_b = PinsB::new(&mut dp.sysconfig, dp.portb); + let pins_c = PinsC::new(&mut dp.sysconfig, dp.portc); + // Configure SPI1 pins. + let (sck, miso, mosi) = ( + pins_b.pb15.into_funsel_1(), + pins_c.pc0.into_funsel_1(), + pins_c.pc1.into_funsel_1(), + ); + + let mut spi_cfg = SpiConfig::default(); + if EXAMPLE_SEL == ExampleSelect::Loopback { + spi_cfg = spi_cfg.loopback(true) + } + let transfer_cfg = + TransferConfig::new_no_hw_cs(SPI_SPEED_KHZ.kHz(), SPI_MODE, BLOCKMODE, false); + // Create SPI peripheral. + let mut spi0 = Spi::new( + dp.spi0, + (sck, miso, mosi), + &clocks, + spi_cfg, + &mut dp.sysconfig, + Some(&transfer_cfg.downgrade()), + ); + spi0.set_fill_word(FILL_WORD); + loop { + let mut tx_buf: [u8; 3] = [1, 2, 3]; + let mut rx_buf: [u8; 3] = [0; 3]; + // Can't really verify correct reply here. + spi0.write(&[0x42]).expect("write failed"); + // Need small delay.. otherwise we will read back the sent byte (which we don't want here). + // The write function will return as soon as all bytes were shifted out, ignoring the + // reply bytes. + delay_sysclk.delay_us(50); + // Because of the loopback mode, we should get back the fill word here. + spi0.read(&mut rx_buf[0..1]).unwrap(); + assert_eq!(rx_buf[0], FILL_WORD); + + spi0.transfer_in_place(&mut tx_buf) + .expect("SPI transfer_in_place failed"); + assert_eq!([1, 2, 3], tx_buf); + spi0.transfer(&mut rx_buf, &tx_buf) + .expect("SPI transfer failed"); + assert_eq!(rx_buf, tx_buf); + delay_sysclk.delay_ms(500); + } +} diff --git a/examples/simple/examples/timer-ticks.rs b/examples/simple/examples/timer-ticks.rs new file mode 100644 index 0000000..4eb47e8 --- /dev/null +++ b/examples/simple/examples/timer-ticks.rs @@ -0,0 +1,68 @@ +//! MS and Second counter implemented using the TIM0 and TIM1 peripheral +#![no_main] +#![no_std] + +use core::cell::Cell; +use cortex_m::interrupt::Mutex; +use cortex_m_rt::entry; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use simple_examples::peb1; +use va416xx_hal::{ + pac::{self, interrupt}, + prelude::*, + timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer, MS_COUNTER}, +}; + +#[allow(dead_code)] +enum LibType { + Pac, + Hal, +} + +static SEC_COUNTER: Mutex> = Mutex::new(Cell::new(0)); + +#[entry] +fn main() -> ! { + rtt_init_print!(); + let mut dp = pac::Peripherals::take().unwrap(); + let mut last_ms = 0; + rprintln!("-- Vorago system ticks using timers --"); + // Use the external clock connected to XTAL_N. + let clocks = dp + .clkgen + .constrain() + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze(&mut dp.sysconfig) + .unwrap(); + let _ = set_up_ms_tick(&mut dp.sysconfig, dp.tim0, &clocks); + let mut second_timer = CountdownTimer::new(&mut dp.sysconfig, dp.tim1, &clocks); + second_timer.start(1.Hz()); + second_timer.listen(); + loop { + let current_ms = cortex_m::interrupt::free(|cs| MS_COUNTER.borrow(cs).get()); + if current_ms - last_ms >= 1000 { + last_ms = current_ms; + rprintln!("MS counter: {}", current_ms); + let second = cortex_m::interrupt::free(|cs| SEC_COUNTER.borrow(cs).get()); + rprintln!("Second counter: {}", second); + } + cortex_m::asm::delay(10000); + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn TIM0() { + default_ms_irq_handler() +} + +#[interrupt] +#[allow(non_snake_case)] +fn TIM1() { + cortex_m::interrupt::free(|cs| { + let mut sec = SEC_COUNTER.borrow(cs).get(); + sec += 1; + SEC_COUNTER.borrow(cs).set(sec); + }); +} diff --git a/examples/simple/examples/uart.rs b/examples/simple/examples/uart.rs new file mode 100644 index 0000000..0592d73 --- /dev/null +++ b/examples/simple/examples/uart.rs @@ -0,0 +1,57 @@ +// UART example application. Sends a test string over a UART and then enters +// echo mode +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use embedded_hal_nb::serial::Read; +use embedded_io::Write; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use simple_examples::peb1; +use va416xx_hal::clock::ClkgenExt; +use va416xx_hal::time::Hertz; +use va416xx_hal::{gpio::PinsG, pac, uart}; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("-- VA416xx UART example application--"); + + let mut dp = pac::Peripherals::take().unwrap(); + + // Use the external clock connected to XTAL_N. + let clocks = dp + .clkgen + .constrain() + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze(&mut dp.sysconfig) + .unwrap(); + + let gpiob = PinsG::new(&mut dp.sysconfig, dp.portg); + let tx = gpiob.pg0.into_funsel_1(); + let rx = gpiob.pg1.into_funsel_1(); + + let uart0 = uart::Uart::new( + dp.uart0, + (tx, rx), + Hertz::from_raw(115200), + &mut dp.sysconfig, + &clocks, + ); + let (mut tx, mut rx) = uart0.split(); + writeln!(tx, "Hello World\n\r").unwrap(); + loop { + // Echo what is received on the serial link. + match nb::block!(rx.read()) { + Ok(recvd) => { + if let Err(e) = embedded_hal_nb::serial::Write::write(&mut tx, recvd) { + rprintln!("UART TX error: {:?}", e); + } + } + Err(e) => { + rprintln!("UART RX error {:?}", e); + } + } + } +} diff --git a/examples/simple/examples/wdt.rs b/examples/simple/examples/wdt.rs new file mode 100644 index 0000000..5e989fc --- /dev/null +++ b/examples/simple/examples/wdt.rs @@ -0,0 +1,79 @@ +// Code to test the watchdog timer. +#![no_main] +#![no_std] + +use core::cell::Cell; +use cortex_m::interrupt::Mutex; +use cortex_m_rt::entry; +use panic_rtt_target as _; +use rtt_target::{rprintln, rtt_init_print}; +use simple_examples::peb1; +use va416xx_hal::pac::{self, interrupt}; +use va416xx_hal::prelude::*; +use va416xx_hal::wdt::WdtController; + +static WDT_INTRPT_COUNT: Mutex> = Mutex::new(Cell::new(0)); + +#[derive(Debug, PartialEq, Eq)] +#[allow(dead_code)] +enum TestMode { + // Watchdog is fed by main loop, which runs with high period. + FedByMain, + // Watchdog is fed by watchdog IRQ. + FedByIrq, + AllowReset, +} +const TEST_MODE: TestMode = TestMode::FedByMain; +const WDT_ROLLOVER_MS: u32 = 100; + +#[entry] +fn main() -> ! { + rtt_init_print!(); + rprintln!("-- VA416xx WDT example application--"); + let cp = cortex_m::Peripherals::take().unwrap(); + let mut dp = pac::Peripherals::take().unwrap(); + + // Use the external clock connected to XTAL_N. + let clocks = dp + .clkgen + .constrain() + .xtal_n_clk_with_src_freq(peb1::EXTCLK_FREQ) + .freeze(&mut dp.sysconfig) + .unwrap(); + let mut delay_sysclk = cortex_m::delay::Delay::new(cp.SYST, clocks.apb0().raw()); + + let mut last_interrupt_counter = 0; + let mut wdt_ctrl = + WdtController::start(&mut dp.sysconfig, dp.watch_dog, &clocks, WDT_ROLLOVER_MS); + wdt_ctrl.enable_reset(); + loop { + if TEST_MODE != TestMode::AllowReset { + wdt_ctrl.feed(); + } + let interrupt_counter = cortex_m::interrupt::free(|cs| WDT_INTRPT_COUNT.borrow(cs).get()); + if interrupt_counter > last_interrupt_counter { + rprintln!("interrupt counter has increased to {}", interrupt_counter); + last_interrupt_counter = interrupt_counter; + } + match TEST_MODE { + TestMode::FedByMain => delay_sysclk.delay_ms(WDT_ROLLOVER_MS / 5), + TestMode::FedByIrq => delay_sysclk.delay_ms(WDT_ROLLOVER_MS), + _ => (), + } + } +} + +#[interrupt] +#[allow(non_snake_case)] +fn WATCHDOG() { + cortex_m::interrupt::free(|cs| { + WDT_INTRPT_COUNT + .borrow(cs) + .set(WDT_INTRPT_COUNT.borrow(cs).get() + 1); + }); + let wdt = unsafe { pac::WatchDog::steal() }; + // Clear interrupt. + if TEST_MODE != TestMode::AllowReset { + wdt.wdogintclr().write(|w| unsafe { w.bits(1) }); + } +} diff --git a/examples/simple/src/lib.rs b/examples/simple/src/lib.rs new file mode 100644 index 0000000..c5a45f0 --- /dev/null +++ b/examples/simple/src/lib.rs @@ -0,0 +1,11 @@ +#![no_std] + +/// PEB1 board specific configuration. +pub mod peb1 { + use va416xx_hal::time::Hertz; + + // The clock on the PEB1 board has a 20 MHz clock which is increased to 40 MHz with a configurable + // PLL by default. + pub const EXTCLK_FREQ: Hertz = Hertz::from_raw(40_000_000); + pub const XTAL_FREQ: Hertz = Hertz::from_raw(10_000_000); +} diff --git a/examples/simple/src/main.rs b/examples/simple/src/main.rs new file mode 100644 index 0000000..ddb240e --- /dev/null +++ b/examples/simple/src/main.rs @@ -0,0 +1,13 @@ +//! Dummy app which does not do anything. +#![no_main] +#![no_std] + +use cortex_m_rt::entry; +use panic_rtt_target as _; + +#[entry] +fn main() -> ! { + loop { + cortex_m::asm::nop(); + } +} diff --git a/jlink-gdb.sh b/jlink-gdb.sh new file mode 100755 index 0000000..65e187f --- /dev/null +++ b/jlink-gdb.sh @@ -0,0 +1,5 @@ +#!/bin/bash +# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary +# to disable ROM protection to allow flashing +JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \ + -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript diff --git a/jlink/JLinkSettings.JLinkScript b/jlink/JLinkSettings.JLinkScript new file mode 100644 index 0000000..b6b83a6 --- /dev/null +++ b/jlink/JLinkSettings.JLinkScript @@ -0,0 +1,62 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 1995 - 2018 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +---------------------------------------------------------------------- +File : JLinkSettings.JLinkScript +Purpose : J-Link target setup file for VORAGO VA416xx +---------------------------END-OF-HEADER------------------------------ +*/ + +/********************************************************************* +* +* AfterResetTarget +*/ +int AfterResetTarget (void) { + JLINK_SYS_Report("AfterResetTarget()"); + JLINK_MEM_WriteU32(0x400210C0, 0x1ACCE551); // WDOGLOCK = 0x1ACCE551 + JLINK_MEM_WriteU32(0x40021008, 0x0); // WDOGCONTROL = 0x0 (diable) + return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* BeforeTargetDownload +*/ +int BeforeTargetDownload (void) { + JLINK_SYS_Report("BeforeTargetDownload()"); + return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* AfterTargetDownload +*/ +int AfterTargetDownload (void) { + JLINK_SYS_Report("AfterTargetDownload()"); + return JLINK_MEM_WriteU32(0x40010010, 0x0); // ROM_PROT = 0x0 +} + +/********************************************************************* +* +* HandleBeforeFlashProg +*/ +int HandleBeforeFlashProg(void) { + JLINK_SYS_Report("HandleBeforeFlashProg()"); + return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* HandleAfterFlashProg +*/ +int HandleAfterFlashProg(void) { + JLINK_SYS_Report("HandleAfterFlashProg()"); + return JLINK_MEM_WriteU32(0x40010010, 0x0); // ROM_PROT = 0x0 +} diff --git a/jlink/jlink-reva.gdb b/jlink/jlink-reva.gdb new file mode 100644 index 0000000..8712a8e --- /dev/null +++ b/jlink/jlink-reva.gdb @@ -0,0 +1,13 @@ +target remote localhost:2331 + +# For some reason, this is problematic even if the JLinkScript disabled the remote +# write protection. Therefore, don't do it for now +# This is only problematic on board RevA +# monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/jlink/jlink.gdb b/jlink/jlink.gdb new file mode 100644 index 0000000..54ce1ce --- /dev/null +++ b/jlink/jlink.gdb @@ -0,0 +1,10 @@ +target remote localhost:2331 + +monitor halt +# Reset is problematic on RevA, okay for RevB +monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load diff --git a/memory.x b/memory.x new file mode 100644 index 0000000..811b87a --- /dev/null +++ b/memory.x @@ -0,0 +1,23 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 256K + /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ + RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K + SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +/* SRAM_0 can be used for all busses: Instruction, Data and System */ +/* SRAM_1 only supports the system bus */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); + +/* Define sections for placing symbols into the extra memory regions above. */ +/* This makes them accessible from code. */ +SECTIONS { + .sram1 (NOLOAD) : ALIGN(8) { + *(.sram1 .sram1.*); + . = ALIGN(4); + } > SRAM_1 +}; diff --git a/scripts/VA416xx_Series.yaml b/scripts/VA416xx_Series.yaml new file mode 100644 index 0000000..76e9304 --- /dev/null +++ b/scripts/VA416xx_Series.yaml @@ -0,0 +1,100 @@ +name: VA416xx Series +generated_from_pack: true +pack_file_release: 1.0.5 +variants: +- name: VA416xx + cores: + - name: main + type: armv7em + core_access_options: !Arm + ap: 0 + psel: 0x0 + memory_map: + - !Ram + name: IRAM1 + range: + start: 0x1fff8000 + end: 0x20000000 + cores: + - main + - !Nvm + name: IROM1 + range: + start: 0x0 + end: 0x40000 + is_boot_memory: true + cores: + - main + - !Generic + name: IRAM2 + range: + start: 0x20000000 + end: 0x20008000 + cores: + - main + flash_algorithms: + - va416_spi_fram_256kb + - va416_ebiboot_fram_256kb + - va416_ebi_fram_512kb +flash_algorithms: +- name: va416_spi_fram_256kb + default: true + description: VA416_SPI_FRAM_256KB + instructions: RfYMQMTyAQABaMkHCtEBaMkHBL8BaF/qwXED0QFoyQfy0AC/AWjJBgnVAWjJBkS/AWhf6sFhAtUBaMkG8tQDIQFicEdwRwC/WCAIIcTyAQDA8qgBQWBB8ggBTvJRUsTyAgHB9swiwfi4IAAiCmABaCHwCAEBYAC/AL8CaEX2DEFC8AgCxPIBAQJgAiAAv0hgQPIHQEH4DAxA8oIgQfgIDAMgCGIIaMAHCtEIaMAHBL8IaF/qwHAD0QhowAfy0AC/CGjABgnVCGjABkS/CGhf6sBgAtUIaMAG8tQGIMjyAAADIgpiQfgEDApo0gcK0Qpo0gcEvwpoX+rCcgPRCmjSB/LQAL8KaNIGCdUKaNIGRL8KaF/qwmIC1Qpo0gby1AMiCmJB+AQMCGjABwnRCGjABwS/CGhf6sBwAtEIaMAH8tAIaMAGCdUIaMAGRL8IaF/qwGAC1QhowAby1AMgCGIBIEH4BAxP8ABAQfgEDAhowAcK0QhowAcEvwhoX+rAcAPRCGjAB/LQAL8IaMAGCdUIaMAGRL8IaF/qwGAC1QhowAby1AMiACAKYnBHAL9F9gxBxPIBAQhowAcK0QhowAcEvwhoX+rAcAPRCGjAB/LQAL8IaMAGCdUIaMAGRL8IaF/qwGAC1QhowAby1AYgyPIAAAMiCmJB+AQMCmjSBwrRCmjSBwS/Cmhf6sJyA9EKaNIH8tAAvwpo0gYJ1Qpo0gZEvwpoX+rCYgLVCmjSBvLUAyIKYgEi9zBB+AQsQfgEDAhowAcJ0QhowAcEvwhoX+rAcALRCGjAB/LQCGjABgnVCGjABkS/CGhf6sBgAtUIaMAG8tQDIgAgCmJwRwC/cLVF9gxBQPIGDAAgxPIBAcjyAAwDI0/wAg5P8ABCACQG4AC/ATS09YBvC2IA8KyAQfgEzA1o7QcK0Q1o7QcEvw1oX+rFdQPRDWjtB/LQAL8NaO0GCtUNaO0GRL8NaF/qxWUD1Q1o7Qby1AC/xPMHJQtiQfgE7EH4BFzlskH4BFwAJUH4BFwE4AU1/y1B+AQMTNAOaLYHBtQOaLYHXL8OaF/qhnY+1UH4BAwOaLYHCdQOaLYHXL8OaF/qhnYC1A5otgfy1UH4BAwOaLYHCtQOaLYHXL8OaF/qhnYD1A5otgfy1QC/QfgEDA5otgcK1A5otgdcvw5oX+qGdgPUDmi2B/LVAL9B+AQMDmi2B7zUDmi2B1y/Dmhf6oZ2tdQOaLYH8tWx5w5otgez1bznDWitBwrUDWitB1y/DWhf6oV1A9QNaK0H8tUAv0H4BCwNaO0HCtENaO0HBL8NaF/qxXUD0Q1o7Qfy0AC/DWjtBn/1Wq8NaO0GRL8NaF/qxWV/9VKvDWjtBvDUTecAIHC9ACBwR4C1grBF9gxOxPIBDgAjAZPe+AAw2wcN0d74ADDbBwS/3vgAMF/qw3ME0d74ADDbB+7QAL/e+AAw2wYM1d74ADDbBkS/3vgAMF/qw2MD1d74ADDbBu7UAyPO+CAwBiPI8gADTvgEPN74ADDbBwzR3vgAMNsHBL/e+AAwX+rDcwPR3vgAMNsH7tDe+AAw2wYM1d74ADDbBkS/3vgAMF/qw2MD1d74ADDbBu7UAyPO+CAwAiNN9vAMTvgEPMDzB0PP9v98TvgEPMDzByPAsgEpTvgEPE74BAxA8JKA3vgAAIAHAPEGgd74AACAB1y/3vgAAF/qgHAA8fyA3vgAAIAHXL/e+AAAX+qAcADx8oDe+AAAgAdcv974AABf6oBwAPHogN74AACAB1y/3vgAAF/qgHAA8d6A3vgAAIAHXL/e+AAAX+qAcADx1IDe+AAAgAdcv974AABf6oBwAPHKgN74AACAB1y/3vgAAF/qgHAA8cCA3vgAAIAHXL/e+AAAX+qAcADxtoDe+AAAgAdcv974AABf6oBwAPGsgN74AACAB1y/3vgAAF/qgHAA8aKA3vgAAIAHXL/e+AAAX+qAcADxmIDe+AAAgAdcv974AABf6oBwAPGOgBzxGQx/9H+vheAAvxL4AQsBOU74BAxe+AQMASkAkAGYAPEBAAGQP/Rur2BG3vgAMJsH69Te+AAwmwdcv974ADBf6oNz4tTe+AAwmwdcv974ADBf6oNz2dTe+AAwmwdcv974ADBf6oNz0NTe+AAwmwdcv974ADBf6oNzx9Te+AAwmwdcv974ADBf6oNzvtTe+AAwmwdcv974ADBf6oNztdTe+AAwmwdcv974ADBf6oNzrNTe+AAwmwdcv974ADBf6oNzo9Te+AAwmwdcv974ADBf6oNzmtTe+AAwmwdcv974ADBf6oNzkdTe+AAwmwdcv974ADBf6oNzP/WIr974ADCbB1y/3vgAMF/qg3M/9X6vGTB/9IuvASACsIC9EHgA8QBATvgEDN74AADABwzR3vgAAMAHBL/e+AAAX+rAcAPR3vgAAMAH7tDe+AAAwAYM1d74AADABkS/3vgAAF/qwGAD1d74AADABu7UAyDO+CAAACACsIC9AL8AIHBHsLVF9gxExPIBBCNo2wcJ0SNo2wcEvyNoX+rDcwLRI2jbB/LQI2jbBgnVI2jbBkS/I2hf6sNjAtUjaNsG8tQDIyNiRPgEPMDzB0NE+AQ8wPMHI0T4BDzDskT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwAI0T4BDwjaFsHCdQjaFsHXL8jaF/qQ3MC1CNoWwfy1VT4BDwBs0/wAAxP8AAOAL9E+ATMI2hbBwrUI2hbB1y/I2hf6kNzA9QjaFsH8tUAv1T4BDwVeNuynUIo0Q7xAQ6ORQLxAQLj0U/wAEJE+AQsImjSBwrRImjSBwS/Imhf6sJyA9EiaNIH8tAAvyJo0gYJ1SJo0gZEvyJoX+rCYgLVImjSBvLUAyIIRCJisL1wRLC9AAAAAAAA + pc_init: 0x49 + pc_uninit: 0x1ad + pc_program_page: 0x40d + pc_erase_sector: 0x409 + pc_erase_all: 0x27d + data_section_offset: 0x8d8 + flash_properties: + address_range: + start: 0x0 + end: 0x40000 + page_size: 0x100 + erased_byte_value: 0x0 + program_page_timeout: 3000 + erase_sector_timeout: 3000 + sectors: + - size: 0x2000 + address: 0x0 +- name: va416_ebiboot_fram_256kb + description: VA416_EBIBOOT_256KB + instructions: QfKAAsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HywALE8gECUvggMCP0wEND6kExQvggEHBHAL9B8gASxPIBAlL4IDAj9MBDQ+pBMUL4IBBwRwC/QfJAEsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HyiADE8gEAAmgBIWHzTjICYEJoYfNOMkJggmhh804ygmDCaGHzTjLCYAJpYfNOMgJhQmlh804yQmGCaWHzTjKCYcJpYfNOMsJhAmph804yAmJCamHzTjJCYoJqYfNOMoJiwmph804ywmICa2HzTjICY0JrYfNOMkJjgmth804ygmPCa2HzTjLCYwJsYfNOMgJkQmxh804yQmSCbGHzTjKCZMJsYfNOMsJkAm1h804yAmVCbWHzTjJCZYJtYfNOMoJlwm1h804ywmUCbmHzTjICZkJuYfNOMkJmgm5h804ygmbCbmHzTjLCZgJvYfNOMgJnQm9h804yQmeCb2HzTjKCZ8JvYfNOMsJn0PiAIGHzTjLA+IAg0PiEIGHzTjLA+IQg0PiIIGHzTjLA+Igg0PiMIGHzTjLA+Iwg0PiQIGHzTjLA+JAg0PiUIGHzTjLA+JQg0PiYIGHzTjLA+Jgg0PicIGHzTjLA+Jwg0PioIGHzTjLA+Kgg0PisIGHzTjLA+Kwg0PiwIGHzTjLA+LAg0Pi0IGHzTjLA+LQg0Pi4IGHzTjLA+Lgg0Pi8IGHzTjLA+LwgcEcQtVgkACDE8gEEw/Y5QGBgIGhA9IAwIGD/9xj/T/YAccDytjEAIGFhEL0AvwAgcEeAtU/wwEBP9IAhAPA7+AAggL0AvwAgcEcB8AEDGURLCCnQWR4A8cBAAykD8AMME9Mj8AMDMvgIGwQ7IPgIGzL4Bhwg+AYcMvgEHCD4BBwy+AIcIPgCHO3RvPEADwvQEYi88QEPAYAG0FGIvPECD0GAHL+RiIGAACBwRwC/ACBwRwhEcEdP8AACALUTRpRGlkYgOSK/oOgMUKDoDFCx8SABv/T3rwkHKL+g6AxQSL8MwF34BOuJACi/QPgEKwi/cEdIvyD4AisR8IBPGL8A+AErcEcAAAAAAAA= + pc_init: 0x225 + pc_uninit: 0x251 + pc_program_page: 0x26d + pc_erase_sector: 0x269 + pc_erase_all: 0x255 + data_section_offset: 0x328 + flash_properties: + address_range: + start: 0x0 + end: 0x40000 + page_size: 0x100 + erased_byte_value: 0x0 + program_page_timeout: 3000 + erase_sector_timeout: 3000 + sectors: + - size: 0x2000 + address: 0x0 +- name: va416_ebi_fram_512kb + description: VA416_EBI_512KB + instructions: QfKAAsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HywALE8gECUvggMCP0wEND6kExQvggEHBHAL9B8gASxPIBAlL4IDAj9MBDQ+pBMUL4IBBwRwC/QfJAEsTyAQJS+CAwI/TAQ0PqQTFC+CAQcEcAv0HyiADE8gEAAmgBIWHzTjICYEJoYfNOMkJggmhh804ygmDCaGHzTjLCYAJpYfNOMgJhQmlh804yQmGCaWHzTjKCYcJpYfNOMsJhAmph804yAmJCamHzTjJCYoJqYfNOMoJiwmph804ywmICa2HzTjICY0JrYfNOMkJjgmth804ygmPCa2HzTjLCYwJsYfNOMgJkQmxh804yQmSCbGHzTjKCZMJsYfNOMsJkAm1h804yAmVCbWHzTjJCZYJtYfNOMoJlwm1h804ywmUCbmHzTjICZkJuYfNOMkJmgm5h804ygmbCbmHzTjLCZgJvYfNOMgJnQm9h804yQmeCb2HzTjKCZ8JvYfNOMsJn0PiAIGHzTjLA+IAg0PiEIGHzTjLA+IQg0PiIIGHzTjLA+Igg0PiMIGHzTjLA+Iwg0PiQIGHzTjLA+JAg0PiUIGHzTjLA+JQg0PiYIGHzTjLA+Jgg0PicIGHzTjLA+Jwg0PioIGHzTjLA+Kgg0PisIGHzTjLA+Kwg0PiwIGHzTjLA+LAg0Pi0IGHzTjLA+LQg0Pi4IGHzTjLA+Lgg0Pi8IGHzTjLA+LwgcEcQtVgkxPIBBCBoQPSAMCBgACDD9jlAYGD/9xj/T/YAcMDytjBgYU7yhBDO8gAAT/QAUQFgRvIAAb/zT4/E8gABGCC/82+PiGAwIgAgCmAQvQAgcEeAtU/wgFBP9AAhAPB4+AAggL0AvwAgcEcB8AEDGURLCCfQWR4DKQPwAwwT0yPwAwMy+AgbBDsg+AgbMvgGHCD4Bhwy+AQcIPgEHDL4Ahwg+AIc7dG88QAPC9ARiLzxAQ8BgAbQUYi88QIPQYAcv5GIgYAAIHBHAL8AIHBHLenwRQHwAQMZRF/qUQwr0OJGvPEBD5i/T/ABCsrxAA6q8QEIACMw+BNQMvgTYLVCItGYRRjQAutDBQDrQwZ3iGyIp0IT0Q7rAwe8HAzQtIipiIxCDdH5HAbQ8YjsiKFCCdEEM5pF3tFgRL3o8IUBMwLgAjMA4AMzT+pDDGBEvejwhU/wAAIAtRNGlEaWRiA5Ir+g6AxQoOgMULHxIAG/9PevCQcov6DoDFBIvwzAXfgE64kAKL9A+AQrCL9wR0i/IPgCKxHwgE8YvwD4AStwRwAAAAA= + pc_init: 0x225 + pc_uninit: 0x275 + pc_program_page: 0x291 + pc_erase_sector: 0x28d + pc_erase_all: 0x279 + data_section_offset: 0x3c4 + flash_properties: + address_range: + start: 0x10000000 + end: 0x10080000 + page_size: 0x100 + erased_byte_value: 0x0 + program_page_timeout: 3000 + erase_sector_timeout: 3000 + sectors: + - size: 0x2000 + address: 0x0 diff --git a/scripts/prep-flash.gdb b/scripts/prep-flash.gdb new file mode 100644 index 0000000..e7b843c --- /dev/null +++ b/scripts/prep-flash.gdb @@ -0,0 +1,8 @@ +target remote localhost:2331 + +echo Disabling watchdog\n +set *0x400210C0 = 0x1ACCE551 +set *0x40021008 = 0x0 + +echo Disabling Instruction Memory protection\n +set *0x40010010 = 0x1 diff --git a/scripts/prep-flash.sh b/scripts/prep-flash.sh new file mode 100755 index 0000000..1afc35a --- /dev/null +++ b/scripts/prep-flash.sh @@ -0,0 +1,3 @@ +#!/bin/bash +# Alternative way to unlock the ROM protection of the VA416XX to allow flashing +gdb-multiarch -q --batch -ex 'source prep-flash.gdb' \ No newline at end of file diff --git a/va416xx-hal/.cargo/config.toml b/va416xx-hal/.cargo/config.toml new file mode 100644 index 0000000..7318f9a --- /dev/null +++ b/va416xx-hal/.cargo/config.toml @@ -0,0 +1,38 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# uncomment ONE of these three option to make `cargo run` start a GDB session +# which option to pick depends on your system +# If the RevA board is used, replace jlink.gdb with jlink-reva.gdb +# runner = "arm-none-eabi-gdb -q -x jlink.gdb" +# runner = "gdb-multiarch -q -x jlink.gdb" +# runner = "gdb -q -x openocd.gdb" +# runner = "gdb-multiarch -q -x jlink.gdb" + +rustflags = [ + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", + + # LLD (shipped with the Rust toolchain) is used as the default linker + "-C", "link-arg=-Tlink.x", + + # if you run into problems with LLD switch to the GNU linker by commenting out + # this line + # "-C", "linker=arm-none-eabi-ld", + + # if you need to link to pre-compiled C libraries provided by a C toolchain + # use GCC as the linker by commenting out both lines above and then + # uncommenting the three lines below + # "-C", "linker=arm-none-eabi-gcc", + # "-C", "link-arg=-Wl,-Tlink.x", + # "-C", "link-arg=-nostartfiles", +] + +[build] +# Pick ONE of these compilation targets +# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ +# target = "thumbv7m-none-eabi" # Cortex-M3 +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) +target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) +# target = "thumbv8m.base-none-eabi" # Cortex-M23 +# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU) +# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU) \ No newline at end of file diff --git a/va416xx-hal/.cargo/def-config.toml b/va416xx-hal/.cargo/def-config.toml new file mode 100644 index 0000000..74cd913 --- /dev/null +++ b/va416xx-hal/.cargo/def-config.toml @@ -0,0 +1,39 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# uncomment ONE of these three option to make `cargo run` start a GDB session +# which option to pick depends on your system +# If the RevA board is used, replace jlink.gdb with jlink-reva.gdb +# runner = "arm-none-eabi-gdb -q -x jlink/jlink.gdb" +# runner = "gdb-multiarch -q -x jlink/jlink.gdb" + +# runner = "arm-none-eabi-gdb -q -x jlink/jlink-reva.gdb" +# runner = "gdb-multiarch -q -x jlink/jlink-reva.gdb" + +rustflags = [ + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", + + # LLD (shipped with the Rust toolchain) is used as the default linker + "-C", "link-arg=-Tlink.x", + + # if you run into problems with LLD switch to the GNU linker by commenting out + # this line + # "-C", "linker=arm-none-eabi-ld", + + # if you need to link to pre-compiled C libraries provided by a C toolchain + # use GCC as the linker by commenting out both lines above and then + # uncommenting the three lines below + # "-C", "linker=arm-none-eabi-gcc", + # "-C", "link-arg=-Wl,-Tlink.x", + # "-C", "link-arg=-nostartfiles", +] + +[build] +# Pick ONE of these compilation targets +# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ +# target = "thumbv7m-none-eabi" # Cortex-M3 +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) +target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) +# target = "thumbv8m.base-none-eabi" # Cortex-M23 +# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU) +# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU) \ No newline at end of file diff --git a/va416xx-hal/.gitignore b/va416xx-hal/.gitignore new file mode 100644 index 0000000..96ef6c0 --- /dev/null +++ b/va416xx-hal/.gitignore @@ -0,0 +1,2 @@ +/target +Cargo.lock diff --git a/va416xx-hal/Cargo.toml b/va416xx-hal/Cargo.toml new file mode 100644 index 0000000..aa91a5e --- /dev/null +++ b/va416xx-hal/Cargo.toml @@ -0,0 +1,43 @@ +[package] +name = "va416xx-hal" +version = "0.1.0" +authors = ["Robin Mueller "] +edition = "2021" +description = "HAL for the Vorago VA416xx family of MCUs" +homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx-hal" +repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx-hal" +license = "Apache-2.0" +keywords = ["no-std", "hal", "cortex-m", "vorago", "va416xx"] +categories = ["embedded", "no-std", "hardware-support"] + +[dependencies] +cortex-m = { version = "0.7", features = ["critical-section-single-core"] } +nb = "1" +paste = "1" +embedded-hal-nb = "1" +embedded-hal = "1" +embedded-io = "0.6" +typenum = "1" +defmt = { version = "0.3", optional = true } +fugit = "0.3" +delegate = "0.12" + +[dependencies.void] +version = "1" +default-features = false + +[dependencies.va416xx] +path = "../va416xx" +default-features = false +version = "0.1.0" +features = ["critical-section"] + +[features] +default = ["rt", "revb"] +rt = ["va416xx/rt"] +defmt = ["dep:defmt", "fugit/defmt"] +revb = [] + +[package.metadata.docs.rs] +all-features = true +rustdoc-args = ["--generate-link-to-definition"] diff --git a/va416xx-hal/LICENSE-APACHE b/va416xx-hal/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/va416xx-hal/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. 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You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. 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However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS + +APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/va416xx-hal/NOTICE b/va416xx-hal/NOTICE new file mode 100644 index 0000000..5a0a3dc --- /dev/null +++ b/va416xx-hal/NOTICE @@ -0,0 +1,3 @@ +Rust Hardware Abstraction Layer (HAL) crate for the Vorago VA416xx family of MCUs + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/va416xx-hal/README.md b/va416xx-hal/README.md new file mode 100644 index 0000000..ae7a0e3 --- /dev/null +++ b/va416xx-hal/README.md @@ -0,0 +1,67 @@ +# HAL for the Vorago VA416xx MCU family + +This repository contains the **H**ardware **A**bstraction **L**ayer (HAL), which is an additional +hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx). + +It is the result of reading the datasheet for the device and encoding a type-safe layer over the +raw PAC. This crate also implements traits specified by the +[embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with +various drivers in the embedded rust ecosystem. + +## Supported Boards + + The first way to use this HAL will probably be with the + [PEB1 development board](https://www.voragotech.com/products/peb1va416x0-development-kit). + The BSP provided for this board also contains instructions how to flash the board. + +## Building + +Building an application requires the `thumbv7em-none-eabihf` cross-compiler toolchain. +If you have not installed it yet, you can do so with + +```sh +rustup target add thumbv7em-none-eabihf +``` + +After that, you can use `cargo build` to build the development version of the crate. + +If you have not done this yet, it is recommended to read some of the excellent resources +available to learn Rust: + +- [Rust Embedded Book](https://docs.rust-embedded.org/book/) +- [Rust Discovery Book](https://docs.rust-embedded.org/discovery/) + +## Setting up your own binary crate + +If you have a custom board, you might be interested in setting up a new binary crate for your +project. These steps aim to provide a complete list to get a binary crate working to flash +your custom board. + +The hello world of embedded development is usually to blinky a LED. This example +is contained within the +[examples folder](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/blinky.rs). + +1. Set up your Rust cross-compiler if you have not done so yet. See more in the [build chapter](#Building) +2. Create a new binary crate with `cargo init` +3. To ensure that `cargo build` cross-compiles, it is recommended to create a `.cargo/config.toml` + file. A sample `.cargo/config.toml` file is provided in this repository as well +4. Copy the `memory.x` file into your project. This file contains information required by the linker. +5. Copy the `blinky.rs` file to the `src/main.rs` file in your binary crate +6. You need to add some dependencies to your `Cargo.toml` file + + ```toml + [dependencies] + cortex-m = "" + cortex-m-rt = "" + panic-halt = "" + embedded-hal = "" + + [dependencies.va416xx-hal] + version = "" + features = ["rt"] + ``` + +6. Build the application with `cargo build` + +7. Flashing the board might work differently for different boards and there is usually + more than one way. You can find example instructions in primary README. diff --git a/va416xx-hal/jlink-gdb.sh b/va416xx-hal/jlink-gdb.sh new file mode 100755 index 0000000..65e187f --- /dev/null +++ b/va416xx-hal/jlink-gdb.sh @@ -0,0 +1,5 @@ +#!/bin/bash +# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary +# to disable ROM protection to allow flashing +JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \ + -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript diff --git a/va416xx-hal/jlink/JLinkSettings.JLinkScript b/va416xx-hal/jlink/JLinkSettings.JLinkScript new file mode 100644 index 0000000..59cff80 --- /dev/null +++ b/va416xx-hal/jlink/JLinkSettings.JLinkScript @@ -0,0 +1,77 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 1995 - 2018 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +---------------------------------------------------------------------- +File : JLinkSettings.JLinkScript +Purpose : J-Link target setup file for VORAGO VA416xx +---------------------------END-OF-HEADER------------------------------ +*/ + +int DisableRomProt(void) { + JLINK_SYS_Report("VA416XX: Disabling ROM protection"); + return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1 +} + +int DisableWatchdog(void) { + JLINK_MEM_WriteU32(0x400210C0, 0x1ACCE551); // WDOGLOCK = 0x1ACCE551 + JLINK_MEM_WriteU32(0x40021008, 0x0); // WDOGCONTROL = 0x0 (diable) +} + +int SetupTarget (void) { + JLINK_SYS_Report("SetupTarget()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* AfterResetTarget +*/ +int AfterResetTarget (void) { + JLINK_SYS_Report("AfterResetTarget()"); + // disable watchdog and unlock code RAM for write + DisableWatchdog(); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* BeforeTargetDownload +*/ +int BeforeTargetDownload (void) { + JLINK_SYS_Report("BeforeTargetDownload()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* AfterTargetDownload +*/ +int AfterTargetDownload (void) { + JLINK_SYS_Report("AfterTargetDownload()"); + return DisableRomProt(); // ROM_PROT = 0x0 +} + +/********************************************************************* +* +* HandleBeforeFlashProg +*/ +int HandleBeforeFlashProg(void) { + JLINK_SYS_Report("HandleBeforeFlashProg()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* HandleAfterFlashProg +*/ +int HandleAfterFlashProg(void) { + JLINK_SYS_Report("HandleAfterFlashProg()"); + return DisableRomProt(); // ROM_PROT = 0x0 +} \ No newline at end of file diff --git a/va416xx-hal/jlink/jlink-reva.gdb b/va416xx-hal/jlink/jlink-reva.gdb new file mode 100644 index 0000000..8712a8e --- /dev/null +++ b/va416xx-hal/jlink/jlink-reva.gdb @@ -0,0 +1,13 @@ +target remote localhost:2331 + +# For some reason, this is problematic even if the JLinkScript disabled the remote +# write protection. Therefore, don't do it for now +# This is only problematic on board RevA +# monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/va416xx-hal/jlink/jlink.gdb b/va416xx-hal/jlink/jlink.gdb new file mode 100644 index 0000000..615efdc --- /dev/null +++ b/va416xx-hal/jlink/jlink.gdb @@ -0,0 +1,11 @@ +target remote localhost:2331 + +# Reset is problematic on RevA, okay for RevB +monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/va416xx-hal/memory.x b/va416xx-hal/memory.x new file mode 100644 index 0000000..cf01aa3 --- /dev/null +++ b/va416xx-hal/memory.x @@ -0,0 +1,14 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 256K + /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ + RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K + SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +/* SRAM_0 can be used for all busses: Instruction, Data and System */ +/* SRAM_1 only supports the system bus */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM) - 4; diff --git a/va416xx-hal/src/clock.rs b/va416xx-hal/src/clock.rs new file mode 100644 index 0000000..81468a2 --- /dev/null +++ b/va416xx-hal/src/clock.rs @@ -0,0 +1,537 @@ +//! API for using the [crate::pac::Clkgen] peripheral. +//! +//! It also includes functionality to enable the peripheral clocks. +//! Calling [ClkgenExt::constrain] on the [crate::pac::Clkgen] peripheral generates the +//! [ClkgenCfgr] structure which can be used to configure and set up the clock. +//! +//! Calling [ClkgenCfgr::freeze] returns the frozen clock configuration inside the [Clocks] +//! structure. This structure can also be used to configure other structures provided by this HAL. +//! +//! # Examples +//! +//! - [UART example on the PEB1 board](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs) +use crate::pac; + +use crate::time::Hertz; + +pub const HBO_FREQ: Hertz = Hertz::from_raw(20_000_000); +pub const XTAL_OSC_TSTART_MS: u32 = 15; + +#[derive(Copy, Clone, PartialEq)] +pub enum PeripheralSelect { + Spi0 = 0, + Spi1 = 1, + Spi2 = 2, + Spi3 = 3, + Uart0 = 4, + Uart1 = 5, + Uart2 = 6, + I2c0 = 7, + I2c1 = 8, + I2c2 = 9, + Can0 = 10, + Can1 = 11, + Rng = 12, + Adc = 13, + Dac = 14, + Dma = 15, + Ebi = 16, + Eth = 17, + Spw = 18, + Clkgen = 19, + IrqRouter = 20, + IoConfig = 21, + Utility = 22, + Watchdog = 23, + PortA = 24, + PortB = 25, + PortC = 26, + PortD = 27, + PortE = 28, + PortF = 29, + PortG = 30, +} + +pub type PeripheralClocks = PeripheralSelect; + +#[derive(Debug, PartialEq, Eq)] +pub enum FilterClkSel { + SysClk = 0, + Clk1 = 1, + Clk2 = 2, + Clk3 = 3, + Clk4 = 4, + Clk5 = 5, + Clk6 = 6, + Clk7 = 7, +} + +#[inline(always)] +pub fn enable_peripheral_clock(syscfg: &mut pac::Sysconfig, clock: PeripheralSelect) { + syscfg + .peripheral_clk_enable() + .modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) }); +} + +#[inline(always)] +pub fn disable_peripheral_clock(syscfg: &mut pac::Sysconfig, clock: PeripheralSelect) { + syscfg + .peripheral_clk_enable() + .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) }); +} + +#[inline(always)] +pub fn assert_periph_reset(syscfg: &mut pac::Sysconfig, periph: PeripheralSelect) { + syscfg + .peripheral_reset() + .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << periph as u8)) }); +} + +#[inline(always)] +pub fn deassert_periph_reset(syscfg: &mut pac::Sysconfig, periph: PeripheralSelect) { + syscfg + .peripheral_reset() + .modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph as u8)) }); +} + +pub trait SyscfgExt { + fn enable_peripheral_clock(&mut self, clock: PeripheralClocks); + + fn disable_peripheral_clock(&mut self, clock: PeripheralClocks); + + fn assert_periph_reset(&mut self, clock: PeripheralSelect); + + fn deassert_periph_reset(&mut self, clock: PeripheralSelect); +} + +impl SyscfgExt for pac::Sysconfig { + #[inline(always)] + fn enable_peripheral_clock(&mut self, clock: PeripheralClocks) { + enable_peripheral_clock(self, clock) + } + + #[inline(always)] + fn disable_peripheral_clock(&mut self, clock: PeripheralClocks) { + disable_peripheral_clock(self, clock) + } + + #[inline(always)] + fn assert_periph_reset(&mut self, clock: PeripheralSelect) { + assert_periph_reset(self, clock) + } + + #[inline(always)] + fn deassert_periph_reset(&mut self, clock: PeripheralSelect) { + deassert_periph_reset(self, clock) + } +} + +/// Refer to chapter 8 (p.57) of the programmers guide for detailed information. +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkselSys { + // Internal Heart-Beat Osciallator. Not tightly controlled (+/-20 %). Not recommended as the regular clock! + Hbo = 0b00, + // External clock signal on XTAL_N line, 1-100 MHz + XtalN = 0b01, + // Internal Phase-Locked Loop. + Pll = 0b10, + // Crystal oscillator amplified, 4-10 MHz. + XtalOsc = 0b11, +} + +/// This selects the input clock to the the CLKGEN peripheral in addition to the HBO clock. +/// +/// This can either be a clock connected directly on the XTAL_N line or a chrystal on the XTAL_P +/// line which goes through an oscillator amplifier. +/// +/// Refer to chapter 8 (p.57) of the programmers guide for detailed information. +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum RefClkSel { + #[default] + None = 0b00, + XtalOsc = 0b01, + XtalN = 0b10, +} + +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkDivSel { + #[default] + Div1 = 0b00, + Div2 = 0b01, + Div4 = 0b10, + Div8 = 0b11, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum AdcClkDivSel { + Div8 = 0b00, + Div4 = 0b01, + Div2 = 0b10, + Div1 = 0b11, +} + +#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct PllCfg { + /// Reference clock divider. + pub clkr: u8, + /// Clock divider on feedback path + pub clkf: u8, + // Output clock divider. + pub clkod: u8, + /// Bandwidth adjustment + pub bwadj: u8, +} + +pub fn clk_after_div(clk: Hertz, div_sel: ClkDivSel) -> Hertz { + match div_sel { + ClkDivSel::Div1 => clk, + ClkDivSel::Div2 => clk / 2, + ClkDivSel::Div4 => clk / 4, + ClkDivSel::Div8 => clk / 8, + } +} + +/// Wait for 500 reference clock cycles like specified in the datasheet. +pub fn pll_setup_delay() { + for _ in 0..500 { + cortex_m::asm::nop() + } +} + +pub trait ClkgenExt { + fn constrain(self) -> ClkgenCfgr; +} + +impl ClkgenExt for pac::Clkgen { + fn constrain(self) -> ClkgenCfgr { + ClkgenCfgr { + source_clk: None, + ref_clk_sel: RefClkSel::None, + clksel_sys: ClkselSys::Hbo, + clk_div_sel: ClkDivSel::Div1, + clk_lost_detection: false, + pll_lock_lost_detection: false, + pll_cfg: None, + clkgen: self, + } + } +} + +pub struct ClkgenCfgr { + ref_clk_sel: RefClkSel, + clksel_sys: ClkselSys, + clk_div_sel: ClkDivSel, + /// The source clock frequency which is either an external clock connected to XTAL_N, or a + /// crystal connected to the XTAL_OSC input. + source_clk: Option, + pll_cfg: Option, + clk_lost_detection: bool, + /// Feature only works on revision B of the board. + #[cfg(feature = "revb")] + pll_lock_lost_detection: bool, + clkgen: pac::Clkgen, +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct ClkSourceFreqNotSet; + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum ClkCfgError { + ClkSourceFreqNotSet, + PllConfigNotSet, + PllInitError, + InconsistentCfg, +} + +/// Delays a given amount of milliseconds. +/// +/// Taken from the HAL implementation. This implementation is probably not precise and it +/// also blocks! +pub fn hbo_clock_delay_ms(ms: u32) { + let wdt = unsafe { pac::WatchDog::steal() }; + for _ in 0..ms { + for _ in 0..10_000 { + cortex_m::asm::nop(); + } + wdt.wdogintclr().write(|w| unsafe { w.bits(1) }); + } +} + +impl ClkgenCfgr { + #[inline] + pub fn source_clk(mut self, src_clk: Hertz) -> Self { + self.source_clk = Some(src_clk); + self + } + + /// This function can be used to utilize the XTAL_N clock input directly without the + /// oscillator. + /// + /// It sets the internal configuration to [ClkselSys::XtalN] and [RefClkSel::XtalN]. + #[inline] + pub fn xtal_n_clk(mut self) -> Self { + self.clksel_sys = ClkselSys::XtalN; + self.ref_clk_sel = RefClkSel::XtalN; + self + } + + #[inline] + pub fn xtal_n_clk_with_src_freq(mut self, src_clk: Hertz) -> Self { + self = self.xtal_n_clk(); + self.source_clk(src_clk) + } + + #[inline] + pub fn clksel_sys(mut self, clksel_sys: ClkselSys) -> Self { + self.clksel_sys = clksel_sys; + self + } + + #[inline] + pub fn ref_clk_sel(mut self, ref_clk_sel: RefClkSel) -> Self { + self.ref_clk_sel = ref_clk_sel; + self + } + + /// Configures all clocks and return a clock configuration structure containing the final + /// frozen clock. + /// + /// Internal implementation details: This implementation is based on the HAL implementation + /// which performs a lot of delays. I do not know if all of those are necessary, but + /// I am going to be conservative here and assume that the vendor has tested though and + /// might have had a reason for those, so I am going to keep them. Chances are, this + /// process only has to be performed once, and it does not matter if it takes a few + /// microseconds or milliseconds longer. + pub fn freeze(self, syscfg: &mut pac::Sysconfig) -> Result { + // Sanitize configuration. + if self.source_clk.is_none() { + return Err(ClkCfgError::ClkSourceFreqNotSet); + } + if self.clksel_sys == ClkselSys::XtalOsc && self.ref_clk_sel != RefClkSel::XtalOsc { + return Err(ClkCfgError::InconsistentCfg); + } + if self.clksel_sys == ClkselSys::XtalN && self.ref_clk_sel != RefClkSel::XtalN { + return Err(ClkCfgError::InconsistentCfg); + } + if self.clksel_sys == ClkselSys::Pll && self.pll_cfg.is_none() { + return Err(ClkCfgError::PllConfigNotSet); + } + + syscfg.enable_peripheral_clock(PeripheralSelect::Clkgen); + let mut final_sysclk = self.source_clk.unwrap(); + // The HAL forces back the HBO clock here with a delay.. Even though this is + // not stricly necessary when coming from a fresh start, it could be still become relevant + // later if the clock lost detection mechanism require a re-configuration of the clocks. + // Therefore, we do it here as well. + self.clkgen + .ctrl0() + .modify(|_, w| unsafe { w.clksel_sys().bits(ClkselSys::Hbo as u8) }); + pll_setup_delay(); + self.clkgen + .ctrl0() + .modify(|_, w| unsafe { w.clk_div_sel().bits(ClkDivSel::Div1 as u8) }); + + // Set up oscillator and PLL input clock. + self.clkgen + .ctrl0() + .modify(|_, w| unsafe { w.ref_clk_sel().bits(self.ref_clk_sel as u8) }); + self.clkgen.ctrl1().modify(|_, w| { + w.xtal_en().clear_bit(); + w.xtal_n_en().clear_bit(); + w + }); + match self.ref_clk_sel { + RefClkSel::None => pll_setup_delay(), + RefClkSel::XtalOsc => { + self.clkgen.ctrl1().modify(|_, w| w.xtal_en().set_bit()); + hbo_clock_delay_ms(XTAL_OSC_TSTART_MS); + } + RefClkSel::XtalN => { + self.clkgen.ctrl1().modify(|_, w| w.xtal_n_en().set_bit()); + pll_setup_delay() + } + } + + // Set up PLL configuration. + match self.pll_cfg { + Some(cfg) => { + self.clkgen.ctrl0().modify(|_, w| w.pll_pwdn().clear_bit()); + // Done in C HAL. I guess this gives the PLL some time to power down properly. + cortex_m::asm::nop(); + cortex_m::asm::nop(); + self.clkgen.ctrl0().modify(|_, w| { + unsafe { + w.pll_clkf().bits(cfg.clkf); + } + unsafe { + w.pll_clkr().bits(cfg.clkr); + } + unsafe { + w.pll_clkod().bits(cfg.clkod); + } + unsafe { + w.pll_bwadj().bits(cfg.bwadj); + } + w.pll_test().clear_bit(); + w.pll_bypass().clear_bit(); + w.pll_intfb().set_bit() + }); + // Taken from SystemCoreClockUpdate implementation from Vorago. + final_sysclk /= cfg.clkr as u32 + 1; + final_sysclk *= cfg.clkf as u32 + 1; + final_sysclk /= cfg.clkod as u32 + 1; + + // Reset PLL. + self.clkgen.ctrl0().modify(|_, w| w.pll_reset().set_bit()); + // The HAL does this, the datasheet specifies a delay of 5 us. I guess it does not + // really matter because the PLL lock detect is used later.. + pll_setup_delay(); + self.clkgen.ctrl0().modify(|_, w| w.pll_reset().clear_bit()); + pll_setup_delay(); + + // check for lock + let stat = self.clkgen.stat().read(); + if stat.fbslip().bit() || stat.rfslip().bit() { + pll_setup_delay(); + if stat.fbslip().bit() || stat.rfslip().bit() { + // This is what the HAL does. We could continue, but then we would at least + // have to somehow report a partial error.. Chances are, the user does not + // want to continue with a broken PLL clock. + return Err(ClkCfgError::PllInitError); + } + } + } + None => self.clkgen.ctrl0().modify(|_, w| w.pll_pwdn().set_bit()), + } + + if self.clk_lost_detection { + rearm_sysclk_lost_with_periph(&self.clkgen) + } + #[cfg(feature = "revb")] + if self.pll_lock_lost_detection { + rearm_pll_lock_lost_with_periph(&self.clkgen) + } + + self.clkgen + .ctrl0() + .modify(|_, w| unsafe { w.clk_div_sel().bits(self.clk_div_sel as u8) }); + final_sysclk = clk_after_div(final_sysclk, self.clk_div_sel); + + // The HAL does this. I don't know why.. + pll_setup_delay(); + + self.clkgen + .ctrl0() + .modify(|_, w| unsafe { w.clksel_sys().bits(self.clksel_sys as u8) }); + + // I will just do the ADC stuff like Vorago does it. + // ADC clock (must be 2-12.5 MHz) + // NOTE: Not using divide by 1 or /2 ratio in REVA silicon because of triggering issue + // For this reason, keep SYSCLK above 8MHz to have the ADC /4 ratio in range) + if final_sysclk.raw() <= 50_000_000 { + self.clkgen + .ctrl1() + .modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div4 as u8) }); + } else { + self.clkgen + .ctrl1() + .modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div8 as u8) }); + } + + Ok(Clocks { + sysclk: final_sysclk, + apb1: final_sysclk / 2, + apb2: final_sysclk / 4, + }) + } +} + +/// Frozen clock frequencies +/// +/// The existence of this value indicates that the clock configuration can no longer be changed. +/// The [self] module documentation gives some more information on how to retrieve an instance +/// of this structure. +#[derive(Copy, Clone, PartialEq, Eq, Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct Clocks { + sysclk: Hertz, + apb1: Hertz, + apb2: Hertz, +} + +impl Clocks { + /// Returns the frequency of the HBO clock + pub fn hbo(&self) -> Hertz { + HBO_FREQ + } + + /// Returns the frequency of the APB0 which is equal to the system clock. + pub fn apb0(&self) -> Hertz { + self.sysclk() + } + + /// Returns system clock divied by 2. + pub fn apb1(&self) -> Hertz { + self.apb1 + } + + /// Returns system clock divied by 4. + pub fn apb2(&self) -> Hertz { + self.apb2 + } + + /// Returns the system (core) frequency + pub fn sysclk(&self) -> Hertz { + self.sysclk + } +} + +pub fn rearm_sysclk_lost() { + rearm_sysclk_lost_with_periph(&unsafe { pac::Clkgen::steal() }) +} + +fn rearm_sysclk_lost_with_periph(clkgen: &pac::Clkgen) { + clkgen + .ctrl0() + .modify(|_, w| w.sys_clk_lost_det_en().set_bit()); + clkgen + .ctrl1() + .write(|w| w.sys_clk_lost_det_rearm().set_bit()); + clkgen + .ctrl1() + .write(|w| w.sys_clk_lost_det_rearm().clear_bit()); +} + +#[cfg(feature = "revb")] +pub fn rearm_pll_lock_lost() { + rearm_pll_lock_lost_with_periph(&unsafe { pac::Clkgen::steal() }) +} + +fn rearm_pll_lock_lost_with_periph(clkgen: &pac::Clkgen) { + clkgen + .ctrl1() + .modify(|_, w| w.pll_lost_lock_det_en().set_bit()); + clkgen.ctrl1().write(|w| w.pll_lck_det_rearm().set_bit()); + clkgen.ctrl1().write(|w| w.pll_lck_det_rearm().clear_bit()); +} + +#[cfg(test)] +mod tests { + + use super::*; + + #[test] + fn test_basic_div() { + assert_eq!( + clk_after_div(Hertz::from_raw(10_000_000), super::ClkDivSel::Div2), + Hertz::from_raw(5_000_000) + ); + } +} diff --git a/va416xx-hal/src/gpio/dynpin.rs b/va416xx-hal/src/gpio/dynpin.rs new file mode 100644 index 0000000..ab1c20c --- /dev/null +++ b/va416xx-hal/src/gpio/dynpin.rs @@ -0,0 +1,453 @@ +use embedded_hal::digital::{ErrorKind, ErrorType, InputPin, OutputPin, StatefulOutputPin}; + +use super::{ + reg::RegisterInterface, FilterClkSel, FilterType, InterruptEdge, InterruptLevel, Pin, PinId, + PinMode, PinState, +}; + +//================================================================================================== +// DynPinMode configurations +//================================================================================================== + +/// Value-level `enum` for disabled configurations +#[derive(PartialEq, Eq, Clone, Copy)] +pub enum DynDisabled { + Floating, + PullDown, + PullUp, +} + +/// Value-level `enum` for input configurations +#[derive(PartialEq, Eq, Clone, Copy)] +pub enum DynInput { + Floating, + PullDown, + PullUp, +} + +/// Value-level `enum` for output configurations +#[derive(PartialEq, Eq, Clone, Copy)] +pub enum DynOutput { + PushPull, + OpenDrain, + ReadablePushPull, + ReadableOpenDrain, +} + +pub type DynAlternate = crate::FunSel; + +//================================================================================================== +// DynPinMode +//================================================================================================== + +/// Value-level `enum` representing pin modes +#[derive(PartialEq, Eq, Clone, Copy)] +pub enum DynPinMode { + Input(DynInput), + Output(DynOutput), + Alternate(DynAlternate), +} + +/// Value-level variant of [`DynPinMode`] for floating input mode +pub const DYN_FLOATING_INPUT: DynPinMode = DynPinMode::Input(DynInput::Floating); +/// Value-level variant of [`DynPinMode`] for pull-down input mode +pub const DYN_PULL_DOWN_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullDown); +/// Value-level variant of [`DynPinMode`] for pull-up input mode +pub const DYN_PULL_UP_INPUT: DynPinMode = DynPinMode::Input(DynInput::PullUp); + +/// Value-level variant of [`DynPinMode`] for push-pull output mode +pub const DYN_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::PushPull); +/// Value-level variant of [`DynPinMode`] for open-drain output mode +pub const DYN_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::OpenDrain); +/// Value-level variant of [`DynPinMode`] for readable push-pull output mode +pub const DYN_RD_PUSH_PULL_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadablePushPull); +/// Value-level variant of [`DynPinMode`] for readable opendrain output mode +pub const DYN_RD_OPEN_DRAIN_OUTPUT: DynPinMode = DynPinMode::Output(DynOutput::ReadableOpenDrain); + +/// Value-level variant of [`DynPinMode`] for function select 1 +pub const DYN_ALT_FUNC_1: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel1); +/// Value-level variant of [`DynPinMode`] for function select 2 +pub const DYN_ALT_FUNC_2: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel2); +/// Value-level variant of [`DynPinMode`] for function select 3 +pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel3); + +//================================================================================================== +// DynGroup & DynPinId +//================================================================================================== + +/// Value-level `enum` for pin groups +#[derive(PartialEq, Eq, Clone, Copy)] +pub enum DynGroup { + A, + B, + C, + D, + E, + F, + G, +} + +/// Value-level `struct` representing pin IDs +#[derive(PartialEq, Eq, Clone, Copy)] +pub struct DynPinId { + pub group: DynGroup, + pub num: u8, +} + +//============================================================================== +// DynRegisters +//============================================================================== + +/// Provide a safe register interface for [`DynPin`]s +/// +/// This `struct` takes ownership of a [`DynPinId`] and provides an API to +/// access the corresponding regsiters. +struct DynRegisters { + id: DynPinId, +} + +// [`DynRegisters`] takes ownership of the [`DynPinId`], and [`DynPin`] +// guarantees that each pin is a singleton, so this implementation is safe. +unsafe impl RegisterInterface for DynRegisters { + #[inline] + fn id(&self) -> DynPinId { + self.id + } +} + +impl DynRegisters { + /// Create a new instance of [`DynRegisters`] + /// + /// # Safety + /// + /// Users must never create two simultaneous instances of this `struct` with + /// the same [`DynPinId`] + #[inline] + unsafe fn new(id: DynPinId) -> Self { + DynRegisters { id } + } +} + +//============================================================================== +// Error +//============================================================================== + +/// GPIO error type +/// +/// [`DynPin`]s are not tracked and verified at compile-time, so run-time +/// operations are fallible. This `enum` represents the corresponding errors. +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InvalidPinTypeError(pub(crate) ()); + +impl embedded_hal::digital::Error for InvalidPinTypeError { + fn kind(&self) -> embedded_hal::digital::ErrorKind { + ErrorKind::Other + } +} + +//================================================================================================== +// DynPin +//================================================================================================== + +/// A value-level pin, parameterized by [`DynPinId`] and [`DynPinMode`] +/// +/// This type acts as a type-erased version of [`Pin`]. Every pin is represented +/// by the same type, and pins are tracked and distinguished at run-time. +pub struct DynPin { + regs: DynRegisters, + mode: DynPinMode, +} + +impl DynPin { + /// Create a new [`DynPin`] + /// + /// # Safety + /// + /// Each [`DynPin`] must be a singleton. For a given [`DynPinId`], there + /// must be at most one corresponding [`DynPin`] in existence at any given + /// time. Violating this requirement is `unsafe`. + #[inline] + unsafe fn new(id: DynPinId, mode: DynPinMode) -> Self { + DynPin { + regs: DynRegisters::new(id), + mode, + } + } + + /// Return a copy of the pin ID + #[inline] + pub fn id(&self) -> DynPinId { + self.regs.id + } + + /// Return a copy of the pin mode + #[inline] + pub fn mode(&self) -> DynPinMode { + self.mode + } + + /// Convert the pin to the requested [`DynPinMode`] + #[inline] + pub fn into_mode(&mut self, mode: DynPinMode) { + // Only modify registers if we are actually changing pin mode + if mode != self.mode { + self.regs.change_mode(mode); + self.mode = mode; + } + } + + #[inline] + pub fn into_funsel_1(&mut self) { + self.into_mode(DYN_ALT_FUNC_1); + } + + #[inline] + pub fn into_funsel_2(&mut self) { + self.into_mode(DYN_ALT_FUNC_2); + } + + #[inline] + pub fn into_funsel_3(&mut self) { + self.into_mode(DYN_ALT_FUNC_3); + } + + /// Configure the pin to operate as a floating input + #[inline] + pub fn into_floating_input(&mut self) { + self.into_mode(DYN_FLOATING_INPUT); + } + + /// Configure the pin to operate as a pulled down input + #[inline] + pub fn into_pull_down_input(&mut self) { + self.into_mode(DYN_PULL_DOWN_INPUT); + } + + /// Configure the pin to operate as a pulled up input + #[inline] + pub fn into_pull_up_input(&mut self) { + self.into_mode(DYN_PULL_UP_INPUT); + } + + /// Configure the pin to operate as a push-pull output + #[inline] + pub fn into_push_pull_output(&mut self) { + self.into_mode(DYN_PUSH_PULL_OUTPUT); + } + + /// Configure the pin to operate as a push-pull output + #[inline] + pub fn into_open_drain_output(&mut self) { + self.into_mode(DYN_OPEN_DRAIN_OUTPUT); + } + + /// Configure the pin to operate as a push-pull output + #[inline] + pub fn into_readable_push_pull_output(&mut self) { + self.into_mode(DYN_RD_PUSH_PULL_OUTPUT); + } + + /// Configure the pin to operate as a push-pull output + #[inline] + pub fn into_readable_open_drain_output(&mut self) { + self.into_mode(DYN_RD_OPEN_DRAIN_OUTPUT); + } + + common_reg_if_functions!(); + + /// See p.53 of the programmers guide for more information. + /// Possible delays in clock cycles: + /// - Delay 1: 1 + /// - Delay 2: 2 + /// - Delay 1 + Delay 2: 3 + #[inline] + pub fn delay(self, delay_1: bool, delay_2: bool) -> Result { + match self.mode { + DynPinMode::Output(_) => { + self.regs.delay(delay_1, delay_2); + Ok(self) + } + _ => Err(InvalidPinTypeError(())), + } + } + + /// See p.52 of the programmers guide for more information. + /// When configured for pulse mode, a given pin will set the non-default state for exactly + /// one clock cycle before returning to the configured default state + pub fn pulse_mode( + self, + enable: bool, + default_state: PinState, + ) -> Result { + match self.mode { + DynPinMode::Output(_) => { + self.regs.pulse_mode(enable, default_state); + Ok(self) + } + _ => Err(InvalidPinTypeError(())), + } + } + + /// See p.37 and p.38 of the programmers guide for more information. + #[inline] + pub fn filter_type( + self, + filter: FilterType, + clksel: FilterClkSel, + ) -> Result { + match self.mode { + DynPinMode::Input(_) => { + self.regs.filter_type(filter, clksel); + Ok(self) + } + _ => Err(InvalidPinTypeError(())), + } + } + + pub fn interrupt_edge(mut self, edge_type: InterruptEdge) -> Result { + match self.mode { + DynPinMode::Input(_) | DynPinMode::Output(_) => { + self.regs.interrupt_edge(edge_type); + self.irq_enb(); + Ok(self) + } + _ => Err(InvalidPinTypeError(())), + } + } + + pub fn interrupt_level( + mut self, + level_type: InterruptLevel, + ) -> Result { + match self.mode { + DynPinMode::Input(_) | DynPinMode::Output(_) => { + self.regs.interrupt_level(level_type); + self.irq_enb(); + Ok(self) + } + _ => Err(InvalidPinTypeError(())), + } + } + + #[inline] + fn _read(&self) -> Result { + match self.mode { + DynPinMode::Input(_) | DYN_RD_OPEN_DRAIN_OUTPUT | DYN_RD_PUSH_PULL_OUTPUT => { + Ok(self.regs.read_pin()) + } + _ => Err(InvalidPinTypeError(())), + } + } + #[inline] + fn _write(&mut self, bit: bool) -> Result<(), InvalidPinTypeError> { + match self.mode { + DynPinMode::Output(_) => { + self.regs.write_pin(bit); + Ok(()) + } + _ => Err(InvalidPinTypeError(())), + } + } + + #[inline] + fn _is_low(&self) -> Result { + self._read().map(|v| !v) + } + #[inline] + fn _is_high(&self) -> Result { + self._read() + } + #[inline] + fn _set_low(&mut self) -> Result<(), InvalidPinTypeError> { + self._write(false) + } + #[inline] + fn _set_high(&mut self) -> Result<(), InvalidPinTypeError> { + self._write(true) + } +} + +//============================================================================== +// Convert between Pin and DynPin +//============================================================================== + +impl From> for DynPin +where + I: PinId, + M: PinMode, +{ + /// Erase the type-level information in a [`Pin`] and return a value-level + /// [`DynPin`] + #[inline] + fn from(_pin: Pin) -> Self { + // The `Pin` is consumed, so it is safe to replace it with the + // corresponding `DynPin` + unsafe { DynPin::new(I::DYN, M::DYN) } + } +} + +impl TryFrom for Pin +where + I: PinId, + M: PinMode, +{ + type Error = InvalidPinTypeError; + + /// Try to recreate a type-level [`Pin`] from a value-level [`DynPin`] + /// + /// There is no way for the compiler to know if the conversion will be + /// successful at compile-time. We must verify the conversion at run-time + /// or refuse to perform it. + #[inline] + fn try_from(pin: DynPin) -> Result { + if pin.regs.id == I::DYN && pin.mode == M::DYN { + // The `DynPin` is consumed, so it is safe to replace it with the + // corresponding `Pin` + Ok(unsafe { Self::new() }) + } else { + Err(InvalidPinTypeError(())) + } + } +} + +//============================================================================== +// Embedded HAL v1 traits +//============================================================================== + +impl ErrorType for DynPin { + type Error = InvalidPinTypeError; +} + +impl OutputPin for DynPin { + #[inline] + fn set_high(&mut self) -> Result<(), Self::Error> { + self._set_high() + } + #[inline] + fn set_low(&mut self) -> Result<(), Self::Error> { + self._set_low() + } +} + +impl InputPin for DynPin { + #[inline] + fn is_high(&mut self) -> Result { + self._is_high() + } + #[inline] + fn is_low(&mut self) -> Result { + self._is_low() + } +} + +impl StatefulOutputPin for DynPin { + #[inline] + fn is_set_high(&mut self) -> Result { + self._is_high() + } + #[inline] + fn is_set_low(&mut self) -> Result { + self._is_low() + } +} diff --git a/va416xx-hal/src/gpio/mod.rs b/va416xx-hal/src/gpio/mod.rs new file mode 100644 index 0000000..6290bda --- /dev/null +++ b/va416xx-hal/src/gpio/mod.rs @@ -0,0 +1,82 @@ +//! # API for the GPIO peripheral +//! +//! The implementation of this GPIO module is heavily based on the +//! [ATSAMD HAL implementation](https://docs.rs/atsamd-hal/latest/atsamd_hal/gpio/index.html). +//! +//! This API provides two different submodules, [pin] and [dynpin], +//! representing two different ways to handle GPIO pins. The default, [pin], +//! is a type-level API that tracks the state of each pin at compile-time. The +//! alternative, [dynpin] is a type-erased, value-level API that tracks the +//! state of each pin at run-time. +//! +//! The type-level API is strongly preferred. By representing the state of each +//! pin within the type system, the compiler can detect logic errors at +//! compile-time. Furthermore, the type-level API has absolutely zero run-time +//! cost. +//! +//! If needed, [dynpin] can be used to erase the type-level differences +//! between pins. However, by doing so, pins must now be tracked at run-time, +//! and each pin has a non-zero memory footprint. +//! +//! ## Examples +//! +//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/blinky.rs) + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct IsMaskedError; + +macro_rules! common_reg_if_functions { + () => { + paste::paste!( + #[inline] + pub fn datamask(&self) -> bool { + self.regs.datamask() + } + + #[inline] + pub fn clear_datamask(self) -> Self { + self.regs.clear_datamask(); + self + } + + #[inline] + pub fn set_datamask(self) -> Self { + self.regs.set_datamask(); + self + } + + #[inline] + pub fn is_high_masked(&self) -> Result { + self.regs.read_pin_masked() + } + + #[inline] + pub fn is_low_masked(&self) -> Result { + self.regs.read_pin_masked().map(|v| !v) + } + + #[inline] + pub fn set_high_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> { + self.regs.write_pin_masked(true) + } + + #[inline] + pub fn set_low_masked(&mut self) -> Result<(), crate::gpio::IsMaskedError> { + self.regs.write_pin_masked(false) + } + + fn irq_enb(&mut self) { + self.regs.enable_irq(); + } + ); + }; +} + +pub mod pin; +pub use pin::*; + +pub mod dynpin; +pub use dynpin::*; + +mod reg; diff --git a/va416xx-hal/src/gpio/pin.rs b/va416xx-hal/src/gpio/pin.rs new file mode 100644 index 0000000..863b881 --- /dev/null +++ b/va416xx-hal/src/gpio/pin.rs @@ -0,0 +1,911 @@ +//! # Type-level module for GPIO pins +//! +//! This documentation is strongly based on the +//! [atsamd documentation](https://docs.rs/atsamd-hal/latest/atsamd_hal/gpio/pin/index.html). +//! +//! This module provides a type-level API for GPIO pins. It uses the type system +//! to track the state of pins at compile-time. Representing GPIO pins in this +//! manner incurs no run-time overhead. Each [`Pin`] struct is zero-sized, so +//! there is no data to copy around. Instead, real code is generated as a side +//! effect of type transformations, and the resulting assembly is nearly +//! identical to the equivalent, hand-written C. +//! +//! To track the state of pins at compile-time, this module uses traits to +//! represent [type classes] and types as instances of those type classes. For +//! example, the trait [`InputConfig`] acts as a [type-level enum] of the +//! available input configurations, and the types [`Floating`], [`PullDown`] and +//! [`PullUp`] are its type-level variants. +//! +//! Type-level [`Pin`]s are parameterized by two type-level enums, [`PinId`] and +//! [`PinMode`]. +//! +//! ``` +//! pub struct Pin +//! where +//! I: PinId, +//! M: PinMode, +//! { +//! // ... +//! } +//! ``` +//! +//! A `PinId` identifies a pin by it's group (A to G) and pin number. Each +//! `PinId` instance is named according to its datasheet identifier, e.g. +//! [PA2]. +//! +//! A `PinMode` represents the various pin modes. The available `PinMode` +//! variants are [`Input`], [`Output`] and [`Alternate`], each with its own +//! corresponding configurations. +//! +//! It is not possible for users to create new instances of a [`Pin`]. Singleton +//! instances of each pin are made available to users through the PinsX +//! struct. +//! +//! Example for the pins of PORT A: +//! +//! To create the [PinsA] struct, users must supply the PAC +//! [Port](crate::pac::Porta) peripheral. The [PinsA] struct takes +//! ownership of the [Porta] and provides the corresponding pins. Each [`Pin`] +//! within the [PinsA] struct can be moved out and used individually. +//! +//! +//! ```no_run +//! let mut peripherals = Peripherals::take().unwrap(); +//! let pinsa = PinsA::new(peripherals.porta); +//! ``` +//! +//! Pins can be converted between modes using several different methods. +//! +//! ```no_run +//! // Use one of the literal function names +//! let pa0 = pinsa.pa0.into_floating_input(); +//! // Use a generic method and one of the `PinMode` variant types +//! let pa0 = pinsa.pa0.into_mode::(); +//! // Specify the target type and use `From`/`Into` +//! let pa0: Pin = pinsa.pa27.into(); +//! ``` +//! +//! # Embedded HAL traits +//! +//! This module implements all of the embedded HAL GPIO traits for each [`Pin`] +//! in the corresponding [`PinMode`]s, namely: [`InputPin`], [`OutputPin`], +//! and [`StatefulOutputPin`]. +use core::{convert::Infallible, marker::PhantomData, mem::transmute}; + +pub use crate::clock::FilterClkSel; +use crate::typelevel::Sealed; +use embedded_hal::digital::{ErrorType, InputPin, OutputPin, StatefulOutputPin}; +use va416xx::{Porta, Portb, Portc, Portd, Porte, Portf, Portg}; + +use super::{ + reg::RegisterInterface, DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode, +}; + +//================================================================================================== +// Errors and Definitions +//================================================================================================== + +#[derive(Debug, PartialEq, Eq)] +pub enum InterruptEdge { + HighToLow, + LowToHigh, + BothEdges, +} + +#[derive(Debug, PartialEq, Eq)] +pub enum InterruptLevel { + Low = 0, + High = 1, +} + +#[derive(Debug, PartialEq, Eq)] +pub enum PinState { + Low = 0, + High = 1, +} + +//================================================================================================== +// Input configuration +//================================================================================================== + +/// Type-level enum for input configurations +/// +/// The valid options are [Floating], [PullDown] and [PullUp]. +pub trait InputConfig: Sealed { + /// Corresponding [DynInput] + const DYN: DynInput; +} + +pub enum Floating {} +pub enum PullDown {} +pub enum PullUp {} + +impl InputConfig for Floating { + const DYN: DynInput = DynInput::Floating; +} +impl InputConfig for PullDown { + const DYN: DynInput = DynInput::PullDown; +} +impl InputConfig for PullUp { + const DYN: DynInput = DynInput::PullUp; +} + +impl Sealed for Floating {} +impl Sealed for PullDown {} +impl Sealed for PullUp {} + +/// Type-level variant of [PinMode] for floating input mode +pub type InputFloating = Input; +/// Type-level variant of [PinMode] for pull-down input mode +pub type InputPullDown = Input; +/// Type-level variant of [PinMode] for pull-up input mode +pub type InputPullUp = Input; + +/// Type-level variant of [PinMode] for input modes +/// +/// Type `C` is one of three input configurations: [Floating], [PullDown] or +/// [PullUp] +pub struct Input { + cfg: PhantomData, +} + +impl Sealed for Input {} + +#[derive(Debug, PartialEq, Eq)] +pub enum FilterType { + SystemClock = 0, + DirectInputWithSynchronization = 1, + FilterOneClockCycle = 2, + FilterTwoClockCycles = 3, + FilterThreeClockCycles = 4, + FilterFourClockCycles = 5, +} + +//================================================================================================== +// Output configuration +//================================================================================================== + +pub trait OutputConfig: Sealed { + const DYN: DynOutput; +} + +pub trait ReadableOutput: Sealed {} + +/// Type-level variant of [`OutputConfig`] for a push-pull configuration +pub enum PushPull {} +/// Type-level variant of [`OutputConfig`] for an open drain configuration +pub enum OpenDrain {} + +/// Type-level variant of [`OutputConfig`] for a readable push-pull configuration +pub enum ReadablePushPull {} +/// Type-level variant of [`OutputConfig`] for a readable open-drain configuration +pub enum ReadableOpenDrain {} + +impl Sealed for PushPull {} +impl Sealed for OpenDrain {} +impl Sealed for ReadableOpenDrain {} +impl Sealed for ReadablePushPull {} +impl ReadableOutput for ReadableOpenDrain {} +impl ReadableOutput for ReadablePushPull {} + +impl OutputConfig for PushPull { + const DYN: DynOutput = DynOutput::PushPull; +} +impl OutputConfig for OpenDrain { + const DYN: DynOutput = DynOutput::OpenDrain; +} +impl OutputConfig for ReadablePushPull { + const DYN: DynOutput = DynOutput::ReadablePushPull; +} +impl OutputConfig for ReadableOpenDrain { + const DYN: DynOutput = DynOutput::ReadableOpenDrain; +} + +/// Type-level variant of [`PinMode`] for output modes +/// +/// Type `C` is one of four output configurations: [`PushPull`], [`OpenDrain`] or +/// their respective readable versions +pub struct Output { + cfg: PhantomData, +} + +impl Sealed for Output {} + +/// Type-level variant of [`PinMode`] for push-pull output mode +pub type PushPullOutput = Output; +/// Type-level variant of [`PinMode`] for open drain output mode +pub type OutputOpenDrain = Output; + +pub type OutputReadablePushPull = Output; +pub type OutputReadableOpenDrain = Output; + +//================================================================================================== +// Alternate configurations +//================================================================================================== + +/// Type-level enum for alternate peripheral function configurations +pub trait AlternateConfig: Sealed { + const DYN: DynAlternate; +} + +pub enum Funsel1 {} +pub enum Funsel2 {} +pub enum Funsel3 {} + +impl AlternateConfig for Funsel1 { + const DYN: DynAlternate = DynAlternate::Sel1; +} +impl AlternateConfig for Funsel2 { + const DYN: DynAlternate = DynAlternate::Sel2; +} +impl AlternateConfig for Funsel3 { + const DYN: DynAlternate = DynAlternate::Sel3; +} + +impl Sealed for Funsel1 {} +impl Sealed for Funsel2 {} +impl Sealed for Funsel3 {} + +/// Type-level variant of [`PinMode`] for alternate peripheral functions +/// +/// Type `C` is an [`AlternateConfig`] +pub struct Alternate { + cfg: PhantomData, +} + +impl Sealed for Alternate {} + +pub type AltFunc1 = Alternate; +pub type AltFunc2 = Alternate; +pub type AltFunc3 = Alternate; + +/// Type alias for the [`PinMode`] at reset +pub type Reset = InputFloating; + +//================================================================================================== +// Pin modes +//================================================================================================== + +/// Type-level enum representing pin modes +/// +/// The valid options are [Input], [Output] and [Alternate]. +pub trait PinMode: Sealed { + /// Corresponding [DynPinMode] + const DYN: DynPinMode; +} + +impl PinMode for Input { + const DYN: DynPinMode = DynPinMode::Input(C::DYN); +} +impl PinMode for Output { + const DYN: DynPinMode = DynPinMode::Output(C::DYN); +} +impl PinMode for Alternate { + const DYN: DynPinMode = DynPinMode::Alternate(C::DYN); +} + +//================================================================================================== +// Pin IDs +//================================================================================================== + +/// Type-level enum for pin IDs +pub trait PinId: Sealed { + /// Corresponding [DynPinId] + const DYN: DynPinId; +} + +macro_rules! pin_id { + ($Group:ident, $Id:ident, $NUM:literal) => { + // Need paste macro to use ident in doc attribute + paste::paste! { + #[doc = "Pin ID representing pin " $Id] + pub enum $Id {} + impl Sealed for $Id {} + impl PinId for $Id { + const DYN: DynPinId = DynPinId { + group: DynGroup::$Group, + num: $NUM, + }; + } + } + }; +} + +//================================================================================================== +// Pin +//================================================================================================== + +/// A type-level GPIO pin, parameterized by [`PinId`] and [`PinMode`] types + +pub struct Pin { + pub(in crate::gpio) regs: Registers, + mode: PhantomData, +} + +impl Pin { + /// Create a new [`Pin`] + /// + /// # Safety + /// + /// Each [`Pin`] must be a singleton. For a given [`PinId`], there must be + /// at most one corresponding [`Pin`] in existence at any given time. + /// Violating this requirement is `unsafe`. + #[inline] + pub(crate) unsafe fn new() -> Pin { + Pin { + regs: Registers::new(), + mode: PhantomData, + } + } + + /// Convert the pin to the requested [`PinMode`] + #[inline] + pub fn into_mode(mut self) -> Pin { + // Only modify registers if we are actually changing pin mode + // This check should compile away + if N::DYN != M::DYN { + self.regs.change_mode::(); + } + // Safe because we drop the existing Pin + unsafe { Pin::new() } + } + + /// Configure the pin for function select 1. See Programmer Guide p.40 for the function table + #[inline] + pub fn into_funsel_1(self) -> Pin { + self.into_mode() + } + + /// Configure the pin for function select 2. See Programmer Guide p.40 for the function table + #[inline] + pub fn into_funsel_2(self) -> Pin { + self.into_mode() + } + + /// Configure the pin for function select 3. See Programmer Guide p.40 for the function table + #[inline] + pub fn into_funsel_3(self) -> Pin { + self.into_mode() + } + + /// Configure the pin to operate as a floating input + #[inline] + pub fn into_floating_input(self) -> Pin { + self.into_mode() + } + + /// Configure the pin to operate as a pulled down input + #[inline] + pub fn into_pull_down_input(self) -> Pin { + self.into_mode() + } + + /// Configure the pin to operate as a pulled up input + #[inline] + pub fn into_pull_up_input(self) -> Pin { + self.into_mode() + } + + /// Configure the pin to operate as a push-pull output + #[inline] + pub fn into_push_pull_output(self) -> Pin { + self.into_mode() + } + + /// Configure the pin to operate as a readable push-pull output + #[inline] + pub fn into_readable_push_pull_output(self) -> Pin { + self.into_mode() + } + + /// Configure the pin to operate as a readable open-drain output + #[inline] + pub fn into_readable_open_drain_output(self) -> Pin { + self.into_mode() + } + + common_reg_if_functions!(); + + #[inline] + pub(crate) fn _set_high(&mut self) { + self.regs.write_pin(true) + } + + #[inline] + pub(crate) fn _set_low(&mut self) { + self.regs.write_pin(false) + } + + #[inline] + pub(crate) fn _is_low(&self) -> bool { + !self.regs.read_pin() + } + + #[inline] + pub(crate) fn _is_high(&self) -> bool { + self.regs.read_pin() + } +} + +//============================================================================== +// AnyPin +//============================================================================== + +/// Type class for [`Pin`] types +/// +/// This trait uses the [`AnyKind`] trait pattern to create a [type class] for +/// [`Pin`] types. See the `AnyKind` documentation for more details on the +/// pattern. +/// +/// ## `v1` Compatibility +/// +/// Normally, this trait would use `Is>` as a super +/// trait. But doing so would restrict implementations to only the `v2` `Pin` +/// type in this module. To aid in backwards compatibility, we want to implement +/// `AnyPin` for the `v1` `Pin` type as well. This is possible for a few +/// reasons. First, both structs are zero-sized, so there is no meaningful +/// memory layout to begin with. And even if there were, the `v1` `Pin` type is +/// a newtype wrapper around a `v2` `Pin`, and single-field structs are +/// guaranteed to have the same layout as the field, even for `repr(Rust)`. +/// +/// [`AnyKind`]: crate::typelevel#anykind-trait-pattern +/// [type class]: crate::typelevel#type-classes +pub trait AnyPin +where + Self: Sealed, + Self: From>, + Self: Into>, + Self: AsRef>, + Self: AsMut>, +{ + /// [`PinId`] of the corresponding [`Pin`] + type Id: PinId; + /// [`PinMode`] of the corresponding [`Pin`] + type Mode: PinMode; +} + +impl Sealed for Pin +where + I: PinId, + M: PinMode, +{ +} + +impl AnyPin for Pin +where + I: PinId, + M: PinMode, +{ + type Id = I; + type Mode = M; +} + +/// Type alias to recover the specific [`Pin`] type from an implementation of +/// [`AnyPin`] +/// +/// See the [`AnyKind`] documentation for more details on the pattern. +/// +/// [`AnyKind`]: crate::typelevel#anykind-trait-pattern +pub type SpecificPin

= Pin<

::Id,

::Mode>; + +impl AsRef

for SpecificPin

{ + #[inline] + fn as_ref(&self) -> &P { + // SAFETY: This is guaranteed to be safe, because P == SpecificPin

+ // Transmuting between `v1` and `v2` `Pin` types is also safe, because + // both are zero-sized, and single-field, newtype structs are guaranteed + // to have the same layout as the field anyway, even for repr(Rust). + unsafe { transmute(self) } + } +} + +impl AsMut

for SpecificPin

{ + #[inline] + fn as_mut(&mut self) -> &mut P { + // SAFETY: This is guaranteed to be safe, because P == SpecificPin

+ // Transmuting between `v1` and `v2` `Pin` types is also safe, because + // both are zero-sized, and single-field, newtype structs are guaranteed + // to have the same layout as the field anyway, even for repr(Rust). + unsafe { transmute(self) } + } +} + +//================================================================================================== +// Additional functionality +//================================================================================================== + +impl Pin> { + pub fn interrupt_edge(mut self, edge_type: InterruptEdge) -> Self { + self.regs.interrupt_edge(edge_type); + self.irq_enb(); + self + } + + pub fn interrupt_level(mut self, level_type: InterruptLevel) -> Self { + self.regs.interrupt_level(level_type); + self.irq_enb(); + self + } +} + +impl Pin> { + /// See p.53 of the programmers guide for more information. + /// Possible delays in clock cycles: + /// - Delay 1: 1 + /// - Delay 2: 2 + /// - Delay 1 + Delay 2: 3 + #[inline] + pub fn delay(self, delay_1: bool, delay_2: bool) -> Self { + self.regs.delay(delay_1, delay_2); + self + } + + /// See p.52 of the programmers guide for more information. + /// When configured for pulse mode, a given pin will set the non-default state for exactly + /// one clock cycle before returning to the configured default state + pub fn pulse_mode(self, enable: bool, default_state: PinState) -> Self { + self.regs.pulse_mode(enable, default_state); + self + } + + pub fn interrupt_edge(mut self, edge_type: InterruptEdge) -> Self { + self.regs.interrupt_edge(edge_type); + self.irq_enb(); + self + } + + pub fn interrupt_level(mut self, level_type: InterruptLevel) -> Self { + self.regs.interrupt_level(level_type); + self.irq_enb(); + self + } +} + +impl Pin> { + /// See p.37 and p.38 of the programmers guide for more information. + #[inline] + pub fn filter_type(self, filter: FilterType, clksel: FilterClkSel) -> Self { + self.regs.filter_type(filter, clksel); + self + } +} + +//================================================================================================== +// Embedded HAL traits +//================================================================================================== + +impl ErrorType for Pin +where + I: PinId, + M: PinMode, +{ + type Error = Infallible; +} + +impl OutputPin for Pin> { + #[inline] + fn set_high(&mut self) -> Result<(), Self::Error> { + self._set_high(); + Ok(()) + } + + #[inline] + fn set_low(&mut self) -> Result<(), Self::Error> { + self._set_low(); + Ok(()) + } +} + +impl InputPin for Pin> +where + I: PinId, + C: InputConfig, +{ + #[inline] + fn is_high(&mut self) -> Result { + Ok(self._is_high()) + } + #[inline] + fn is_low(&mut self) -> Result { + Ok(self._is_low()) + } +} + +impl StatefulOutputPin for Pin> +where + I: PinId, + C: OutputConfig + ReadableOutput, +{ + #[inline] + fn is_set_high(&mut self) -> Result { + Ok(self._is_high()) + } + #[inline] + fn is_set_low(&mut self) -> Result { + Ok(self._is_low()) + } +} + +impl InputPin for Pin> +where + I: PinId, + C: OutputConfig + ReadableOutput, +{ + #[inline] + fn is_high(&mut self) -> Result { + Ok(self._is_high()) + } + + #[inline] + fn is_low(&mut self) -> Result { + Ok(self._is_low()) + } +} + +//================================================================================================== +// Registers +//================================================================================================== + +/// Provide a safe register interface for [`Pin`]s +/// +/// This `struct` takes ownership of a [`PinId`] and provides an API to +/// access the corresponding registers. +pub(in crate::gpio) struct Registers { + id: PhantomData, +} + +// [`Registers`] takes ownership of the [`PinId`], and [`Pin`] guarantees that +// each pin is a singleton, so this implementation is safe. +unsafe impl RegisterInterface for Registers { + #[inline] + fn id(&self) -> DynPinId { + I::DYN + } +} + +impl Registers { + /// Create a new instance of [`Registers`] + /// + /// # Safety + /// + /// Users must never create two simultaneous instances of this `struct` with + /// the same [`PinId`] + #[inline] + unsafe fn new() -> Self { + Registers { id: PhantomData } + } + + /// Provide a type-level equivalent for the + /// [`RegisterInterface::change_mode`] method. + #[inline] + pub(in crate::gpio) fn change_mode(&mut self) { + RegisterInterface::change_mode(self, M::DYN); + } +} + +//================================================================================================== +// Pin definitions +//================================================================================================== + +macro_rules! pins { + ( + $Port:ident, $PinsName:ident, $($Id:ident,)+, + ) => { + paste::paste!( + /// Collection of all the individual [`Pin`]s for a given port (PORTA or PORTB) + pub struct $PinsName { + port: $Port, + $( + #[doc = "Pin " $Id] + pub [<$Id:lower>]: Pin<$Id, Reset>, + )+ + } + + impl $PinsName { + /// Create a new struct containing all the Pins. Passing the IOCONFIG peripheral + /// is optional because it might be required to create pin definitions for both + /// ports. + #[inline] + pub fn new( + syscfg: &mut va416xx::Sysconfig, + port: $Port + ) -> $PinsName { + syscfg.peripheral_clk_enable().modify(|_, w| { + w.[<$Port:lower>]().set_bit(); + w.ioconfig().set_bit() + }); + $PinsName { + port, + // Safe because we only create one `Pin` per `PinId` + $( + [<$Id:lower>]: unsafe { Pin::new() }, + )+ + } + } + + /// Get the peripheral ID + /// Safety: Read-only register + pub fn get_perid() -> u32 { + let port = unsafe { &(*$Port::ptr()) }; + port.perid().read().bits() + } + + /// Consumes the Pins struct and returns the port definitions + pub fn release(self) -> $Port { + self.port + } + } + ); + } +} + +macro_rules! declare_pins { + ( + $Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal),)+] + ) => { + pins!($Port, $PinsName, $($Id,)+,); + $( + pin_id!($Group, $Id, $NUM); + )+ + } +} + +declare_pins!( + A, + PinsA, + Porta, + [ + (PA0, 0), + (PA1, 1), + (PA2, 2), + (PA3, 3), + (PA4, 4), + (PA5, 5), + (PA6, 6), + (PA7, 7), + (PA8, 8), + (PA9, 9), + (PA10, 10), + (PA11, 11), + (PA12, 12), + (PA13, 13), + (PA14, 14), + (PA15, 15), + ] +); + +declare_pins!( + B, + PinsB, + Portb, + [ + (PB0, 0), + (PB1, 1), + (PB2, 2), + (PB3, 3), + (PB4, 4), + (PB5, 5), + (PB6, 6), + (PB7, 7), + (PB8, 8), + (PB9, 9), + (PB10, 10), + (PB11, 11), + (PB12, 12), + (PB13, 13), + (PB14, 14), + (PB15, 15), + ] +); + +declare_pins!( + C, + PinsC, + Portc, + [ + (PC0, 0), + (PC1, 1), + (PC2, 2), + (PC3, 3), + (PC4, 4), + (PC5, 5), + (PC6, 6), + (PC7, 7), + (PC8, 8), + (PC9, 9), + (PC10, 10), + (PC11, 11), + (PC12, 12), + (PC13, 13), + (PC14, 14), + (PC15, 15), + ] +); + +declare_pins!( + D, + PinsD, + Portd, + [ + (PD0, 0), + (PD1, 1), + (PD2, 2), + (PD3, 3), + (PD4, 4), + (PD5, 5), + (PD6, 6), + (PD7, 7), + (PD8, 8), + (PD9, 9), + (PD10, 10), + (PD11, 11), + (PD12, 12), + (PD13, 13), + (PD14, 14), + (PD15, 15), + ] +); + +declare_pins!( + E, + PinsE, + Porte, + [ + (PE0, 0), + (PE1, 1), + (PE2, 2), + (PE3, 3), + (PE4, 4), + (PE5, 5), + (PE6, 6), + (PE7, 7), + (PE8, 8), + (PE9, 9), + (PE10, 10), + (PE11, 11), + (PE12, 12), + (PE13, 13), + (PE14, 14), + (PE15, 15), + ] +); + +declare_pins!( + F, + PinsF, + Portf, + [ + (PF0, 0), + (PF1, 1), + (PF2, 2), + (PF3, 3), + (PF4, 4), + (PF5, 5), + (PF6, 6), + (PF7, 7), + (PF8, 8), + (PF9, 9), + (PF10, 10), + (PF11, 11), + (PF12, 12), + (PF13, 13), + (PF14, 14), + (PF15, 15), + ] +); + +declare_pins!( + G, + PinsG, + Portg, + [ + (PG0, 0), + (PG1, 1), + (PG2, 2), + (PG3, 3), + (PG4, 4), + (PG5, 5), + (PG6, 6), + (PG7, 7), + ] +); diff --git a/va416xx-hal/src/gpio/reg.rs b/va416xx-hal/src/gpio/reg.rs new file mode 100644 index 0000000..d8a9022 --- /dev/null +++ b/va416xx-hal/src/gpio/reg.rs @@ -0,0 +1,387 @@ +use crate::FunSel; + +use super::{ + dynpin::{self, DynGroup, DynPinId}, + DynPinMode, FilterClkSel, FilterType, InterruptEdge, InterruptLevel, IsMaskedError, PinState, +}; +use va416xx::{ioconfig, porta, Ioconfig, Porta, Portb, Portc, Portd, Porte, Portf, Portg}; + +/// Type definition to avoid confusion: These register blocks are identical +type PortRegisterBlock = porta::RegisterBlock; + +//================================================================================================== +// ModeFields +//================================================================================================== + +/// Collect all fields needed to set the [`PinMode`](super::PinMode) +#[derive(Default)] +struct ModeFields { + dir: bool, + opendrn: bool, + pull_en: bool, + /// true for pullup, false for pulldown + pull_dir: bool, + funsel: u8, + enb_input: bool, +} + +impl From for ModeFields { + #[inline] + fn from(mode: DynPinMode) -> Self { + let mut fields = Self::default(); + use DynPinMode::*; + match mode { + Input(config) => { + use dynpin::DynInput::*; + fields.dir = false; + fields.funsel = FunSel::Sel0 as u8; + match config { + Floating => (), + PullUp => { + fields.pull_en = true; + fields.pull_dir = true; + } + PullDown => { + fields.pull_en = true; + } + } + } + Output(config) => { + use dynpin::DynOutput::*; + fields.dir = true; + fields.funsel = FunSel::Sel0 as u8; + match config { + PushPull => (), + OpenDrain => { + fields.opendrn = true; + } + ReadableOpenDrain => { + fields.enb_input = true; + fields.opendrn = true; + } + ReadablePushPull => { + fields.enb_input = true; + } + } + } + Alternate(config) => { + fields.funsel = config as u8; + } + } + fields + } +} + +//============================================================================== +// RegisterInterface +//============================================================================== + +pub type PortReg = ioconfig::Porta; + +/// Provide a safe register interface for pin objects +/// +/// [`PORT`], like every PAC `struct`, is [`Send`] but not [`Sync`], because it +/// points to a `RegisterBlock` of `VolatileCell`s. Unfortunately, such an +/// interface is quite restrictive. Instead, it would be ideal if we could split +/// the [`PORT`] into independent pins that are both [`Send`] and [`Sync`]. +/// +/// [`PORT`] is a single, zero-sized marker `struct` that provides access to +/// every [`PORT`] register. Instead, we would like to create zero-sized marker +/// `struct`s for every pin, where each pin is only allowed to control its own +/// registers. Furthermore, each pin `struct` should be a singleton, so that +/// exclusive access to the `struct` also guarantees exclusive access to the +/// corresponding registers. Finally, the pin `struct`s should not have any +/// interior mutability. Together, these requirements would allow the pin +/// `struct`s to be both [`Send`] and [`Sync`]. +/// +/// This trait creates a safe API for accomplishing these goals. Implementers +/// supply a pin ID through the [`id`] function. The remaining functions provide +/// a safe API for accessing the registers associated with that pin ID. Any +/// modification of the registers requires `&mut self`, which destroys interior +/// mutability. +/// +/// # Safety +/// +/// Users should only implement the [`id`] function. No default function +/// implementations should be overridden. The implementing type must also have +/// "control" over the corresponding pin ID, i.e. it must guarantee that a each +/// pin ID is a singleton. +/// +/// [`id`]: Self::id +pub(super) unsafe trait RegisterInterface { + /// Provide a [`DynPinId`] identifying the set of registers controlled by + /// this type. + fn id(&self) -> DynPinId; + + const PORTA: *const PortRegisterBlock = Porta::ptr(); + const PORTB: *const PortRegisterBlock = Portb::ptr(); + const PORTC: *const PortRegisterBlock = Portc::ptr(); + const PORTD: *const PortRegisterBlock = Portd::ptr(); + const PORTE: *const PortRegisterBlock = Porte::ptr(); + const PORTF: *const PortRegisterBlock = Portf::ptr(); + const PORTG: *const PortRegisterBlock = Portg::ptr(); + + /// Change the pin mode + #[inline] + fn change_mode(&mut self, mode: DynPinMode) { + let ModeFields { + dir, + funsel, + opendrn, + pull_dir, + pull_en, + enb_input, + } = mode.into(); + let (portreg, iocfg) = (self.port_reg(), self.iocfg_port()); + iocfg.write(|w| { + w.opendrn().bit(opendrn); + w.pen().bit(pull_en); + w.plevel().bit(pull_dir); + w.iewo().bit(enb_input); + unsafe { w.funsel().bits(funsel) } + }); + let mask = self.mask_32(); + unsafe { + if dir { + portreg.dir().modify(|r, w| w.bits(r.bits() | mask)); + // Clear output + portreg.clrout().write(|w| w.bits(mask)); + } else { + portreg.dir().modify(|r, w| w.bits(r.bits() & !mask)); + } + } + } + + #[inline] + fn port_reg(&self) -> &PortRegisterBlock { + match self.id().group { + DynGroup::A => unsafe { &(*Self::PORTA) }, + DynGroup::B => unsafe { &(*Self::PORTB) }, + DynGroup::C => unsafe { &(*Self::PORTC) }, + DynGroup::D => unsafe { &(*Self::PORTD) }, + DynGroup::E => unsafe { &(*Self::PORTE) }, + DynGroup::F => unsafe { &(*Self::PORTF) }, + DynGroup::G => unsafe { &(*Self::PORTG) }, + } + } + + fn iocfg_port(&self) -> &PortReg { + let ioconfig = unsafe { Ioconfig::ptr().as_ref().unwrap() }; + match self.id().group { + DynGroup::A => ioconfig.porta(self.id().num as usize), + DynGroup::B => ioconfig.portb0(self.id().num as usize), + DynGroup::C => ioconfig.portc0(self.id().num as usize), + DynGroup::D => ioconfig.portd0(self.id().num as usize), + DynGroup::E => ioconfig.porte0(self.id().num as usize), + DynGroup::F => ioconfig.portf0(self.id().num as usize), + DynGroup::G => ioconfig.portg0(self.id().num as usize), + } + } + + #[inline] + fn mask_32(&self) -> u32 { + 1 << self.id().num + } + + #[inline] + fn enable_irq(&self) { + self.port_reg() + .irq_enb() + .modify(|r, w| unsafe { w.bits(r.bits() | self.mask_32()) }); + } + + #[inline] + /// Read the logic level of an output pin + fn read_pin(&self) -> bool { + let portreg = self.port_reg(); + ((portreg.datainraw().read().bits() >> self.id().num) & 0x01) == 1 + } + + // Get DATAMASK bit for this particular pin + #[inline(always)] + fn datamask(&self) -> bool { + let portreg = self.port_reg(); + (portreg.datamask().read().bits() >> self.id().num) == 1 + } + + /// Read a pin but use the masked version but check whether the datamask for the pin is + /// cleared as well + #[inline(always)] + fn read_pin_masked(&self) -> Result { + if !self.datamask() { + Err(IsMaskedError) + } else { + Ok(((self.port_reg().datain().read().bits() >> self.id().num) & 0x01) == 1) + } + } + + /// Write the logic level of an output pin + #[inline(always)] + fn write_pin(&mut self, bit: bool) { + // Safety: SETOUT is a "mask" register, and we only write the bit for + // this pin ID + unsafe { + if bit { + self.port_reg().setout().write(|w| w.bits(self.mask_32())); + } else { + self.port_reg().clrout().write(|w| w.bits(self.mask_32())); + } + } + } + + /// Write the logic level of an output pin but check whether the datamask for the pin is + /// cleared as well + #[inline] + fn write_pin_masked(&mut self, bit: bool) -> Result<(), IsMaskedError> { + if !self.datamask() { + Err(IsMaskedError) + } else { + // Safety: SETOUT is a "mask" register, and we only write the bit for + // this pin ID + unsafe { + if bit { + self.port_reg().setout().write(|w| w.bits(self.mask_32())); + } else { + self.port_reg().clrout().write(|w| w.bits(self.mask_32())); + } + Ok(()) + } + } + } + + /// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure + /// When using edge mode, it is possible to generate interrupts on both edges as well + #[inline] + fn interrupt_edge(&mut self, edge_type: InterruptEdge) { + unsafe { + self.port_reg() + .irq_sen() + .modify(|r, w| w.bits(r.bits() & !self.mask_32())); + match edge_type { + InterruptEdge::HighToLow => { + self.port_reg() + .irq_evt() + .modify(|r, w| w.bits(r.bits() & !self.mask_32())); + } + InterruptEdge::LowToHigh => { + self.port_reg() + .irq_evt() + .modify(|r, w| w.bits(r.bits() | self.mask_32())); + } + InterruptEdge::BothEdges => { + self.port_reg() + .irq_edge() + .modify(|r, w| w.bits(r.bits() | self.mask_32())); + } + } + } + } + + /// Configure which edge or level type triggers an interrupt + #[inline] + fn interrupt_level(&mut self, level: InterruptLevel) { + unsafe { + self.port_reg() + .irq_sen() + .modify(|r, w| w.bits(r.bits() | self.mask_32())); + if level == InterruptLevel::Low { + self.port_reg() + .irq_evt() + .modify(|r, w| w.bits(r.bits() & !self.mask_32())); + } else { + self.port_reg() + .irq_evt() + .modify(|r, w| w.bits(r.bits() | self.mask_32())); + } + } + } + + /// Only useful for input pins + #[inline] + fn filter_type(&self, filter: FilterType, clksel: FilterClkSel) { + self.iocfg_port().modify(|_, w| { + // Safety: Only write to register for this Pin ID + unsafe { + w.flttype().bits(filter as u8); + w.fltclk().bits(clksel as u8) + } + }); + } + + /// Set DATAMASK bit for this particular pin. 1 is the default + /// state of the bit and allows access of the corresponding bit + #[inline(always)] + fn set_datamask(&self) { + let portreg = self.port_reg(); + unsafe { + portreg + .datamask() + .modify(|r, w| w.bits(r.bits() | self.mask_32())) + } + } + + /// Clear DATAMASK bit for this particular pin. This prevents access + /// of the corresponding bit for output and input operations + #[inline(always)] + fn clear_datamask(&self) { + let portreg = self.port_reg(); + unsafe { + portreg + .datamask() + .modify(|r, w| w.bits(r.bits() & !self.mask_32())) + } + } + + /// Only useful for output pins + /// See p.52 of the programmers guide for more information. + /// When configured for pulse mode, a given pin will set the non-default state for exactly + /// one clock cycle before returning to the configured default state + fn pulse_mode(&self, enable: bool, default_state: PinState) { + let portreg = self.port_reg(); + unsafe { + if enable { + portreg + .pulse() + .modify(|r, w| w.bits(r.bits() | self.mask_32())); + } else { + portreg + .pulse() + .modify(|r, w| w.bits(r.bits() & !self.mask_32())); + } + if default_state == PinState::Low { + portreg + .pulsebase() + .modify(|r, w| w.bits(r.bits() & !self.mask_32())); + } else { + portreg + .pulsebase() + .modify(|r, w| w.bits(r.bits() | self.mask_32())); + } + } + } + + /// Only useful for output pins + fn delay(&self, delay_1: bool, delay_2: bool) { + let portreg = self.port_reg(); + unsafe { + if delay_1 { + portreg + .delay1() + .modify(|r, w| w.bits(r.bits() | self.mask_32())); + } else { + portreg + .delay1() + .modify(|r, w| w.bits(r.bits() & !self.mask_32())); + } + if delay_2 { + portreg + .delay2() + .modify(|r, w| w.bits(r.bits() | self.mask_32())); + } else { + portreg + .delay2() + .modify(|r, w| w.bits(r.bits() & !self.mask_32())); + } + } + } +} diff --git a/va416xx-hal/src/i2c.rs b/va416xx-hal/src/i2c.rs new file mode 100644 index 0000000..ae7b42d --- /dev/null +++ b/va416xx-hal/src/i2c.rs @@ -0,0 +1,904 @@ +//! API for the I2C peripheral +//! +//! ## Examples +//! +//! - [PEB1 accelerometer example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/peb1-accelerometer.rs) +use crate::{ + clock::{ + assert_periph_reset, deassert_periph_reset, enable_peripheral_clock, Clocks, + PeripheralSelect, + }, + pac, + time::Hertz, + typelevel::Sealed, +}; +use core::{marker::PhantomData, ops::Deref}; +use embedded_hal::i2c::{self, Operation, SevenBitAddress, TenBitAddress}; + +//================================================================================================== +// Defintions +//================================================================================================== + +const CLK_100K: Hertz = Hertz::from_raw(100_000); +const CLK_400K: Hertz = Hertz::from_raw(400_000); +const MIN_CLK_400K: Hertz = Hertz::from_raw(10_000_000); + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum FifoEmptyMode { + Stall = 0, + EndTransaction = 1, +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct ClockTooSlowForFastI2c; + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Error { + InvalidTimingParams, + ArbitrationLost, + NackAddr, + /// Data not acknowledged in write operation + NackData, + /// Not enough data received in read operation + InsufficientDataReceived, + /// Number of bytes in transfer too large (larger than 0x7fe) + DataTooLarge, +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum InitError { + /// Wrong address used in constructor + WrongAddrMode, + /// APB1 clock is too slow for fast I2C mode. + ClkTooSlow(ClockTooSlowForFastI2c), +} + +impl From for InitError { + fn from(value: ClockTooSlowForFastI2c) -> Self { + Self::ClkTooSlow(value) + } +} + +impl embedded_hal::i2c::Error for Error { + fn kind(&self) -> embedded_hal::i2c::ErrorKind { + match self { + Error::ArbitrationLost => embedded_hal::i2c::ErrorKind::ArbitrationLoss, + Error::NackAddr => { + embedded_hal::i2c::ErrorKind::NoAcknowledge(i2c::NoAcknowledgeSource::Address) + } + Error::NackData => { + embedded_hal::i2c::ErrorKind::NoAcknowledge(i2c::NoAcknowledgeSource::Data) + } + Error::DataTooLarge | Error::InsufficientDataReceived | Error::InvalidTimingParams => { + embedded_hal::i2c::ErrorKind::Other + } + } + } +} + +#[derive(Debug, PartialEq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +enum I2cCmd { + Start = 0b00, + Stop = 0b10, + StartWithStop = 0b11, + Cancel = 0b100, +} + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum I2cSpeed { + Regular100khz = 0, + Fast400khz = 1, +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum I2cDirection { + Send = 0, + Read = 1, +} + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum I2cAddress { + Regular(u8), + TenBit(u16), +} + +pub type I2cRegBlock = pac::i2c0::RegisterBlock; + +/// Common trait implemented by all PAC peripheral access structures. The register block +/// format is the same for all SPI blocks. +pub trait Instance: Deref { + const IDX: u8; + const PERIPH_SEL: PeripheralSelect; + + fn ptr() -> *const I2cRegBlock; +} + +impl Instance for pac::I2c0 { + const IDX: u8 = 0; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::I2c0; + + fn ptr() -> *const I2cRegBlock { + Self::ptr() + } +} + +impl Instance for pac::I2c1 { + const IDX: u8 = 1; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::I2c1; + + fn ptr() -> *const I2cRegBlock { + Self::ptr() + } +} + +impl Instance for pac::I2c2 { + const IDX: u8 = 2; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::I2c2; + + fn ptr() -> *const I2cRegBlock { + Self::ptr() + } +} + +//================================================================================================== +// Config +//================================================================================================== + +pub struct TrTfThighTlow(u8, u8, u8, u8); +pub struct TsuStoTsuStaThdStaTBuf(u8, u8, u8, u8); + +pub struct TimingCfg { + // 4 bit max width + tr: u8, + // 4 bit max width + tf: u8, + // 4 bit max width + thigh: u8, + // 4 bit max width + tlow: u8, + // 4 bit max width + tsu_sto: u8, + // 4 bit max width + tsu_sta: u8, + // 4 bit max width + thd_sta: u8, + // 4 bit max width + tbuf: u8, +} + +impl TimingCfg { + pub fn new( + first_16_bits: TrTfThighTlow, + second_16_bits: TsuStoTsuStaThdStaTBuf, + ) -> Result { + if first_16_bits.0 > 0xf + || first_16_bits.1 > 0xf + || first_16_bits.2 > 0xf + || first_16_bits.3 > 0xf + || second_16_bits.0 > 0xf + || second_16_bits.1 > 0xf + || second_16_bits.2 > 0xf + || second_16_bits.3 > 0xf + { + return Err(Error::InvalidTimingParams); + } + Ok(TimingCfg { + tr: first_16_bits.0, + tf: first_16_bits.1, + thigh: first_16_bits.2, + tlow: first_16_bits.3, + tsu_sto: second_16_bits.0, + tsu_sta: second_16_bits.1, + thd_sta: second_16_bits.2, + tbuf: second_16_bits.3, + }) + } + + pub fn reg(&self) -> u32 { + (self.tbuf as u32) << 28 + | (self.thd_sta as u32) << 24 + | (self.tsu_sta as u32) << 20 + | (self.tsu_sto as u32) << 16 + | (self.tlow as u32) << 12 + | (self.thigh as u32) << 8 + | (self.tf as u32) << 4 + | (self.tr as u32) + } +} + +impl Default for TimingCfg { + fn default() -> Self { + TimingCfg { + tr: 0x02, + tf: 0x01, + thigh: 0x08, + tlow: 0x09, + tsu_sto: 0x8, + tsu_sta: 0x0a, + thd_sta: 0x8, + tbuf: 0xa, + } + } +} + +pub struct MasterConfig { + pub tx_fe_mode: FifoEmptyMode, + pub rx_fe_mode: FifoEmptyMode, + /// Enable the analog delay glitch filter + pub alg_filt: bool, + /// Enable the digital glitch filter + pub dlg_filt: bool, + pub tm_cfg: Option, + // Loopback mode + // lbm: bool, +} + +impl Default for MasterConfig { + fn default() -> Self { + MasterConfig { + tx_fe_mode: FifoEmptyMode::Stall, + rx_fe_mode: FifoEmptyMode::Stall, + alg_filt: false, + dlg_filt: false, + tm_cfg: None, + } + } +} + +impl Sealed for MasterConfig {} + +pub struct SlaveConfig { + pub tx_fe_mode: FifoEmptyMode, + pub rx_fe_mode: FifoEmptyMode, + /// Maximum number of words before issuing a negative acknowledge. + /// Range should be 0 to 0x7fe. Setting the value to 0x7ff has the same effect as not setting + /// the enable bit since RXCOUNT stops counting at 0x7fe. + pub max_words: Option, + /// A received address is compared to the ADDRESS register (addr) using the address mask + /// (addr_mask). Those bits with a 1 in the address mask must match for there to be an address + /// match + pub addr: I2cAddress, + /// The default address mask will be 0x3ff to only allow full matches + pub addr_mask: Option, + /// Optionally specify a second I2C address the slave interface responds to + pub addr_b: Option, + pub addr_b_mask: Option, +} + +impl SlaveConfig { + /// Build a default slave config given a specified slave address to respond to + pub fn new(addr: I2cAddress) -> Self { + SlaveConfig { + tx_fe_mode: FifoEmptyMode::Stall, + rx_fe_mode: FifoEmptyMode::Stall, + max_words: None, + addr, + addr_mask: None, + addr_b: None, + addr_b_mask: None, + } + } +} + +impl Sealed for SlaveConfig {} + +//================================================================================================== +// I2C Base +//================================================================================================== + +pub struct I2cBase { + i2c: I2c, + clock: Hertz, +} + +impl I2cBase { + #[inline] + fn unwrap_addr(addr: I2cAddress) -> (u16, u32) { + match addr { + I2cAddress::Regular(addr) => (addr as u16, 0 << 15), + I2cAddress::TenBit(addr) => (addr, 1 << 15), + } + } +} + +impl I2cBase { + pub fn new( + i2c: I2c, + sys_cfg: &mut pac::Sysconfig, + clocks: &Clocks, + speed_mode: I2cSpeed, + ms_cfg: Option<&MasterConfig>, + sl_cfg: Option<&SlaveConfig>, + ) -> Result { + enable_peripheral_clock(sys_cfg, I2c::PERIPH_SEL); + assert_periph_reset(sys_cfg, I2c::PERIPH_SEL); + cortex_m::asm::nop(); + cortex_m::asm::nop(); + deassert_periph_reset(sys_cfg, I2c::PERIPH_SEL); + + let mut i2c_base = I2cBase { + i2c, + clock: clocks.apb1(), + }; + if let Some(ms_cfg) = ms_cfg { + i2c_base.cfg_master(ms_cfg); + } + + if let Some(sl_cfg) = sl_cfg { + i2c_base.cfg_slave(sl_cfg); + } + i2c_base.cfg_clk_scale(speed_mode)?; + Ok(i2c_base) + } + + fn cfg_master(&mut self, ms_cfg: &MasterConfig) { + let (txfemd, rxfemd) = match (ms_cfg.tx_fe_mode, ms_cfg.rx_fe_mode) { + (FifoEmptyMode::Stall, FifoEmptyMode::Stall) => (false, false), + (FifoEmptyMode::Stall, FifoEmptyMode::EndTransaction) => (false, true), + (FifoEmptyMode::EndTransaction, FifoEmptyMode::Stall) => (true, false), + (FifoEmptyMode::EndTransaction, FifoEmptyMode::EndTransaction) => (true, true), + }; + self.i2c.ctrl().modify(|_, w| { + w.txfemd().bit(txfemd); + w.rxffmd().bit(rxfemd); + w.dlgfilter().bit(ms_cfg.dlg_filt); + w.algfilter().bit(ms_cfg.alg_filt) + }); + if let Some(ref tm_cfg) = ms_cfg.tm_cfg { + self.i2c + .tmconfig() + .write(|w| unsafe { w.bits(tm_cfg.reg()) }); + } + self.i2c.fifo_clr().write(|w| { + w.rxfifo().set_bit(); + w.txfifo().set_bit() + }); + } + + fn cfg_slave(&mut self, sl_cfg: &SlaveConfig) { + let (txfemd, rxfemd) = match (sl_cfg.tx_fe_mode, sl_cfg.rx_fe_mode) { + (FifoEmptyMode::Stall, FifoEmptyMode::Stall) => (false, false), + (FifoEmptyMode::Stall, FifoEmptyMode::EndTransaction) => (false, true), + (FifoEmptyMode::EndTransaction, FifoEmptyMode::Stall) => (true, false), + (FifoEmptyMode::EndTransaction, FifoEmptyMode::EndTransaction) => (true, true), + }; + self.i2c.s0_ctrl().modify(|_, w| { + w.txfemd().bit(txfemd); + w.rxffmd().bit(rxfemd) + }); + self.i2c.s0_fifo_clr().write(|w| { + w.rxfifo().set_bit(); + w.txfifo().set_bit() + }); + let max_words = sl_cfg.max_words; + if let Some(max_words) = max_words { + self.i2c + .s0_maxwords() + .write(|w| unsafe { w.bits(1 << 31 | max_words as u32) }); + } + let (addr, addr_mode_mask) = Self::unwrap_addr(sl_cfg.addr); + // The first bit is the read/write value. Normally, both read and write are matched + // using the RWMASK bit of the address mask register + self.i2c + .s0_address() + .write(|w| unsafe { w.bits((addr << 1) as u32 | addr_mode_mask) }); + if let Some(addr_mask) = sl_cfg.addr_mask { + self.i2c + .s0_addressmask() + .write(|w| unsafe { w.bits((addr_mask << 1) as u32) }); + } + if let Some(addr_b) = sl_cfg.addr_b { + let (addr, addr_mode_mask) = Self::unwrap_addr(addr_b); + self.i2c + .s0_addressb() + .write(|w| unsafe { w.bits((addr << 1) as u32 | addr_mode_mask) }) + } + if let Some(addr_b_mask) = sl_cfg.addr_b_mask { + self.i2c + .s0_addressmaskb() + .write(|w| unsafe { w.bits((addr_b_mask << 1) as u32) }) + } + } + + #[inline] + pub fn filters(&mut self, digital_filt: bool, analog_filt: bool) { + self.i2c.ctrl().modify(|_, w| { + w.dlgfilter().bit(digital_filt); + w.algfilter().bit(analog_filt) + }); + } + + #[inline] + pub fn fifo_empty_mode(&mut self, rx: FifoEmptyMode, tx: FifoEmptyMode) { + self.i2c.ctrl().modify(|_, w| { + w.txfemd().bit(tx as u8 != 0); + w.rxffmd().bit(rx as u8 != 0) + }); + } + + fn calc_clk_div(&self, speed_mode: I2cSpeed) -> Result { + if speed_mode == I2cSpeed::Regular100khz { + Ok(((self.clock.raw() / CLK_100K.raw() / 20) - 1) as u8) + } else { + if self.clock.raw() < MIN_CLK_400K.raw() { + return Err(ClockTooSlowForFastI2c); + } + Ok(((self.clock.raw() / CLK_400K.raw() / 25) - 1) as u8) + } + } + + /// Configures the clock scale for a given speed mode setting + pub fn cfg_clk_scale(&mut self, speed_mode: I2cSpeed) -> Result<(), ClockTooSlowForFastI2c> { + let clk_div = self.calc_clk_div(speed_mode)?; + self.i2c + .clkscale() + .write(|w| unsafe { w.bits((speed_mode as u32) << 31 | clk_div as u32) }); + Ok(()) + } + + pub fn load_address(&mut self, addr: u16) { + // Load address + self.i2c + .address() + .write(|w| unsafe { w.bits((addr << 1) as u32) }); + } + + #[inline] + fn stop_cmd(&mut self) { + self.i2c + .cmd() + .write(|w| unsafe { w.bits(I2cCmd::Stop as u32) }); + } +} + +//================================================================================================== +// I2C Master +//================================================================================================== + +pub struct I2cMaster { + i2c_base: I2cBase, + addr: PhantomData, +} + +impl I2cMaster { + pub fn new( + i2c: I2c, + sys_cfg: &mut pac::Sysconfig, + cfg: MasterConfig, + clocks: &Clocks, + speed_mode: I2cSpeed, + ) -> Result { + Ok(I2cMaster { + i2c_base: I2cBase::new(i2c, sys_cfg, clocks, speed_mode, Some(&cfg), None)?, + addr: PhantomData, + } + .enable_master()) + } + + #[inline] + pub fn cancel_transfer(&self) { + self.i2c_base + .i2c + .cmd() + .write(|w| unsafe { w.bits(I2cCmd::Cancel as u32) }); + } + + #[inline] + pub fn clear_tx_fifo(&self) { + self.i2c_base.i2c.fifo_clr().write(|w| w.txfifo().set_bit()); + } + + #[inline] + pub fn clear_rx_fifo(&self) { + self.i2c_base.i2c.fifo_clr().write(|w| w.rxfifo().set_bit()); + } + + #[inline] + pub fn enable_master(self) -> Self { + self.i2c_base.i2c.ctrl().modify(|_, w| w.enable().set_bit()); + self + } + + #[inline] + pub fn disable_master(self) -> Self { + self.i2c_base + .i2c + .ctrl() + .modify(|_, w| w.enable().clear_bit()); + self + } + + #[inline(always)] + fn load_fifo(&self, word: u8) { + self.i2c_base + .i2c + .data() + .write(|w| unsafe { w.bits(word as u32) }); + } + + #[inline(always)] + fn read_fifo(&self) -> u8 { + self.i2c_base.i2c.data().read().bits() as u8 + } + + fn error_handler_write(&mut self, init_cmd: &I2cCmd) { + self.clear_tx_fifo(); + if *init_cmd == I2cCmd::Start { + self.i2c_base.stop_cmd() + } + } + + fn write_base( + &mut self, + addr: I2cAddress, + init_cmd: I2cCmd, + bytes: impl IntoIterator, + ) -> Result<(), Error> { + let mut iter = bytes.into_iter(); + // Load address + let (addr, addr_mode_bit) = I2cBase::::unwrap_addr(addr); + self.i2c_base.i2c.address().write(|w| unsafe { + w.bits(I2cDirection::Send as u32 | (addr << 1) as u32 | addr_mode_bit) + }); + + self.i2c_base + .i2c + .cmd() + .write(|w| unsafe { w.bits(init_cmd as u32) }); + let mut load_if_next_available = || { + if let Some(next_byte) = iter.next() { + self.load_fifo(next_byte); + } + }; + loop { + let status_reader = self.i2c_base.i2c.status().read(); + if status_reader.arblost().bit_is_set() { + self.error_handler_write(&init_cmd); + return Err(Error::ArbitrationLost); + } else if status_reader.nackaddr().bit_is_set() { + self.error_handler_write(&init_cmd); + return Err(Error::NackAddr); + } else if status_reader.nackdata().bit_is_set() { + self.error_handler_write(&init_cmd); + return Err(Error::NackData); + } else if status_reader.idle().bit_is_set() { + return Ok(()); + } else { + while !status_reader.txnfull().bit_is_set() { + load_if_next_available(); + } + } + } + } + + fn write_from_buffer( + &mut self, + init_cmd: I2cCmd, + addr: I2cAddress, + output: &[u8], + ) -> Result<(), Error> { + let len = output.len(); + // It should theoretically possible to transfer larger data sizes by tracking + // the number of sent words and setting it to 0x7fe as soon as only that many + // bytes are remaining. However, large transfer like this are not common. This + // feature will therefore not be supported for now. + if len > 0x7fe { + return Err(Error::DataTooLarge); + } + // Load number of words + self.i2c_base + .i2c + .words() + .write(|w| unsafe { w.bits(len as u32) }); + let mut bytes = output.iter(); + // FIFO has a depth of 16. We load slightly above the trigger level + // but not all of it because the transaction might fail immediately + const FILL_DEPTH: usize = 12; + + // load the FIFO + for _ in 0..core::cmp::min(FILL_DEPTH, len) { + self.load_fifo(*bytes.next().unwrap()); + } + + self.write_base(addr, init_cmd, output.iter().cloned()) + } + + fn read_internal(&mut self, addr: I2cAddress, buffer: &mut [u8]) -> Result<(), Error> { + let len = buffer.len(); + // It should theoretically possible to transfer larger data sizes by tracking + // the number of sent words and setting it to 0x7fe as soon as only that many + // bytes are remaining. However, large transfer like this are not common. This + // feature will therefore not be supported for now. + if len > 0x7fe { + return Err(Error::DataTooLarge); + } + // Clear the receive FIFO + self.clear_rx_fifo(); + + // Load number of words + self.i2c_base + .i2c + .words() + .write(|w| unsafe { w.bits(len as u32) }); + let (addr, addr_mode_bit) = match addr { + I2cAddress::Regular(addr) => (addr as u16, 0 << 15), + I2cAddress::TenBit(addr) => (addr, 1 << 15), + }; + // Load address + self.i2c_base.i2c.address().write(|w| unsafe { + w.bits(I2cDirection::Read as u32 | (addr << 1) as u32 | addr_mode_bit) + }); + + let mut buf_iter = buffer.iter_mut(); + let mut read_bytes = 0; + // Start receive transfer + self.i2c_base + .i2c + .cmd() + .write(|w| unsafe { w.bits(I2cCmd::StartWithStop as u32) }); + let mut read_if_next_available = || { + if let Some(next_byte) = buf_iter.next() { + *next_byte = self.read_fifo(); + } + }; + loop { + let status_reader = self.i2c_base.i2c.status().read(); + if status_reader.arblost().bit_is_set() { + self.clear_rx_fifo(); + return Err(Error::ArbitrationLost); + } else if status_reader.nackaddr().bit_is_set() { + self.clear_rx_fifo(); + return Err(Error::NackAddr); + } else if status_reader.idle().bit_is_set() { + if read_bytes != len { + return Err(Error::InsufficientDataReceived); + } + return Ok(()); + } else if status_reader.rxnempty().bit_is_set() { + read_if_next_available(); + read_bytes += 1; + } + } + } +} + +//====================================================================================== +// Embedded HAL I2C implementations +//====================================================================================== + +impl embedded_hal::i2c::ErrorType for I2cMaster { + type Error = Error; +} + +impl embedded_hal::i2c::I2c for I2cMaster { + fn transaction( + &mut self, + address: SevenBitAddress, + operations: &mut [Operation<'_>], + ) -> Result<(), Self::Error> { + for operation in operations { + match operation { + Operation::Read(buf) => self.read_internal(I2cAddress::Regular(address), buf)?, + Operation::Write(buf) => self.write_from_buffer( + I2cCmd::StartWithStop, + I2cAddress::Regular(address), + buf, + )?, + } + } + Ok(()) + } +} + +impl embedded_hal::i2c::ErrorType for I2cMaster { + type Error = Error; +} + +impl embedded_hal::i2c::I2c for I2cMaster { + fn transaction( + &mut self, + address: TenBitAddress, + operations: &mut [Operation<'_>], + ) -> Result<(), Self::Error> { + for operation in operations { + match operation { + Operation::Read(buf) => self.read_internal(I2cAddress::TenBit(address), buf)?, + Operation::Write(buf) => { + self.write_from_buffer(I2cCmd::StartWithStop, I2cAddress::TenBit(address), buf)? + } + } + } + Ok(()) + } +} + +//================================================================================================== +// I2C Slave +//================================================================================================== + +pub struct I2cSlave { + i2c_base: I2cBase, + addr: PhantomData, +} + +impl I2cSlave { + fn new_generic( + i2c: I2c, + sys_cfg: &mut pac::Sysconfig, + cfg: SlaveConfig, + clocks: &Clocks, + speed_mode: I2cSpeed, + ) -> Result { + Ok(I2cSlave { + i2c_base: I2cBase::new(i2c, sys_cfg, clocks, speed_mode, None, Some(&cfg))?, + addr: PhantomData, + } + .enable_slave()) + } + + #[inline] + pub fn enable_slave(self) -> Self { + self.i2c_base + .i2c + .s0_ctrl() + .modify(|_, w| w.enable().set_bit()); + self + } + + #[inline] + pub fn disable_slave(self) -> Self { + self.i2c_base + .i2c + .s0_ctrl() + .modify(|_, w| w.enable().clear_bit()); + self + } + + #[inline(always)] + fn load_fifo(&self, word: u8) { + self.i2c_base + .i2c + .s0_data() + .write(|w| unsafe { w.bits(word as u32) }); + } + + #[inline(always)] + fn read_fifo(&self) -> u8 { + self.i2c_base.i2c.s0_data().read().bits() as u8 + } + + #[inline] + fn clear_tx_fifo(&self) { + self.i2c_base + .i2c + .s0_fifo_clr() + .write(|w| w.txfifo().set_bit()); + } + + #[inline] + fn clear_rx_fifo(&self) { + self.i2c_base + .i2c + .s0_fifo_clr() + .write(|w| w.rxfifo().set_bit()); + } + + /// Get the last address that was matched by the slave control and the corresponding + /// master direction + pub fn last_address(&self) -> (I2cDirection, u32) { + let bits = self.i2c_base.i2c.s0_lastaddress().read().bits(); + match bits & 0x01 { + 0 => (I2cDirection::Send, bits >> 1), + 1 => (I2cDirection::Read, bits >> 1), + _ => (I2cDirection::Send, bits >> 1), + } + } + + pub fn write(&mut self, output: &[u8]) -> Result<(), Error> { + let len = output.len(); + // It should theoretically possible to transfer larger data sizes by tracking + // the number of sent words and setting it to 0x7fe as soon as only that many + // bytes are remaining. However, large transfer like this are not common. This + // feature will therefore not be supported for now. + if len > 0x7fe { + return Err(Error::DataTooLarge); + } + let mut bytes = output.iter(); + // FIFO has a depth of 16. We load slightly above the trigger level + // but not all of it because the transaction might fail immediately + const FILL_DEPTH: usize = 12; + + // load the FIFO + for _ in 0..core::cmp::min(FILL_DEPTH, len) { + self.load_fifo(*bytes.next().unwrap()); + } + + let status_reader = self.i2c_base.i2c.s0_status().read(); + let mut load_if_next_available = || { + if let Some(next_byte) = bytes.next() { + self.load_fifo(*next_byte); + } + }; + loop { + if status_reader.nackdata().bit_is_set() { + self.clear_tx_fifo(); + return Err(Error::NackData); + } else if status_reader.idle().bit_is_set() { + return Ok(()); + } else { + while !status_reader.txnfull().bit_is_set() { + load_if_next_available(); + } + } + } + } + + pub fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> { + let len = buffer.len(); + // It should theoretically possible to transfer larger data sizes by tracking + // the number of sent words and setting it to 0x7fe as soon as only that many + // bytes are remaining. However, large transfer like this are not common. This + // feature will therefore not be supported for now. + if len > 0x7fe { + return Err(Error::DataTooLarge); + } + // Clear the receive FIFO + self.clear_rx_fifo(); + + let mut buf_iter = buffer.iter_mut(); + let mut read_bytes = 0; + let mut read_if_next_available = || { + if let Some(next_byte) = buf_iter.next() { + *next_byte = self.read_fifo(); + } + }; + loop { + let status_reader = self.i2c_base.i2c.s0_status().read(); + if status_reader.idle().bit_is_set() { + if read_bytes != len { + return Err(Error::InsufficientDataReceived); + } + return Ok(()); + } else if status_reader.rxnempty().bit_is_set() { + read_bytes += 1; + read_if_next_available(); + } + } + } +} + +impl I2cSlave { + /// Create a new I2C slave for seven bit addresses + pub fn new( + i2c: I2c, + sys_cfg: &mut pac::Sysconfig, + cfg: SlaveConfig, + clocks: &Clocks, + speed_mode: I2cSpeed, + ) -> Result { + if let I2cAddress::TenBit(_) = cfg.addr { + return Err(InitError::WrongAddrMode); + } + Ok(Self::new_generic(i2c, sys_cfg, cfg, clocks, speed_mode)?) + } +} + +impl I2cSlave { + pub fn new_ten_bit_addr( + i2c: I2c, + sys_cfg: &mut pac::Sysconfig, + cfg: SlaveConfig, + clocks: &Clocks, + speed_mode: I2cSpeed, + ) -> Result { + Self::new_generic(i2c, sys_cfg, cfg, clocks, speed_mode) + } +} diff --git a/va416xx-hal/src/lib.rs b/va416xx-hal/src/lib.rs new file mode 100644 index 0000000..ec5521d --- /dev/null +++ b/va416xx-hal/src/lib.rs @@ -0,0 +1,46 @@ +#![no_std] +#![cfg_attr(docsrs, feature(doc_auto_cfg))] +#[cfg(test)] +extern crate std; + +pub use va416xx as device; +pub use va416xx as pac; + +pub mod prelude; + +pub mod clock; +pub mod gpio; +pub mod i2c; +pub mod pwm; +pub mod spi; +pub mod time; +pub mod timer; +pub mod typelevel; +pub mod uart; +pub mod wdt; + +#[derive(Debug, Eq, Copy, Clone, PartialEq)] +pub enum FunSel { + Sel0 = 0b00, + Sel1 = 0b01, + Sel2 = 0b10, + Sel3 = 0b11, +} + +/// Enable a specific interrupt using the NVIC peripheral. +/// +/// # Safety +/// +/// This function is `unsafe` because it can break mask-based critical sections. +#[inline] +pub unsafe fn enable_interrupt(irq: pac::Interrupt) { + unsafe { + cortex_m::peripheral::NVIC::unmask(irq); + } +} + +/// Disable a specific interrupt using the NVIC peripheral. +#[inline] +pub fn disable_interrupt(irq: pac::Interrupt) { + cortex_m::peripheral::NVIC::mask(irq); +} diff --git a/va416xx-hal/src/prelude.rs b/va416xx-hal/src/prelude.rs new file mode 100644 index 0000000..e67a9ed --- /dev/null +++ b/va416xx-hal/src/prelude.rs @@ -0,0 +1,4 @@ +//! Prelude +pub use crate::clock::{ClkgenExt, SyscfgExt}; +pub use fugit::ExtU32 as _; +pub use fugit::RateExtU32 as _; diff --git a/va416xx-hal/src/pwm.rs b/va416xx-hal/src/pwm.rs new file mode 100644 index 0000000..deb5db4 --- /dev/null +++ b/va416xx-hal/src/pwm.rs @@ -0,0 +1,388 @@ +//! API for Pulse-Width Modulation (PWM) +//! +//! The Vorago VA416xx devices use the TIM peripherals to perform PWM related tasks. +//! +//! ## Examples +//! +//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/pwm.rs) +use core::convert::Infallible; +use core::marker::PhantomData; + +use crate::pac; +use crate::{clock::Clocks, gpio::DynPinId}; +pub use crate::{gpio::PinId, time::Hertz, timer::*}; + +const DUTY_MAX: u16 = u16::MAX; + +pub struct PwmBase { + clock: Hertz, + /// For PWMB, this is the upper limit + current_duty: u16, + /// For PWMA, this value will not be used + current_lower_limit: u16, + current_period: Hertz, + current_rst_val: u32, +} + +enum StatusSelPwm { + PwmA = 3, + PwmB = 4, +} + +pub struct PwmA {} +pub struct PwmB {} + +//================================================================================================== +// Common +//================================================================================================== + +macro_rules! pwm_common_func { + () => { + #[inline] + fn enable_pwm_a(&mut self) { + self.reg + .reg() + .ctrl() + .modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmA as u8) }); + } + + #[inline] + fn enable_pwm_b(&mut self) { + self.reg + .reg() + .ctrl() + .modify(|_, w| unsafe { w.status_sel().bits(StatusSelPwm::PwmB as u8) }); + } + + #[inline] + pub fn get_period(&self) -> Hertz { + self.pwm_base.current_period + } + + #[inline] + pub fn set_period(&mut self, period: impl Into) { + self.pwm_base.current_period = period.into(); + // Avoid division by 0 + if self.pwm_base.current_period.raw() == 0 { + return; + } + self.pwm_base.current_rst_val = + self.pwm_base.clock.raw() / self.pwm_base.current_period.raw(); + self.reg + .reg() + .rst_value() + .write(|w| unsafe { w.bits(self.pwm_base.current_rst_val) }); + } + + #[inline] + pub fn disable(&mut self) { + self.reg.reg().ctrl().modify(|_, w| w.enable().clear_bit()); + } + + #[inline] + pub fn enable(&mut self) { + self.reg.reg().ctrl().modify(|_, w| w.enable().set_bit()); + } + + #[inline] + pub fn period(&self) -> Hertz { + self.pwm_base.current_period + } + + #[inline(always)] + pub fn duty(&self) -> u16 { + self.pwm_base.current_duty + } + }; +} + +macro_rules! pwmb_func { + () => { + pub fn pwmb_lower_limit(&self) -> u16 { + self.pwm_base.current_lower_limit + } + + pub fn pwmb_upper_limit(&self) -> u16 { + self.pwm_base.current_duty + } + + /// Set the lower limit for PWMB + /// + /// The PWM signal will be 1 as long as the current RST counter is larger than + /// the lower limit. For example, with a lower limit of 0.5 and and an upper limit + /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high + /// state + pub fn set_pwmb_lower_limit(&mut self, duty: u16) { + self.pwm_base.current_lower_limit = duty; + let pwmb_val: u64 = (self.pwm_base.current_rst_val as u64 + * self.pwm_base.current_lower_limit as u64) + / DUTY_MAX as u64; + self.reg + .reg() + .pwmb_value() + .write(|w| unsafe { w.bits(pwmb_val as u32) }); + } + + /// Set the higher limit for PWMB + /// + /// The PWM signal will be 1 as long as the current RST counter is smaller than + /// the higher limit. For example, with a lower limit of 0.5 and and an upper limit + /// of 0.7, Only a fixed period between 0.5 * period and 0.7 * period will be in a high + /// state + pub fn set_pwmb_upper_limit(&mut self, duty: u16) { + self.pwm_base.current_duty = duty; + let pwma_val: u64 = (self.pwm_base.current_rst_val as u64 + * self.pwm_base.current_duty as u64) + / DUTY_MAX as u64; + self.reg + .reg() + .pwma_value() + .write(|w| unsafe { w.bits(pwma_val as u32) }); + } + }; +} + +//================================================================================================== +// Strongly typed PWM pin +//================================================================================================== + +pub struct PwmPin { + reg: TimAndPinRegister, + pwm_base: PwmBase, + mode: PhantomData, +} + +impl PwmPin +where + (Pin, Tim): ValidTimAndPin, +{ + /// Create a new stronlgy typed PWM pin + pub fn new( + pin_and_tim: (Pin, Tim), + sys_cfg: &mut pac::Sysconfig, + clocks: &Clocks, + initial_period: impl Into + Copy, + ) -> Self { + let mut pin = PwmPin { + pwm_base: PwmBase { + current_duty: 0, + current_lower_limit: 0, + current_period: initial_period.into(), + current_rst_val: 0, + clock: Tim::clock(clocks), + }, + reg: unsafe { TimAndPinRegister::new(pin_and_tim.0, pin_and_tim.1) }, + mode: PhantomData, + }; + sys_cfg + .tim_clk_enable() + .modify(|r, w| unsafe { w.bits(r.bits() | pin.reg.mask_32()) }); + pin.enable_pwm_a(); + pin.set_period(initial_period); + pin + } + + pub fn release(self) -> (Pin, Tim) { + self.reg.release() + } + + pwm_common_func!(); +} + +impl From> for PwmPin +where + (Pin, Tim): ValidTimAndPin, +{ + fn from(other: PwmPin) -> Self { + let mut pwmb = Self { + reg: other.reg, + pwm_base: other.pwm_base, + mode: PhantomData, + }; + pwmb.enable_pwm_b(); + pwmb + } +} + +impl From> for PwmPin +where + (PIN, TIM): ValidTimAndPin, +{ + fn from(other: PwmPin) -> Self { + let mut pwmb = Self { + reg: other.reg, + pwm_base: other.pwm_base, + mode: PhantomData, + }; + pwmb.enable_pwm_a(); + pwmb + } +} + +impl PwmPin +where + (Pin, Tim): ValidTimAndPin, +{ + pub fn pwma( + tim_and_pin: (Pin, Tim), + sys_cfg: &mut pac::Sysconfig, + clocks: &Clocks, + initial_period: impl Into + Copy, + ) -> Self { + let mut pin: PwmPin = + Self::new(tim_and_pin, sys_cfg, clocks, initial_period); + pin.enable_pwm_a(); + pin + } +} + +impl PwmPin +where + (Pin, Tim): ValidTimAndPin, +{ + pub fn pwmb( + tim_and_pin: (Pin, Tim), + sys_cfg: &mut pac::Sysconfig, + clocks: &Clocks, + initial_period: impl Into + Copy, + ) -> Self { + let mut pin: PwmPin = + Self::new(tim_and_pin, sys_cfg, clocks, initial_period); + pin.enable_pwm_b(); + pin + } +} + +//================================================================================================== +// Reduced PWM pin +//================================================================================================== + +/// Reduced version where type information is deleted +pub struct ReducedPwmPin { + reg: TimDynRegister, + pwm_base: PwmBase, + pin_id: DynPinId, + mode: PhantomData, +} + +impl From> for ReducedPwmPin { + fn from(pwm_pin: PwmPin) -> Self { + ReducedPwmPin { + reg: TimDynRegister::from(pwm_pin.reg), + pwm_base: pwm_pin.pwm_base, + pin_id: PIN::DYN, + mode: PhantomData, + } + } +} + +impl ReducedPwmPin { + pwm_common_func!(); +} + +impl From> for ReducedPwmPin { + fn from(other: ReducedPwmPin) -> Self { + let mut pwmb = Self { + reg: other.reg, + pwm_base: other.pwm_base, + pin_id: other.pin_id, + mode: PhantomData, + }; + pwmb.enable_pwm_b(); + pwmb + } +} + +impl From> for ReducedPwmPin { + fn from(other: ReducedPwmPin) -> Self { + let mut pwmb = Self { + reg: other.reg, + pwm_base: other.pwm_base, + pin_id: other.pin_id, + mode: PhantomData, + }; + pwmb.enable_pwm_a(); + pwmb + } +} + +//================================================================================================== +// PWMB implementations +//================================================================================================== + +impl PwmPin +where + (PIN, TIM): ValidTimAndPin, +{ + pwmb_func!(); +} + +impl ReducedPwmPin { + pwmb_func!(); +} + +//================================================================================================== +// Embedded HAL implementation: PWMA only +//================================================================================================== + +impl embedded_hal::pwm::ErrorType for PwmPin { + type Error = Infallible; +} + +impl embedded_hal::pwm::ErrorType for ReducedPwmPin { + type Error = Infallible; +} + +impl embedded_hal::pwm::SetDutyCycle for ReducedPwmPin { + #[inline] + fn max_duty_cycle(&self) -> u16 { + DUTY_MAX + } + + #[inline] + fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> { + self.pwm_base.current_duty = duty; + let pwma_val: u64 = (self.pwm_base.current_rst_val as u64 + * (DUTY_MAX as u64 - self.pwm_base.current_duty as u64)) + / DUTY_MAX as u64; + self.reg + .reg() + .pwma_value() + .write(|w| unsafe { w.bits(pwma_val as u32) }); + Ok(()) + } +} + +impl embedded_hal::pwm::SetDutyCycle for PwmPin { + #[inline] + fn max_duty_cycle(&self) -> u16 { + DUTY_MAX + } + + #[inline] + fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> { + self.pwm_base.current_duty = duty; + let pwma_val: u64 = (self.pwm_base.current_rst_val as u64 + * (DUTY_MAX as u64 - self.pwm_base.current_duty as u64)) + / DUTY_MAX as u64; + self.reg + .reg() + .pwma_value() + .write(|w| unsafe { w.bits(pwma_val as u32) }); + Ok(()) + } +} + +/// Get the corresponding u16 duty cycle from a percent value ranging between 0.0 and 1.0. +/// +/// Please note that this might load a lot of floating point code because this processor does not +/// have a FPU +pub fn get_duty_from_percent(percent: f32) -> u16 { + if percent > 1.0 { + DUTY_MAX + } else if percent <= 0.0 { + 0 + } else { + (percent * DUTY_MAX as f32) as u16 + } +} diff --git a/va416xx-hal/src/spi.rs b/va416xx-hal/src/spi.rs new file mode 100644 index 0000000..cc1acb3 --- /dev/null +++ b/va416xx-hal/src/spi.rs @@ -0,0 +1,978 @@ +//! API for the SPI peripheral +//! +//! ## Examples +//! +//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/spi.rs) +use core::{convert::Infallible, marker::PhantomData, ops::Deref}; + +use embedded_hal::spi::Mode; + +use crate::{ + clock::PeripheralSelect, + gpio::{ + AltFunc1, AltFunc2, AltFunc3, Pin, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PB0, + PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PC0, PC1, + PC10, PC11, PC7, PC8, PC9, PE10, PE11, PE12, PE13, PE14, PE15, PE5, PE6, PE7, PE8, PE9, + PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PG2, PG3, PG4, + }, + pac, + time::Hertz, + typelevel::{NoneT, Sealed}, +}; + +//================================================================================================== +// Defintions +//================================================================================================== + +// FIFO has a depth of 16. +const FILL_DEPTH: usize = 12; + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +pub enum HwChipSelectId { + Id0 = 0, + Id1 = 1, + Id2 = 2, + Id3 = 3, + Id4 = 4, + Id5 = 5, + Id6 = 6, + Id7 = 7, + Invalid = 0xff, +} + +#[derive(Debug)] +pub enum SpiId { + Spi0, + Spi1, + Spi2, + Spi3, + Invalid, +} + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +pub enum WordSize { + OneBit = 0x00, + FourBits = 0x03, + EightBits = 0x07, + SixteenBits = 0x0f, +} + +//================================================================================================== +// Pin type definitions +//================================================================================================== + +pub trait PinSck: Sealed {} +pub trait PinMosi: Sealed {} +pub trait PinMiso: Sealed {} + +pub trait HwCsProvider: Sealed { + const CS_ID: HwChipSelectId; + const SPI_ID: SpiId; +} + +pub trait OptionalHwCs: HwCsProvider + Sealed {} + +macro_rules! hw_cs_pins { + ($SPIx:path, $portId: path: + $( + ($PXx:ident, $AFx:ident, $HwCsIdent:path, $typedef:ident), + )+ + ) => { + $( + impl HwCsProvider for Pin<$PXx, $AFx> { + const CS_ID: HwChipSelectId = $HwCsIdent; + const SPI_ID: SpiId = $portId; + } + impl OptionalHwCs<$SPIx> for Pin<$PXx, $AFx> {} + pub type $typedef = Pin<$PXx, $AFx>; + )+ + }; +} + +impl HwCsProvider for NoneT { + const CS_ID: HwChipSelectId = HwChipSelectId::Invalid; + const SPI_ID: SpiId = SpiId::Invalid; +} + +impl OptionalHwCs for NoneT {} +impl OptionalHwCs for NoneT {} +impl OptionalHwCs for NoneT {} +impl OptionalHwCs for NoneT {} + +// SPI 0 + +impl PinSck for Pin {} +impl PinMosi for Pin {} +impl PinMiso for Pin {} + +// SPI 1 + +impl PinSck for Pin {} +impl PinMosi for Pin {} +impl PinMiso for Pin {} + +impl PinSck for Pin {} +impl PinMosi for Pin {} +impl PinMiso for Pin {} + +impl PinSck for Pin {} +impl PinMiso for Pin {} + +impl PinSck for Pin {} +impl PinMosi for Pin {} +impl PinMiso for Pin {} + +impl PinSck for Pin {} +impl PinMosi for Pin {} +impl PinMiso for Pin {} + +// SPI 2 + +impl PinSck for Pin {} +impl PinMosi for Pin {} +impl PinMiso for Pin {} + +impl PinSck for Pin {} +impl PinMosi for Pin {} +impl PinMiso for Pin {} + +// SPI3 is shared with the ROM SPI pins and has its own dedicated pins. + +// SPI 0 HW CS pins + +hw_cs_pins!( + pac::Spi0, SpiId::Spi0: + (PB14, AltFunc1, HwChipSelectId::Id0, HwCs0Spi0), + (PB13, AltFunc1, HwChipSelectId::Id1, HwCs1Spi0), + (PB12, AltFunc1, HwChipSelectId::Id2, HwCs2Spi0), + (PB11, AltFunc1, HwChipSelectId::Id3, HwCs3Spi0), +); + +hw_cs_pins!( + pac::Spi1, SpiId::Spi1: + (PB7, AltFunc3, HwChipSelectId::Id0, HwCs0Spi1Pb), + (PB6, AltFunc3, HwChipSelectId::Id1, HwCs1Spi1Pb), + (PB5, AltFunc3, HwChipSelectId::Id2, HwCs2Spi1Pb), + (PB4, AltFunc3, HwChipSelectId::Id3, HwCs3Spi1Pb), + (PB3, AltFunc3, HwChipSelectId::Id4, HwCs4Spi1Pb), + (PB2, AltFunc3, HwChipSelectId::Id5, HwCs5Spi1Pb), + (PB1, AltFunc3, HwChipSelectId::Id6, HwCs6Spi1Pb), + (PB0, AltFunc3, HwChipSelectId::Id7, HwCs7Spi1Pb), + (PC8, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pc), + (PC7, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pc), + (PE12, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pe), + (PE11, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pe), + (PE10, AltFunc2, HwChipSelectId::Id2, HwCs2Spi1Pe), + (PE9, AltFunc2, HwChipSelectId::Id3, HwCs3Spi1Pe), + (PE8, AltFunc2, HwChipSelectId::Id4, HwCs4Spi1Pe), + (PE7, AltFunc3, HwChipSelectId::Id5, HwCs5Spi1Pe), + (PE6, AltFunc3, HwChipSelectId::Id6, HwCs6Spi1Pe), + (PE5, AltFunc3, HwChipSelectId::Id7, HwCs7Spi1Pe), + (PF2, AltFunc1, HwChipSelectId::Id0, HwCs0Spi1Pf), + (PG2, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pg), +); + +hw_cs_pins!( + pac::Spi2, SpiId::Spi2: + (PA4, AltFunc2, HwChipSelectId::Id0, HwCs0Spi2Pa), + (PA3, AltFunc2, HwChipSelectId::Id1, HwCs1Spi2Pa), + (PA2, AltFunc2, HwChipSelectId::Id2, HwCs2Spi2Pa), + (PA1, AltFunc2, HwChipSelectId::Id3, HwCs3Spi2Pa), + (PA0, AltFunc2, HwChipSelectId::Id4, HwCs4Spi2Pa), + (PA8, AltFunc2, HwChipSelectId::Id6, HwCs6Spi2Pa), + (PA9, AltFunc2, HwChipSelectId::Id5, HwCs5Spi2Pa), + (PF0, AltFunc2, HwChipSelectId::Id4, HwCs4Spi2Pf), + (PF1, AltFunc2, HwChipSelectId::Id3, HwCs3Spi2Pf), + (PF2, AltFunc2, HwChipSelectId::Id2, HwCs2Spi2Pf), + (PF3, AltFunc2, HwChipSelectId::Id1, HwCs1Spi2Pf), + (PF4, AltFunc2, HwChipSelectId::Id0, HwCs0Spi2Pf), +); + +//================================================================================================== +// Config +//================================================================================================== + +pub trait TransferConfigProvider { + fn sod(&mut self, sod: bool); + fn blockmode(&mut self, blockmode: bool); + fn mode(&mut self, mode: Mode); + fn frequency(&mut self, spi_clk: Hertz); + fn hw_cs_id(&self) -> u8; +} + +/// This struct contains all configuration parameter which are transfer specific +/// and might change for transfers to different SPI slaves +#[derive(Copy, Clone)] +pub struct TransferConfig { + pub spi_clk: Hertz, + pub mode: Mode, + /// This only works if the Slave Output Disable (SOD) bit of the [`SpiConfig`] is set to + /// false + pub hw_cs: Option, + pub sod: bool, + /// If this is enabled, all data in the FIFO is transmitted in a single frame unless + /// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the + /// duration of multiple data words + pub blockmode: bool, +} + +/// Type erased variant of the transfer configuration. This is required to avoid generics in +/// the SPI constructor. +pub struct ErasedTransferConfig { + pub spi_clk: Hertz, + pub mode: Mode, + pub sod: bool, + /// If this is enabled, all data in the FIFO is transmitted in a single frame unless + /// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the + /// duration of multiple data words + pub blockmode: bool, + pub hw_cs: HwChipSelectId, +} + +impl TransferConfig { + pub fn new_no_hw_cs(spi_clk: impl Into, mode: Mode, blockmode: bool, sod: bool) -> Self { + TransferConfig { + spi_clk: spi_clk.into(), + mode, + hw_cs: None, + sod, + blockmode, + } + } +} + +impl TransferConfig { + pub fn new( + spi_clk: impl Into, + mode: Mode, + hw_cs: Option, + blockmode: bool, + sod: bool, + ) -> Self { + TransferConfig { + spi_clk: spi_clk.into(), + mode, + hw_cs, + sod, + blockmode, + } + } + + pub fn downgrade(self) -> ErasedTransferConfig { + ErasedTransferConfig { + spi_clk: self.spi_clk, + mode: self.mode, + sod: self.sod, + blockmode: self.blockmode, + hw_cs: HwCs::CS_ID, + } + } +} + +impl TransferConfigProvider for TransferConfig { + /// Slave Output Disable + fn sod(&mut self, sod: bool) { + self.sod = sod; + } + + fn blockmode(&mut self, blockmode: bool) { + self.blockmode = blockmode; + } + + fn mode(&mut self, mode: Mode) { + self.mode = mode; + } + + fn frequency(&mut self, spi_clk: Hertz) { + self.spi_clk = spi_clk; + } + + fn hw_cs_id(&self) -> u8 { + HwCs::CS_ID as u8 + } +} + +#[derive(Default)] +/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details +pub struct SpiConfig { + /// Serial clock rate divider. Together with the CLKPRESCALE register, it determines + /// the SPI clock rate in master mode. 0 by default. Specifying a higher value + /// limits the maximum attainable SPI speed + pub ser_clock_rate_div: u8, + /// By default, configure SPI for master mode (ms == false) + ms: bool, + /// Slave output disable. Useful if separate GPIO pins or decoders are used for CS control + pub slave_output_disable: bool, + /// Loopback mode. If you use this, don't connect MISO to MOSI, they will be tied internally + pub loopback_mode: bool, + /// Enable Master Delayer Capture Mode. See Programmers Guide p.92 for more details + pub master_delayer_capture: bool, +} + +impl SpiConfig { + pub fn loopback(mut self, enable: bool) -> Self { + self.loopback_mode = enable; + self + } + + pub fn master_mode(mut self, master: bool) -> Self { + self.ms = !master; + self + } + + pub fn slave_output_disable(mut self, sod: bool) -> Self { + self.slave_output_disable = sod; + self + } +} + +//================================================================================================== +// Word Size +//================================================================================================== + +/// Configuration trait for the Word Size used by the SPI peripheral +pub trait WordProvider: Copy + Default + Into + TryFrom + 'static { + const MASK: u32; + fn word_reg() -> u8; +} + +impl WordProvider for u8 { + const MASK: u32 = 0xff; + fn word_reg() -> u8 { + 0x07 + } +} + +impl WordProvider for u16 { + const MASK: u32 = 0xffff; + fn word_reg() -> u8 { + 0x0f + } +} + +pub type SpiRegBlock = pac::spi0::RegisterBlock; + +/// Common trait implemented by all PAC peripheral access structures. The register block +/// format is the same for all SPI blocks. +pub trait Instance: Deref { + const IDX: u8; + const PERIPH_SEL: PeripheralSelect; + + fn ptr() -> *const SpiRegBlock; +} + +impl Instance for pac::Spi0 { + const IDX: u8 = 0; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi0; + + fn ptr() -> *const SpiRegBlock { + Self::ptr() + } +} + +impl Instance for pac::Spi1 { + const IDX: u8 = 1; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi1; + + fn ptr() -> *const SpiRegBlock { + Self::ptr() + } +} + +impl Instance for pac::Spi2 { + const IDX: u8 = 2; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Spi2; + + fn ptr() -> *const SpiRegBlock { + Self::ptr() + } +} + +//================================================================================================== +// Spi +//================================================================================================== + +pub struct SpiBase { + spi: SpiInstance, + cfg: SpiConfig, + apb1_clk: Hertz, + /// Fill word for read-only SPI transactions. + pub fill_word: Word, + blockmode: bool, + word: PhantomData, +} + +pub struct Spi { + inner: SpiBase, + pins: Pins, +} + +fn mode_to_cpo_cph_bit(mode: embedded_hal::spi::Mode) -> (bool, bool) { + match mode { + embedded_hal::spi::MODE_0 => (false, false), + embedded_hal::spi::MODE_1 => (false, true), + embedded_hal::spi::MODE_2 => (true, false), + embedded_hal::spi::MODE_3 => (true, true), + } +} + +impl SpiBase +where + >::Error: core::fmt::Debug, +{ + #[inline] + pub fn cfg_clock(&mut self, spi_clk: impl Into) { + let clk_prescale = + self.apb1_clk.raw() / (spi_clk.into().raw() * (self.cfg.ser_clock_rate_div as u32 + 1)); + self.spi + .clkprescale() + .write(|w| unsafe { w.bits(clk_prescale) }); + } + + #[inline] + pub fn cfg_mode(&mut self, mode: Mode) { + let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(mode); + self.spi.ctrl0().modify(|_, w| { + w.spo().bit(cpo_bit); + w.sph().bit(cph_bit) + }); + } + + #[inline] + pub fn clear_tx_fifo(&self) { + self.spi.fifo_clr().write(|w| w.txfifo().set_bit()); + } + + #[inline] + pub fn clear_rx_fifo(&self) { + self.spi.fifo_clr().write(|w| w.rxfifo().set_bit()); + } + + #[inline] + pub fn perid(&self) -> u32 { + self.spi.perid().read().bits() + } + + #[inline] + pub fn cfg_hw_cs(&mut self, hw_cs: HwChipSelectId) { + if hw_cs == HwChipSelectId::Invalid { + return; + } + self.spi.ctrl1().modify(|_, w| { + w.sod().clear_bit(); + unsafe { + w.ss().bits(hw_cs as u8); + } + w + }); + } + + #[inline] + pub fn cfg_hw_cs_with_pin>(&mut self, _: &HwCs) { + self.cfg_hw_cs(HwCs::CS_ID); + } + + pub fn cfg_hw_cs_disable(&mut self) { + self.spi.ctrl1().modify(|_, w| { + w.sod().set_bit(); + w + }); + } + + pub fn cfg_transfer>( + &mut self, + transfer_cfg: &TransferConfig, + ) { + self.cfg_clock(transfer_cfg.spi_clk); + self.cfg_mode(transfer_cfg.mode); + self.blockmode = transfer_cfg.blockmode; + self.spi.ctrl1().modify(|_, w| { + if transfer_cfg.sod { + w.sod().set_bit(); + } else if transfer_cfg.hw_cs.is_some() { + w.sod().clear_bit(); + unsafe { + w.ss().bits(HwCs::CS_ID as u8); + } + } else { + w.sod().clear_bit(); + } + if transfer_cfg.blockmode { + w.blockmode().set_bit(); + } else { + w.blockmode().clear_bit(); + } + w + }); + } + + /// Sends a word to the slave + #[inline(always)] + fn send_blocking(&self, word: Word) { + // TODO: Upper limit for wait cycles to avoid complete hangups? + while self.spi.status().read().tnf().bit_is_clear() {} + self.send(word) + } + + #[inline(always)] + fn send(&self, word: Word) { + self.spi.data().write(|w| unsafe { w.bits(word.into()) }); + } + + /// Read a word from the slave. Must be preceeded by a [`send`](Self::send) call + #[inline(always)] + fn read_blocking(&self) -> Word { + // TODO: Upper limit for wait cycles to avoid complete hangups? + while self.spi.status().read().rne().bit_is_clear() {} + self.read_single_word() + } + + #[inline(always)] + fn read_single_word(&self) -> Word { + (self.spi.data().read().bits() & Word::MASK) + .try_into() + .unwrap() + } + + fn transfer_preparation(&self, words: &[Word]) -> Result<(), Infallible> { + if words.is_empty() { + return Ok(()); + } + let mut status_reg = self.spi.status().read(); + // Wait until all bytes have been transferred. + while status_reg.tfe().bit_is_clear() { + // Ignore all received read words. + if status_reg.rne().bit_is_set() { + self.clear_rx_fifo(); + } + status_reg = self.spi.status().read(); + } + // Ignore all received read words. + if status_reg.rne().bit_is_set() { + self.clear_rx_fifo(); + } + Ok(()) + } + + fn initial_send_fifo_pumping(&self, words: Option<&[Word]>) -> usize { + if self.blockmode { + self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit()) + } + // Fill the first half of the write FIFO + let mut current_write_idx = 0; + for _ in 0..core::cmp::min(FILL_DEPTH, words.map_or(0, |words| words.len())) { + self.send_blocking(words.map_or(self.fill_word, |words| words[current_write_idx])); + current_write_idx += 1; + } + if self.blockmode { + self.spi.ctrl1().modify(|_, w| w.mtxpause().clear_bit()) + } + current_write_idx + } +} + +/* +macro_rules! spi_ctor { + ($spiI:ident, $PeriphSel: path) => { + /// Create a new SPI struct + /// + /// You can delete the pin type information by calling the + /// [`downgrade`](Self::downgrade) function + /// + /// ## Arguments + /// * `spi` - SPI bus to use + /// * `pins` - Pins to be used for SPI transactions. These pins are consumed + /// to ensure the pins can not be used for other purposes anymore + /// * `spi_cfg` - Configuration specific to the SPI bus + /// * `transfer_cfg` - Optional initial transfer configuration which includes + /// configuration which can change across individual SPI transfers like SPI mode + /// or SPI clock. If only one device is connected, this configuration only needs + /// to be done once. + /// * `syscfg` - Can be passed optionally to enable the peripheral clock + pub fn $spiI( + spi: SpiI, + pins: (Sck, Miso, Mosi), + clocks: &crate::clock::Clocks, + spi_cfg: SpiConfig, + syscfg: &mut pac::Sysconfig, + transfer_cfg: Option<&ErasedTransferConfig>, + ) -> Self { + crate::clock::enable_peripheral_clock(syscfg, $PeriphSel); + let SpiConfig { + ser_clock_rate_div, + ms, + slave_output_disable, + loopback_mode, + master_delayer_capture, + } = spi_cfg; + let mut mode = embedded_hal::spi::MODE_0; + let mut clk_prescale = 0x02; + let mut ss = 0; + let mut init_blockmode = false; + let apb1_clk = clocks.apb1(); + if let Some(transfer_cfg) = transfer_cfg { + mode = transfer_cfg.mode; + clk_prescale = + apb1_clk.raw() / (transfer_cfg.spi_clk.raw() * (ser_clock_rate_div as u32 + 1)); + if transfer_cfg.hw_cs != HwChipSelectId::Invalid { + ss = transfer_cfg.hw_cs as u8; + } + init_blockmode = transfer_cfg.blockmode; + } + + let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(mode); + spi.ctrl0().write(|w| { + unsafe { + w.size().bits(Word::word_reg()); + w.scrdv().bits(ser_clock_rate_div); + // Clear clock phase and polarity. Will be set to correct value for each + // transfer + w.spo().bit(cpo_bit); + w.sph().bit(cph_bit) + } + }); + spi.ctrl1().write(|w| { + w.lbm().bit(loopback_mode); + w.sod().bit(slave_output_disable); + w.ms().bit(ms); + w.mdlycap().bit(master_delayer_capture); + w.blockmode().bit(init_blockmode); + unsafe { w.ss().bits(ss) } + }); + + spi.fifo_clr().write(|w| { + w.rxfifo().set_bit(); + w.txfifo().set_bit() + }); + spi.clkprescale().write(|w| unsafe { w.bits(clk_prescale) }); + // Enable the peripheral as the last step as recommended in the + // programmers guide + spi.ctrl1().modify(|_, w| w.enable().set_bit()); + Spi { + inner: SpiBase { + spi, + cfg: spi_cfg, + apb1_clk, + fill_word: Default::default(), + blockmode: init_blockmode, + word: PhantomData, + }, + pins, + } + } + }; +} +*/ + +impl< + SpiI: Instance, + Sck: PinSck, + Miso: PinMiso, + Mosi: PinMosi, + Word: WordProvider, + > Spi +where + >::Error: core::fmt::Debug, +{ + /// Create a new SPI struct + /// + /// You can delete the pin type information by calling the + /// [`downgrade`](Self::downgrade) function + /// + /// ## Arguments + /// * `spi` - SPI bus to use + /// * `pins` - Pins to be used for SPI transactions. These pins are consumed + /// to ensure the pins can not be used for other purposes anymore + /// * `spi_cfg` - Configuration specific to the SPI bus + /// * `transfer_cfg` - Optional initial transfer configuration which includes + /// configuration which can change across individual SPI transfers like SPI mode + /// or SPI clock. If only one device is connected, this configuration only needs + /// to be done once. + /// * `syscfg` - Can be passed optionally to enable the peripheral clock + pub fn new( + spi: SpiI, + pins: (Sck, Miso, Mosi), + clocks: &crate::clock::Clocks, + spi_cfg: SpiConfig, + syscfg: &mut pac::Sysconfig, + transfer_cfg: Option<&ErasedTransferConfig>, + ) -> Self { + crate::clock::enable_peripheral_clock(syscfg, SpiI::PERIPH_SEL); + let SpiConfig { + ser_clock_rate_div, + ms, + slave_output_disable, + loopback_mode, + master_delayer_capture, + } = spi_cfg; + let mut mode = embedded_hal::spi::MODE_0; + let mut clk_prescale = 0x02; + let mut ss = 0; + let mut init_blockmode = false; + let apb1_clk = clocks.apb1(); + if let Some(transfer_cfg) = transfer_cfg { + mode = transfer_cfg.mode; + clk_prescale = + apb1_clk.raw() / (transfer_cfg.spi_clk.raw() * (ser_clock_rate_div as u32 + 1)); + if transfer_cfg.hw_cs != HwChipSelectId::Invalid { + ss = transfer_cfg.hw_cs as u8; + } + init_blockmode = transfer_cfg.blockmode; + } + + let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(mode); + spi.ctrl0().write(|w| { + unsafe { + w.size().bits(Word::word_reg()); + w.scrdv().bits(ser_clock_rate_div); + // Clear clock phase and polarity. Will be set to correct value for each + // transfer + w.spo().bit(cpo_bit); + w.sph().bit(cph_bit) + } + }); + spi.ctrl1().write(|w| { + w.lbm().bit(loopback_mode); + w.sod().bit(slave_output_disable); + w.ms().bit(ms); + w.mdlycap().bit(master_delayer_capture); + w.blockmode().bit(init_blockmode); + unsafe { w.ss().bits(ss) } + }); + + spi.fifo_clr().write(|w| { + w.rxfifo().set_bit(); + w.txfifo().set_bit() + }); + spi.clkprescale().write(|w| unsafe { w.bits(clk_prescale) }); + // Enable the peripheral as the last step as recommended in the + // programmers guide + spi.ctrl1().modify(|_, w| w.enable().set_bit()); + Spi { + inner: SpiBase { + spi, + cfg: spi_cfg, + apb1_clk, + fill_word: Default::default(), + blockmode: init_blockmode, + word: PhantomData, + }, + pins, + } + } + + #[inline] + pub fn cfg_clock(&mut self, spi_clk: impl Into) { + self.inner.cfg_clock(spi_clk); + } + + #[inline] + pub fn cfg_mode(&mut self, mode: Mode) { + self.inner.cfg_mode(mode); + } + + pub fn set_fill_word(&mut self, fill_word: Word) { + self.inner.fill_word = fill_word; + } + + pub fn fill_word(&self) -> Word { + self.inner.fill_word + } + + #[inline] + pub fn perid(&self) -> u32 { + self.inner.perid() + } + + pub fn cfg_transfer>(&mut self, transfer_cfg: &TransferConfig) { + self.inner.cfg_transfer(transfer_cfg); + } + + /// Releases the SPI peripheral and associated pins + pub fn release(self) -> (SpiI, (Sck, Miso, Mosi), SpiConfig) { + (self.inner.spi, self.pins, self.inner.cfg) + } + + pub fn downgrade(self) -> SpiBase { + self.inner + } +} + +/// Changing the word size also requires a type conversion +impl, Miso: PinMiso, Mosi: PinMosi> + From> for Spi +{ + fn from(old_spi: Spi) -> Self { + old_spi + .inner + .spi + .ctrl0() + .modify(|_, w| unsafe { w.size().bits(WordSize::SixteenBits as u8) }); + Spi { + inner: SpiBase { + spi: old_spi.inner.spi, + cfg: old_spi.inner.cfg, + blockmode: old_spi.inner.blockmode, + fill_word: Default::default(), + apb1_clk: old_spi.inner.apb1_clk, + word: PhantomData, + }, + pins: old_spi.pins, + } + } +} + +/// Changing the word size also requires a type conversion +impl, Miso: PinMiso, Mosi: PinMosi> + From> for Spi +{ + fn from(old_spi: Spi) -> Self { + old_spi + .inner + .spi + .ctrl0() + .modify(|_, w| unsafe { w.size().bits(WordSize::EightBits as u8) }); + Spi { + inner: SpiBase { + spi: old_spi.inner.spi, + cfg: old_spi.inner.cfg, + blockmode: old_spi.inner.blockmode, + apb1_clk: old_spi.inner.apb1_clk, + fill_word: Default::default(), + word: PhantomData, + }, + pins: old_spi.pins, + } + } +} + +impl embedded_hal::spi::ErrorType for SpiBase { + type Error = Infallible; +} + +impl embedded_hal::spi::SpiBus for SpiBase +where + >::Error: core::fmt::Debug, +{ + fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> { + self.transfer_preparation(words)?; + let mut current_read_idx = 0; + let mut current_write_idx = self.initial_send_fifo_pumping(None); + loop { + if current_write_idx < words.len() { + self.send_blocking(self.fill_word); + current_write_idx += 1; + } + if current_read_idx < words.len() { + words[current_read_idx] = self.read_blocking(); + current_read_idx += 1; + } + if current_read_idx >= words.len() && current_write_idx >= words.len() { + break; + } + } + Ok(()) + } + + fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> { + self.transfer_preparation(words)?; + let mut current_write_idx = self.initial_send_fifo_pumping(Some(words)); + while current_write_idx < words.len() { + self.send_blocking(words[current_write_idx]); + current_write_idx += 1; + // Ignore received words. + if self.spi.status().read().rne().bit_is_set() { + self.clear_rx_fifo(); + } + } + Ok(()) + } + + fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> { + self.transfer_preparation(write)?; + let mut current_read_idx = 0; + let mut current_write_idx = self.initial_send_fifo_pumping(Some(write)); + while current_read_idx < read.len() || current_write_idx < write.len() { + if current_write_idx < write.len() { + self.send_blocking(write[current_write_idx]); + current_write_idx += 1; + } + if current_read_idx < read.len() { + read[current_read_idx] = self.read_blocking(); + current_read_idx += 1; + } + } + + Ok(()) + } + + fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> { + self.transfer_preparation(words)?; + let mut current_read_idx = 0; + let mut current_write_idx = self.initial_send_fifo_pumping(Some(words)); + + while current_read_idx < words.len() || current_write_idx < words.len() { + if current_write_idx < words.len() { + self.send_blocking(words[current_write_idx]); + current_write_idx += 1; + } + if current_read_idx < words.len() && current_read_idx < current_write_idx { + words[current_read_idx] = self.read_blocking(); + current_read_idx += 1; + } + } + Ok(()) + } + + fn flush(&mut self) -> Result<(), Self::Error> { + let status_reg = self.spi.status().read(); + while status_reg.tfe().bit_is_clear() || status_reg.rne().bit_is_set() { + if status_reg.rne().bit_is_set() { + self.read_single_word(); + } + } + Ok(()) + } +} + +impl< + SpiI: Instance, + Word: WordProvider, + Sck: PinSck, + Miso: PinMiso, + Mosi: PinMosi, + > embedded_hal::spi::ErrorType for Spi +{ + type Error = Infallible; +} + +impl< + SpiI: Instance, + Word: WordProvider, + Sck: PinSck, + Miso: PinMiso, + Mosi: PinMosi, + > embedded_hal::spi::SpiBus for Spi +where + >::Error: core::fmt::Debug, +{ + fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> { + self.inner.read(words) + } + + fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> { + self.inner.write(words) + } + + fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> { + self.inner.transfer(read, write) + } + + fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> { + self.inner.transfer_in_place(words) + } + + fn flush(&mut self) -> Result<(), Self::Error> { + self.inner.flush() + } +} diff --git a/va416xx-hal/src/time.rs b/va416xx-hal/src/time.rs new file mode 100644 index 0000000..9808028 --- /dev/null +++ b/va416xx-hal/src/time.rs @@ -0,0 +1,26 @@ +//! Time units + +// Frequency based + +/// Hertz +pub type Hertz = fugit::HertzU32; + +/// KiloHertz +pub type KiloHertz = fugit::KilohertzU32; + +/// MegaHertz +pub type MegaHertz = fugit::MegahertzU32; + +// Period based + +/// Seconds +pub type Seconds = fugit::SecsDurationU32; + +/// Milliseconds +pub type Milliseconds = fugit::MillisDurationU32; + +/// Microseconds +pub type Microseconds = fugit::MicrosDurationU32; + +/// Nanoseconds +pub type Nanoseconds = fugit::NanosDurationU32; diff --git a/va416xx-hal/src/timer.rs b/va416xx-hal/src/timer.rs new file mode 100644 index 0000000..e3831b8 --- /dev/null +++ b/va416xx-hal/src/timer.rs @@ -0,0 +1,801 @@ +//! API for the TIM peripherals +//! +//! ## Examples +//! +//! TODO. +use core::cell::Cell; + +use cortex_m::interrupt::Mutex; + +use crate::clock::Clocks; +use crate::gpio::{ + AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14, + PA15, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB2, PB3, + PB4, PB5, PB6, PB7, PB8, PB9, PC0, PC1, PD0, PD1, PD10, PD11, PD12, PD13, PD14, PD15, PD2, PD3, + PD4, PD5, PD6, PD7, PD8, PD9, PE0, PE1, PE10, PE11, PE12, PE13, PE14, PE15, PE2, PE3, PE4, PE5, + PE6, PE7, PE8, PE9, PF0, PF1, PF10, PF11, PF12, PF13, PF14, PF15, PF2, PF3, PF4, PF5, PF6, PF7, + PF8, PF9, PG0, PG1, PG2, PG3, PG6, +}; +use crate::time::Hertz; +use crate::typelevel::Sealed; +use crate::{disable_interrupt, prelude::*}; +use crate::{enable_interrupt, pac}; + +pub static MS_COUNTER: Mutex> = Mutex::new(Cell::new(0)); + +//================================================================================================== +// Defintions +//================================================================================================== + +/// Interrupt events +//pub enum Event { +/// Timer timed out / count down ended +//TimeOut, +//} + +#[derive(Default, Debug, PartialEq, Eq, Copy, Clone)] +pub struct CascadeCtrl { + /// Enable Cascade 0 signal active as a requirement for counting + pub enb_start_src_csd0: bool, + /// Invert Cascade 0, making it active low + pub inv_csd0: bool, + /// Enable Cascade 1 signal active as a requirement for counting + pub enb_start_src_csd1: bool, + /// Invert Cascade 1, making it active low + pub inv_csd1: bool, + /// Specify required operation if both Cascade 0 and Cascade 1 are active. + /// 0 is a logical AND of both cascade signals, 1 is a logical OR + pub dual_csd_op: bool, + /// Enable trigger mode for Cascade 0. In trigger mode, couting will start with the selected + /// cascade signal active, but once the counter is active, cascade control will be ignored + pub trg_csd0: bool, + /// Trigger mode, identical to [`trg_csd0`](CascadeCtrl) but for Cascade 1 + pub trg_csd1: bool, + /// Enable Cascade 2 signal active as a requirement to stop counting. This mode is similar + /// to the REQ_STOP control bit, but signalled by a Cascade source + pub enb_stop_src_csd2: bool, + /// Invert Cascade 2, making it active low + pub inv_csd2: bool, + /// The counter is automatically disabled if the corresponding Cascade 2 level-sensitive input + /// souce is active when the count reaches 0. If the counter is not 0, the cascade control is + /// ignored + pub trg_csd2: bool, +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum CascadeSel { + Sel0 = 0, + Sel1 = 1, + Sel2 = 2, +} + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct InvalidCascadeSourceId; + +#[derive(Debug, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum CascadeSource { + PortA(u8), + PortB(u8), + PortC(u8), + PortD(u8), + PortE(u8), + Tim(u8), + TxEv, + AdcIrq, + RomSbe, + RomMbe, + Ram0Sbe, + Ram0Mbe, + Ram1Sbe, + Ram2Mbe, + WdogIrq, +} + +impl CascadeSource { + fn id(&self) -> Result { + let port_check = |base: u8, id: u8| { + if id > 15 { + return Err(InvalidCascadeSourceId); + } + Ok(base + id) + }; + match self { + CascadeSource::PortA(id) => port_check(0, *id), + CascadeSource::PortB(id) => port_check(16, *id), + CascadeSource::PortC(id) => port_check(32, *id), + CascadeSource::PortD(id) => port_check(48, *id), + CascadeSource::PortE(id) => port_check(65, *id), + CascadeSource::Tim(id) => { + if *id > 23 { + return Err(InvalidCascadeSourceId); + } + Ok(80 + id) + } + CascadeSource::TxEv => Ok(104), + CascadeSource::AdcIrq => Ok(105), + CascadeSource::RomSbe => Ok(106), + CascadeSource::RomMbe => Ok(106), + CascadeSource::Ram0Sbe => Ok(108), + CascadeSource::Ram0Mbe => Ok(109), + CascadeSource::Ram1Sbe => Ok(110), + CascadeSource::Ram2Mbe => Ok(111), + CascadeSource::WdogIrq => Ok(112), + } + } +} + +//================================================================================================== +// Valid TIM and PIN combinations +//================================================================================================== + +pub trait TimPin { + const DYN: DynPinId; +} + +pub trait ValidTim { + // TIM ID ranging from 0 to 23 for 24 TIM peripherals + const TIM_ID: u8; + const IRQ: pac::Interrupt; + + fn clock(clocks: &Clocks) -> Hertz { + if Self::TIM_ID <= 15 { + clocks.apb1() + } else { + clocks.apb2() + } + } +} + +macro_rules! tim_markers { + ( + $( + ($TimX:path, $id:expr, $Irq:path), + )+ + ) => { + $( + impl ValidTim for $TimX { + const TIM_ID: u8 = $id; + const IRQ: pac::Interrupt = $Irq; + } + )+ + }; +} + +tim_markers!( + (pac::Tim0, 0, pac::Interrupt::TIM0), + (pac::Tim1, 1, pac::Interrupt::TIM1), + (pac::Tim2, 2, pac::Interrupt::TIM2), + (pac::Tim3, 3, pac::Interrupt::TIM3), + (pac::Tim4, 4, pac::Interrupt::TIM4), + (pac::Tim5, 5, pac::Interrupt::TIM5), + (pac::Tim6, 6, pac::Interrupt::TIM6), + (pac::Tim7, 7, pac::Interrupt::TIM7), + (pac::Tim8, 8, pac::Interrupt::TIM8), + (pac::Tim9, 9, pac::Interrupt::TIM9), + (pac::Tim10, 10, pac::Interrupt::TIM10), + (pac::Tim11, 11, pac::Interrupt::TIM11), + (pac::Tim12, 12, pac::Interrupt::TIM12), + (pac::Tim13, 13, pac::Interrupt::TIM13), + (pac::Tim14, 14, pac::Interrupt::TIM14), + (pac::Tim15, 15, pac::Interrupt::TIM15), + (pac::Tim16, 16, pac::Interrupt::TIM16), + (pac::Tim17, 17, pac::Interrupt::TIM17), + (pac::Tim18, 18, pac::Interrupt::TIM18), + (pac::Tim19, 19, pac::Interrupt::TIM19), + (pac::Tim20, 20, pac::Interrupt::TIM20), + (pac::Tim21, 21, pac::Interrupt::TIM21), + (pac::Tim22, 22, pac::Interrupt::TIM22), + (pac::Tim23, 23, pac::Interrupt::TIM23), +); + +pub trait ValidTimAndPin: Sealed {} + +macro_rules! valid_pin_and_tims { + ( + $( + ($PinX:ident, $AltFunc:ident, $TimX:path), + )+ + ) => { + $( + impl TimPin for Pin<$PinX, $AltFunc> + where + $PinX: PinId, + { + const DYN: DynPinId = $PinX::DYN; + } + + impl< + PinInstance: TimPin, + Tim: ValidTim + > ValidTimAndPin for (Pin<$PinX, $AltFunc>, $TimX) + where + Pin<$PinX, $AltFunc>: TimPin, + $PinX: PinId, + { + } + + impl Sealed for (Pin<$PinX, $AltFunc>, $TimX) {} + )+ + }; +} + +valid_pin_and_tims!( + (PA0, AltFunc1, pac::Tim0), + (PA1, AltFunc1, pac::Tim1), + (PA2, AltFunc1, pac::Tim2), + (PA3, AltFunc1, pac::Tim3), + (PA4, AltFunc1, pac::Tim4), + (PA5, AltFunc1, pac::Tim5), + (PA6, AltFunc1, pac::Tim6), + (PA7, AltFunc1, pac::Tim7), + (PA10, AltFunc2, pac::Tim23), + (PA11, AltFunc2, pac::Tim22), + (PA12, AltFunc2, pac::Tim21), + (PA13, AltFunc2, pac::Tim20), + (PA14, AltFunc2, pac::Tim19), + (PA15, AltFunc2, pac::Tim18), + (PB0, AltFunc2, pac::Tim17), + (PB1, AltFunc2, pac::Tim16), + (PB2, AltFunc2, pac::Tim15), + (PB3, AltFunc2, pac::Tim14), + (PB4, AltFunc2, pac::Tim13), + (PB5, AltFunc2, pac::Tim12), + (PB6, AltFunc2, pac::Tim11), + (PB7, AltFunc2, pac::Tim10), + (PB8, AltFunc2, pac::Tim9), + (PB9, AltFunc2, pac::Tim8), + (PB10, AltFunc2, pac::Tim7), + (PB11, AltFunc2, pac::Tim6), + (PB12, AltFunc2, pac::Tim5), + (PB13, AltFunc2, pac::Tim4), + (PB14, AltFunc2, pac::Tim3), + (PB15, AltFunc2, pac::Tim2), + (PC0, AltFunc2, pac::Tim1), + (PC1, AltFunc2, pac::Tim0), + (PD0, AltFunc2, pac::Tim0), + (PD1, AltFunc2, pac::Tim1), + (PD2, AltFunc2, pac::Tim2), + (PD3, AltFunc2, pac::Tim3), + (PD4, AltFunc2, pac::Tim4), + (PD5, AltFunc2, pac::Tim5), + (PD6, AltFunc2, pac::Tim6), + (PD7, AltFunc2, pac::Tim7), + (PD8, AltFunc2, pac::Tim8), + (PD9, AltFunc2, pac::Tim9), + (PD10, AltFunc2, pac::Tim10), + (PD11, AltFunc2, pac::Tim11), + (PD12, AltFunc2, pac::Tim12), + (PD13, AltFunc2, pac::Tim13), + (PD14, AltFunc2, pac::Tim14), + (PD15, AltFunc2, pac::Tim15), + (PE0, AltFunc2, pac::Tim16), + (PE1, AltFunc2, pac::Tim17), + (PE2, AltFunc2, pac::Tim18), + (PE3, AltFunc2, pac::Tim19), + (PE4, AltFunc2, pac::Tim20), + (PE5, AltFunc2, pac::Tim21), + (PE6, AltFunc2, pac::Tim22), + (PE7, AltFunc2, pac::Tim23), + (PE8, AltFunc3, pac::Tim16), + (PE9, AltFunc3, pac::Tim17), + (PE10, AltFunc3, pac::Tim18), + (PE11, AltFunc3, pac::Tim19), + (PE12, AltFunc3, pac::Tim20), + (PE13, AltFunc3, pac::Tim21), + (PE14, AltFunc3, pac::Tim22), + (PE15, AltFunc3, pac::Tim23), + (PF0, AltFunc3, pac::Tim0), + (PF1, AltFunc3, pac::Tim1), + (PF2, AltFunc3, pac::Tim2), + (PF3, AltFunc3, pac::Tim3), + (PF4, AltFunc3, pac::Tim4), + (PF5, AltFunc3, pac::Tim5), + (PF6, AltFunc3, pac::Tim6), + (PF7, AltFunc3, pac::Tim7), + (PF8, AltFunc3, pac::Tim8), + (PF9, AltFunc3, pac::Tim9), + (PF10, AltFunc3, pac::Tim10), + (PF11, AltFunc3, pac::Tim11), + (PF12, AltFunc3, pac::Tim12), + (PF13, AltFunc2, pac::Tim19), + (PF14, AltFunc2, pac::Tim20), + (PF15, AltFunc2, pac::Tim21), + (PG0, AltFunc2, pac::Tim22), + (PG1, AltFunc2, pac::Tim23), + (PG2, AltFunc1, pac::Tim9), + (PG3, AltFunc1, pac::Tim10), + (PG6, AltFunc1, pac::Tim12), +); + +//================================================================================================== +// Register Interface for TIM registers and TIM pins +//================================================================================================== + +/// Clear the reset bit of the TIM, holding it in reset +/// +/// # Safety +/// +/// Only the bit related to the corresponding TIM peripheral is modified +#[inline] +fn assert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) { + syscfg + .tim_reset() + .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << tim_id as u32)) }) +} + +#[inline] +fn deassert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) { + syscfg + .tim_reset() + .modify(|r, w| unsafe { w.bits(r.bits() | (1 << tim_id as u32)) }) +} + +pub type TimRegBlock = pac::tim0::RegisterBlock; + +/// Register interface. +/// +/// This interface provides valid TIM pins a way to access their corresponding TIM +/// registers +/// +/// # Safety +/// +/// Users should only implement the [`tim_id`] function. No default function +/// implementations should be overridden. The implementing type must also have +/// "control" over the corresponding pin ID, i.e. it must guarantee that a each +/// pin ID is a singleton. +pub(super) unsafe trait TimRegInterface { + fn tim_id(&self) -> u8; + + const PORT_BASE: *const pac::tim0::RegisterBlock = pac::Tim0::ptr() as *const _; + + /// All 24 TIM blocks are identical. This helper functions returns the correct + /// memory mapped peripheral depending on the TIM ID. + #[inline(always)] + fn reg(&self) -> &TimRegBlock { + unsafe { &*Self::PORT_BASE.offset(self.tim_id() as isize) } + } + + #[inline(always)] + fn mask_32(&self) -> u32 { + 1 << self.tim_id() + } + + /// Clear the reset bit of the TIM, holding it in reset + /// + /// # Safety + /// + /// Only the bit related to the corresponding TIM peripheral is modified + #[inline] + #[allow(dead_code)] + fn assert_tim_reset(&self, syscfg: &mut pac::Sysconfig) { + assert_tim_reset(syscfg, self.tim_id()); + } + + #[inline] + #[allow(dead_code)] + fn deassert_time_reset(&self, syscfg: &mut pac::Sysconfig) { + deassert_tim_reset(syscfg, self.tim_id()); + } +} + +/// Provide a safe register interface for [`ValidTimAndPin`]s +/// +/// This `struct` takes ownership of a [`ValidTimAndPin`] and provides an API to +/// access the corresponding registers. +pub(super) struct TimAndPinRegister { + pin: Pin, + tim: Tim, +} + +pub(super) struct TimRegister { + tim: TIM, +} + +impl TimRegister { + #[inline] + pub(super) unsafe fn new(tim: TIM) -> Self { + TimRegister { tim } + } + + pub(super) fn release(self) -> TIM { + self.tim + } +} + +unsafe impl TimRegInterface for TimRegister { + #[inline(always)] + fn tim_id(&self) -> u8 { + Tim::TIM_ID + } +} + +impl TimAndPinRegister +where + (Pin, Tim): ValidTimAndPin, +{ + #[inline] + pub(super) unsafe fn new(pin: Pin, tim: Tim) -> Self { + TimAndPinRegister { pin, tim } + } + + pub(super) fn release(self) -> (Pin, Tim) { + (self.pin, self.tim) + } +} + +unsafe impl TimRegInterface for TimAndPinRegister { + #[inline(always)] + fn tim_id(&self) -> u8 { + Tim::TIM_ID + } +} + +pub(super) struct TimDynRegister { + tim_id: u8, + #[allow(dead_code)] + pin_id: DynPinId, +} + +impl From> for TimDynRegister { + fn from(_reg: TimAndPinRegister) -> Self { + Self { + tim_id: Tim::TIM_ID, + pin_id: Pin::DYN, + } + } +} + +unsafe impl TimRegInterface for TimDynRegister { + #[inline(always)] + fn tim_id(&self) -> u8 { + self.tim_id + } +} + +//================================================================================================== +// Timers +//================================================================================================== + +/// Hardware timers +pub struct CountdownTimer { + tim: TimRegister, + curr_freq: Hertz, + clock: Hertz, + rst_val: u32, + last_cnt: u32, + listening: bool, +} + +#[inline] +fn enable_tim_clk(syscfg: &mut pac::Sysconfig, idx: u8) { + syscfg + .tim_clk_enable() + .modify(|r, w| unsafe { w.bits(r.bits() | (1 << idx)) }); +} + +unsafe impl TimRegInterface for CountdownTimer { + #[inline] + fn tim_id(&self) -> u8 { + TIM::TIM_ID + } +} + +impl CountdownTimer { + /// Create a new countdown timer, but does not start it. + /// + /// You can use [Self::start] to start the countdown timer, and you may optionally call + /// [Self::listen] to enable interrupts for the TIM peripheral as well. + pub fn new(syscfg: &mut pac::Sysconfig, tim: Tim, clocks: &Clocks) -> Self { + enable_tim_clk(syscfg, Tim::TIM_ID); + assert_tim_reset(syscfg, Tim::TIM_ID); + cortex_m::asm::nop(); + cortex_m::asm::nop(); + deassert_tim_reset(syscfg, Tim::TIM_ID); + + CountdownTimer { + tim: unsafe { TimRegister::new(tim) }, + clock: Tim::clock(clocks), + rst_val: 0, + curr_freq: 0_u32.Hz(), + listening: false, + last_cnt: 0, + } + } + + #[inline] + pub fn start(&mut self, timeout: impl Into) { + self.load(timeout); + self.enable(); + } + + /// Listen for events. Depending on the IRQ configuration, this also activates the IRQ in the + /// IRQSEL peripheral for the provided interrupt and unmasks the interrupt + pub fn listen(&mut self) { + self.listening = true; + self.enable_interrupt(); + unsafe { enable_interrupt(Tim::IRQ) } + } + + /// Return `Ok` if the timer has wrapped. Peripheral will automatically clear the + /// flag and restart the time if configured correctly + pub fn wait(&mut self) -> nb::Result<(), void::Void> { + let cnt = self.tim.reg().cnt_value().read().bits(); + if (cnt > self.last_cnt) || cnt == 0 { + self.last_cnt = self.rst_val; + Ok(()) + } else { + self.last_cnt = cnt; + Err(nb::Error::WouldBlock) + } + } + + pub fn stop(&mut self) { + self.tim.reg().ctrl().write(|w| w.enable().clear_bit()); + } + + pub fn unlisten(&mut self) { + self.listening = true; + self.disable_interrupt(); + disable_interrupt(Tim::IRQ); + } + + #[inline(always)] + pub fn enable_interrupt(&mut self) { + self.tim.reg().ctrl().modify(|_, w| w.irq_enb().set_bit()); + } + + #[inline(always)] + pub fn disable_interrupt(&mut self) { + self.tim.reg().ctrl().modify(|_, w| w.irq_enb().clear_bit()); + } + + pub fn release(self, syscfg: &mut pac::Sysconfig) -> Tim { + self.tim.reg().ctrl().write(|w| w.enable().clear_bit()); + syscfg + .tim_clk_enable() + .modify(|r, w| unsafe { w.bits(r.bits() & !(1 << Tim::TIM_ID)) }); + self.tim.release() + } + + /// Load the count down timer with a timeout but do not start it. + pub fn load(&mut self, timeout: impl Into) { + self.tim.reg().ctrl().modify(|_, w| w.enable().clear_bit()); + self.curr_freq = timeout.into(); + self.rst_val = self.clock.raw() / self.curr_freq.raw(); + self.set_reload(self.rst_val); + self.set_count(0); + } + + #[inline(always)] + pub fn set_reload(&mut self, val: u32) { + self.tim.reg().rst_value().write(|w| unsafe { w.bits(val) }); + } + + #[inline(always)] + pub fn set_count(&mut self, val: u32) { + self.tim.reg().cnt_value().write(|w| unsafe { w.bits(val) }); + } + + #[inline(always)] + pub fn count(&self) -> u32 { + self.tim.reg().cnt_value().read().bits() + } + + #[inline(always)] + pub fn enable(&mut self) { + self.tim.reg().ctrl().modify(|_, w| w.enable().set_bit()); + } + + #[inline(always)] + pub fn disable(&mut self) { + self.tim.reg().ctrl().modify(|_, w| w.enable().clear_bit()); + } + + /// Disable the counter, setting both enable and active bit to 0 + #[inline] + pub fn auto_disable(self, enable: bool) -> Self { + if enable { + self.tim + .reg() + .ctrl() + .modify(|_, w| w.auto_disable().set_bit()); + } else { + self.tim + .reg() + .ctrl() + .modify(|_, w| w.auto_disable().clear_bit()); + } + self + } + + /// This option only applies when the Auto-Disable functionality is 0. + /// + /// The active bit is changed to 0 when count reaches 0, but the counter stays + /// enabled. When Auto-Disable is 1, Auto-Deactivate is implied + #[inline] + pub fn auto_deactivate(self, enable: bool) -> Self { + if enable { + self.tim + .reg() + .ctrl() + .modify(|_, w| w.auto_deactivate().set_bit()); + } else { + self.tim + .reg() + .ctrl() + .modify(|_, w| w.auto_deactivate().clear_bit()); + } + self + } + + /// Configure the cascade parameters + #[inline] + pub fn cascade_control(&mut self, ctrl: CascadeCtrl) { + self.tim.reg().csd_ctrl().write(|w| { + w.csden0().bit(ctrl.enb_start_src_csd0); + w.csdinv0().bit(ctrl.inv_csd0); + w.csden1().bit(ctrl.enb_start_src_csd1); + w.csdinv1().bit(ctrl.inv_csd1); + w.dcasop().bit(ctrl.dual_csd_op); + w.csdtrg0().bit(ctrl.trg_csd0); + w.csdtrg1().bit(ctrl.trg_csd1); + w.csden2().bit(ctrl.enb_stop_src_csd2); + w.csdinv2().bit(ctrl.inv_csd2); + w.csdtrg2().bit(ctrl.trg_csd2) + }); + } + + #[inline] + pub fn cascade_0_source(&mut self, src: CascadeSource) -> Result<(), InvalidCascadeSourceId> { + let id = src.id()?; + self.tim + .reg() + .cascade0() + .write(|w| unsafe { w.cassel().bits(id) }); + Ok(()) + } + + #[inline] + pub fn cascade_1_source(&mut self, src: CascadeSource) -> Result<(), InvalidCascadeSourceId> { + let id = src.id()?; + self.tim + .reg() + .cascade1() + .write(|w| unsafe { w.cassel().bits(id) }); + Ok(()) + } + + #[inline] + pub fn cascade_2_source(&mut self, src: CascadeSource) -> Result<(), InvalidCascadeSourceId> { + let id = src.id()?; + self.tim + .reg() + .cascade2() + .write(|w| unsafe { w.cassel().bits(id) }); + Ok(()) + } + + #[inline] + pub fn curr_freq(&self) -> Hertz { + self.curr_freq + } + + #[inline] + pub fn listening(&self) -> bool { + self.listening + } +} + +impl embedded_hal::delay::DelayNs for CountdownTimer { + fn delay_ns(&mut self, ns: u32) { + let ticks = (u64::from(ns)) * (u64::from(self.clock.raw())) / 1_000_000_000; + + let full_cycles = ticks >> 32; + let mut last_count; + let mut new_count; + if full_cycles > 0 { + self.set_reload(u32::MAX); + self.set_count(u32::MAX); + self.enable(); + + for _ in 0..full_cycles { + // Always ensure that both values are the same at the start. + new_count = self.count(); + last_count = new_count; + loop { + new_count = self.count(); + if new_count == 0 { + // Wait till timer has wrapped. + while self.count() == 0 { + cortex_m::asm::nop() + } + break; + } + // Timer has definitely wrapped. + if new_count > last_count { + break; + } + last_count = new_count; + } + } + } + let ticks = (ticks & u32::MAX as u64) as u32; + self.disable(); + if ticks > 1 { + self.set_reload(ticks); + self.set_count(ticks); + self.enable(); + last_count = ticks; + + loop { + new_count = self.count(); + if new_count == 0 || (new_count > last_count) { + break; + } + last_count = new_count; + } + } + + self.disable(); + } +} + +//================================================================================================== +// MS tick implementations +//================================================================================================== + +// Set up a millisecond timer on TIM0. Please note that the user still has to provide an IRQ handler +// which should call [default_ms_irq_handler]. +pub fn set_up_ms_tick( + sys_cfg: &mut pac::Sysconfig, + tim: Tim, + clocks: &Clocks, +) -> CountdownTimer { + let mut ms_timer = CountdownTimer::new(sys_cfg, tim, clocks); + ms_timer.listen(); + ms_timer.start(1000.Hz()); + ms_timer +} + +/// This function can be called in a specified interrupt handler to increment +/// the MS counter +pub fn default_ms_irq_handler() { + cortex_m::interrupt::free(|cs| { + let mut ms = MS_COUNTER.borrow(cs).get(); + ms += 1; + MS_COUNTER.borrow(cs).set(ms); + }); +} + +/// Get the current MS tick count +pub fn get_ms_ticks() -> u32 { + cortex_m::interrupt::free(|cs| MS_COUNTER.borrow(cs).get()) +} + +pub struct DelayMs(CountdownTimer); + +impl DelayMs { + pub fn new(timer: CountdownTimer) -> Option { + if timer.curr_freq() != Hertz::from_raw(1000) || !timer.listening() { + return None; + } + Some(Self(timer)) + } +} + +/// This assumes that the user has already set up a MS tick timer with [set_up_ms_tick] +impl embedded_hal::delay::DelayNs for DelayMs { + fn delay_ns(&mut self, ns: u32) { + let ns_as_ms = ns / 1_000_000; + if self.0.curr_freq() != Hertz::from_raw(1000) || !self.0.listening() { + return; + } + let start_time = get_ms_ticks(); + while get_ms_ticks() - start_time < ns_as_ms { + cortex_m::asm::nop(); + } + } +} diff --git a/va416xx-hal/src/typelevel.rs b/va416xx-hal/src/typelevel.rs new file mode 100644 index 0000000..7803c20 --- /dev/null +++ b/va416xx-hal/src/typelevel.rs @@ -0,0 +1,155 @@ +//! Module supporting type-level programming +//! +//! This module is identical to the +//! [atsamd typelevel](https://docs.rs/atsamd-hal/latest/atsamd_hal/typelevel/index.html). + +use core::ops::{Add, Sub}; + +use typenum::{Add1, Bit, Sub1, UInt, Unsigned, B1, U0}; + +mod private { + /// Super trait used to mark traits with an exhaustive set of + /// implementations + pub trait Sealed {} + + impl Sealed for u8 {} + impl Sealed for i8 {} + impl Sealed for u16 {} + impl Sealed for i16 {} + impl Sealed for u32 {} + impl Sealed for i32 {} + impl Sealed for f32 {} + + /// Mapping from an instance of a countable type to its successor + pub trait Increment { + /// Successor type of `Self` + type Inc; + /// Consume an instance of `Self` and return its successor + fn inc(self) -> Self::Inc; + } + + /// Mapping from an instance of a countable type to its predecessor + pub trait Decrement { + /// Predecessor type of `Self` + type Dec; + /// Consume an instance of `Self` and return its predecessor + fn dec(self) -> Self::Dec; + } +} + +pub(crate) use private::Decrement as PrivateDecrement; +pub(crate) use private::Increment as PrivateIncrement; +pub(crate) use private::Sealed; + +/// Type-level version of the [`None`] variant +#[derive(Default)] +pub struct NoneT; + +impl Sealed for NoneT {} + +//============================================================================== +// Is +//============================================================================== + +/// Marker trait for type identity +/// +/// This trait is used as part of the [`AnyKind`] trait pattern. It represents +/// the concept of type identity, because all implementors have +/// `::Type == Self`. When used as a trait bound with a specific +/// type, it guarantees that the corresponding type parameter is exactly the +/// specific type. Stated differently, it guarantees that `T == Specific` in +/// the following example. +/// +/// ```ignore +/// where T: Is +/// ``` +/// +/// Moreover, the super traits guarantee that any instance of or reference to a +/// type `T` can be converted into the `Specific` type. +/// +/// ```ignore +/// fn example(mut any: T) +/// where +/// T: Is, +/// { +/// let specific_mut: &mut Specific = any.as_mut(); +/// let specific_ref: &Specific = any.as_ref(); +/// let specific: Specific = any.into(); +/// } +/// ``` +/// +/// [`AnyKind`]: #anykind-trait-pattern +pub trait Is +where + Self: Sealed, + Self: From>, + Self: Into>, + Self: AsRef>, + Self: AsMut>, +{ + type Type; +} + +/// Type alias for [`Is::Type`] +pub type IsType = ::Type; + +impl Is for T +where + T: Sealed + AsRef + AsMut, +{ + type Type = T; +} + +//============================================================================== +// Counting +//============================================================================== + +/// Implement `Sealed` for [`U0`] +impl Sealed for U0 {} + +/// Implement `Sealed` for all type-level, [`Unsigned`] integers *except* [`U0`] +impl Sealed for UInt {} + +/// Trait mapping each countable type to its successor +/// +/// This trait maps each countable type to its corresponding successor type. The +/// actual implementation of this trait is contained within `PrivateIncrement`. +/// Access to `PrivateIncrement` is restricted, so that safe HAL APIs can be +/// built with it. +pub trait Increment: PrivateIncrement {} + +impl Increment for T {} + +/// Trait mapping each countable type to its predecessor +/// +/// This trait maps each countable type to its corresponding predecessor type. +/// The actual implementation of this trait is contained within +/// `PrivateDecrement`. Access to `PrivateDecrement` is restricted, so that safe +/// HAL APIs can be built with it. +pub trait Decrement: PrivateDecrement {} + +impl Decrement for T {} + +impl PrivateIncrement for N +where + N: Unsigned + Add, + Add1: Unsigned, +{ + type Inc = Add1; + #[inline] + fn inc(self) -> Self::Inc { + Self::Inc::default() + } +} + +impl PrivateDecrement for N +where + N: Unsigned + Sub, + Sub1: Unsigned, +{ + type Dec = Sub1; + #[inline] + fn dec(self) -> Self::Dec { + Self::Dec::default() + } +} diff --git a/va416xx-hal/src/uart.rs b/va416xx-hal/src/uart.rs new file mode 100644 index 0000000..d9b8cf4 --- /dev/null +++ b/va416xx-hal/src/uart.rs @@ -0,0 +1,1014 @@ +//! # API for the UART peripheral +//! +//! ## Examples +//! +//! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs) +use core::marker::PhantomData; +use core::ops::Deref; + +use embedded_hal_nb::serial::Read; +use fugit::RateExtU32; + +use crate::clock::{Clocks, PeripheralSelect}; +use crate::gpio::{AltFunc1, Pin, PD11, PD12, PE2, PE3, PF11, PF12, PF8, PF9, PG0, PG1}; +use crate::time::Hertz; +use crate::{disable_interrupt, enable_interrupt}; +use crate::{ + gpio::{AltFunc2, AltFunc3, PA2, PA3, PB14, PB15, PC14, PC15, PC4, PC5}, + pac::{self, uart0 as uart_base, Uart0, Uart1, Uart2}, +}; + +//================================================================================================== +// Type-Level support +//================================================================================================== + +pub trait TxRxPins {} + +impl TxRxPins for (Pin, Pin) {} +impl TxRxPins for (Pin, Pin) {} +impl TxRxPins for (Pin, Pin) {} +impl TxRxPins for (Pin, Pin) {} + +impl TxRxPins for (Pin, Pin) {} +impl TxRxPins for (Pin, Pin) {} +impl TxRxPins for (Pin, Pin) {} + +impl TxRxPins for (Pin, Pin) {} +impl TxRxPins for (Pin, Pin) {} + +//================================================================================================== +// Regular Definitions +//================================================================================================== + +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Error { + Overrun, + FramingError, + ParityError, + BreakCondition, + TransferPending, + BufferTooShort, +} + +#[derive(Debug, PartialEq, Eq, Copy, Clone)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Event { + // Receiver FIFO interrupt enable. Generates interrupt + // when FIFO is at least half full. Half full is defined as FIFO + // count >= RXFIFOIRQTRG + RxFifoHalfFull, + // Framing error, Overrun error, Parity Error and Break error + RxError, + // Event for timeout condition: Data in the FIFO and no receiver + // FIFO activity for 4 character times + RxTimeout, + + // Transmitter FIFO interrupt enable. Generates interrupt + // when FIFO is at least half full. Half full is defined as FIFO + // count >= TXFIFOIRQTRG + TxFifoHalfFull, + // FIFO overflow error + TxError, + // Generate interrupt when transmit FIFO is empty and TXBUSY is 0 + TxEmpty, + // Interrupt when CTSn changes value + TxCts, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum Parity { + None, + Odd, + Even, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum StopBits { + One = 0, + Two = 1, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum WordSize { + Five = 0, + Six = 1, + Seven = 2, + Eight = 3, +} + +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct Config { + pub baudrate: Hertz, + pub parity: Parity, + pub stopbits: StopBits, + // When false, use standard 16x baud clock, other 8x baud clock + pub baud8: bool, + pub wordsize: WordSize, + pub enable_tx: bool, + pub enable_rx: bool, +} + +impl Config { + pub fn baudrate(mut self, baudrate: Hertz) -> Self { + self.baudrate = baudrate; + self + } + + pub fn parity_none(mut self) -> Self { + self.parity = Parity::None; + self + } + + pub fn parity_even(mut self) -> Self { + self.parity = Parity::Even; + self + } + + pub fn parity_odd(mut self) -> Self { + self.parity = Parity::Odd; + self + } + + pub fn stopbits(mut self, stopbits: StopBits) -> Self { + self.stopbits = stopbits; + self + } + + pub fn wordsize(mut self, wordsize: WordSize) -> Self { + self.wordsize = wordsize; + self + } + + pub fn baud8(mut self, baud: bool) -> Self { + self.baud8 = baud; + self + } +} + +impl Default for Config { + fn default() -> Config { + Config { + baudrate: 115200_u32.Hz(), + parity: Parity::None, + stopbits: StopBits::One, + baud8: false, + wordsize: WordSize::Eight, + enable_tx: true, + enable_rx: true, + } + } +} + +impl From for Config { + fn from(value: Hertz) -> Self { + Config::default().baudrate(value) + } +} + +//================================================================================================== +// IRQ Definitions +//================================================================================================== + +struct IrqInfo { + rx_len: usize, + rx_idx: usize, + mode: IrqReceptionMode, +} + +pub enum IrqResultMask { + Complete = 0, + Overflow = 1, + FramingError = 2, + ParityError = 3, + Break = 4, + Timeout = 5, + Addr9 = 6, + /// Should not happen + Unknown = 7, +} + +/// This struct is used to return the default IRQ handler result to the user +#[derive(Debug, Default)] +pub struct IrqResult { + raw_res: u32, + pub bytes_read: usize, +} + +impl IrqResult { + pub const fn new() -> Self { + IrqResult { + raw_res: 0, + bytes_read: 0, + } + } +} + +impl IrqResult { + #[inline] + pub fn raw_result(&self) -> u32 { + self.raw_res + } + + #[inline] + pub(crate) fn clear_result(&mut self) { + self.raw_res = 0; + } + #[inline] + pub(crate) fn set_result(&mut self, flag: IrqResultMask) { + self.raw_res |= 1 << flag as u32; + } + + #[inline] + pub fn complete(&self) -> bool { + if ((self.raw_res >> IrqResultMask::Complete as u32) & 0x01) == 0x01 { + return true; + } + false + } + + #[inline] + pub fn error(&self) -> bool { + if self.overflow_error() || self.framing_error() || self.parity_error() { + return true; + } + false + } + + #[inline] + pub fn overflow_error(&self) -> bool { + if ((self.raw_res >> IrqResultMask::Overflow as u32) & 0x01) == 0x01 { + return true; + } + false + } + + #[inline] + pub fn framing_error(&self) -> bool { + if ((self.raw_res >> IrqResultMask::FramingError as u32) & 0x01) == 0x01 { + return true; + } + false + } + + #[inline] + pub fn parity_error(&self) -> bool { + if ((self.raw_res >> IrqResultMask::ParityError as u32) & 0x01) == 0x01 { + return true; + } + false + } + + #[inline] + pub fn timeout(&self) -> bool { + if ((self.raw_res >> IrqResultMask::Timeout as u32) & 0x01) == 0x01 { + return true; + } + false + } +} + +#[derive(Debug, PartialEq)] +enum IrqReceptionMode { + Idle, + Pending, +} + +//================================================================================================== +// UART implementation +//================================================================================================== + +/// Type erased variant of a UART. Can be created with the [Uart::downgrade] function. +pub struct UartBase { + uart: Uart, + tx: Tx, + rx: Rx, +} +/// Serial abstraction. Entry point to create a new UART +pub struct Uart { + inner: UartBase, + pins: Pins, +} + +/// UART using the IRQ capabilities of the peripheral. Can be created with the +/// [`Uart::into_uart_with_irq`] function. Currently, only the RX side for IRQ based reception +/// is implemented. +pub struct UartWithIrq { + base: UartWithIrqBase, + pins: Pins, +} + +/// Type-erased UART using the IRQ capabilities of the peripheral. Can be created with the +/// [`UartWithIrq::downgrade`] function. Currently, only the RX side for IRQ based reception +/// is implemented. +pub struct UartWithIrqBase { + pub inner: UartBase, + irq_info: IrqInfo, +} + +/// Serial receiver +pub struct Rx { + _usart: PhantomData, +} + +/// Serial transmitter +pub struct Tx { + _usart: PhantomData, +} + +impl Rx { + fn new() -> Self { + Self { + _usart: PhantomData, + } + } +} + +impl Tx { + fn new() -> Self { + Self { + _usart: PhantomData, + } + } +} + +pub trait Instance: Deref { + const IDX: u8; + const PERIPH_SEL: PeripheralSelect; + const IRQ_RX: pac::Interrupt; + const IRQ_TX: pac::Interrupt; + + fn ptr() -> *const uart_base::RegisterBlock; +} + +impl Instance for Uart0 { + const IDX: u8 = 0; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart0; + const IRQ_RX: pac::Interrupt = pac::Interrupt::UART0_RX; + const IRQ_TX: pac::Interrupt = pac::Interrupt::UART0_TX; + + fn ptr() -> *const uart_base::RegisterBlock { + Uart0::ptr() as *const _ + } +} + +impl Instance for Uart1 { + const IDX: u8 = 1; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart1; + const IRQ_RX: pac::Interrupt = pac::Interrupt::UART1_RX; + const IRQ_TX: pac::Interrupt = pac::Interrupt::UART1_TX; + + fn ptr() -> *const uart_base::RegisterBlock { + Uart1::ptr() as *const _ + } +} + +impl Instance for Uart2 { + const IDX: u8 = 2; + const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Uart2; + const IRQ_RX: pac::Interrupt = pac::Interrupt::UART2_RX; + const IRQ_TX: pac::Interrupt = pac::Interrupt::UART2_TX; + + fn ptr() -> *const uart_base::RegisterBlock { + Uart2::ptr() as *const _ + } +} + +impl UartBase { + fn init(self, config: Config, clocks: &Clocks) -> Self { + if Uart::IDX == 2 { + self.init_with_clock_freq(config, clocks.apb1()) + } else { + self.init_with_clock_freq(config, clocks.apb2()) + } + } + + /// This function assumes that the peripheral clock was alredy enabled + /// in the SYSCONFIG register + fn init_with_clock_freq(self, config: Config, apb_clk: Hertz) -> Self { + let baud_multiplier = match config.baud8 { + false => 16, + true => 8, + }; + // This is the calculation: (64.0 * (x - integer_part as f32) + 0.5) as u32 without floating + // point calculations. + let frac = ((apb_clk.raw() % (config.baudrate.raw() * 16)) * 64 + + (config.baudrate.raw() * 8)) + / (config.baudrate.raw() * 16); + // Calculations here are derived from chapter 10.4.4 (p.74) of the datasheet. + let x = apb_clk.raw() as f32 / (config.baudrate.raw() * baud_multiplier) as f32; + let integer_part = x as u32; + self.uart.clkscale().write(|w| unsafe { + w.frac().bits(frac as u8); + w.int().bits(integer_part) + }); + + let (paren, pareven) = match config.parity { + Parity::None => (false, false), + Parity::Odd => (true, false), + Parity::Even => (true, true), + }; + let stopbits = match config.stopbits { + StopBits::One => false, + StopBits::Two => true, + }; + let wordsize = config.wordsize as u8; + let baud8 = config.baud8; + self.uart.ctrl().write(|w| { + w.paren().bit(paren); + w.pareven().bit(pareven); + w.stopbits().bit(stopbits); + w.baud8().bit(baud8); + unsafe { w.wordsize().bits(wordsize) } + }); + let (txenb, rxenb) = (config.enable_tx, config.enable_rx); + // Clear the FIFO + self.uart.fifo_clr().write(|w| { + w.rxfifo().set_bit(); + w.txfifo().set_bit() + }); + self.uart.enable().write(|w| { + w.rxenable().bit(rxenb); + w.txenable().bit(txenb) + }); + self + } + + #[inline] + pub fn enable_rx(&mut self) { + self.uart.enable().modify(|_, w| w.rxenable().set_bit()); + } + + #[inline] + pub fn disable_rx(&mut self) { + self.uart.enable().modify(|_, w| w.rxenable().clear_bit()); + } + + #[inline] + pub fn enable_tx(&mut self) { + self.uart.enable().modify(|_, w| w.txenable().set_bit()); + } + + #[inline] + pub fn disable_tx(&mut self) { + self.uart.enable().modify(|_, w| w.txenable().clear_bit()); + } + + #[inline] + pub fn clear_rx_fifo(&mut self) { + self.uart.fifo_clr().write(|w| w.rxfifo().set_bit()); + } + + #[inline] + pub fn clear_tx_fifo(&mut self) { + self.uart.fifo_clr().write(|w| w.txfifo().set_bit()); + } + + pub fn listen(&self, event: Event) { + self.uart.irq_enb().modify(|_, w| match event { + Event::RxError => w.irq_rx_status().set_bit(), + Event::RxFifoHalfFull => w.irq_rx().set_bit(), + Event::RxTimeout => w.irq_rx_to().set_bit(), + Event::TxEmpty => w.irq_tx_empty().set_bit(), + Event::TxError => w.irq_tx_status().set_bit(), + Event::TxFifoHalfFull => w.irq_tx().set_bit(), + Event::TxCts => w.irq_tx_cts().set_bit(), + }); + } + + pub fn unlisten(&self, event: Event) { + self.uart.irq_enb().modify(|_, w| match event { + Event::RxError => w.irq_rx_status().clear_bit(), + Event::RxFifoHalfFull => w.irq_rx().clear_bit(), + Event::RxTimeout => w.irq_rx_to().clear_bit(), + Event::TxEmpty => w.irq_tx_empty().clear_bit(), + Event::TxError => w.irq_tx_status().clear_bit(), + Event::TxFifoHalfFull => w.irq_tx().clear_bit(), + Event::TxCts => w.irq_tx_cts().clear_bit(), + }); + } + + pub fn release(self) -> Uart { + // Clear the FIFO + self.uart.fifo_clr().write(|w| { + w.rxfifo().set_bit(); + w.txfifo().set_bit() + }); + self.uart.enable().write(|w| { + w.rxenable().clear_bit(); + w.txenable().clear_bit() + }); + disable_interrupt(Uart::IRQ_RX); + self.uart + } + + pub fn split(self) -> (Tx, Rx) { + (self.tx, self.rx) + } +} + +impl Uart { + pub fn new( + uart: UartInstance, + pins: Pins, + config: impl Into, + syscfg: &mut va416xx::Sysconfig, + clocks: &Clocks, + ) -> Self { + crate::clock::enable_peripheral_clock(syscfg, UartInstance::PERIPH_SEL); + Uart { + inner: UartBase { + uart, + tx: Tx::new(), + rx: Rx::new(), + }, + pins, + } + .init(config.into(), clocks) + } + + pub fn new_with_clock_freq( + uart: UartInstance, + pins: Pins, + config: impl Into, + syscfg: &mut va416xx::Sysconfig, + clock: impl Into, + ) -> Self { + crate::clock::enable_peripheral_clock(syscfg, UartInstance::PERIPH_SEL); + Uart { + inner: UartBase { + uart, + tx: Tx::new(), + rx: Rx::new(), + }, + pins, + } + .init_with_clock_freq(config.into(), clock.into()) + } + + fn init(mut self, config: Config, clocks: &Clocks) -> Self { + self.inner = self.inner.init(config, clocks); + self + } + + /// This function assumes that the peripheral clock was already enabled + /// in the SYSCONFIG register + #[allow(dead_code)] + fn init_with_clock_freq(mut self, config: Config, sys_clk: Hertz) -> Self { + self.inner = self.inner.init_with_clock_freq(config, sys_clk); + self + } + + /// If the IRQ capabilities of the peripheral are used, the UART needs to be converted + /// with this function + pub fn into_uart_with_irq(self) -> UartWithIrq { + let (inner, pins) = self.downgrade_internal(); + UartWithIrq { + pins, + base: UartWithIrqBase { + inner, + irq_info: IrqInfo { + rx_len: 0, + rx_idx: 0, + mode: IrqReceptionMode::Idle, + }, + }, + } + } + + delegate::delegate! { + to self.inner { + #[inline] + pub fn enable_rx(&mut self); + #[inline] + pub fn disable_rx(&mut self); + + #[inline] + pub fn enable_tx(&mut self); + #[inline] + pub fn disable_tx(&mut self); + + #[inline] + pub fn clear_rx_fifo(&mut self); + #[inline] + pub fn clear_tx_fifo(&mut self); + + #[inline] + pub fn listen(&self, event: Event); + #[inline] + pub fn unlisten(&self, event: Event); + #[inline] + pub fn split(self) -> (Tx, Rx); + } + } + + fn downgrade_internal(self) -> (UartBase, Pins) { + let base = UartBase { + uart: self.inner.uart, + tx: self.inner.tx, + rx: self.inner.rx, + }; + (base, self.pins) + } + + pub fn downgrade(self) -> UartBase { + UartBase { + uart: self.inner.uart, + tx: self.inner.tx, + rx: self.inner.rx, + } + } + + pub fn release(self) -> (UartInstance, Pins) { + (self.inner.release(), self.pins) + } +} + +#[derive(Default, Debug)] +pub struct IrqUartError { + overflow: bool, + framing: bool, + parity: bool, +} + +impl IrqUartError { + pub fn error(&self) -> bool { + self.overflow || self.framing || self.parity + } +} + +#[derive(Debug)] +pub enum IrqError { + BufferTooShort { found: usize, expected: usize }, + Uart(IrqUartError), +} + +impl UartWithIrqBase { + /// This initializes a non-blocking read transfer using the IRQ capabilities of the UART + /// peripheral. + /// + /// The only required information is the maximum length for variable sized reception + /// or the expected length for fixed length reception. If variable sized packets are expected, + /// the timeout functionality of the IRQ should be enabled as well. After calling this function, + /// the [`irq_handler`](Self::irq_handler) function should be called in the user interrupt + /// handler to read the received packets and reinitiate another transfer if desired. + pub fn read_fixed_len_using_irq( + &mut self, + max_len: usize, + enb_timeout_irq: bool, + ) -> Result<(), Error> { + if self.irq_info.mode != IrqReceptionMode::Idle { + return Err(Error::TransferPending); + } + self.irq_info.mode = IrqReceptionMode::Pending; + self.irq_info.rx_idx = 0; + self.irq_info.rx_len = max_len; + self.inner.enable_rx(); + self.inner.enable_tx(); + self.enable_rx_irq_sources(enb_timeout_irq); + unsafe { enable_interrupt(Uart::IRQ_RX) }; + Ok(()) + } + + #[inline] + fn enable_rx_irq_sources(&mut self, timeout: bool) { + self.inner.uart.irq_enb().modify(|_, w| { + if timeout { + w.irq_rx_to().set_bit(); + } + w.irq_rx_status().set_bit(); + w.irq_rx().set_bit() + }); + } + + #[inline] + fn disable_rx_irq_sources(&mut self) { + self.inner.uart.irq_enb().modify(|_, w| { + w.irq_rx_to().clear_bit(); + w.irq_rx_status().clear_bit(); + w.irq_rx().clear_bit() + }); + } + + #[inline] + pub fn enable_tx(&mut self) { + self.inner.enable_tx() + } + + #[inline] + pub fn disable_tx(&mut self) { + self.inner.disable_tx() + } + + pub fn cancel_transfer(&mut self) { + self.disable_rx_irq_sources(); + self.inner.clear_tx_fifo(); + self.irq_info.rx_idx = 0; + self.irq_info.rx_len = 0; + } + + /// Default IRQ handler which can be used to read the packets arriving on the UART peripheral. + /// + /// If passed buffer is equal to or larger than the specified maximum length, an + /// [`Error::BufferTooShort`] will be returned + pub fn irq_handler(&mut self, buf: &mut [u8]) -> Result { + if buf.len() < self.irq_info.rx_len { + return Err(IrqError::BufferTooShort { + found: buf.len(), + expected: self.irq_info.rx_len, + }); + } + let mut res = IrqResult::default(); + let mut possible_error = IrqUartError::default(); + + let rx_status = self.inner.uart.rxstatus().read(); + res.raw_res = rx_status.bits(); + let irq_end = self.inner.uart.irq_end().read(); + let enb_status = self.inner.uart.enable().read(); + let rx_enabled = enb_status.rxenable().bit_is_set(); + let _tx_enabled = enb_status.txenable().bit_is_set(); + let read_handler = |res: &mut IrqResult, + possible_error: &mut IrqUartError, + read_res: nb::Result| + -> Option { + match read_res { + Ok(byte) => Some(byte), + Err(nb::Error::WouldBlock) => None, + Err(nb::Error::Other(e)) => { + match e { + Error::Overrun => { + possible_error.overflow = true; + } + Error::FramingError => { + possible_error.framing = true; + } + Error::ParityError => { + possible_error.parity = true; + } + _ => { + res.set_result(IrqResultMask::Unknown); + } + } + None + } + } + }; + if irq_end.irq_rx().bit_is_set() { + // If this interrupt bit is set, the trigger level is available at the very least. + // Read everything as fast as possible + for _ in 0..core::cmp::min( + self.inner.uart.rxfifoirqtrg().read().bits() as usize, + self.irq_info.rx_len, + ) { + buf[self.irq_info.rx_idx] = (self.inner.uart.data().read().bits() & 0xff) as u8; + self.irq_info.rx_idx += 1; + } + + // While there is data in the FIFO, write it into the reception buffer + loop { + if self.irq_info.rx_idx == self.irq_info.rx_len { + self.irq_completion_handler(&mut res); + return Ok(res); + } + if let Some(byte) = read_handler(&mut res, &mut possible_error, self.inner.read()) { + buf[self.irq_info.rx_idx] = byte; + self.irq_info.rx_idx += 1; + } else { + break; + } + } + } + + // RX transfer not complete, check for RX errors + if (self.irq_info.rx_idx < self.irq_info.rx_len) && rx_enabled { + // Read status register again, might have changed since reading received data + let rx_status = self.inner.uart.rxstatus().read(); + res.raw_res = rx_status.bits(); + if rx_status.rxovr().bit_is_set() { + possible_error.overflow = true; + } + if rx_status.rxfrm().bit_is_set() { + possible_error.framing = true; + } + if rx_status.rxpar().bit_is_set() { + possible_error.parity = true; + } + if rx_status.rxto().bit_is_set() { + // A timeout has occured but there might be some leftover data in the FIFO, + // so read that data as well + while let Some(byte) = + read_handler(&mut res, &mut possible_error, self.inner.read()) + { + buf[self.irq_info.rx_idx] = byte; + self.irq_info.rx_idx += 1; + } + self.irq_completion_handler(&mut res); + res.set_result(IrqResultMask::Timeout); + return Ok(res); + } + + // If it is not a timeout, it's an error + if possible_error.error() { + self.disable_rx_irq_sources(); + return Err(IrqError::Uart(possible_error)); + } + } + + // Clear the interrupt status bits + self.inner + .uart + .irq_clr() + .write(|w| unsafe { w.bits(irq_end.bits()) }); + Ok(res) + } + + fn irq_completion_handler(&mut self, res: &mut IrqResult) { + self.disable_rx_irq_sources(); + self.inner.disable_rx(); + res.bytes_read = self.irq_info.rx_idx; + res.clear_result(); + res.set_result(IrqResultMask::Complete); + self.irq_info.mode = IrqReceptionMode::Idle; + self.irq_info.rx_idx = 0; + self.irq_info.rx_len = 0; + } + + pub fn release(self) -> Uart { + self.inner.release() + } +} + +impl UartWithIrq { + /// See [`UartWithIrqBase::read_fixed_len_using_irq`] doc + pub fn read_fixed_len_using_irq( + &mut self, + max_len: usize, + enb_timeout_irq: bool, + ) -> Result<(), Error> { + self.base.read_fixed_len_using_irq(max_len, enb_timeout_irq) + } + + pub fn cancel_transfer(&mut self) { + self.base.cancel_transfer() + } + + /// See [`UartWithIrqBase::irq_handler`] doc + pub fn irq_handler(&mut self, buf: &mut [u8]) -> Result { + self.base.irq_handler(buf) + } + + pub fn release(self) -> (Uart, Pins) { + (self.base.release(), self.pins) + } + + pub fn downgrade(self) -> (UartWithIrqBase, Pins) { + (self.base, self.pins) + } +} + +impl embedded_io::Error for Error { + fn kind(&self) -> embedded_io::ErrorKind { + embedded_io::ErrorKind::Other + } +} + +impl embedded_hal_nb::serial::Error for Error { + fn kind(&self) -> embedded_hal_nb::serial::ErrorKind { + embedded_hal_nb::serial::ErrorKind::Other + } +} + +impl embedded_io::ErrorType for Rx { + type Error = Error; +} + +impl embedded_hal_nb::serial::ErrorType for Rx { + type Error = Error; +} + +impl embedded_hal_nb::serial::Read for Rx { + fn read(&mut self) -> nb::Result { + let uart = unsafe { &(*Uart::ptr()) }; + let status_reader = uart.rxstatus().read(); + let err = if status_reader.rxovr().bit_is_set() { + Some(Error::Overrun) + } else if status_reader.rxfrm().bit_is_set() { + Some(Error::FramingError) + } else if status_reader.rxpar().bit_is_set() { + Some(Error::ParityError) + } else { + None + }; + if let Some(err) = err { + // The status code is always related to the next bit for the framing + // and parity status bits. We have to read the DATA register + // so that the next status reflects the next DATA word + // For overrun error, we read as well to clear the peripheral + uart.data().read().bits(); + Err(err.into()) + } else if status_reader.rdavl().bit_is_set() { + let data = uart.data().read().bits(); + Ok((data & 0xff) as u8) + } else { + Err(nb::Error::WouldBlock) + } + } +} + +impl embedded_io::Read for Rx { + fn read(&mut self, buf: &mut [u8]) -> Result { + if buf.is_empty() { + return Ok(0); + } + + for byte in buf.iter_mut() { + let w = nb::block!(>::read(self))?; + *byte = w; + } + + Ok(buf.len()) + } +} + +impl embedded_io::ErrorType for Tx { + type Error = Error; +} + +impl embedded_hal_nb::serial::ErrorType for Tx { + type Error = Error; +} + +impl embedded_hal_nb::serial::Write for Tx { + fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { + let reader = unsafe { &(*Uart::ptr()) }.txstatus().read(); + if reader.wrrdy().bit_is_clear() { + return Err(nb::Error::WouldBlock); + } else { + // DPARITY bit not supported yet + unsafe { + // NOTE(unsafe) atomic write to data register + // NOTE(write_volatile) 8-bit write that's not + // possible through the svd2rust API + (*Uart::ptr()).data().write(|w| w.bits(word as u32)); + } + } + Ok(()) + } + + fn flush(&mut self) -> nb::Result<(), Self::Error> { + // SAFETY: Only TX related registers are used. + let reader = unsafe { &(*Uart::ptr()) }.txstatus().read(); + if reader.wrbusy().bit_is_set() { + return Err(nb::Error::WouldBlock); + } + Ok(()) + } +} + +impl embedded_io::Write for Tx { + fn write(&mut self, buf: &[u8]) -> Result { + if buf.is_empty() { + return Ok(0); + } + + for byte in buf.iter() { + nb::block!(>::write( + self, *byte + ))?; + } + + Ok(buf.len()) + } + + fn flush(&mut self) -> Result<(), Self::Error> { + nb::block!(>::flush(self)) + } +} + +impl embedded_io::ErrorType for UartBase { + type Error = Error; +} + +impl embedded_hal_nb::serial::ErrorType for UartBase { + type Error = Error; +} + +impl embedded_hal_nb::serial::Read for UartBase { + fn read(&mut self) -> nb::Result { + self.rx.read() + } +} + +impl embedded_hal_nb::serial::Write for UartBase { + fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> { + self.tx.write(word) + } + + fn flush(&mut self) -> nb::Result<(), Self::Error> { + self.tx.flush() + } +} diff --git a/va416xx-hal/src/wdt.rs b/va416xx-hal/src/wdt.rs new file mode 100644 index 0000000..c5594b3 --- /dev/null +++ b/va416xx-hal/src/wdt.rs @@ -0,0 +1,118 @@ +//! # API for the Watchdog peripheral +//! +//! ## Examples +//! +//! - [Watchdog simple example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/wdt.rs) +use crate::time::Hertz; +use crate::{ + clock::{Clocks, PeripheralSelect}, + pac, + prelude::SyscfgExt, +}; +use crate::{disable_interrupt, enable_interrupt}; + +pub const WDT_UNLOCK_VALUE: u32 = 0x1ACC_E551; + +pub struct WdtController { + clock_freq: Hertz, + wdt: pac::WatchDog, +} + +/// Enable the watchdog interrupt +/// +/// # Safety +/// +/// This function is `unsafe` because it can break mask-based critical sections. +#[inline] +pub unsafe fn enable_wdt_interrupts() { + enable_interrupt(pac::Interrupt::WATCHDOG) +} + +#[inline] +pub fn disable_wdt_interrupts() { + disable_interrupt(pac::Interrupt::WATCHDOG) +} + +impl WdtController { + pub fn new( + &self, + syscfg: &mut pac::Sysconfig, + wdt: pac::WatchDog, + clocks: &Clocks, + wdt_freq_ms: u32, + ) -> Self { + Self::start(syscfg, wdt, clocks, wdt_freq_ms) + } + + pub fn start( + syscfg: &mut pac::Sysconfig, + wdt: pac::WatchDog, + clocks: &Clocks, + wdt_freq_ms: u32, + ) -> Self { + syscfg.enable_peripheral_clock(PeripheralSelect::Watchdog); + // It's done like that in Vorago examples. Not exactly sure why the reset is necessary + // though.. + syscfg.assert_periph_reset(PeripheralSelect::Watchdog); + cortex_m::asm::nop(); + cortex_m::asm::nop(); + syscfg.deassert_periph_reset(PeripheralSelect::Watchdog); + + let wdt_clock = clocks.apb2(); + let mut wdt_ctrl = Self { + clock_freq: wdt_clock, + wdt, + }; + wdt_ctrl.set_freq(wdt_freq_ms); + wdt_ctrl.wdt.wdogcontrol().write(|w| w.inten().set_bit()); + wdt_ctrl.feed(); + // Unmask the watchdog interrupt + unsafe { + enable_wdt_interrupts(); + } + wdt_ctrl + } + + #[inline] + pub fn set_freq(&mut self, freq_ms: u32) { + let counter = (self.clock_freq.raw() / 1000) * freq_ms; + self.wdt.wdogload().write(|w| unsafe { w.bits(counter) }); + } + + #[inline] + pub fn disable_reset(&mut self) { + self.wdt.wdogcontrol().modify(|_, w| w.resen().clear_bit()) + } + + #[inline] + pub fn enable_reset(&mut self) { + self.wdt.wdogcontrol().modify(|_, w| w.resen().set_bit()) + } + + #[inline] + pub fn counter(&self) -> u32 { + self.wdt.wdogvalue().read().bits() + } + + #[inline] + pub fn feed(&self) { + self.wdt.wdogintclr().write(|w| unsafe { w.bits(1) }); + } + + #[inline] + pub fn lock(&self) { + self.wdt.wdoglock().write(|w| unsafe { w.bits(0) }); + } + + #[inline] + pub fn unlock(&self) { + self.wdt + .wdoglock() + .write(|w| unsafe { w.bits(WDT_UNLOCK_VALUE) }); + } + + #[inline] + pub fn is_locked(&self) -> bool { + self.wdt.wdogload().read().bits() == 1 + } +} diff --git a/va416xx/.github/bors.toml b/va416xx/.github/bors.toml new file mode 100644 index 0000000..1779788 --- /dev/null +++ b/va416xx/.github/bors.toml @@ -0,0 +1,2 @@ +status = ["ci"] +delete_merged_branches = true diff --git a/va416xx/.github/workflows/changelog.yml b/va416xx/.github/workflows/changelog.yml new file mode 100644 index 0000000..dbba297 --- /dev/null +++ b/va416xx/.github/workflows/changelog.yml @@ -0,0 +1,20 @@ +on: + pull_request_target: + +name: Changelog check + +jobs: + changelog: + name: Changelog check + runs-on: ubuntu-latest + steps: + - name: Checkout sources + uses: actions/checkout@v2 + + - name: Changelog updated + uses: Zomzog/changelog-checker@v1.2.0 + with: + fileName: CHANGELOG.md + noChangelogLabel: no changelog + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} diff --git a/va416xx/.github/workflows/ci.yml b/va416xx/.github/workflows/ci.yml new file mode 100644 index 0000000..63cf53c --- /dev/null +++ b/va416xx/.github/workflows/ci.yml @@ -0,0 +1,64 @@ +on: [push] + +name: build + +jobs: + check: + name: Check + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + target: thumbv7em-none-eabihf + override: true + - uses: actions-rs/cargo@v1 + with: + use-cross: true + command: check + args: --target thumbv7em-none-eabihf + + fmt: + name: Rustfmt + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + override: true + - run: rustup component add rustfmt + - uses: actions-rs/cargo@v1 + with: + command: fmt + args: --all -- --check + + clippy: + name: Clippy + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: actions-rs/toolchain@v1 + with: + profile: minimal + toolchain: stable + target: thumbv7em-none-eabihf + override: true + - run: rustup component add clippy + - uses: actions-rs/cargo@v1 + with: + use-cross: true + command: clippy + args: --target thumbv7em-none-eabihf -- -D warnings + + ci: + if: ${{ success() }} + # all new jobs must be added to this list + needs: [check, fmt, clippy] + runs-on: ubuntu-latest + steps: + - name: CI succeeded + run: exit 0 \ No newline at end of file diff --git a/va416xx/.gitignore b/va416xx/.gitignore new file mode 100644 index 0000000..96ef6c0 --- /dev/null +++ b/va416xx/.gitignore @@ -0,0 +1,2 @@ +/target +Cargo.lock diff --git a/va416xx/CHANGELOG.md b/va416xx/CHANGELOG.md new file mode 100644 index 0000000..5a08cf4 --- /dev/null +++ b/va416xx/CHANGELOG.md @@ -0,0 +1,21 @@ +Change Log +======= + +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/) +and this project adheres to [Semantic Versioning](http://semver.org/). + +## [unreleased] + +## [v0.1.1] + +- Clippy issue fixed by regenerating PAC with patched `svd2rust`: + https://github.com/rust-embedded/svd2rust/pull/558 + +## [v0.1.0] + +- Clippy currently complains about unsound code which should still work. + Related issue: https://github.com/rust-embedded/svd2rust/issues/557 + Clippy is disabled in CI/CD for now. +- Initial release diff --git a/va416xx/Cargo.toml b/va416xx/Cargo.toml new file mode 100644 index 0000000..c33a564 --- /dev/null +++ b/va416xx/Cargo.toml @@ -0,0 +1,29 @@ +[package] +name = "va416xx" +version = "0.1.1" +authors = ["Robin Mueller "] +edition = "2021" +description = "PAC for the Vorago VA416xx family of MCUs" +homepage = "https://egit.irs.uni-stuttgart.de/rust/va416xx" +repository = "https://egit.irs.uni-stuttgart.de/rust/va416xx" +license = "Apache-2.0" +keywords = ["no-std", "arm", "cortex-m", "vorago", "va416xx"] +categories = ["embedded", "no-std", "hardware-support"] + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +cortex-m = "0.7" +vcell = "0.1.3" +critical-section = { version = "1", optional = true } + +[dependencies.cortex-m-rt] +optional = true +version = ">=0.6.15,<0.8" + +[features] +rt = ["cortex-m-rt/device"] + +[package.metadata.docs.rs] +all-features = true +rustdoc-args = ["--generate-link-to-definition"] diff --git a/va416xx/LICENSE-APACHE b/va416xx/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/va416xx/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + +4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/va416xx/NOTICE b/va416xx/NOTICE new file mode 100644 index 0000000..321b896 --- /dev/null +++ b/va416xx/NOTICE @@ -0,0 +1,3 @@ +Rust Peripheral Access Crate (PAC) crate for the Vorago VA416xx family of MCUs + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/va416xx/README.md b/va416xx/README.md new file mode 100644 index 0000000..0737264 --- /dev/null +++ b/va416xx/README.md @@ -0,0 +1,58 @@ +[![Crates.io](https://img.shields.io/crates/v/va416xx)](https://crates.io/crates/va416xx) +[![docs.rs](https://img.shields.io/docsrs/va416xx)](https://docs.rs/va416xx) + +# PAC for the Vorago VA416xx microcontroller family + +This repository contains the Peripheral Access Crate (PAC) for +Voragos VA416xx series of Cortex-M4 based microcontrollers. + +The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust). + +## Usage + +To use this crate, add this to your `Cargo.toml` + +```toml +[dependencies.va416xx] +version = "" +features = ["rt"] +``` + +The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`. + +For full details on the autgenerated API, you can read the +[svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/). + +## Regenerating the PAC + +If you want to re-generate the PAC, for example if the register file `va416xx.svd` changes +or the `svd2rust` version is updated, you can do some using the following these steps: + +1. Make sure all necessary tools are installed: [`svd2rust`](https://docs.rs/svd2rust/latest/svd2rust/), + [`svdtools`](https://github.com/rust-embedded/svdtools) and [`form`](https://crates.io/crates/form). + You can install all tools with `cargo`: + + ```sh + cargo install --locked svd2rust svdtools form + ``` + +2. Patch the vendor-provided SVD file `svd/va41xx.svd`. This can be done using `svdtools` in + conjunction with the `svd/va416xx-patch.yml` file. + + ```sh + svdtools patch svd/va416xx-patch.yml + ``` + +3. Use `svd2rust` to generate the Rust library + + ```sh + svd2rust -i svd/va416xx.svd.patched + ``` + +4. Use the `form` tool to split the generated `lib.rs` into individual modules. + + ```sh + form -i lib.rs -o src/ + ``` + +The `gen-helper.sh` automates steps 2-4. diff --git a/va416xx/automation/Dockerfile b/va416xx/automation/Dockerfile new file mode 100644 index 0000000..b9a76c6 --- /dev/null +++ b/va416xx/automation/Dockerfile @@ -0,0 +1,11 @@ +# Run the following commands from root directory to build and run locally +# docker build -f automation/Dockerfile -t . +# docker run -it +FROM rust:latest +RUN apt-get update +RUN apt-get --yes upgrade +# tzdata is a dependency, won't install otherwise +ARG DEBIAN_FRONTEND=noninteractive + +RUN rustup target add thumbv7em-none-eabihf && \ + rustup component add rustfmt clippy diff --git a/va416xx/automation/Jenkinsfile b/va416xx/automation/Jenkinsfile new file mode 100644 index 0000000..925c94e --- /dev/null +++ b/va416xx/automation/Jenkinsfile @@ -0,0 +1,39 @@ +pipeline { + agent any + + stages { + stage('Clippy') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo clippy' + } + } + stage('Rustfmt') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo fmt' + } + } + stage('Check') { + agent { + dockerfile { + dir 'automation' + reuseNode true + } + } + steps { + sh 'cargo check --target thumbv7em-none-eabihf' + } + } + } +} \ No newline at end of file diff --git a/va416xx/build.rs b/va416xx/build.rs new file mode 100644 index 0000000..d0781ac --- /dev/null +++ b/va416xx/build.rs @@ -0,0 +1,17 @@ +#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/va416xx/device.x b/va416xx/device.x new file mode 100644 index 0000000..983fc7c --- /dev/null +++ b/va416xx/device.x @@ -0,0 +1,197 @@ +PROVIDE(U0 = DefaultHandler); +PROVIDE(U1 = DefaultHandler); +PROVIDE(U2 = DefaultHandler); +PROVIDE(U3 = DefaultHandler); +PROVIDE(U4 = DefaultHandler); +PROVIDE(U5 = DefaultHandler); +PROVIDE(U6 = DefaultHandler); +PROVIDE(U7 = DefaultHandler); +PROVIDE(U8 = DefaultHandler); +PROVIDE(U9 = DefaultHandler); +PROVIDE(U10 = DefaultHandler); +PROVIDE(U11 = DefaultHandler); +PROVIDE(U12 = DefaultHandler); +PROVIDE(U13 = DefaultHandler); +PROVIDE(U14 = DefaultHandler); +PROVIDE(U15 = DefaultHandler); +PROVIDE(SPI0_TX = DefaultHandler); +PROVIDE(SPI0_RX = DefaultHandler); +PROVIDE(SPI1_TX = DefaultHandler); +PROVIDE(SPI1_RX = DefaultHandler); +PROVIDE(SPI2_TX = DefaultHandler); +PROVIDE(SPI2_RX = DefaultHandler); +PROVIDE(SPI3_TX = DefaultHandler); +PROVIDE(SPI3_RX = DefaultHandler); +PROVIDE(UART0_TX = DefaultHandler); +PROVIDE(UART0_RX = DefaultHandler); +PROVIDE(UART1_TX = DefaultHandler); +PROVIDE(UART1_RX = DefaultHandler); +PROVIDE(UART2_TX = DefaultHandler); +PROVIDE(UART2_RX = DefaultHandler); +PROVIDE(I2C0_MS = DefaultHandler); +PROVIDE(I2C0_SL = DefaultHandler); +PROVIDE(I2C1_MS = DefaultHandler); +PROVIDE(I2C1_SL = DefaultHandler); +PROVIDE(I2C2_MS = DefaultHandler); +PROVIDE(I2C2_SL = DefaultHandler); +PROVIDE(Ethernet = DefaultHandler); +PROVIDE(U37 = DefaultHandler); +PROVIDE(SpW = DefaultHandler); +PROVIDE(U39 = DefaultHandler); +PROVIDE(DAC0 = DefaultHandler); +PROVIDE(DAC1 = DefaultHandler); +PROVIDE(TRNG = DefaultHandler); +PROVIDE(DMA_ERROR = DefaultHandler); +PROVIDE(ADC = DefaultHandler); +PROVIDE(LoCLK = DefaultHandler); +PROVIDE(LVD = DefaultHandler); +PROVIDE(WATCHDOG = DefaultHandler); +PROVIDE(TIM0 = DefaultHandler); +PROVIDE(TIM1 = DefaultHandler); +PROVIDE(TIM2 = DefaultHandler); +PROVIDE(TIM3 = DefaultHandler); +PROVIDE(TIM4 = DefaultHandler); +PROVIDE(TIM5 = DefaultHandler); +PROVIDE(TIM6 = DefaultHandler); +PROVIDE(TIM7 = DefaultHandler); +PROVIDE(TIM8 = DefaultHandler); +PROVIDE(TIM9 = DefaultHandler); +PROVIDE(TIM10 = DefaultHandler); +PROVIDE(TIM11 = DefaultHandler); +PROVIDE(TIM12 = DefaultHandler); +PROVIDE(TIM13 = DefaultHandler); +PROVIDE(TIM14 = DefaultHandler); +PROVIDE(TIM15 = DefaultHandler); +PROVIDE(TIM16 = DefaultHandler); +PROVIDE(TIM17 = DefaultHandler); +PROVIDE(TIM18 = DefaultHandler); +PROVIDE(TIM19 = DefaultHandler); +PROVIDE(TIM20 = DefaultHandler); +PROVIDE(TIM21 = DefaultHandler); +PROVIDE(TIM22 = DefaultHandler); +PROVIDE(TIM23 = DefaultHandler); +PROVIDE(CAN0 = DefaultHandler); +PROVIDE(U73 = DefaultHandler); +PROVIDE(CAN1 = DefaultHandler); +PROVIDE(U75 = DefaultHandler); +PROVIDE(EDAC_MBE = DefaultHandler); +PROVIDE(EDAC_SBE = DefaultHandler); +PROVIDE(PORTA0 = DefaultHandler); +PROVIDE(PORTA1 = DefaultHandler); +PROVIDE(PORTA2 = DefaultHandler); +PROVIDE(PORTA3 = DefaultHandler); +PROVIDE(PORTA4 = DefaultHandler); +PROVIDE(PORTA5 = DefaultHandler); +PROVIDE(PORTA6 = DefaultHandler); +PROVIDE(PORTA7 = DefaultHandler); +PROVIDE(PORTA8 = DefaultHandler); +PROVIDE(PORTA9 = DefaultHandler); +PROVIDE(PORTA10 = DefaultHandler); +PROVIDE(PORTA11 = DefaultHandler); +PROVIDE(PORTA12 = DefaultHandler); +PROVIDE(PORTA13 = DefaultHandler); +PROVIDE(PORTA14 = DefaultHandler); +PROVIDE(PORTA15 = DefaultHandler); +PROVIDE(PORTB0 = DefaultHandler); +PROVIDE(PORTB1 = DefaultHandler); +PROVIDE(PORTB2 = DefaultHandler); +PROVIDE(PORTB3 = DefaultHandler); +PROVIDE(PORTB4 = DefaultHandler); +PROVIDE(PORTB5 = DefaultHandler); +PROVIDE(PORTB6 = DefaultHandler); +PROVIDE(PORTB7 = DefaultHandler); +PROVIDE(PORTB8 = DefaultHandler); +PROVIDE(PORTB9 = DefaultHandler); +PROVIDE(PORTB10 = DefaultHandler); +PROVIDE(PORTB11 = DefaultHandler); +PROVIDE(PORTB12 = DefaultHandler); +PROVIDE(PORTB13 = DefaultHandler); +PROVIDE(PORTB14 = DefaultHandler); +PROVIDE(PORTB15 = DefaultHandler); +PROVIDE(PORTC0 = DefaultHandler); +PROVIDE(PORTC1 = DefaultHandler); +PROVIDE(PORTC2 = DefaultHandler); +PROVIDE(PORTC3 = DefaultHandler); +PROVIDE(PORTC4 = DefaultHandler); +PROVIDE(PORTC5 = DefaultHandler); +PROVIDE(PORTC6 = DefaultHandler); +PROVIDE(PORTC7 = DefaultHandler); +PROVIDE(PORTC8 = DefaultHandler); +PROVIDE(PORTC9 = DefaultHandler); +PROVIDE(PORTC10 = DefaultHandler); +PROVIDE(PORTC11 = DefaultHandler); +PROVIDE(PORTC12 = DefaultHandler); +PROVIDE(PORTC13 = DefaultHandler); +PROVIDE(PORTC14 = DefaultHandler); +PROVIDE(PORTC15 = DefaultHandler); +PROVIDE(PORTD0 = DefaultHandler); +PROVIDE(PORTD1 = DefaultHandler); +PROVIDE(PORTD2 = DefaultHandler); +PROVIDE(PORTD3 = DefaultHandler); +PROVIDE(PORTD4 = DefaultHandler); +PROVIDE(PORTD5 = DefaultHandler); +PROVIDE(PORTD6 = DefaultHandler); +PROVIDE(PORTD7 = DefaultHandler); +PROVIDE(PORTD8 = DefaultHandler); +PROVIDE(PORTD9 = DefaultHandler); +PROVIDE(PORTD10 = DefaultHandler); +PROVIDE(PORTD11 = DefaultHandler); +PROVIDE(PORTD12 = DefaultHandler); +PROVIDE(PORTD13 = DefaultHandler); +PROVIDE(PORTD14 = DefaultHandler); +PROVIDE(PORTD15 = DefaultHandler); +PROVIDE(PORTE0 = DefaultHandler); +PROVIDE(PORTE1 = DefaultHandler); +PROVIDE(PORTE2 = DefaultHandler); +PROVIDE(PORTE3 = DefaultHandler); +PROVIDE(PORTE4 = DefaultHandler); +PROVIDE(PORTE5 = DefaultHandler); +PROVIDE(PORTE6 = DefaultHandler); +PROVIDE(PORTE7 = DefaultHandler); +PROVIDE(PORTE8 = DefaultHandler); +PROVIDE(PORTE9 = DefaultHandler); +PROVIDE(PORTE10 = DefaultHandler); +PROVIDE(PORTE11 = DefaultHandler); +PROVIDE(PORTE12 = DefaultHandler); +PROVIDE(PORTE13 = DefaultHandler); +PROVIDE(PORTE14 = DefaultHandler); +PROVIDE(PORTE15 = DefaultHandler); +PROVIDE(PORTF0 = DefaultHandler); +PROVIDE(PORTF1 = DefaultHandler); +PROVIDE(PORTF2 = DefaultHandler); +PROVIDE(PORTF3 = DefaultHandler); +PROVIDE(PORTF4 = DefaultHandler); +PROVIDE(PORTF5 = DefaultHandler); +PROVIDE(PORTF6 = DefaultHandler); +PROVIDE(PORTF7 = DefaultHandler); +PROVIDE(PORTF8 = DefaultHandler); +PROVIDE(PORTF9 = DefaultHandler); +PROVIDE(PORTF10 = DefaultHandler); +PROVIDE(PORTF11 = DefaultHandler); +PROVIDE(PORTF12 = DefaultHandler); +PROVIDE(PORTF13 = DefaultHandler); +PROVIDE(PORTF14 = DefaultHandler); +PROVIDE(PORTF15 = DefaultHandler); +PROVIDE(DMA_ACTIVE0 = DefaultHandler); +PROVIDE(DMA_ACTIVE1 = DefaultHandler); +PROVIDE(DMA_ACTIVE2 = DefaultHandler); +PROVIDE(DMA_ACTIVE3 = DefaultHandler); +PROVIDE(DMA_DONE0 = DefaultHandler); +PROVIDE(DMA_DONE1 = DefaultHandler); +PROVIDE(DMA_DONE2 = DefaultHandler); +PROVIDE(DMA_DONE3 = DefaultHandler); +PROVIDE(I2C0_MS_RX = DefaultHandler); +PROVIDE(I2C0_MS_TX = DefaultHandler); +PROVIDE(I2C0_SL_RX = DefaultHandler); +PROVIDE(I2C0_SL_TX = DefaultHandler); +PROVIDE(I2C1_MS_RX = DefaultHandler); +PROVIDE(I2C1_MS_TX = DefaultHandler); +PROVIDE(I2C1_SL_RX = DefaultHandler); +PROVIDE(I2C1_SL_TX = DefaultHandler); +PROVIDE(I2C2_MS_RX = DefaultHandler); +PROVIDE(I2C2_MS_TX = DefaultHandler); +PROVIDE(I2C2_SL_RX = DefaultHandler); +PROVIDE(I2C2_SL_TX = DefaultHandler); +PROVIDE(FPU = DefaultHandler); +PROVIDE(TXEV = DefaultHandler); + diff --git a/va416xx/gen-helper.sh b/va416xx/gen-helper.sh new file mode 100755 index 0000000..60a9a59 --- /dev/null +++ b/va416xx/gen-helper.sh @@ -0,0 +1,42 @@ +#!/bin/sh + +# Use installed tool by default +svd2rust_bin="svd2rust" +# Automates the steps specified in https://docs.rs/svd2rust/0.19.0/svd2rust/ +if [ -f svd2rust ]; then + # If the local directory contains svd2rust, use that version instead + svd2rust_bin="./svd2rust" +elif [ -f ../svd2rust ]; then + # Keeps the repository clean + svd2rust_bin="../svd2rust" +fi +if [ -x "$(${svd2rust_bin} --version)" ]; then + echo "No svd2rust found locally or installed." \ + "Install it with cargo install svd2rust" + exit +fi + +if ! command -v form &> /dev/null +then + echo "form tool was not found" + exit 1 +fi + +if ! command -v svdtools &> /dev/null +then + echo "svdtools was not found" + exit 1 +fi + +svdtools patch svd/va416xx-patch.yml +${svd2rust_bin} --reexport-interrupt -i svd/va416xx.svd.patched + +result=$? +if [ $result -ne 0 ]; then + echo "svd2rust failed with code $result" + exit +fi + +rm -rf src +form -i lib.rs -o src/ && rm lib.rs +cargo fmt diff --git a/va416xx/src/adc.rs b/va416xx/src/adc.rs new file mode 100644 index 0000000..b5d9d91 --- /dev/null +++ b/va416xx/src/adc.rs @@ -0,0 +1,127 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + fifo_data: FifoData, + status: Status, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + fifo_clr: FifoClr, + _reserved9: [u8; 0x0fd8], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - FIFO data"] + #[inline(always)] + pub const fn fifo_data(&self) -> &FifoData { + &self.fifo_data + } + #[doc = "0x08 - Status"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x0c - Interrupt Enable"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x10 - Raw Interrupt Status"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x14 - Enabled Interrupt Status"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x18 - Clear Interrupt"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x1c - Receive FIFO Interrupt Trigger Value"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x20 - FIFO Clear"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] +module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "FIFO_DATA (r) register accessor: FIFO data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_data`] +module"] +#[doc(alias = "FIFO_DATA")] +pub type FifoData = crate::Reg; +#[doc = "FIFO data"] +pub mod fifo_data; +#[doc = "STATUS (r) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] +module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] +module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod irq_enb; +#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] +module"] +#[doc(alias = "IRQ_RAW")] +pub type IrqRaw = crate::Reg; +#[doc = "Raw Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END (r) register accessor: Enabled Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] +module"] +#[doc(alias = "IRQ_END")] +pub type IrqEnd = crate::Reg; +#[doc = "Enabled Interrupt Status"] +pub mod irq_end; +#[doc = "IRQ_CLR (w) register accessor: Clear Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_clr`] +module"] +#[doc(alias = "IRQ_CLR")] +pub type IrqClr = crate::Reg; +#[doc = "Clear Interrupt"] +pub mod irq_clr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] +module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Receive FIFO Interrupt Trigger Value"] +pub mod rxfifoirqtrg; +#[doc = "FIFO_CLR (rw) register accessor: FIFO Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] +module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "FIFO Clear"] +pub mod fifo_clr; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/adc/ctrl.rs b/va416xx/src/adc/ctrl.rs new file mode 100644 index 0000000..4fce290 --- /dev/null +++ b/va416xx/src/adc/ctrl.rs @@ -0,0 +1,115 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CHAN_EN` reader - Enables the channel for data collection"] +pub type ChanEnR = crate::FieldReader; +#[doc = "Field `CHAN_EN` writer - Enables the channel for data collection"] +pub type ChanEnW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `CHAN_TAG_EN` reader - Enables the channel tag to be saved with the ADC data"] +pub type ChanTagEnR = crate::BitReader; +#[doc = "Field `CHAN_TAG_EN` writer - Enables the channel tag to be saved with the ADC data"] +pub type ChanTagEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SWEEP_EN` reader - ADC data acquisition for all enabled channel"] +pub type SweepEnR = crate::BitReader; +#[doc = "Field `SWEEP_EN` writer - ADC data acquisition for all enabled channel"] +pub type SweepEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXT_TRIG_EN` reader - Allows the external trigger to start analog acquisition"] +pub type ExtTrigEnR = crate::BitReader; +#[doc = "Field `EXT_TRIG_EN` writer - Allows the external trigger to start analog acquisition"] +pub type ExtTrigEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MANUAL_TRIG` reader - Starts analog acquisition"] +pub type ManualTrigR = crate::BitReader; +#[doc = "Field `MANUAL_TRIG` writer - Starts analog acquisition"] +pub type ManualTrigW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CONV_CNT` reader - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] +pub type ConvCntR = crate::FieldReader; +#[doc = "Field `CONV_CNT` writer - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] +pub type ConvCntW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:15 - Enables the channel for data collection"] + #[inline(always)] + pub fn chan_en(&self) -> ChanEnR { + ChanEnR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"] + #[inline(always)] + pub fn chan_tag_en(&self) -> ChanTagEnR { + ChanTagEnR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - ADC data acquisition for all enabled channel"] + #[inline(always)] + pub fn sweep_en(&self) -> SweepEnR { + SweepEnR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Allows the external trigger to start analog acquisition"] + #[inline(always)] + pub fn ext_trig_en(&self) -> ExtTrigEnR { + ExtTrigEnR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Starts analog acquisition"] + #[inline(always)] + pub fn manual_trig(&self) -> ManualTrigR { + ManualTrigR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] + #[inline(always)] + pub fn conv_cnt(&self) -> ConvCntR { + ConvCntR::new(((self.bits >> 20) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Enables the channel for data collection"] + #[inline(always)] + #[must_use] + pub fn chan_en(&mut self) -> ChanEnW { + ChanEnW::new(self, 0) + } + #[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"] + #[inline(always)] + #[must_use] + pub fn chan_tag_en(&mut self) -> ChanTagEnW { + ChanTagEnW::new(self, 16) + } + #[doc = "Bit 17 - ADC data acquisition for all enabled channel"] + #[inline(always)] + #[must_use] + pub fn sweep_en(&mut self) -> SweepEnW { + SweepEnW::new(self, 17) + } + #[doc = "Bit 18 - Allows the external trigger to start analog acquisition"] + #[inline(always)] + #[must_use] + pub fn ext_trig_en(&mut self) -> ExtTrigEnW { + ExtTrigEnW::new(self, 18) + } + #[doc = "Bit 19 - Starts analog acquisition"] + #[inline(always)] + #[must_use] + pub fn manual_trig(&mut self) -> ManualTrigW { + ManualTrigW::new(self, 19) + } + #[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"] + #[inline(always)] + #[must_use] + pub fn conv_cnt(&mut self) -> ConvCntW { + ConvCntW::new(self, 20) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/adc/fifo_clr.rs b/va416xx/src/adc/fifo_clr.rs new file mode 100644 index 0000000..d3f8ab8 --- /dev/null +++ b/va416xx/src/adc/fifo_clr.rs @@ -0,0 +1,31 @@ +#[doc = "Register `FIFO_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_CLR` writer - Clears the ADC FIFO. Always reads 0"] +pub type FifoClrW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clears the ADC FIFO. Always reads 0"] + #[inline(always)] + #[must_use] + pub fn fifo_clr(&mut self) -> FifoClrW { + FifoClrW::new(self, 0) + } +} +#[doc = "FIFO Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_clr::R`](R) reader structure"] +impl crate::Readable for FifoClrSpec {} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/adc/fifo_data.rs b/va416xx/src/adc/fifo_data.rs new file mode 100644 index 0000000..b4722b4 --- /dev/null +++ b/va416xx/src/adc/fifo_data.rs @@ -0,0 +1,29 @@ +#[doc = "Register `FIFO_DATA` reader"] +pub type R = crate::R; +#[doc = "Field `ADC_DATA` reader - ADC acquisition data from the FIFO"] +pub type AdcDataR = crate::FieldReader; +#[doc = "Field `CHAN_TAG` reader - If enabled, this will include the number of the channel corresponding to the measurement"] +pub type ChanTagR = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - ADC acquisition data from the FIFO"] + #[inline(always)] + pub fn adc_data(&self) -> AdcDataR { + AdcDataR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:15 - If enabled, this will include the number of the channel corresponding to the measurement"] + #[inline(always)] + pub fn chan_tag(&self) -> ChanTagR { + ChanTagR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +#[doc = "FIFO data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoDataSpec; +impl crate::RegisterSpec for FifoDataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_data::R`](R) reader structure"] +impl crate::Readable for FifoDataSpec {} +#[doc = "`reset()` method sets FIFO_DATA to value 0"] +impl crate::Resettable for FifoDataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/adc/irq_clr.rs b/va416xx/src/adc/irq_clr.rs new file mode 100644 index 0000000..5efb9b7 --- /dev/null +++ b/va416xx/src/adc/irq_clr.rs @@ -0,0 +1,51 @@ +#[doc = "Register `IRQ_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_OFLOW` writer - Clears the FIFO overflow interrupt status. Always reads 0"] +pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_UFLOW` writer - Clears the FIFO underflow interrupt status. Always reads 0"] +pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_DONE` writer - Clears the ADC done interrupt status. Always reads 0"] +pub type AdcDoneW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRIG_ERROR` writer - Clears the trigger error interrupt status. Always reads 0"] +pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clears the FIFO overflow interrupt status. Always reads 0"] + #[inline(always)] + #[must_use] + pub fn fifo_oflow(&mut self) -> FifoOflowW { + FifoOflowW::new(self, 0) + } + #[doc = "Bit 1 - Clears the FIFO underflow interrupt status. Always reads 0"] + #[inline(always)] + #[must_use] + pub fn fifo_uflow(&mut self) -> FifoUflowW { + FifoUflowW::new(self, 1) + } + #[doc = "Bit 2 - Clears the ADC done interrupt status. Always reads 0"] + #[inline(always)] + #[must_use] + pub fn adc_done(&mut self) -> AdcDoneW { + AdcDoneW::new(self, 2) + } + #[doc = "Bit 3 - Clears the trigger error interrupt status. Always reads 0"] + #[inline(always)] + #[must_use] + pub fn trig_error(&mut self) -> TrigErrorW { + TrigErrorW::new(self, 3) + } +} +#[doc = "Clear Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqClrSpec; +impl crate::RegisterSpec for IrqClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`irq_clr::W`](W) writer structure"] +impl crate::Writable for IrqClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_CLR to value 0"] +impl crate::Resettable for IrqClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/adc/irq_enb.rs b/va416xx/src/adc/irq_enb.rs new file mode 100644 index 0000000..2f5221e --- /dev/null +++ b/va416xx/src/adc/irq_enb.rs @@ -0,0 +1,130 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"] +pub type FifoEmptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"] +pub type FifoFullW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"] +pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"] +pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_DONE` reader - Enables the interrupt for an ADC data acquisition completion"] +pub type AdcDoneR = crate::BitReader; +#[doc = "Field `ADC_DONE` writer - Enables the interrupt for an ADC data acquisition completion"] +pub type AdcDoneW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"] +pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub type FifoDepthTrigR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub type FifoDepthTrigW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"] + #[inline(always)] + pub fn adc_done(&self) -> AdcDoneR { + AdcDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + #[must_use] + pub fn fifo_empty(&mut self) -> FifoEmptyW { + FifoEmptyW::new(self, 0) + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + #[must_use] + pub fn fifo_full(&mut self) -> FifoFullW { + FifoFullW::new(self, 1) + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + #[must_use] + pub fn fifo_oflow(&mut self) -> FifoOflowW { + FifoOflowW::new(self, 2) + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + #[must_use] + pub fn fifo_uflow(&mut self) -> FifoUflowW { + FifoUflowW::new(self, 3) + } + #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"] + #[inline(always)] + #[must_use] + pub fn adc_done(&mut self) -> AdcDoneW { + AdcDoneW::new(self, 4) + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + #[must_use] + pub fn trig_error(&mut self) -> TrigErrorW { + TrigErrorW::new(self, 5) + } + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + #[must_use] + pub fn fifo_depth_trig(&mut self) -> FifoDepthTrigW { + FifoDepthTrigW::new(self, 6) + } +} +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/adc/irq_end.rs b/va416xx/src/adc/irq_end.rs new file mode 100644 index 0000000..b581ede --- /dev/null +++ b/va416xx/src/adc/irq_end.rs @@ -0,0 +1,64 @@ +#[doc = "Register `IRQ_END` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty and the interrupt is enabled"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full and the interrupt is enabled"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred and the interrupt is enabled"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` reader - Indicates a FIFO underflow occurred and the interrupt is enabled"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `ADC_DONE` reader - Indicates that a ADC conversion is done and the interrupt is enabled"] +pub type AdcDoneR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub type FifoDepthTrigR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates the FIFO is empty and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates a FIFO underflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates that a ADC conversion is done and the interrupt is enabled"] + #[inline(always)] + pub fn adc_done(&self) -> AdcDoneR { + AdcDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "Enabled Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEndSpec; +impl crate::RegisterSpec for IrqEndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"] +impl crate::Readable for IrqEndSpec {} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IrqEndSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/adc/irq_raw.rs b/va416xx/src/adc/irq_raw.rs new file mode 100644 index 0000000..04ce1a3 --- /dev/null +++ b/va416xx/src/adc/irq_raw.rs @@ -0,0 +1,64 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` reader - Indicates data was unavailable when a new trigger for ADC update is received"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `ADC_DONE` reader - Indicates that a ADC conversion is done"] +pub type AdcDoneR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] +pub type FifoDepthTrigR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates the FIFO is empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates data was unavailable when a new trigger for ADC update is received"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates that a ADC conversion is done"] + #[inline(always)] + pub fn adc_done(&self) -> AdcDoneR { + AdcDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqRawSpec; +impl crate::RegisterSpec for IrqRawSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"] +impl crate::Readable for IrqRawSpec {} +#[doc = "`reset()` method sets IRQ_RAW to value 0x01"] +impl crate::Resettable for IrqRawSpec { + const RESET_VALUE: u32 = 0x01; +} diff --git a/va416xx/src/adc/perid.rs b/va416xx/src/adc/perid.rs new file mode 100644 index 0000000..d1a0f97 --- /dev/null +++ b/va416xx/src/adc/perid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0019_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0019_07e9; +} diff --git a/va416xx/src/adc/rxfifoirqtrg.rs b/va416xx/src/adc/rxfifoirqtrg.rs new file mode 100644 index 0000000..aa189b8 --- /dev/null +++ b/va416xx/src/adc/rxfifoirqtrg.rs @@ -0,0 +1,40 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[doc = "Field `LEVEL` reader - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub type LevelR = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + pub fn level(&self) -> LevelR { + LevelR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + #[must_use] + pub fn level(&mut self) -> LevelW { + LevelW::new(self, 0) + } +} +#[doc = "Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0x10"] +impl crate::Resettable for RxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0x10; +} diff --git a/va416xx/src/adc/status.rs b/va416xx/src/adc/status.rs new file mode 100644 index 0000000..bda6875 --- /dev/null +++ b/va416xx/src/adc/status.rs @@ -0,0 +1,29 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_ENTRY_CNT` reader - Indicates the number of entries in the FIFO"] +pub type FifoEntryCntR = crate::FieldReader; +#[doc = "Field `ADC_BUSY` reader - Indicates an ADC data acquisition is in process"] +pub type AdcBusyR = crate::BitReader; +impl R { + #[doc = "Bits 0:5 - Indicates the number of entries in the FIFO"] + #[inline(always)] + pub fn fifo_entry_cnt(&self) -> FifoEntryCntR { + FifoEntryCntR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Indicates an ADC data acquisition is in process"] + #[inline(always)] + pub fn adc_busy(&self) -> AdcBusyR { + AdcBusyR::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0.rs b/va416xx/src/can0.rs new file mode 100644 index 0000000..894adbb --- /dev/null +++ b/va416xx/src/can0.rs @@ -0,0 +1,1710 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + cnstat_cmb0: CnstatCmb0, + tstp_cmb0: TstpCmb0, + data3_cmb0: Data3Cmb0, + data2_cmb0: Data2Cmb0, + data1_cmb0: Data1Cmb0, + data0_cmb0: Data0Cmb0, + id0_cmb0: Id0Cmb0, + id1_cmb0: Id1Cmb0, + cnstat_cmb1: CnstatCmb1, + tstp_cmb1: TstpCmb1, + data3_cmb1: Data3Cmb1, + data2_cmb1: Data2Cmb1, + data1_cmb1: Data1Cmb1, + data0_cmb1: Data0Cmb1, + id0_cmb1: Id0Cmb1, + id1_cmb1: Id1Cmb1, + cnstat_cmb2: CnstatCmb2, + tstp_cmb2: TstpCmb2, + data3_cmb2: Data3Cmb2, + data2_cmb2: Data2Cmb2, + data1_cmb2: Data1Cmb2, + data0_cmb2: Data0Cmb2, + id0_cmb2: Id0Cmb2, + id1_cmb2: Id1Cmb2, + cnstat_cmb3: CnstatCmb3, + tstp_cmb3: TstpCmb3, + data3_cmb3: Data3Cmb3, + data2_cmb3: Data2Cmb3, + data1_cmb3: Data1Cmb3, + data0_cmb3: Data0Cmb3, + id0_cmb3: Id0Cmb3, + id1_cmb3: Id1Cmb3, + cnstat_cmb4: CnstatCmb4, + tstp_cmb4: TstpCmb4, + data3_cmb4: Data3Cmb4, + data2_cmb4: Data2Cmb4, + data1_cmb4: Data1Cmb4, + data0_cmb4: Data0Cmb4, + id0_cmb4: Id0Cmb4, + id1_cmb4: Id1Cmb4, + cnstat_cmb5: CnstatCmb5, + tstp_cmb5: TstpCmb5, + data3_cmb5: Data3Cmb5, + data2_cmb5: Data2Cmb5, + data1_cmb5: Data1Cmb5, + data0_cmb5: Data0Cmb5, + id0_cmb5: Id0Cmb5, + id1_cmb5: Id1Cmb5, + cnstat_cmb6: CnstatCmb6, + tstp_cmb6: TstpCmb6, + data3_cmb6: Data3Cmb6, + data2_cmb6: Data2Cmb6, + data1_cmb6: Data1Cmb6, + data0_cmb6: Data0Cmb6, + id0_cmb6: Id0Cmb6, + id1_cmb6: Id1Cmb6, + cnstat_cmb7: CnstatCmb7, + tstp_cmb7: TstpCmb7, + data3_cmb7: Data3Cmb7, + data2_cmb7: Data2Cmb7, + data1_cmb7: Data1Cmb7, + data0_cmb7: Data0Cmb7, + id0_cmb7: Id0Cmb7, + id1_cmb7: Id1Cmb7, + cnstat_cmb8: CnstatCmb8, + tstp_cmb8: TstpCmb8, + data3_cmb8: Data3Cmb8, + data2_cmb8: Data2Cmb8, + data1_cmb8: Data1Cmb8, + data0_cmb8: Data0Cmb8, + id0_cmb8: Id0Cmb8, + id1_cmb8: Id1Cmb8, + cnstat_cmb9: CnstatCmb9, + tstp_cmb9: TstpCmb9, + data3_cmb9: Data3Cmb9, + data2_cmb9: Data2Cmb9, + data1_cmb9: Data1Cmb9, + data0_cmb9: Data0Cmb9, + id0_cmb9: Id0Cmb9, + id1_cmb9: Id1Cmb9, + cnstat_cmb10: CnstatCmb10, + tstp_cmb10: TstpCmb10, + data3_cmb10: Data3Cmb10, + data2_cmb10: Data2Cmb10, + data1_cmb10: Data1Cmb10, + data0_cmb10: Data0Cmb10, + id0_cmb10: Id0Cmb10, + id1_cmb10: Id1Cmb10, + cnstat_cmb11: CnstatCmb11, + tstp_cmb11: TstpCmb11, + data3_cmb11: Data3Cmb11, + data2_cmb11: Data2Cmb11, + data1_cmb11: Data1Cmb11, + data0_cmb11: Data0Cmb11, + id0_cmb11: Id0Cmb11, + id1_cmb11: Id1Cmb11, + cnstat_cmb12: CnstatCmb12, + tstp_cmb12: TstpCmb12, + data3_cmb12: Data3Cmb12, + data2_cmb12: Data2Cmb12, + data1_cmb12: Data1Cmb12, + data0_cmb12: Data0Cmb12, + id0_cmb12: Id0Cmb12, + id1_cmb12: Id1Cmb12, + cnstat_cmb13: CnstatCmb13, + tstp_cmb13: TstpCmb13, + data3_cmb13: Data3Cmb13, + data2_cmb13: Data2Cmb13, + data1_cmb13: Data1Cmb13, + data0_cmb13: Data0Cmb13, + id0_cmb13: Id0Cmb13, + id1_cmb13: Id1Cmb13, + cnstat_cmb14: CnstatCmb14, + tstp_cmb14: TstpCmb14, + data3_cmb14: Data3Cmb14, + data2_cmb14: Data2Cmb14, + data1_cmb14: Data1Cmb14, + data0_cmb14: Data0Cmb14, + id0_cmb14: Id0Cmb14, + id1_cmb14: Id1Cmb14, + cnstat_hcmb: CnstatHcmb, + tstp_hcmb: TstpHcmb, + data3_hcmb: Data3Hcmb, + data2_hcmb: Data2Hcmb, + data1_hcmb: Data1Hcmb, + data0_hcmb: Data0Hcmb, + id0_hcmb: Id0Hcmb, + id1_hcmb: Id1Hcmb, + cgcr: Cgcr, + ctim: Ctim, + gmskx: Gmskx, + gmskb: Gmskb, + bmskx: Bmskx, + bmskb: Bmskb, + cien: Cien, + cipnd: Cipnd, + ciclr: Ciclr, + cicen: Cicen, + cstpnd: Cstpnd, + canec: Canec, + cediag: Cediag, + ctmr: Ctmr, +} +impl RegisterBlock { + #[doc = "0x00 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb0(&self) -> &CnstatCmb0 { + &self.cnstat_cmb0 + } + #[doc = "0x04 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb0(&self) -> &TstpCmb0 { + &self.tstp_cmb0 + } + #[doc = "0x08 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb0(&self) -> &Data3Cmb0 { + &self.data3_cmb0 + } + #[doc = "0x0c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb0(&self) -> &Data2Cmb0 { + &self.data2_cmb0 + } + #[doc = "0x10 - CAN Frame Data Word 1"] + #[inline(always)] + pub const fn data1_cmb0(&self) -> &Data1Cmb0 { + &self.data1_cmb0 + } + #[doc = "0x14 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb0(&self) -> &Data0Cmb0 { + &self.data0_cmb0 + } + #[doc = "0x18 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb0(&self) -> &Id0Cmb0 { + &self.id0_cmb0 + } + #[doc = "0x1c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb0(&self) -> &Id1Cmb0 { + &self.id1_cmb0 + } + #[doc = "0x20 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb1(&self) -> &CnstatCmb1 { + &self.cnstat_cmb1 + } + #[doc = "0x24 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb1(&self) -> &TstpCmb1 { + &self.tstp_cmb1 + } + #[doc = "0x28 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb1(&self) -> &Data3Cmb1 { + &self.data3_cmb1 + } + #[doc = "0x2c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb1(&self) -> &Data2Cmb1 { + &self.data2_cmb1 + } + #[doc = "0x30 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb1(&self) -> &Data1Cmb1 { + &self.data1_cmb1 + } + #[doc = "0x34 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb1(&self) -> &Data0Cmb1 { + &self.data0_cmb1 + } + #[doc = "0x38 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb1(&self) -> &Id0Cmb1 { + &self.id0_cmb1 + } + #[doc = "0x3c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb1(&self) -> &Id1Cmb1 { + &self.id1_cmb1 + } + #[doc = "0x40 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb2(&self) -> &CnstatCmb2 { + &self.cnstat_cmb2 + } + #[doc = "0x44 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb2(&self) -> &TstpCmb2 { + &self.tstp_cmb2 + } + #[doc = "0x48 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb2(&self) -> &Data3Cmb2 { + &self.data3_cmb2 + } + #[doc = "0x4c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb2(&self) -> &Data2Cmb2 { + &self.data2_cmb2 + } + #[doc = "0x50 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb2(&self) -> &Data1Cmb2 { + &self.data1_cmb2 + } + #[doc = "0x54 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb2(&self) -> &Data0Cmb2 { + &self.data0_cmb2 + } + #[doc = "0x58 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb2(&self) -> &Id0Cmb2 { + &self.id0_cmb2 + } + #[doc = "0x5c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb2(&self) -> &Id1Cmb2 { + &self.id1_cmb2 + } + #[doc = "0x60 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb3(&self) -> &CnstatCmb3 { + &self.cnstat_cmb3 + } + #[doc = "0x64 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb3(&self) -> &TstpCmb3 { + &self.tstp_cmb3 + } + #[doc = "0x68 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb3(&self) -> &Data3Cmb3 { + &self.data3_cmb3 + } + #[doc = "0x6c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb3(&self) -> &Data2Cmb3 { + &self.data2_cmb3 + } + #[doc = "0x70 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb3(&self) -> &Data1Cmb3 { + &self.data1_cmb3 + } + #[doc = "0x74 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb3(&self) -> &Data0Cmb3 { + &self.data0_cmb3 + } + #[doc = "0x78 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb3(&self) -> &Id0Cmb3 { + &self.id0_cmb3 + } + #[doc = "0x7c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb3(&self) -> &Id1Cmb3 { + &self.id1_cmb3 + } + #[doc = "0x80 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb4(&self) -> &CnstatCmb4 { + &self.cnstat_cmb4 + } + #[doc = "0x84 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb4(&self) -> &TstpCmb4 { + &self.tstp_cmb4 + } + #[doc = "0x88 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb4(&self) -> &Data3Cmb4 { + &self.data3_cmb4 + } + #[doc = "0x8c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb4(&self) -> &Data2Cmb4 { + &self.data2_cmb4 + } + #[doc = "0x90 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb4(&self) -> &Data1Cmb4 { + &self.data1_cmb4 + } + #[doc = "0x94 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb4(&self) -> &Data0Cmb4 { + &self.data0_cmb4 + } + #[doc = "0x98 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb4(&self) -> &Id0Cmb4 { + &self.id0_cmb4 + } + #[doc = "0x9c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb4(&self) -> &Id1Cmb4 { + &self.id1_cmb4 + } + #[doc = "0xa0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb5(&self) -> &CnstatCmb5 { + &self.cnstat_cmb5 + } + #[doc = "0xa4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb5(&self) -> &TstpCmb5 { + &self.tstp_cmb5 + } + #[doc = "0xa8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb5(&self) -> &Data3Cmb5 { + &self.data3_cmb5 + } + #[doc = "0xac - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb5(&self) -> &Data2Cmb5 { + &self.data2_cmb5 + } + #[doc = "0xb0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb5(&self) -> &Data1Cmb5 { + &self.data1_cmb5 + } + #[doc = "0xb4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb5(&self) -> &Data0Cmb5 { + &self.data0_cmb5 + } + #[doc = "0xb8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb5(&self) -> &Id0Cmb5 { + &self.id0_cmb5 + } + #[doc = "0xbc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb5(&self) -> &Id1Cmb5 { + &self.id1_cmb5 + } + #[doc = "0xc0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb6(&self) -> &CnstatCmb6 { + &self.cnstat_cmb6 + } + #[doc = "0xc4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb6(&self) -> &TstpCmb6 { + &self.tstp_cmb6 + } + #[doc = "0xc8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb6(&self) -> &Data3Cmb6 { + &self.data3_cmb6 + } + #[doc = "0xcc - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb6(&self) -> &Data2Cmb6 { + &self.data2_cmb6 + } + #[doc = "0xd0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb6(&self) -> &Data1Cmb6 { + &self.data1_cmb6 + } + #[doc = "0xd4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb6(&self) -> &Data0Cmb6 { + &self.data0_cmb6 + } + #[doc = "0xd8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb6(&self) -> &Id0Cmb6 { + &self.id0_cmb6 + } + #[doc = "0xdc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb6(&self) -> &Id1Cmb6 { + &self.id1_cmb6 + } + #[doc = "0xe0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb7(&self) -> &CnstatCmb7 { + &self.cnstat_cmb7 + } + #[doc = "0xe4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb7(&self) -> &TstpCmb7 { + &self.tstp_cmb7 + } + #[doc = "0xe8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb7(&self) -> &Data3Cmb7 { + &self.data3_cmb7 + } + #[doc = "0xec - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb7(&self) -> &Data2Cmb7 { + &self.data2_cmb7 + } + #[doc = "0xf0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb7(&self) -> &Data1Cmb7 { + &self.data1_cmb7 + } + #[doc = "0xf4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb7(&self) -> &Data0Cmb7 { + &self.data0_cmb7 + } + #[doc = "0xf8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb7(&self) -> &Id0Cmb7 { + &self.id0_cmb7 + } + #[doc = "0xfc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb7(&self) -> &Id1Cmb7 { + &self.id1_cmb7 + } + #[doc = "0x100 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb8(&self) -> &CnstatCmb8 { + &self.cnstat_cmb8 + } + #[doc = "0x104 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb8(&self) -> &TstpCmb8 { + &self.tstp_cmb8 + } + #[doc = "0x108 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb8(&self) -> &Data3Cmb8 { + &self.data3_cmb8 + } + #[doc = "0x10c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb8(&self) -> &Data2Cmb8 { + &self.data2_cmb8 + } + #[doc = "0x110 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb8(&self) -> &Data1Cmb8 { + &self.data1_cmb8 + } + #[doc = "0x114 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb8(&self) -> &Data0Cmb8 { + &self.data0_cmb8 + } + #[doc = "0x118 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb8(&self) -> &Id0Cmb8 { + &self.id0_cmb8 + } + #[doc = "0x11c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb8(&self) -> &Id1Cmb8 { + &self.id1_cmb8 + } + #[doc = "0x120 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb9(&self) -> &CnstatCmb9 { + &self.cnstat_cmb9 + } + #[doc = "0x124 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb9(&self) -> &TstpCmb9 { + &self.tstp_cmb9 + } + #[doc = "0x128 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb9(&self) -> &Data3Cmb9 { + &self.data3_cmb9 + } + #[doc = "0x12c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb9(&self) -> &Data2Cmb9 { + &self.data2_cmb9 + } + #[doc = "0x130 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb9(&self) -> &Data1Cmb9 { + &self.data1_cmb9 + } + #[doc = "0x134 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb9(&self) -> &Data0Cmb9 { + &self.data0_cmb9 + } + #[doc = "0x138 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb9(&self) -> &Id0Cmb9 { + &self.id0_cmb9 + } + #[doc = "0x13c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb9(&self) -> &Id1Cmb9 { + &self.id1_cmb9 + } + #[doc = "0x140 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb10(&self) -> &CnstatCmb10 { + &self.cnstat_cmb10 + } + #[doc = "0x144 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb10(&self) -> &TstpCmb10 { + &self.tstp_cmb10 + } + #[doc = "0x148 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb10(&self) -> &Data3Cmb10 { + &self.data3_cmb10 + } + #[doc = "0x14c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb10(&self) -> &Data2Cmb10 { + &self.data2_cmb10 + } + #[doc = "0x150 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb10(&self) -> &Data1Cmb10 { + &self.data1_cmb10 + } + #[doc = "0x154 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb10(&self) -> &Data0Cmb10 { + &self.data0_cmb10 + } + #[doc = "0x158 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb10(&self) -> &Id0Cmb10 { + &self.id0_cmb10 + } + #[doc = "0x15c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb10(&self) -> &Id1Cmb10 { + &self.id1_cmb10 + } + #[doc = "0x160 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb11(&self) -> &CnstatCmb11 { + &self.cnstat_cmb11 + } + #[doc = "0x164 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb11(&self) -> &TstpCmb11 { + &self.tstp_cmb11 + } + #[doc = "0x168 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb11(&self) -> &Data3Cmb11 { + &self.data3_cmb11 + } + #[doc = "0x16c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb11(&self) -> &Data2Cmb11 { + &self.data2_cmb11 + } + #[doc = "0x170 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb11(&self) -> &Data1Cmb11 { + &self.data1_cmb11 + } + #[doc = "0x174 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb11(&self) -> &Data0Cmb11 { + &self.data0_cmb11 + } + #[doc = "0x178 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb11(&self) -> &Id0Cmb11 { + &self.id0_cmb11 + } + #[doc = "0x17c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb11(&self) -> &Id1Cmb11 { + &self.id1_cmb11 + } + #[doc = "0x180 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb12(&self) -> &CnstatCmb12 { + &self.cnstat_cmb12 + } + #[doc = "0x184 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb12(&self) -> &TstpCmb12 { + &self.tstp_cmb12 + } + #[doc = "0x188 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb12(&self) -> &Data3Cmb12 { + &self.data3_cmb12 + } + #[doc = "0x18c - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb12(&self) -> &Data2Cmb12 { + &self.data2_cmb12 + } + #[doc = "0x190 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb12(&self) -> &Data1Cmb12 { + &self.data1_cmb12 + } + #[doc = "0x194 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb12(&self) -> &Data0Cmb12 { + &self.data0_cmb12 + } + #[doc = "0x198 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb12(&self) -> &Id0Cmb12 { + &self.id0_cmb12 + } + #[doc = "0x19c - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb12(&self) -> &Id1Cmb12 { + &self.id1_cmb12 + } + #[doc = "0x1a0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb13(&self) -> &CnstatCmb13 { + &self.cnstat_cmb13 + } + #[doc = "0x1a4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb13(&self) -> &TstpCmb13 { + &self.tstp_cmb13 + } + #[doc = "0x1a8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb13(&self) -> &Data3Cmb13 { + &self.data3_cmb13 + } + #[doc = "0x1ac - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb13(&self) -> &Data2Cmb13 { + &self.data2_cmb13 + } + #[doc = "0x1b0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb13(&self) -> &Data1Cmb13 { + &self.data1_cmb13 + } + #[doc = "0x1b4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb13(&self) -> &Data0Cmb13 { + &self.data0_cmb13 + } + #[doc = "0x1b8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb13(&self) -> &Id0Cmb13 { + &self.id0_cmb13 + } + #[doc = "0x1bc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb13(&self) -> &Id1Cmb13 { + &self.id1_cmb13 + } + #[doc = "0x1c0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_cmb14(&self) -> &CnstatCmb14 { + &self.cnstat_cmb14 + } + #[doc = "0x1c4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_cmb14(&self) -> &TstpCmb14 { + &self.tstp_cmb14 + } + #[doc = "0x1c8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_cmb14(&self) -> &Data3Cmb14 { + &self.data3_cmb14 + } + #[doc = "0x1cc - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_cmb14(&self) -> &Data2Cmb14 { + &self.data2_cmb14 + } + #[doc = "0x1d0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_cmb14(&self) -> &Data1Cmb14 { + &self.data1_cmb14 + } + #[doc = "0x1d4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_cmb14(&self) -> &Data0Cmb14 { + &self.data0_cmb14 + } + #[doc = "0x1d8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_cmb14(&self) -> &Id0Cmb14 { + &self.id0_cmb14 + } + #[doc = "0x1dc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_cmb14(&self) -> &Id1Cmb14 { + &self.id1_cmb14 + } + #[doc = "0x1e0 - Buffer Status / Control Register"] + #[inline(always)] + pub const fn cnstat_hcmb(&self) -> &CnstatHcmb { + &self.cnstat_hcmb + } + #[doc = "0x1e4 - CAN Frame Timestamp"] + #[inline(always)] + pub const fn tstp_hcmb(&self) -> &TstpHcmb { + &self.tstp_hcmb + } + #[doc = "0x1e8 - CAN Frame Data Word 3"] + #[inline(always)] + pub const fn data3_hcmb(&self) -> &Data3Hcmb { + &self.data3_hcmb + } + #[doc = "0x1ec - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data2_hcmb(&self) -> &Data2Hcmb { + &self.data2_hcmb + } + #[doc = "0x1f0 - CAN Frame Data Word 2"] + #[inline(always)] + pub const fn data1_hcmb(&self) -> &Data1Hcmb { + &self.data1_hcmb + } + #[doc = "0x1f4 - CAN Frame Data Word 0"] + #[inline(always)] + pub const fn data0_hcmb(&self) -> &Data0Hcmb { + &self.data0_hcmb + } + #[doc = "0x1f8 - CAN Frame Identifier Word 0"] + #[inline(always)] + pub const fn id0_hcmb(&self) -> &Id0Hcmb { + &self.id0_hcmb + } + #[doc = "0x1fc - CAN Frame Identifier Word 1"] + #[inline(always)] + pub const fn id1_hcmb(&self) -> &Id1Hcmb { + &self.id1_hcmb + } + #[doc = "0x200 - CAN Global Configuration Register"] + #[inline(always)] + pub const fn cgcr(&self) -> &Cgcr { + &self.cgcr + } + #[doc = "0x204 - CAN Timing Register"] + #[inline(always)] + pub const fn ctim(&self) -> &Ctim { + &self.ctim + } + #[doc = "0x208 - CAN Global Mask Extension"] + #[inline(always)] + pub const fn gmskx(&self) -> &Gmskx { + &self.gmskx + } + #[doc = "0x20c - CAN Global Mask Base"] + #[inline(always)] + pub const fn gmskb(&self) -> &Gmskb { + &self.gmskb + } + #[doc = "0x210 - CAN Basic Mask Extension"] + #[inline(always)] + pub const fn bmskx(&self) -> &Bmskx { + &self.bmskx + } + #[doc = "0x214 - CAN Basic Mask Base"] + #[inline(always)] + pub const fn bmskb(&self) -> &Bmskb { + &self.bmskb + } + #[doc = "0x218 - CAN Interrupt Enable Register"] + #[inline(always)] + pub const fn cien(&self) -> &Cien { + &self.cien + } + #[doc = "0x21c - CAN Interrupt Pending Register"] + #[inline(always)] + pub const fn cipnd(&self) -> &Cipnd { + &self.cipnd + } + #[doc = "0x220 - CAN Interrupt Clear Register"] + #[inline(always)] + pub const fn ciclr(&self) -> &Ciclr { + &self.ciclr + } + #[doc = "0x224 - CAN Interrupt Code Enable Register"] + #[inline(always)] + pub const fn cicen(&self) -> &Cicen { + &self.cicen + } + #[doc = "0x228 - CAN Status Pending Register"] + #[inline(always)] + pub const fn cstpnd(&self) -> &Cstpnd { + &self.cstpnd + } + #[doc = "0x22c - CAN Error Counter Register"] + #[inline(always)] + pub const fn canec(&self) -> &Canec { + &self.canec + } + #[doc = "0x230 - CAN Error Diagnostic Register"] + #[inline(always)] + pub const fn cediag(&self) -> &Cediag { + &self.cediag + } + #[doc = "0x234 - CAN Timer Register"] + #[inline(always)] + pub const fn ctmr(&self) -> &Ctmr { + &self.ctmr + } +} +#[doc = "CNSTAT_CMB0 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb0`] +module"] +#[doc(alias = "CNSTAT_CMB0")] +pub type CnstatCmb0 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb0; +#[doc = "TSTP_CMB0 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb0`] +module"] +#[doc(alias = "TSTP_CMB0")] +pub type TstpCmb0 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb0; +#[doc = "DATA3_CMB0 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb0`] +module"] +#[doc(alias = "DATA3_CMB0")] +pub type Data3Cmb0 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb0; +#[doc = "DATA2_CMB0 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb0`] +module"] +#[doc(alias = "DATA2_CMB0")] +pub type Data2Cmb0 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb0; +#[doc = "DATA1_CMB0 (rw) register accessor: CAN Frame Data Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb0`] +module"] +#[doc(alias = "DATA1_CMB0")] +pub type Data1Cmb0 = crate::Reg; +#[doc = "CAN Frame Data Word 1"] +pub mod data1_cmb0; +#[doc = "DATA0_CMB0 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb0`] +module"] +#[doc(alias = "DATA0_CMB0")] +pub type Data0Cmb0 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb0; +#[doc = "ID0_CMB0 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb0`] +module"] +#[doc(alias = "ID0_CMB0")] +pub type Id0Cmb0 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb0; +#[doc = "ID1_CMB0 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb0`] +module"] +#[doc(alias = "ID1_CMB0")] +pub type Id1Cmb0 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb0; +#[doc = "CNSTAT_CMB1 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb1`] +module"] +#[doc(alias = "CNSTAT_CMB1")] +pub type CnstatCmb1 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb1; +#[doc = "TSTP_CMB1 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb1`] +module"] +#[doc(alias = "TSTP_CMB1")] +pub type TstpCmb1 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb1; +#[doc = "DATA3_CMB1 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb1`] +module"] +#[doc(alias = "DATA3_CMB1")] +pub type Data3Cmb1 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb1; +#[doc = "DATA2_CMB1 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb1`] +module"] +#[doc(alias = "DATA2_CMB1")] +pub type Data2Cmb1 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb1; +#[doc = "DATA1_CMB1 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb1`] +module"] +#[doc(alias = "DATA1_CMB1")] +pub type Data1Cmb1 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb1; +#[doc = "DATA0_CMB1 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb1`] +module"] +#[doc(alias = "DATA0_CMB1")] +pub type Data0Cmb1 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb1; +#[doc = "ID0_CMB1 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb1`] +module"] +#[doc(alias = "ID0_CMB1")] +pub type Id0Cmb1 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb1; +#[doc = "ID1_CMB1 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb1`] +module"] +#[doc(alias = "ID1_CMB1")] +pub type Id1Cmb1 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb1; +#[doc = "CNSTAT_CMB2 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb2`] +module"] +#[doc(alias = "CNSTAT_CMB2")] +pub type CnstatCmb2 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb2; +#[doc = "TSTP_CMB2 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb2`] +module"] +#[doc(alias = "TSTP_CMB2")] +pub type TstpCmb2 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb2; +#[doc = "DATA3_CMB2 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb2`] +module"] +#[doc(alias = "DATA3_CMB2")] +pub type Data3Cmb2 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb2; +#[doc = "DATA2_CMB2 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb2`] +module"] +#[doc(alias = "DATA2_CMB2")] +pub type Data2Cmb2 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb2; +#[doc = "DATA1_CMB2 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb2`] +module"] +#[doc(alias = "DATA1_CMB2")] +pub type Data1Cmb2 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb2; +#[doc = "DATA0_CMB2 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb2`] +module"] +#[doc(alias = "DATA0_CMB2")] +pub type Data0Cmb2 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb2; +#[doc = "ID0_CMB2 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb2`] +module"] +#[doc(alias = "ID0_CMB2")] +pub type Id0Cmb2 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb2; +#[doc = "ID1_CMB2 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb2`] +module"] +#[doc(alias = "ID1_CMB2")] +pub type Id1Cmb2 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb2; +#[doc = "CNSTAT_CMB3 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb3`] +module"] +#[doc(alias = "CNSTAT_CMB3")] +pub type CnstatCmb3 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb3; +#[doc = "TSTP_CMB3 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb3`] +module"] +#[doc(alias = "TSTP_CMB3")] +pub type TstpCmb3 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb3; +#[doc = "DATA3_CMB3 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb3`] +module"] +#[doc(alias = "DATA3_CMB3")] +pub type Data3Cmb3 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb3; +#[doc = "DATA2_CMB3 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb3`] +module"] +#[doc(alias = "DATA2_CMB3")] +pub type Data2Cmb3 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb3; +#[doc = "DATA1_CMB3 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb3`] +module"] +#[doc(alias = "DATA1_CMB3")] +pub type Data1Cmb3 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb3; +#[doc = "DATA0_CMB3 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb3`] +module"] +#[doc(alias = "DATA0_CMB3")] +pub type Data0Cmb3 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb3; +#[doc = "ID0_CMB3 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb3`] +module"] +#[doc(alias = "ID0_CMB3")] +pub type Id0Cmb3 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb3; +#[doc = "ID1_CMB3 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb3`] +module"] +#[doc(alias = "ID1_CMB3")] +pub type Id1Cmb3 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb3; +#[doc = "CNSTAT_CMB4 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb4`] +module"] +#[doc(alias = "CNSTAT_CMB4")] +pub type CnstatCmb4 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb4; +#[doc = "TSTP_CMB4 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb4`] +module"] +#[doc(alias = "TSTP_CMB4")] +pub type TstpCmb4 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb4; +#[doc = "DATA3_CMB4 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb4`] +module"] +#[doc(alias = "DATA3_CMB4")] +pub type Data3Cmb4 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb4; +#[doc = "DATA2_CMB4 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb4`] +module"] +#[doc(alias = "DATA2_CMB4")] +pub type Data2Cmb4 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb4; +#[doc = "DATA1_CMB4 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb4`] +module"] +#[doc(alias = "DATA1_CMB4")] +pub type Data1Cmb4 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb4; +#[doc = "DATA0_CMB4 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb4`] +module"] +#[doc(alias = "DATA0_CMB4")] +pub type Data0Cmb4 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb4; +#[doc = "ID0_CMB4 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb4`] +module"] +#[doc(alias = "ID0_CMB4")] +pub type Id0Cmb4 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb4; +#[doc = "ID1_CMB4 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb4`] +module"] +#[doc(alias = "ID1_CMB4")] +pub type Id1Cmb4 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb4; +#[doc = "CNSTAT_CMB5 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb5`] +module"] +#[doc(alias = "CNSTAT_CMB5")] +pub type CnstatCmb5 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb5; +#[doc = "TSTP_CMB5 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb5`] +module"] +#[doc(alias = "TSTP_CMB5")] +pub type TstpCmb5 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb5; +#[doc = "DATA3_CMB5 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb5`] +module"] +#[doc(alias = "DATA3_CMB5")] +pub type Data3Cmb5 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb5; +#[doc = "DATA2_CMB5 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb5`] +module"] +#[doc(alias = "DATA2_CMB5")] +pub type Data2Cmb5 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb5; +#[doc = "DATA1_CMB5 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb5`] +module"] +#[doc(alias = "DATA1_CMB5")] +pub type Data1Cmb5 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb5; +#[doc = "DATA0_CMB5 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb5`] +module"] +#[doc(alias = "DATA0_CMB5")] +pub type Data0Cmb5 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb5; +#[doc = "ID0_CMB5 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb5`] +module"] +#[doc(alias = "ID0_CMB5")] +pub type Id0Cmb5 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb5; +#[doc = "ID1_CMB5 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb5`] +module"] +#[doc(alias = "ID1_CMB5")] +pub type Id1Cmb5 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb5; +#[doc = "CNSTAT_CMB6 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb6`] +module"] +#[doc(alias = "CNSTAT_CMB6")] +pub type CnstatCmb6 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb6; +#[doc = "TSTP_CMB6 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb6`] +module"] +#[doc(alias = "TSTP_CMB6")] +pub type TstpCmb6 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb6; +#[doc = "DATA3_CMB6 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb6`] +module"] +#[doc(alias = "DATA3_CMB6")] +pub type Data3Cmb6 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb6; +#[doc = "DATA2_CMB6 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb6`] +module"] +#[doc(alias = "DATA2_CMB6")] +pub type Data2Cmb6 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb6; +#[doc = "DATA1_CMB6 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb6`] +module"] +#[doc(alias = "DATA1_CMB6")] +pub type Data1Cmb6 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb6; +#[doc = "DATA0_CMB6 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb6`] +module"] +#[doc(alias = "DATA0_CMB6")] +pub type Data0Cmb6 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb6; +#[doc = "ID0_CMB6 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb6`] +module"] +#[doc(alias = "ID0_CMB6")] +pub type Id0Cmb6 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb6; +#[doc = "ID1_CMB6 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb6`] +module"] +#[doc(alias = "ID1_CMB6")] +pub type Id1Cmb6 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb6; +#[doc = "CNSTAT_CMB7 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb7`] +module"] +#[doc(alias = "CNSTAT_CMB7")] +pub type CnstatCmb7 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb7; +#[doc = "TSTP_CMB7 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb7`] +module"] +#[doc(alias = "TSTP_CMB7")] +pub type TstpCmb7 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb7; +#[doc = "DATA3_CMB7 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb7`] +module"] +#[doc(alias = "DATA3_CMB7")] +pub type Data3Cmb7 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb7; +#[doc = "DATA2_CMB7 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb7`] +module"] +#[doc(alias = "DATA2_CMB7")] +pub type Data2Cmb7 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb7; +#[doc = "DATA1_CMB7 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb7`] +module"] +#[doc(alias = "DATA1_CMB7")] +pub type Data1Cmb7 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb7; +#[doc = "DATA0_CMB7 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb7`] +module"] +#[doc(alias = "DATA0_CMB7")] +pub type Data0Cmb7 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb7; +#[doc = "ID0_CMB7 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb7`] +module"] +#[doc(alias = "ID0_CMB7")] +pub type Id0Cmb7 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb7; +#[doc = "ID1_CMB7 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb7`] +module"] +#[doc(alias = "ID1_CMB7")] +pub type Id1Cmb7 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb7; +#[doc = "CNSTAT_CMB8 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb8`] +module"] +#[doc(alias = "CNSTAT_CMB8")] +pub type CnstatCmb8 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb8; +#[doc = "TSTP_CMB8 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb8`] +module"] +#[doc(alias = "TSTP_CMB8")] +pub type TstpCmb8 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb8; +#[doc = "DATA3_CMB8 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb8`] +module"] +#[doc(alias = "DATA3_CMB8")] +pub type Data3Cmb8 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb8; +#[doc = "DATA2_CMB8 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb8`] +module"] +#[doc(alias = "DATA2_CMB8")] +pub type Data2Cmb8 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb8; +#[doc = "DATA1_CMB8 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb8`] +module"] +#[doc(alias = "DATA1_CMB8")] +pub type Data1Cmb8 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb8; +#[doc = "DATA0_CMB8 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb8`] +module"] +#[doc(alias = "DATA0_CMB8")] +pub type Data0Cmb8 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb8; +#[doc = "ID0_CMB8 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb8`] +module"] +#[doc(alias = "ID0_CMB8")] +pub type Id0Cmb8 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb8; +#[doc = "ID1_CMB8 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb8::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb8::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb8`] +module"] +#[doc(alias = "ID1_CMB8")] +pub type Id1Cmb8 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb8; +#[doc = "CNSTAT_CMB9 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb9`] +module"] +#[doc(alias = "CNSTAT_CMB9")] +pub type CnstatCmb9 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb9; +#[doc = "TSTP_CMB9 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb9`] +module"] +#[doc(alias = "TSTP_CMB9")] +pub type TstpCmb9 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb9; +#[doc = "DATA3_CMB9 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb9`] +module"] +#[doc(alias = "DATA3_CMB9")] +pub type Data3Cmb9 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb9; +#[doc = "DATA2_CMB9 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb9`] +module"] +#[doc(alias = "DATA2_CMB9")] +pub type Data2Cmb9 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb9; +#[doc = "DATA1_CMB9 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb9`] +module"] +#[doc(alias = "DATA1_CMB9")] +pub type Data1Cmb9 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb9; +#[doc = "DATA0_CMB9 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb9`] +module"] +#[doc(alias = "DATA0_CMB9")] +pub type Data0Cmb9 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb9; +#[doc = "ID0_CMB9 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb9`] +module"] +#[doc(alias = "ID0_CMB9")] +pub type Id0Cmb9 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb9; +#[doc = "ID1_CMB9 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb9`] +module"] +#[doc(alias = "ID1_CMB9")] +pub type Id1Cmb9 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb9; +#[doc = "CNSTAT_CMB10 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb10`] +module"] +#[doc(alias = "CNSTAT_CMB10")] +pub type CnstatCmb10 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb10; +#[doc = "TSTP_CMB10 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb10`] +module"] +#[doc(alias = "TSTP_CMB10")] +pub type TstpCmb10 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb10; +#[doc = "DATA3_CMB10 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb10`] +module"] +#[doc(alias = "DATA3_CMB10")] +pub type Data3Cmb10 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb10; +#[doc = "DATA2_CMB10 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb10`] +module"] +#[doc(alias = "DATA2_CMB10")] +pub type Data2Cmb10 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb10; +#[doc = "DATA1_CMB10 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb10`] +module"] +#[doc(alias = "DATA1_CMB10")] +pub type Data1Cmb10 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb10; +#[doc = "DATA0_CMB10 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb10`] +module"] +#[doc(alias = "DATA0_CMB10")] +pub type Data0Cmb10 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb10; +#[doc = "ID0_CMB10 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb10`] +module"] +#[doc(alias = "ID0_CMB10")] +pub type Id0Cmb10 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb10; +#[doc = "ID1_CMB10 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb10`] +module"] +#[doc(alias = "ID1_CMB10")] +pub type Id1Cmb10 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb10; +#[doc = "CNSTAT_CMB11 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb11`] +module"] +#[doc(alias = "CNSTAT_CMB11")] +pub type CnstatCmb11 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb11; +#[doc = "TSTP_CMB11 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb11`] +module"] +#[doc(alias = "TSTP_CMB11")] +pub type TstpCmb11 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb11; +#[doc = "DATA3_CMB11 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb11`] +module"] +#[doc(alias = "DATA3_CMB11")] +pub type Data3Cmb11 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb11; +#[doc = "DATA2_CMB11 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb11`] +module"] +#[doc(alias = "DATA2_CMB11")] +pub type Data2Cmb11 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb11; +#[doc = "DATA1_CMB11 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb11`] +module"] +#[doc(alias = "DATA1_CMB11")] +pub type Data1Cmb11 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb11; +#[doc = "DATA0_CMB11 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb11`] +module"] +#[doc(alias = "DATA0_CMB11")] +pub type Data0Cmb11 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb11; +#[doc = "ID0_CMB11 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb11`] +module"] +#[doc(alias = "ID0_CMB11")] +pub type Id0Cmb11 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb11; +#[doc = "ID1_CMB11 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb11::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb11::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb11`] +module"] +#[doc(alias = "ID1_CMB11")] +pub type Id1Cmb11 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb11; +#[doc = "CNSTAT_CMB12 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb12`] +module"] +#[doc(alias = "CNSTAT_CMB12")] +pub type CnstatCmb12 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb12; +#[doc = "TSTP_CMB12 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb12`] +module"] +#[doc(alias = "TSTP_CMB12")] +pub type TstpCmb12 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb12; +#[doc = "DATA3_CMB12 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb12`] +module"] +#[doc(alias = "DATA3_CMB12")] +pub type Data3Cmb12 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb12; +#[doc = "DATA2_CMB12 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb12`] +module"] +#[doc(alias = "DATA2_CMB12")] +pub type Data2Cmb12 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb12; +#[doc = "DATA1_CMB12 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb12`] +module"] +#[doc(alias = "DATA1_CMB12")] +pub type Data1Cmb12 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb12; +#[doc = "DATA0_CMB12 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb12`] +module"] +#[doc(alias = "DATA0_CMB12")] +pub type Data0Cmb12 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb12; +#[doc = "ID0_CMB12 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb12`] +module"] +#[doc(alias = "ID0_CMB12")] +pub type Id0Cmb12 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb12; +#[doc = "ID1_CMB12 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb12::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb12::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb12`] +module"] +#[doc(alias = "ID1_CMB12")] +pub type Id1Cmb12 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb12; +#[doc = "CNSTAT_CMB13 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb13`] +module"] +#[doc(alias = "CNSTAT_CMB13")] +pub type CnstatCmb13 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb13; +#[doc = "TSTP_CMB13 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb13`] +module"] +#[doc(alias = "TSTP_CMB13")] +pub type TstpCmb13 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb13; +#[doc = "DATA3_CMB13 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb13`] +module"] +#[doc(alias = "DATA3_CMB13")] +pub type Data3Cmb13 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb13; +#[doc = "DATA2_CMB13 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb13`] +module"] +#[doc(alias = "DATA2_CMB13")] +pub type Data2Cmb13 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb13; +#[doc = "DATA1_CMB13 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb13`] +module"] +#[doc(alias = "DATA1_CMB13")] +pub type Data1Cmb13 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb13; +#[doc = "DATA0_CMB13 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb13`] +module"] +#[doc(alias = "DATA0_CMB13")] +pub type Data0Cmb13 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb13; +#[doc = "ID0_CMB13 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb13`] +module"] +#[doc(alias = "ID0_CMB13")] +pub type Id0Cmb13 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb13; +#[doc = "ID1_CMB13 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb13::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb13::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb13`] +module"] +#[doc(alias = "ID1_CMB13")] +pub type Id1Cmb13 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb13; +#[doc = "CNSTAT_CMB14 (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_cmb14`] +module"] +#[doc(alias = "CNSTAT_CMB14")] +pub type CnstatCmb14 = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_cmb14; +#[doc = "TSTP_CMB14 (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_cmb14`] +module"] +#[doc(alias = "TSTP_CMB14")] +pub type TstpCmb14 = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_cmb14; +#[doc = "DATA3_CMB14 (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_cmb14`] +module"] +#[doc(alias = "DATA3_CMB14")] +pub type Data3Cmb14 = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_cmb14; +#[doc = "DATA2_CMB14 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_cmb14`] +module"] +#[doc(alias = "DATA2_CMB14")] +pub type Data2Cmb14 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_cmb14; +#[doc = "DATA1_CMB14 (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_cmb14`] +module"] +#[doc(alias = "DATA1_CMB14")] +pub type Data1Cmb14 = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_cmb14; +#[doc = "DATA0_CMB14 (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_cmb14`] +module"] +#[doc(alias = "DATA0_CMB14")] +pub type Data0Cmb14 = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_cmb14; +#[doc = "ID0_CMB14 (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_cmb14`] +module"] +#[doc(alias = "ID0_CMB14")] +pub type Id0Cmb14 = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_cmb14; +#[doc = "ID1_CMB14 (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb14::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb14::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_cmb14`] +module"] +#[doc(alias = "ID1_CMB14")] +pub type Id1Cmb14 = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_cmb14; +#[doc = "CNSTAT_HCMB (rw) register accessor: Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_hcmb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_hcmb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnstat_hcmb`] +module"] +#[doc(alias = "CNSTAT_HCMB")] +pub type CnstatHcmb = crate::Reg; +#[doc = "Buffer Status / Control Register"] +pub mod cnstat_hcmb; +#[doc = "TSTP_HCMB (rw) register accessor: CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_hcmb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_hcmb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tstp_hcmb`] +module"] +#[doc(alias = "TSTP_HCMB")] +pub type TstpHcmb = crate::Reg; +#[doc = "CAN Frame Timestamp"] +pub mod tstp_hcmb; +#[doc = "DATA3_HCMB (rw) register accessor: CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_hcmb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_hcmb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data3_hcmb`] +module"] +#[doc(alias = "DATA3_HCMB")] +pub type Data3Hcmb = crate::Reg; +#[doc = "CAN Frame Data Word 3"] +pub mod data3_hcmb; +#[doc = "DATA2_HCMB (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_hcmb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_hcmb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data2_hcmb`] +module"] +#[doc(alias = "DATA2_HCMB")] +pub type Data2Hcmb = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data2_hcmb; +#[doc = "DATA1_HCMB (rw) register accessor: CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_hcmb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_hcmb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data1_hcmb`] +module"] +#[doc(alias = "DATA1_HCMB")] +pub type Data1Hcmb = crate::Reg; +#[doc = "CAN Frame Data Word 2"] +pub mod data1_hcmb; +#[doc = "DATA0_HCMB (rw) register accessor: CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_hcmb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_hcmb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data0_hcmb`] +module"] +#[doc(alias = "DATA0_HCMB")] +pub type Data0Hcmb = crate::Reg; +#[doc = "CAN Frame Data Word 0"] +pub mod data0_hcmb; +#[doc = "ID0_HCMB (rw) register accessor: CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_hcmb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_hcmb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id0_hcmb`] +module"] +#[doc(alias = "ID0_HCMB")] +pub type Id0Hcmb = crate::Reg; +#[doc = "CAN Frame Identifier Word 0"] +pub mod id0_hcmb; +#[doc = "ID1_HCMB (rw) register accessor: CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_hcmb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_hcmb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id1_hcmb`] +module"] +#[doc(alias = "ID1_HCMB")] +pub type Id1Hcmb = crate::Reg; +#[doc = "CAN Frame Identifier Word 1"] +pub mod id1_hcmb; +#[doc = "CGCR (rw) register accessor: CAN Global Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cgcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cgcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cgcr`] +module"] +#[doc(alias = "CGCR")] +pub type Cgcr = crate::Reg; +#[doc = "CAN Global Configuration Register"] +pub mod cgcr; +#[doc = "CTIM (rw) register accessor: CAN Timing Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctim`] +module"] +#[doc(alias = "CTIM")] +pub type Ctim = crate::Reg; +#[doc = "CAN Timing Register"] +pub mod ctim; +#[doc = "GMSKX (rw) register accessor: CAN Global Mask Extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmskx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmskx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmskx`] +module"] +#[doc(alias = "GMSKX")] +pub type Gmskx = crate::Reg; +#[doc = "CAN Global Mask Extension"] +pub mod gmskx; +#[doc = "GMSKB (rw) register accessor: CAN Global Mask Base\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmskb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmskb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gmskb`] +module"] +#[doc(alias = "GMSKB")] +pub type Gmskb = crate::Reg; +#[doc = "CAN Global Mask Base"] +pub mod gmskb; +#[doc = "BMSKX (rw) register accessor: CAN Basic Mask Extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmskx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmskx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmskx`] +module"] +#[doc(alias = "BMSKX")] +pub type Bmskx = crate::Reg; +#[doc = "CAN Basic Mask Extension"] +pub mod bmskx; +#[doc = "BMSKB (rw) register accessor: CAN Basic Mask Base\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmskb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmskb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bmskb`] +module"] +#[doc(alias = "BMSKB")] +pub type Bmskb = crate::Reg; +#[doc = "CAN Basic Mask Base"] +pub mod bmskb; +#[doc = "CIEN (rw) register accessor: CAN Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cien::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cien::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cien`] +module"] +#[doc(alias = "CIEN")] +pub type Cien = crate::Reg; +#[doc = "CAN Interrupt Enable Register"] +pub mod cien; +#[doc = "CIPND (rw) register accessor: CAN Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cipnd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cipnd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cipnd`] +module"] +#[doc(alias = "CIPND")] +pub type Cipnd = crate::Reg; +#[doc = "CAN Interrupt Pending Register"] +pub mod cipnd; +#[doc = "CICLR (rw) register accessor: CAN Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ciclr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ciclr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ciclr`] +module"] +#[doc(alias = "CICLR")] +pub type Ciclr = crate::Reg; +#[doc = "CAN Interrupt Clear Register"] +pub mod ciclr; +#[doc = "CICEN (rw) register accessor: CAN Interrupt Code Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cicen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cicen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cicen`] +module"] +#[doc(alias = "CICEN")] +pub type Cicen = crate::Reg; +#[doc = "CAN Interrupt Code Enable Register"] +pub mod cicen; +#[doc = "CSTPND (rw) register accessor: CAN Status Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cstpnd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cstpnd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cstpnd`] +module"] +#[doc(alias = "CSTPND")] +pub type Cstpnd = crate::Reg; +#[doc = "CAN Status Pending Register"] +pub mod cstpnd; +#[doc = "CANEC (rw) register accessor: CAN Error Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`canec::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`canec::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@canec`] +module"] +#[doc(alias = "CANEC")] +pub type Canec = crate::Reg; +#[doc = "CAN Error Counter Register"] +pub mod canec; +#[doc = "CEDIAG (rw) register accessor: CAN Error Diagnostic Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cediag::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cediag::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cediag`] +module"] +#[doc(alias = "CEDIAG")] +pub type Cediag = crate::Reg; +#[doc = "CAN Error Diagnostic Register"] +pub mod cediag; +#[doc = "CTMR (rw) register accessor: CAN Timer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctmr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctmr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctmr`] +module"] +#[doc(alias = "CTMR")] +pub type Ctmr = crate::Reg; +#[doc = "CAN Timer Register"] +pub mod ctmr; diff --git a/va416xx/src/can0/bmskb.rs b/va416xx/src/can0/bmskb.rs new file mode 100644 index 0000000..833f22b --- /dev/null +++ b/va416xx/src/can0/bmskb.rs @@ -0,0 +1,105 @@ +#[doc = "Register `BMSKB` reader"] +pub type R = crate::R; +#[doc = "Register `BMSKB` writer"] +pub type W = crate::W; +#[doc = "Field `BM0` reader - BM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] +pub type Bm0R = crate::FieldReader; +#[doc = "Field `BM0` writer - BM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] +pub type Bm0W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IDE` reader - Identifier Extension Bit"] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - Identifier Extension Bit"] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTR` reader - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BM1` reader - BM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] +pub type Bm1R = crate::FieldReader; +#[doc = "Field `BM1` writer - BM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] +pub type Bm1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:2 - BM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] + #[inline(always)] + pub fn bm0(&self) -> Bm0R { + Bm0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:15 - BM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] + #[inline(always)] + pub fn bm1(&self) -> Bm1R { + Bm1R::new(((self.bits >> 5) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - BM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] + #[inline(always)] + #[must_use] + pub fn bm0(&mut self) -> Bm0W { + Bm0W::new(self, 0) + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + #[must_use] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 3) + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + #[must_use] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 4) + } + #[doc = "Bits 5:15 - BM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] + #[inline(always)] + #[must_use] + pub fn bm1(&mut self) -> Bm1W { + Bm1W::new(self, 5) + } +} +#[doc = "CAN Basic Mask Base\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmskb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmskb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BmskbSpec; +impl crate::RegisterSpec for BmskbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`bmskb::R`](R) reader structure"] +impl crate::Readable for BmskbSpec {} +#[doc = "`write(|w| ..)` method takes [`bmskb::W`](W) writer structure"] +impl crate::Writable for BmskbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BMSKB to value 0"] +impl crate::Resettable for BmskbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/bmskx.rs b/va416xx/src/can0/bmskx.rs new file mode 100644 index 0000000..4f42df8 --- /dev/null +++ b/va416xx/src/can0/bmskx.rs @@ -0,0 +1,63 @@ +#[doc = "Register `BMSKX` reader"] +pub type R = crate::R; +#[doc = "Register `BMSKX` writer"] +pub type W = crate::W; +#[doc = "Field `XRTR` reader - Extended Remote transmission Request Bit"] +pub type XrtrR = crate::BitReader; +#[doc = "Field `XRTR` writer - Extended Remote transmission Request Bit"] +pub type XrtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BM` reader - BM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] +pub type BmR = crate::FieldReader; +#[doc = "Field `BM` writer - BM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] +pub type BmW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + pub fn xrtr(&self) -> XrtrR { + XrtrR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:15 - BM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] + #[inline(always)] + pub fn bm(&self) -> BmR { + BmR::new(((self.bits >> 1) & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + #[must_use] + pub fn xrtr(&mut self) -> XrtrW { + XrtrW::new(self, 0) + } + #[doc = "Bits 1:15 - BM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] + #[inline(always)] + #[must_use] + pub fn bm(&mut self) -> BmW { + BmW::new(self, 1) + } +} +#[doc = "CAN Basic Mask Extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bmskx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bmskx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BmskxSpec; +impl crate::RegisterSpec for BmskxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`bmskx::R`](R) reader structure"] +impl crate::Readable for BmskxSpec {} +#[doc = "`write(|w| ..)` method takes [`bmskx::W`](W) writer structure"] +impl crate::Writable for BmskxSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets BMSKX to value 0"] +impl crate::Resettable for BmskxSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/canec.rs b/va416xx/src/can0/canec.rs new file mode 100644 index 0000000..4f945fa --- /dev/null +++ b/va416xx/src/can0/canec.rs @@ -0,0 +1,55 @@ +#[doc = "Register `CANEC` reader"] +pub type R = crate::R; +#[doc = "Register `CANEC` writer"] +pub type W = crate::W; +#[doc = "Field `TEC` reader - Transmit Error Counter"] +pub type TecR = crate::FieldReader; +#[doc = "Field `TEC` writer - Transmit Error Counter"] +pub type TecW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `REC` reader - Receive Error Counter"] +pub type RecR = crate::FieldReader; +#[doc = "Field `REC` writer - Receive Error Counter"] +pub type RecW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + pub fn tec(&self) -> TecR { + TecR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Receive Error Counter"] + #[inline(always)] + pub fn rec(&self) -> RecR { + RecR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Transmit Error Counter"] + #[inline(always)] + #[must_use] + pub fn tec(&mut self) -> TecW { + TecW::new(self, 0) + } + #[doc = "Bits 8:15 - Receive Error Counter"] + #[inline(always)] + #[must_use] + pub fn rec(&mut self) -> RecW { + RecW::new(self, 8) + } +} +#[doc = "CAN Error Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`canec::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`canec::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CanecSpec; +impl crate::RegisterSpec for CanecSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`canec::R`](R) reader structure"] +impl crate::Readable for CanecSpec {} +#[doc = "`write(|w| ..)` method takes [`canec::W`](W) writer structure"] +impl crate::Writable for CanecSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CANEC to value 0"] +impl crate::Resettable for CanecSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cediag.rs b/va416xx/src/can0/cediag.rs new file mode 100644 index 0000000..b19a68f --- /dev/null +++ b/va416xx/src/can0/cediag.rs @@ -0,0 +1,130 @@ +#[doc = "Register `CEDIAG` reader"] +pub type R = crate::R; +#[doc = "Register `CEDIAG` writer"] +pub type W = crate::W; +#[doc = "Field `EFID` reader - Error Field Identifier"] +pub type EfidR = crate::FieldReader; +#[doc = "Field `EFID` writer - Error Field Identifier"] +pub type EfidW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `EBID` reader - Error Bit Identifier"] +pub type EbidR = crate::FieldReader; +#[doc = "Field `EBID` writer - Error Bit Identifier"] +pub type EbidW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `TXE` reader - Transmit Error"] +pub type TxeR = crate::BitReader; +#[doc = "Field `TXE` writer - Transmit Error"] +pub type TxeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STUFF` reader - Stuff Error"] +pub type StuffR = crate::BitReader; +#[doc = "Field `STUFF` writer - Stuff Error"] +pub type StuffW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRC` reader - CRC"] +pub type CrcR = crate::BitReader; +#[doc = "Field `CRC` writer - CRC"] +pub type CrcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MON` reader - Monitor"] +pub type MonR = crate::BitReader; +#[doc = "Field `MON` writer - Monitor"] +pub type MonW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DRIVE` reader - Drive"] +pub type DriveR = crate::BitReader; +#[doc = "Field `DRIVE` writer - Drive"] +pub type DriveW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:3 - Error Field Identifier"] + #[inline(always)] + pub fn efid(&self) -> EfidR { + EfidR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:9 - Error Bit Identifier"] + #[inline(always)] + pub fn ebid(&self) -> EbidR { + EbidR::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bit 10 - Transmit Error"] + #[inline(always)] + pub fn txe(&self) -> TxeR { + TxeR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Stuff Error"] + #[inline(always)] + pub fn stuff(&self) -> StuffR { + StuffR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - CRC"] + #[inline(always)] + pub fn crc(&self) -> CrcR { + CrcR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Monitor"] + #[inline(always)] + pub fn mon(&self) -> MonR { + MonR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Drive"] + #[inline(always)] + pub fn drive(&self) -> DriveR { + DriveR::new(((self.bits >> 14) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Error Field Identifier"] + #[inline(always)] + #[must_use] + pub fn efid(&mut self) -> EfidW { + EfidW::new(self, 0) + } + #[doc = "Bits 4:9 - Error Bit Identifier"] + #[inline(always)] + #[must_use] + pub fn ebid(&mut self) -> EbidW { + EbidW::new(self, 4) + } + #[doc = "Bit 10 - Transmit Error"] + #[inline(always)] + #[must_use] + pub fn txe(&mut self) -> TxeW { + TxeW::new(self, 10) + } + #[doc = "Bit 11 - Stuff Error"] + #[inline(always)] + #[must_use] + pub fn stuff(&mut self) -> StuffW { + StuffW::new(self, 11) + } + #[doc = "Bit 12 - CRC"] + #[inline(always)] + #[must_use] + pub fn crc(&mut self) -> CrcW { + CrcW::new(self, 12) + } + #[doc = "Bit 13 - Monitor"] + #[inline(always)] + #[must_use] + pub fn mon(&mut self) -> MonW { + MonW::new(self, 13) + } + #[doc = "Bit 14 - Drive"] + #[inline(always)] + #[must_use] + pub fn drive(&mut self) -> DriveW { + DriveW::new(self, 14) + } +} +#[doc = "CAN Error Diagnostic Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cediag::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cediag::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CediagSpec; +impl crate::RegisterSpec for CediagSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cediag::R`](R) reader structure"] +impl crate::Readable for CediagSpec {} +#[doc = "`write(|w| ..)` method takes [`cediag::W`](W) writer structure"] +impl crate::Writable for CediagSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CEDIAG to value 0"] +impl crate::Resettable for CediagSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cgcr.rs b/va416xx/src/can0/cgcr.rs new file mode 100644 index 0000000..ef91f01 --- /dev/null +++ b/va416xx/src/can0/cgcr.rs @@ -0,0 +1,205 @@ +#[doc = "Register `CGCR` reader"] +pub type R = crate::R; +#[doc = "Register `CGCR` writer"] +pub type W = crate::W; +#[doc = "Field `CANEN` reader - CAN Enable"] +pub type CanenR = crate::BitReader; +#[doc = "Field `CANEN` writer - CAN Enable"] +pub type CanenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRX` reader - RW,Control Receive"] +pub type CrxR = crate::BitReader; +#[doc = "Field `CRX` writer - RW,Control Receive"] +pub type CrxW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CTX` reader - RW,Control Transmit"] +pub type CtxR = crate::BitReader; +#[doc = "Field `CTX` writer - RW,Control Transmit"] +pub type CtxW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BUFFLOCK` reader - Buffer Lock"] +pub type BufflockR = crate::BitReader; +#[doc = "Field `BUFFLOCK` writer - Buffer Lock"] +pub type BufflockW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSTPEN` reader - Time Sync Enable"] +pub type TstpenR = crate::BitReader; +#[doc = "Field `TSTPEN` writer - Time Sync Enable"] +pub type TstpenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DDIR` reader - Data Direction"] +pub type DdirR = crate::BitReader; +#[doc = "Field `DDIR` writer - Data Direction"] +pub type DdirW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LO` reader - Listen Only"] +pub type LoR = crate::BitReader; +#[doc = "Field `LO` writer - Listen Only"] +pub type LoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IGNACK` reader - Ignore Acknowledge"] +pub type IgnackR = crate::BitReader; +#[doc = "Field `IGNACK` writer - Ignore Acknowledge"] +pub type IgnackW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBACK` reader - Loopback"] +pub type LoopbackR = crate::BitReader; +#[doc = "Field `LOOPBACK` writer - Loopback"] +pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTERNAL` reader - Internal"] +pub type InternalR = crate::BitReader; +#[doc = "Field `INTERNAL` writer - Internal"] +pub type InternalW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DIAGEN` reader - Diagnostic Enable"] +pub type DiagenR = crate::BitReader; +#[doc = "Field `DIAGEN` writer - Diagnostic Enable"] +pub type DiagenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EIT` reader - Error Interrupt Type"] +pub type EitR = crate::BitReader; +#[doc = "Field `EIT` writer - Error Interrupt Type"] +pub type EitW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - CAN Enable"] + #[inline(always)] + pub fn canen(&self) -> CanenR { + CanenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RW,Control Receive"] + #[inline(always)] + pub fn crx(&self) -> CrxR { + CrxR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RW,Control Transmit"] + #[inline(always)] + pub fn ctx(&self) -> CtxR { + CtxR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Buffer Lock"] + #[inline(always)] + pub fn bufflock(&self) -> BufflockR { + BufflockR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Time Sync Enable"] + #[inline(always)] + pub fn tstpen(&self) -> TstpenR { + TstpenR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Data Direction"] + #[inline(always)] + pub fn ddir(&self) -> DdirR { + DdirR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Listen Only"] + #[inline(always)] + pub fn lo(&self) -> LoR { + LoR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Ignore Acknowledge"] + #[inline(always)] + pub fn ignack(&self) -> IgnackR { + IgnackR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Loopback"] + #[inline(always)] + pub fn loopback(&self) -> LoopbackR { + LoopbackR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Internal"] + #[inline(always)] + pub fn internal(&self) -> InternalR { + InternalR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Diagnostic Enable"] + #[inline(always)] + pub fn diagen(&self) -> DiagenR { + DiagenR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Error Interrupt Type"] + #[inline(always)] + pub fn eit(&self) -> EitR { + EitR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - CAN Enable"] + #[inline(always)] + #[must_use] + pub fn canen(&mut self) -> CanenW { + CanenW::new(self, 0) + } + #[doc = "Bit 1 - RW,Control Receive"] + #[inline(always)] + #[must_use] + pub fn crx(&mut self) -> CrxW { + CrxW::new(self, 1) + } + #[doc = "Bit 2 - RW,Control Transmit"] + #[inline(always)] + #[must_use] + pub fn ctx(&mut self) -> CtxW { + CtxW::new(self, 2) + } + #[doc = "Bit 3 - Buffer Lock"] + #[inline(always)] + #[must_use] + pub fn bufflock(&mut self) -> BufflockW { + BufflockW::new(self, 3) + } + #[doc = "Bit 4 - Time Sync Enable"] + #[inline(always)] + #[must_use] + pub fn tstpen(&mut self) -> TstpenW { + TstpenW::new(self, 4) + } + #[doc = "Bit 5 - Data Direction"] + #[inline(always)] + #[must_use] + pub fn ddir(&mut self) -> DdirW { + DdirW::new(self, 5) + } + #[doc = "Bit 6 - Listen Only"] + #[inline(always)] + #[must_use] + pub fn lo(&mut self) -> LoW { + LoW::new(self, 6) + } + #[doc = "Bit 7 - Ignore Acknowledge"] + #[inline(always)] + #[must_use] + pub fn ignack(&mut self) -> IgnackW { + IgnackW::new(self, 7) + } + #[doc = "Bit 8 - Loopback"] + #[inline(always)] + #[must_use] + pub fn loopback(&mut self) -> LoopbackW { + LoopbackW::new(self, 8) + } + #[doc = "Bit 9 - Internal"] + #[inline(always)] + #[must_use] + pub fn internal(&mut self) -> InternalW { + InternalW::new(self, 9) + } + #[doc = "Bit 10 - Diagnostic Enable"] + #[inline(always)] + #[must_use] + pub fn diagen(&mut self) -> DiagenW { + DiagenW::new(self, 10) + } + #[doc = "Bit 11 - Error Interrupt Type"] + #[inline(always)] + #[must_use] + pub fn eit(&mut self) -> EitW { + EitW::new(self, 11) + } +} +#[doc = "CAN Global Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cgcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cgcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CgcrSpec; +impl crate::RegisterSpec for CgcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cgcr::R`](R) reader structure"] +impl crate::Readable for CgcrSpec {} +#[doc = "`write(|w| ..)` method takes [`cgcr::W`](W) writer structure"] +impl crate::Writable for CgcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CGCR to value 0"] +impl crate::Resettable for CgcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cicen.rs b/va416xx/src/can0/cicen.rs new file mode 100644 index 0000000..98b87c2 --- /dev/null +++ b/va416xx/src/can0/cicen.rs @@ -0,0 +1,55 @@ +#[doc = "Register `CICEN` reader"] +pub type R = crate::R; +#[doc = "Register `CICEN` writer"] +pub type W = crate::W; +#[doc = "Field `ICEN` reader - Buffer Interrupt Code Enable\\[14:0\\]"] +pub type IcenR = crate::FieldReader; +#[doc = "Field `ICEN` writer - Buffer Interrupt Code Enable\\[14:0\\]"] +pub type IcenW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `EICEN` reader - Error Interrupt Code Enable"] +pub type EicenR = crate::BitReader; +#[doc = "Field `EICEN` writer - Error Interrupt Code Enable"] +pub type EicenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:14 - Buffer Interrupt Code Enable\\[14:0\\]"] + #[inline(always)] + pub fn icen(&self) -> IcenR { + IcenR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 15 - Error Interrupt Code Enable"] + #[inline(always)] + pub fn eicen(&self) -> EicenR { + EicenR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:14 - Buffer Interrupt Code Enable\\[14:0\\]"] + #[inline(always)] + #[must_use] + pub fn icen(&mut self) -> IcenW { + IcenW::new(self, 0) + } + #[doc = "Bit 15 - Error Interrupt Code Enable"] + #[inline(always)] + #[must_use] + pub fn eicen(&mut self) -> EicenW { + EicenW::new(self, 15) + } +} +#[doc = "CAN Interrupt Code Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cicen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cicen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CicenSpec; +impl crate::RegisterSpec for CicenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cicen::R`](R) reader structure"] +impl crate::Readable for CicenSpec {} +#[doc = "`write(|w| ..)` method takes [`cicen::W`](W) writer structure"] +impl crate::Writable for CicenSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CICEN to value 0"] +impl crate::Resettable for CicenSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/ciclr.rs b/va416xx/src/can0/ciclr.rs new file mode 100644 index 0000000..75f5c48 --- /dev/null +++ b/va416xx/src/can0/ciclr.rs @@ -0,0 +1,55 @@ +#[doc = "Register `CICLR` reader"] +pub type R = crate::R; +#[doc = "Register `CICLR` writer"] +pub type W = crate::W; +#[doc = "Field `ICLR` reader - Buffer Interrupt Clear\\[14:0\\]"] +pub type IclrR = crate::FieldReader; +#[doc = "Field `ICLR` writer - Buffer Interrupt Clear\\[14:0\\]"] +pub type IclrW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `EICLR` reader - Error Interrupt Clear"] +pub type EiclrR = crate::BitReader; +#[doc = "Field `EICLR` writer - Error Interrupt Clear"] +pub type EiclrW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:14 - Buffer Interrupt Clear\\[14:0\\]"] + #[inline(always)] + pub fn iclr(&self) -> IclrR { + IclrR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 15 - Error Interrupt Clear"] + #[inline(always)] + pub fn eiclr(&self) -> EiclrR { + EiclrR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:14 - Buffer Interrupt Clear\\[14:0\\]"] + #[inline(always)] + #[must_use] + pub fn iclr(&mut self) -> IclrW { + IclrW::new(self, 0) + } + #[doc = "Bit 15 - Error Interrupt Clear"] + #[inline(always)] + #[must_use] + pub fn eiclr(&mut self) -> EiclrW { + EiclrW::new(self, 15) + } +} +#[doc = "CAN Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ciclr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ciclr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CiclrSpec; +impl crate::RegisterSpec for CiclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ciclr::R`](R) reader structure"] +impl crate::Readable for CiclrSpec {} +#[doc = "`write(|w| ..)` method takes [`ciclr::W`](W) writer structure"] +impl crate::Writable for CiclrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CICLR to value 0"] +impl crate::Resettable for CiclrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cien.rs b/va416xx/src/can0/cien.rs new file mode 100644 index 0000000..65b3550 --- /dev/null +++ b/va416xx/src/can0/cien.rs @@ -0,0 +1,55 @@ +#[doc = "Register `CIEN` reader"] +pub type R = crate::R; +#[doc = "Register `CIEN` writer"] +pub type W = crate::W; +#[doc = "Field `IEN` reader - Buffer Interrupt Enable\\[14:0\\]"] +pub type IenR = crate::FieldReader; +#[doc = "Field `IEN` writer - Buffer Interrupt Enable\\[14:0\\]"] +pub type IenW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `EIEN` reader - Error Interrupt Enable"] +pub type EienR = crate::BitReader; +#[doc = "Field `EIEN` writer - Error Interrupt Enable"] +pub type EienW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:14 - Buffer Interrupt Enable\\[14:0\\]"] + #[inline(always)] + pub fn ien(&self) -> IenR { + IenR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 15 - Error Interrupt Enable"] + #[inline(always)] + pub fn eien(&self) -> EienR { + EienR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:14 - Buffer Interrupt Enable\\[14:0\\]"] + #[inline(always)] + #[must_use] + pub fn ien(&mut self) -> IenW { + IenW::new(self, 0) + } + #[doc = "Bit 15 - Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn eien(&mut self) -> EienW { + EienW::new(self, 15) + } +} +#[doc = "CAN Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cien::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cien::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CienSpec; +impl crate::RegisterSpec for CienSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cien::R`](R) reader structure"] +impl crate::Readable for CienSpec {} +#[doc = "`write(|w| ..)` method takes [`cien::W`](W) writer structure"] +impl crate::Writable for CienSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CIEN to value 0"] +impl crate::Resettable for CienSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cipnd.rs b/va416xx/src/can0/cipnd.rs new file mode 100644 index 0000000..75e828f --- /dev/null +++ b/va416xx/src/can0/cipnd.rs @@ -0,0 +1,55 @@ +#[doc = "Register `CIPND` reader"] +pub type R = crate::R; +#[doc = "Register `CIPND` writer"] +pub type W = crate::W; +#[doc = "Field `IPND` reader - Buffer Interrupt Pending\\[14:0\\]"] +pub type IpndR = crate::FieldReader; +#[doc = "Field `IPND` writer - Buffer Interrupt Pending\\[14:0\\]"] +pub type IpndW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +#[doc = "Field `EIPND` reader - Error Interrupt Pending"] +pub type EipndR = crate::BitReader; +#[doc = "Field `EIPND` writer - Error Interrupt Pending"] +pub type EipndW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:14 - Buffer Interrupt Pending\\[14:0\\]"] + #[inline(always)] + pub fn ipnd(&self) -> IpndR { + IpndR::new((self.bits & 0x7fff) as u16) + } + #[doc = "Bit 15 - Error Interrupt Pending"] + #[inline(always)] + pub fn eipnd(&self) -> EipndR { + EipndR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:14 - Buffer Interrupt Pending\\[14:0\\]"] + #[inline(always)] + #[must_use] + pub fn ipnd(&mut self) -> IpndW { + IpndW::new(self, 0) + } + #[doc = "Bit 15 - Error Interrupt Pending"] + #[inline(always)] + #[must_use] + pub fn eipnd(&mut self) -> EipndW { + EipndW::new(self, 15) + } +} +#[doc = "CAN Interrupt Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cipnd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cipnd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CipndSpec; +impl crate::RegisterSpec for CipndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cipnd::R`](R) reader structure"] +impl crate::Readable for CipndSpec {} +#[doc = "`write(|w| ..)` method takes [`cipnd::W`](W) writer structure"] +impl crate::Writable for CipndSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CIPND to value 0"] +impl crate::Resettable for CipndSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb0.rs b/va416xx/src/can0/cnstat_cmb0.rs new file mode 100644 index 0000000..673daa9 --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb0.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb0Spec; +impl crate::RegisterSpec for CnstatCmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb0::R`](R) reader structure"] +impl crate::Readable for CnstatCmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb0::W`](W) writer structure"] +impl crate::Writable for CnstatCmb0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB0 to value 0"] +impl crate::Resettable for CnstatCmb0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb1.rs b/va416xx/src/can0/cnstat_cmb1.rs new file mode 100644 index 0000000..c6a9f1a --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb1.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb1Spec; +impl crate::RegisterSpec for CnstatCmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb1::R`](R) reader structure"] +impl crate::Readable for CnstatCmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb1::W`](W) writer structure"] +impl crate::Writable for CnstatCmb1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB1 to value 0"] +impl crate::Resettable for CnstatCmb1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb10.rs b/va416xx/src/can0/cnstat_cmb10.rs new file mode 100644 index 0000000..76466e7 --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb10.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb10Spec; +impl crate::RegisterSpec for CnstatCmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb10::R`](R) reader structure"] +impl crate::Readable for CnstatCmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb10::W`](W) writer structure"] +impl crate::Writable for CnstatCmb10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB10 to value 0"] +impl crate::Resettable for CnstatCmb10Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb11.rs b/va416xx/src/can0/cnstat_cmb11.rs new file mode 100644 index 0000000..88cde7a --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb11.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb11Spec; +impl crate::RegisterSpec for CnstatCmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb11::R`](R) reader structure"] +impl crate::Readable for CnstatCmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb11::W`](W) writer structure"] +impl crate::Writable for CnstatCmb11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB11 to value 0"] +impl crate::Resettable for CnstatCmb11Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb12.rs b/va416xx/src/can0/cnstat_cmb12.rs new file mode 100644 index 0000000..54087e8 --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb12.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb12Spec; +impl crate::RegisterSpec for CnstatCmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb12::R`](R) reader structure"] +impl crate::Readable for CnstatCmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb12::W`](W) writer structure"] +impl crate::Writable for CnstatCmb12Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB12 to value 0"] +impl crate::Resettable for CnstatCmb12Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb13.rs b/va416xx/src/can0/cnstat_cmb13.rs new file mode 100644 index 0000000..32073ce --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb13.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb13Spec; +impl crate::RegisterSpec for CnstatCmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb13::R`](R) reader structure"] +impl crate::Readable for CnstatCmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb13::W`](W) writer structure"] +impl crate::Writable for CnstatCmb13Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB13 to value 0"] +impl crate::Resettable for CnstatCmb13Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb14.rs b/va416xx/src/can0/cnstat_cmb14.rs new file mode 100644 index 0000000..7d20dea --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb14.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb14Spec; +impl crate::RegisterSpec for CnstatCmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb14::R`](R) reader structure"] +impl crate::Readable for CnstatCmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb14::W`](W) writer structure"] +impl crate::Writable for CnstatCmb14Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB14 to value 0"] +impl crate::Resettable for CnstatCmb14Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb2.rs b/va416xx/src/can0/cnstat_cmb2.rs new file mode 100644 index 0000000..09fe0d6 --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb2.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb2Spec; +impl crate::RegisterSpec for CnstatCmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb2::R`](R) reader structure"] +impl crate::Readable for CnstatCmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb2::W`](W) writer structure"] +impl crate::Writable for CnstatCmb2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB2 to value 0"] +impl crate::Resettable for CnstatCmb2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb3.rs b/va416xx/src/can0/cnstat_cmb3.rs new file mode 100644 index 0000000..47e5a1d --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb3.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb3Spec; +impl crate::RegisterSpec for CnstatCmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb3::R`](R) reader structure"] +impl crate::Readable for CnstatCmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb3::W`](W) writer structure"] +impl crate::Writable for CnstatCmb3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB3 to value 0"] +impl crate::Resettable for CnstatCmb3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb4.rs b/va416xx/src/can0/cnstat_cmb4.rs new file mode 100644 index 0000000..303896d --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb4.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb4Spec; +impl crate::RegisterSpec for CnstatCmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb4::R`](R) reader structure"] +impl crate::Readable for CnstatCmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb4::W`](W) writer structure"] +impl crate::Writable for CnstatCmb4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB4 to value 0"] +impl crate::Resettable for CnstatCmb4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb5.rs b/va416xx/src/can0/cnstat_cmb5.rs new file mode 100644 index 0000000..062e973 --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb5.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb5Spec; +impl crate::RegisterSpec for CnstatCmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb5::R`](R) reader structure"] +impl crate::Readable for CnstatCmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb5::W`](W) writer structure"] +impl crate::Writable for CnstatCmb5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB5 to value 0"] +impl crate::Resettable for CnstatCmb5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb6.rs b/va416xx/src/can0/cnstat_cmb6.rs new file mode 100644 index 0000000..02e2117 --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb6.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb6Spec; +impl crate::RegisterSpec for CnstatCmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb6::R`](R) reader structure"] +impl crate::Readable for CnstatCmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb6::W`](W) writer structure"] +impl crate::Writable for CnstatCmb6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB6 to value 0"] +impl crate::Resettable for CnstatCmb6Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb7.rs b/va416xx/src/can0/cnstat_cmb7.rs new file mode 100644 index 0000000..d092f65 --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb7.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb7Spec; +impl crate::RegisterSpec for CnstatCmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb7::R`](R) reader structure"] +impl crate::Readable for CnstatCmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb7::W`](W) writer structure"] +impl crate::Writable for CnstatCmb7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB7 to value 0"] +impl crate::Resettable for CnstatCmb7Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb8.rs b/va416xx/src/can0/cnstat_cmb8.rs new file mode 100644 index 0000000..20d4336 --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb8.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb8Spec; +impl crate::RegisterSpec for CnstatCmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb8::R`](R) reader structure"] +impl crate::Readable for CnstatCmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb8::W`](W) writer structure"] +impl crate::Writable for CnstatCmb8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB8 to value 0"] +impl crate::Resettable for CnstatCmb8Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_cmb9.rs b/va416xx/src/can0/cnstat_cmb9.rs new file mode 100644 index 0000000..32dc7bb --- /dev/null +++ b/va416xx/src/can0/cnstat_cmb9.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_cmb9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_cmb9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatCmb9Spec; +impl crate::RegisterSpec for CnstatCmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_cmb9::R`](R) reader structure"] +impl crate::Readable for CnstatCmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_cmb9::W`](W) writer structure"] +impl crate::Writable for CnstatCmb9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_CMB9 to value 0"] +impl crate::Resettable for CnstatCmb9Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cnstat_hcmb.rs b/va416xx/src/can0/cnstat_hcmb.rs new file mode 100644 index 0000000..1b6bd9f --- /dev/null +++ b/va416xx/src/can0/cnstat_hcmb.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CNSTAT_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `CNSTAT_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `ST` reader - Buffer Status"] +pub type StR = crate::FieldReader; +#[doc = "Field `ST` writer - Buffer Status"] +pub type StW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PRI` reader - Transmit Priority Code"] +pub type PriR = crate::FieldReader; +#[doc = "Field `PRI` writer - Transmit Priority Code"] +pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `DLC` reader - Data Length Code"] +pub type DlcR = crate::FieldReader; +#[doc = "Field `DLC` writer - Data Length Code"] +pub type DlcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + pub fn pri(&self) -> PriR { + PriR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + pub fn dlc(&self) -> DlcR { + DlcR::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Buffer Status"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 0) + } + #[doc = "Bits 4:7 - Transmit Priority Code"] + #[inline(always)] + #[must_use] + pub fn pri(&mut self) -> PriW { + PriW::new(self, 4) + } + #[doc = "Bits 12:15 - Data Length Code"] + #[inline(always)] + #[must_use] + pub fn dlc(&mut self) -> DlcW { + DlcW::new(self, 12) + } +} +#[doc = "Buffer Status / Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnstat_hcmb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnstat_hcmb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CnstatHcmbSpec; +impl crate::RegisterSpec for CnstatHcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnstat_hcmb::R`](R) reader structure"] +impl crate::Readable for CnstatHcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`cnstat_hcmb::W`](W) writer structure"] +impl crate::Writable for CnstatHcmbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNSTAT_HCMB to value 0"] +impl crate::Resettable for CnstatHcmbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/cstpnd.rs b/va416xx/src/can0/cstpnd.rs new file mode 100644 index 0000000..a2c908a --- /dev/null +++ b/va416xx/src/can0/cstpnd.rs @@ -0,0 +1,70 @@ +#[doc = "Register `CSTPND` reader"] +pub type R = crate::R; +#[doc = "Register `CSTPND` writer"] +pub type W = crate::W; +#[doc = "Field `IST` reader - Interrupt Source portion of Interrupt Code"] +pub type IstR = crate::FieldReader; +#[doc = "Field `IST` writer - Interrupt Source portion of Interrupt Code"] +pub type IstW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `IRQ` reader - Interrupt Request portion of Interrupt Code"] +pub type IrqR = crate::BitReader; +#[doc = "Field `IRQ` writer - Interrupt Request portion of Interrupt Code"] +pub type IrqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NS` reader - CAN Node Status"] +pub type NsR = crate::FieldReader; +#[doc = "Field `NS` writer - CAN Node Status"] +pub type NsW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl R { + #[doc = "Bits 0:3 - Interrupt Source portion of Interrupt Code"] + #[inline(always)] + pub fn ist(&self) -> IstR { + IstR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 4 - Interrupt Request portion of Interrupt Code"] + #[inline(always)] + pub fn irq(&self) -> IrqR { + IrqR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - CAN Node Status"] + #[inline(always)] + pub fn ns(&self) -> NsR { + NsR::new(((self.bits >> 5) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Interrupt Source portion of Interrupt Code"] + #[inline(always)] + #[must_use] + pub fn ist(&mut self) -> IstW { + IstW::new(self, 0) + } + #[doc = "Bit 4 - Interrupt Request portion of Interrupt Code"] + #[inline(always)] + #[must_use] + pub fn irq(&mut self) -> IrqW { + IrqW::new(self, 4) + } + #[doc = "Bits 5:7 - CAN Node Status"] + #[inline(always)] + #[must_use] + pub fn ns(&mut self) -> NsW { + NsW::new(self, 5) + } +} +#[doc = "CAN Status Pending Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cstpnd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cstpnd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CstpndSpec; +impl crate::RegisterSpec for CstpndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cstpnd::R`](R) reader structure"] +impl crate::Readable for CstpndSpec {} +#[doc = "`write(|w| ..)` method takes [`cstpnd::W`](W) writer structure"] +impl crate::Writable for CstpndSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CSTPND to value 0"] +impl crate::Resettable for CstpndSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/ctim.rs b/va416xx/src/can0/ctim.rs new file mode 100644 index 0000000..872f295 --- /dev/null +++ b/va416xx/src/can0/ctim.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CTIM` reader"] +pub type R = crate::R; +#[doc = "Register `CTIM` writer"] +pub type W = crate::W; +#[doc = "Field `TSEG2` reader - Time Segment 2"] +pub type Tseg2R = crate::FieldReader; +#[doc = "Field `TSEG2` writer - Time Segment 2"] +pub type Tseg2W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `TSEG1` reader - Time Segment 1"] +pub type Tseg1R = crate::FieldReader; +#[doc = "Field `TSEG1` writer - Time Segment 1"] +pub type Tseg1W<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SJW` reader - Synchronization Jump Width"] +pub type SjwR = crate::FieldReader; +#[doc = "Field `SJW` writer - Synchronization Jump Width"] +pub type SjwW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PSC` reader - Prescaler Configuration"] +pub type PscR = crate::FieldReader; +#[doc = "Field `PSC` writer - Prescaler Configuration"] +pub type PscW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:2 - Time Segment 2"] + #[inline(always)] + pub fn tseg2(&self) -> Tseg2R { + Tseg2R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:6 - Time Segment 1"] + #[inline(always)] + pub fn tseg1(&self) -> Tseg1R { + Tseg1R::new(((self.bits >> 3) & 0x0f) as u8) + } + #[doc = "Bits 7:8 - Synchronization Jump Width"] + #[inline(always)] + pub fn sjw(&self) -> SjwR { + SjwR::new(((self.bits >> 7) & 3) as u8) + } + #[doc = "Bits 9:15 - Prescaler Configuration"] + #[inline(always)] + pub fn psc(&self) -> PscR { + PscR::new(((self.bits >> 9) & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Time Segment 2"] + #[inline(always)] + #[must_use] + pub fn tseg2(&mut self) -> Tseg2W { + Tseg2W::new(self, 0) + } + #[doc = "Bits 3:6 - Time Segment 1"] + #[inline(always)] + #[must_use] + pub fn tseg1(&mut self) -> Tseg1W { + Tseg1W::new(self, 3) + } + #[doc = "Bits 7:8 - Synchronization Jump Width"] + #[inline(always)] + #[must_use] + pub fn sjw(&mut self) -> SjwW { + SjwW::new(self, 7) + } + #[doc = "Bits 9:15 - Prescaler Configuration"] + #[inline(always)] + #[must_use] + pub fn psc(&mut self) -> PscW { + PscW::new(self, 9) + } +} +#[doc = "CAN Timing Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctim::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctim::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtimSpec; +impl crate::RegisterSpec for CtimSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctim::R`](R) reader structure"] +impl crate::Readable for CtimSpec {} +#[doc = "`write(|w| ..)` method takes [`ctim::W`](W) writer structure"] +impl crate::Writable for CtimSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTIM to value 0"] +impl crate::Resettable for CtimSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/ctmr.rs b/va416xx/src/can0/ctmr.rs new file mode 100644 index 0000000..25cf22e --- /dev/null +++ b/va416xx/src/can0/ctmr.rs @@ -0,0 +1,31 @@ +#[doc = "Register `CTMR` reader"] +pub type R = crate::R; +#[doc = "Register `CTMR` writer"] +pub type W = crate::W; +#[doc = "Field `CTMR` reader - Time Stamp Counter"] +pub type CtmrR = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Time Stamp Counter"] + #[inline(always)] + pub fn ctmr(&self) -> CtmrR { + CtmrR::new((self.bits & 0xffff) as u16) + } +} +impl W {} +#[doc = "CAN Timer Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctmr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctmr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtmrSpec; +impl crate::RegisterSpec for CtmrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctmr::R`](R) reader structure"] +impl crate::Readable for CtmrSpec {} +#[doc = "`write(|w| ..)` method takes [`ctmr::W`](W) writer structure"] +impl crate::Writable for CtmrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTMR to value 0"] +impl crate::Resettable for CtmrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb0.rs b/va416xx/src/can0/data0_cmb0.rs new file mode 100644 index 0000000..29e0103 --- /dev/null +++ b/va416xx/src/can0/data0_cmb0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb0Spec; +impl crate::RegisterSpec for Data0Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb0::R`](R) reader structure"] +impl crate::Readable for Data0Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb0::W`](W) writer structure"] +impl crate::Writable for Data0Cmb0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB0 to value 0"] +impl crate::Resettable for Data0Cmb0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb1.rs b/va416xx/src/can0/data0_cmb1.rs new file mode 100644 index 0000000..2cb965f --- /dev/null +++ b/va416xx/src/can0/data0_cmb1.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb1Spec; +impl crate::RegisterSpec for Data0Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb1::R`](R) reader structure"] +impl crate::Readable for Data0Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb1::W`](W) writer structure"] +impl crate::Writable for Data0Cmb1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB1 to value 0"] +impl crate::Resettable for Data0Cmb1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb10.rs b/va416xx/src/can0/data0_cmb10.rs new file mode 100644 index 0000000..5c600d6 --- /dev/null +++ b/va416xx/src/can0/data0_cmb10.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb10Spec; +impl crate::RegisterSpec for Data0Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb10::R`](R) reader structure"] +impl crate::Readable for Data0Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb10::W`](W) writer structure"] +impl crate::Writable for Data0Cmb10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB10 to value 0"] +impl crate::Resettable for Data0Cmb10Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb11.rs b/va416xx/src/can0/data0_cmb11.rs new file mode 100644 index 0000000..307de43 --- /dev/null +++ b/va416xx/src/can0/data0_cmb11.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb11Spec; +impl crate::RegisterSpec for Data0Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb11::R`](R) reader structure"] +impl crate::Readable for Data0Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb11::W`](W) writer structure"] +impl crate::Writable for Data0Cmb11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB11 to value 0"] +impl crate::Resettable for Data0Cmb11Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb12.rs b/va416xx/src/can0/data0_cmb12.rs new file mode 100644 index 0000000..05292d6 --- /dev/null +++ b/va416xx/src/can0/data0_cmb12.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb12Spec; +impl crate::RegisterSpec for Data0Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb12::R`](R) reader structure"] +impl crate::Readable for Data0Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb12::W`](W) writer structure"] +impl crate::Writable for Data0Cmb12Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB12 to value 0"] +impl crate::Resettable for Data0Cmb12Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb13.rs b/va416xx/src/can0/data0_cmb13.rs new file mode 100644 index 0000000..22c6992 --- /dev/null +++ b/va416xx/src/can0/data0_cmb13.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb13Spec; +impl crate::RegisterSpec for Data0Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb13::R`](R) reader structure"] +impl crate::Readable for Data0Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb13::W`](W) writer structure"] +impl crate::Writable for Data0Cmb13Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB13 to value 0"] +impl crate::Resettable for Data0Cmb13Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb14.rs b/va416xx/src/can0/data0_cmb14.rs new file mode 100644 index 0000000..72026d5 --- /dev/null +++ b/va416xx/src/can0/data0_cmb14.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb14Spec; +impl crate::RegisterSpec for Data0Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb14::R`](R) reader structure"] +impl crate::Readable for Data0Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb14::W`](W) writer structure"] +impl crate::Writable for Data0Cmb14Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB14 to value 0"] +impl crate::Resettable for Data0Cmb14Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb2.rs b/va416xx/src/can0/data0_cmb2.rs new file mode 100644 index 0000000..b9823de --- /dev/null +++ b/va416xx/src/can0/data0_cmb2.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb2Spec; +impl crate::RegisterSpec for Data0Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb2::R`](R) reader structure"] +impl crate::Readable for Data0Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb2::W`](W) writer structure"] +impl crate::Writable for Data0Cmb2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB2 to value 0"] +impl crate::Resettable for Data0Cmb2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb3.rs b/va416xx/src/can0/data0_cmb3.rs new file mode 100644 index 0000000..488e04b --- /dev/null +++ b/va416xx/src/can0/data0_cmb3.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb3Spec; +impl crate::RegisterSpec for Data0Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb3::R`](R) reader structure"] +impl crate::Readable for Data0Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb3::W`](W) writer structure"] +impl crate::Writable for Data0Cmb3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB3 to value 0"] +impl crate::Resettable for Data0Cmb3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb4.rs b/va416xx/src/can0/data0_cmb4.rs new file mode 100644 index 0000000..8134f20 --- /dev/null +++ b/va416xx/src/can0/data0_cmb4.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb4Spec; +impl crate::RegisterSpec for Data0Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb4::R`](R) reader structure"] +impl crate::Readable for Data0Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb4::W`](W) writer structure"] +impl crate::Writable for Data0Cmb4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB4 to value 0"] +impl crate::Resettable for Data0Cmb4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb5.rs b/va416xx/src/can0/data0_cmb5.rs new file mode 100644 index 0000000..a0033fc --- /dev/null +++ b/va416xx/src/can0/data0_cmb5.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb5Spec; +impl crate::RegisterSpec for Data0Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb5::R`](R) reader structure"] +impl crate::Readable for Data0Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb5::W`](W) writer structure"] +impl crate::Writable for Data0Cmb5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB5 to value 0"] +impl crate::Resettable for Data0Cmb5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb6.rs b/va416xx/src/can0/data0_cmb6.rs new file mode 100644 index 0000000..2f8de4e --- /dev/null +++ b/va416xx/src/can0/data0_cmb6.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb6Spec; +impl crate::RegisterSpec for Data0Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb6::R`](R) reader structure"] +impl crate::Readable for Data0Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb6::W`](W) writer structure"] +impl crate::Writable for Data0Cmb6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB6 to value 0"] +impl crate::Resettable for Data0Cmb6Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb7.rs b/va416xx/src/can0/data0_cmb7.rs new file mode 100644 index 0000000..4734c91 --- /dev/null +++ b/va416xx/src/can0/data0_cmb7.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb7Spec; +impl crate::RegisterSpec for Data0Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb7::R`](R) reader structure"] +impl crate::Readable for Data0Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb7::W`](W) writer structure"] +impl crate::Writable for Data0Cmb7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB7 to value 0"] +impl crate::Resettable for Data0Cmb7Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb8.rs b/va416xx/src/can0/data0_cmb8.rs new file mode 100644 index 0000000..e1e2316 --- /dev/null +++ b/va416xx/src/can0/data0_cmb8.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb8Spec; +impl crate::RegisterSpec for Data0Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb8::R`](R) reader structure"] +impl crate::Readable for Data0Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb8::W`](W) writer structure"] +impl crate::Writable for Data0Cmb8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB8 to value 0"] +impl crate::Resettable for Data0Cmb8Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_cmb9.rs b/va416xx/src/can0/data0_cmb9.rs new file mode 100644 index 0000000..2d708bd --- /dev/null +++ b/va416xx/src/can0/data0_cmb9.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_cmb9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_cmb9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0Cmb9Spec; +impl crate::RegisterSpec for Data0Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_cmb9::R`](R) reader structure"] +impl crate::Readable for Data0Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`data0_cmb9::W`](W) writer structure"] +impl crate::Writable for Data0Cmb9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_CMB9 to value 0"] +impl crate::Resettable for Data0Cmb9Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data0_hcmb.rs b/va416xx/src/can0/data0_hcmb.rs new file mode 100644 index 0000000..4f96c9e --- /dev/null +++ b/va416xx/src/can0/data0_hcmb.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA0_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `DATA0_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE2` reader - Data Byte 2"] +pub type Byte2R = crate::FieldReader; +#[doc = "Field `BYTE2` writer - Data Byte 2"] +pub type Byte2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE1` reader - Data Byte 1"] +pub type Byte1R = crate::FieldReader; +#[doc = "Field `BYTE1` writer - Data Byte 1"] +pub type Byte1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + pub fn byte2(&self) -> Byte2R { + Byte2R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + pub fn byte1(&self) -> Byte1R { + Byte1R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 2"] + #[inline(always)] + #[must_use] + pub fn byte2(&mut self) -> Byte2W { + Byte2W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 1"] + #[inline(always)] + #[must_use] + pub fn byte1(&mut self) -> Byte1W { + Byte1W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data0_hcmb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data0_hcmb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data0HcmbSpec; +impl crate::RegisterSpec for Data0HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data0_hcmb::R`](R) reader structure"] +impl crate::Readable for Data0HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`data0_hcmb::W`](W) writer structure"] +impl crate::Writable for Data0HcmbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA0_HCMB to value 0"] +impl crate::Resettable for Data0HcmbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb0.rs b/va416xx/src/can0/data1_cmb0.rs new file mode 100644 index 0000000..7fb354d --- /dev/null +++ b/va416xx/src/can0/data1_cmb0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb0Spec; +impl crate::RegisterSpec for Data1Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb0::R`](R) reader structure"] +impl crate::Readable for Data1Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb0::W`](W) writer structure"] +impl crate::Writable for Data1Cmb0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB0 to value 0"] +impl crate::Resettable for Data1Cmb0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb1.rs b/va416xx/src/can0/data1_cmb1.rs new file mode 100644 index 0000000..a3f1842 --- /dev/null +++ b/va416xx/src/can0/data1_cmb1.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb1Spec; +impl crate::RegisterSpec for Data1Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb1::R`](R) reader structure"] +impl crate::Readable for Data1Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb1::W`](W) writer structure"] +impl crate::Writable for Data1Cmb1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB1 to value 0"] +impl crate::Resettable for Data1Cmb1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb10.rs b/va416xx/src/can0/data1_cmb10.rs new file mode 100644 index 0000000..25fca4d --- /dev/null +++ b/va416xx/src/can0/data1_cmb10.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb10Spec; +impl crate::RegisterSpec for Data1Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb10::R`](R) reader structure"] +impl crate::Readable for Data1Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb10::W`](W) writer structure"] +impl crate::Writable for Data1Cmb10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB10 to value 0"] +impl crate::Resettable for Data1Cmb10Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb11.rs b/va416xx/src/can0/data1_cmb11.rs new file mode 100644 index 0000000..62ef6af --- /dev/null +++ b/va416xx/src/can0/data1_cmb11.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb11Spec; +impl crate::RegisterSpec for Data1Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb11::R`](R) reader structure"] +impl crate::Readable for Data1Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb11::W`](W) writer structure"] +impl crate::Writable for Data1Cmb11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB11 to value 0"] +impl crate::Resettable for Data1Cmb11Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb12.rs b/va416xx/src/can0/data1_cmb12.rs new file mode 100644 index 0000000..248930f --- /dev/null +++ b/va416xx/src/can0/data1_cmb12.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb12Spec; +impl crate::RegisterSpec for Data1Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb12::R`](R) reader structure"] +impl crate::Readable for Data1Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb12::W`](W) writer structure"] +impl crate::Writable for Data1Cmb12Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB12 to value 0"] +impl crate::Resettable for Data1Cmb12Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb13.rs b/va416xx/src/can0/data1_cmb13.rs new file mode 100644 index 0000000..da85ae6 --- /dev/null +++ b/va416xx/src/can0/data1_cmb13.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb13Spec; +impl crate::RegisterSpec for Data1Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb13::R`](R) reader structure"] +impl crate::Readable for Data1Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb13::W`](W) writer structure"] +impl crate::Writable for Data1Cmb13Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB13 to value 0"] +impl crate::Resettable for Data1Cmb13Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb14.rs b/va416xx/src/can0/data1_cmb14.rs new file mode 100644 index 0000000..67b0621 --- /dev/null +++ b/va416xx/src/can0/data1_cmb14.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb14Spec; +impl crate::RegisterSpec for Data1Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb14::R`](R) reader structure"] +impl crate::Readable for Data1Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb14::W`](W) writer structure"] +impl crate::Writable for Data1Cmb14Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB14 to value 0"] +impl crate::Resettable for Data1Cmb14Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb2.rs b/va416xx/src/can0/data1_cmb2.rs new file mode 100644 index 0000000..9c0f91e --- /dev/null +++ b/va416xx/src/can0/data1_cmb2.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb2Spec; +impl crate::RegisterSpec for Data1Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb2::R`](R) reader structure"] +impl crate::Readable for Data1Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb2::W`](W) writer structure"] +impl crate::Writable for Data1Cmb2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB2 to value 0"] +impl crate::Resettable for Data1Cmb2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb3.rs b/va416xx/src/can0/data1_cmb3.rs new file mode 100644 index 0000000..eb07213 --- /dev/null +++ b/va416xx/src/can0/data1_cmb3.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb3Spec; +impl crate::RegisterSpec for Data1Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb3::R`](R) reader structure"] +impl crate::Readable for Data1Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb3::W`](W) writer structure"] +impl crate::Writable for Data1Cmb3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB3 to value 0"] +impl crate::Resettable for Data1Cmb3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb4.rs b/va416xx/src/can0/data1_cmb4.rs new file mode 100644 index 0000000..1ed478d --- /dev/null +++ b/va416xx/src/can0/data1_cmb4.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb4Spec; +impl crate::RegisterSpec for Data1Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb4::R`](R) reader structure"] +impl crate::Readable for Data1Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb4::W`](W) writer structure"] +impl crate::Writable for Data1Cmb4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB4 to value 0"] +impl crate::Resettable for Data1Cmb4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb5.rs b/va416xx/src/can0/data1_cmb5.rs new file mode 100644 index 0000000..4673b81 --- /dev/null +++ b/va416xx/src/can0/data1_cmb5.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb5Spec; +impl crate::RegisterSpec for Data1Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb5::R`](R) reader structure"] +impl crate::Readable for Data1Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb5::W`](W) writer structure"] +impl crate::Writable for Data1Cmb5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB5 to value 0"] +impl crate::Resettable for Data1Cmb5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb6.rs b/va416xx/src/can0/data1_cmb6.rs new file mode 100644 index 0000000..860282a --- /dev/null +++ b/va416xx/src/can0/data1_cmb6.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb6Spec; +impl crate::RegisterSpec for Data1Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb6::R`](R) reader structure"] +impl crate::Readable for Data1Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb6::W`](W) writer structure"] +impl crate::Writable for Data1Cmb6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB6 to value 0"] +impl crate::Resettable for Data1Cmb6Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb7.rs b/va416xx/src/can0/data1_cmb7.rs new file mode 100644 index 0000000..e45c47c --- /dev/null +++ b/va416xx/src/can0/data1_cmb7.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb7Spec; +impl crate::RegisterSpec for Data1Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb7::R`](R) reader structure"] +impl crate::Readable for Data1Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb7::W`](W) writer structure"] +impl crate::Writable for Data1Cmb7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB7 to value 0"] +impl crate::Resettable for Data1Cmb7Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb8.rs b/va416xx/src/can0/data1_cmb8.rs new file mode 100644 index 0000000..d3dc3cf --- /dev/null +++ b/va416xx/src/can0/data1_cmb8.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb8Spec; +impl crate::RegisterSpec for Data1Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb8::R`](R) reader structure"] +impl crate::Readable for Data1Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb8::W`](W) writer structure"] +impl crate::Writable for Data1Cmb8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB8 to value 0"] +impl crate::Resettable for Data1Cmb8Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_cmb9.rs b/va416xx/src/can0/data1_cmb9.rs new file mode 100644 index 0000000..ae5ea13 --- /dev/null +++ b/va416xx/src/can0/data1_cmb9.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_cmb9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_cmb9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1Cmb9Spec; +impl crate::RegisterSpec for Data1Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_cmb9::R`](R) reader structure"] +impl crate::Readable for Data1Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`data1_cmb9::W`](W) writer structure"] +impl crate::Writable for Data1Cmb9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_CMB9 to value 0"] +impl crate::Resettable for Data1Cmb9Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data1_hcmb.rs b/va416xx/src/can0/data1_hcmb.rs new file mode 100644 index 0000000..f8dcded --- /dev/null +++ b/va416xx/src/can0/data1_hcmb.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA1_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `DATA1_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE4` reader - Data Byte 4"] +pub type Byte4R = crate::FieldReader; +#[doc = "Field `BYTE4` writer - Data Byte 4"] +pub type Byte4W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE3` reader - Data Byte 3"] +pub type Byte3R = crate::FieldReader; +#[doc = "Field `BYTE3` writer - Data Byte 3"] +pub type Byte3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + pub fn byte4(&self) -> Byte4R { + Byte4R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + pub fn byte3(&self) -> Byte3R { + Byte3R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 4"] + #[inline(always)] + #[must_use] + pub fn byte4(&mut self) -> Byte4W { + Byte4W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 3"] + #[inline(always)] + #[must_use] + pub fn byte3(&mut self) -> Byte3W { + Byte3W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data1_hcmb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data1_hcmb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data1HcmbSpec; +impl crate::RegisterSpec for Data1HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data1_hcmb::R`](R) reader structure"] +impl crate::Readable for Data1HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`data1_hcmb::W`](W) writer structure"] +impl crate::Writable for Data1HcmbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA1_HCMB to value 0"] +impl crate::Resettable for Data1HcmbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb0.rs b/va416xx/src/can0/data2_cmb0.rs new file mode 100644 index 0000000..80d924d --- /dev/null +++ b/va416xx/src/can0/data2_cmb0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb0Spec; +impl crate::RegisterSpec for Data2Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb0::R`](R) reader structure"] +impl crate::Readable for Data2Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb0::W`](W) writer structure"] +impl crate::Writable for Data2Cmb0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB0 to value 0"] +impl crate::Resettable for Data2Cmb0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb1.rs b/va416xx/src/can0/data2_cmb1.rs new file mode 100644 index 0000000..404ca8c --- /dev/null +++ b/va416xx/src/can0/data2_cmb1.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb1Spec; +impl crate::RegisterSpec for Data2Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb1::R`](R) reader structure"] +impl crate::Readable for Data2Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb1::W`](W) writer structure"] +impl crate::Writable for Data2Cmb1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB1 to value 0"] +impl crate::Resettable for Data2Cmb1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb10.rs b/va416xx/src/can0/data2_cmb10.rs new file mode 100644 index 0000000..2d96d4b --- /dev/null +++ b/va416xx/src/can0/data2_cmb10.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb10Spec; +impl crate::RegisterSpec for Data2Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb10::R`](R) reader structure"] +impl crate::Readable for Data2Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb10::W`](W) writer structure"] +impl crate::Writable for Data2Cmb10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB10 to value 0"] +impl crate::Resettable for Data2Cmb10Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb11.rs b/va416xx/src/can0/data2_cmb11.rs new file mode 100644 index 0000000..338d3e5 --- /dev/null +++ b/va416xx/src/can0/data2_cmb11.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb11Spec; +impl crate::RegisterSpec for Data2Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb11::R`](R) reader structure"] +impl crate::Readable for Data2Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb11::W`](W) writer structure"] +impl crate::Writable for Data2Cmb11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB11 to value 0"] +impl crate::Resettable for Data2Cmb11Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb12.rs b/va416xx/src/can0/data2_cmb12.rs new file mode 100644 index 0000000..6fe89e8 --- /dev/null +++ b/va416xx/src/can0/data2_cmb12.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb12Spec; +impl crate::RegisterSpec for Data2Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb12::R`](R) reader structure"] +impl crate::Readable for Data2Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb12::W`](W) writer structure"] +impl crate::Writable for Data2Cmb12Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB12 to value 0"] +impl crate::Resettable for Data2Cmb12Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb13.rs b/va416xx/src/can0/data2_cmb13.rs new file mode 100644 index 0000000..2ee2bb7 --- /dev/null +++ b/va416xx/src/can0/data2_cmb13.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb13Spec; +impl crate::RegisterSpec for Data2Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb13::R`](R) reader structure"] +impl crate::Readable for Data2Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb13::W`](W) writer structure"] +impl crate::Writable for Data2Cmb13Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB13 to value 0"] +impl crate::Resettable for Data2Cmb13Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb14.rs b/va416xx/src/can0/data2_cmb14.rs new file mode 100644 index 0000000..ff9ee97 --- /dev/null +++ b/va416xx/src/can0/data2_cmb14.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb14Spec; +impl crate::RegisterSpec for Data2Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb14::R`](R) reader structure"] +impl crate::Readable for Data2Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb14::W`](W) writer structure"] +impl crate::Writable for Data2Cmb14Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB14 to value 0"] +impl crate::Resettable for Data2Cmb14Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb2.rs b/va416xx/src/can0/data2_cmb2.rs new file mode 100644 index 0000000..4cd31dd --- /dev/null +++ b/va416xx/src/can0/data2_cmb2.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb2Spec; +impl crate::RegisterSpec for Data2Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb2::R`](R) reader structure"] +impl crate::Readable for Data2Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb2::W`](W) writer structure"] +impl crate::Writable for Data2Cmb2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB2 to value 0"] +impl crate::Resettable for Data2Cmb2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb3.rs b/va416xx/src/can0/data2_cmb3.rs new file mode 100644 index 0000000..2511577 --- /dev/null +++ b/va416xx/src/can0/data2_cmb3.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb3Spec; +impl crate::RegisterSpec for Data2Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb3::R`](R) reader structure"] +impl crate::Readable for Data2Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb3::W`](W) writer structure"] +impl crate::Writable for Data2Cmb3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB3 to value 0"] +impl crate::Resettable for Data2Cmb3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb4.rs b/va416xx/src/can0/data2_cmb4.rs new file mode 100644 index 0000000..9a2deef --- /dev/null +++ b/va416xx/src/can0/data2_cmb4.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb4Spec; +impl crate::RegisterSpec for Data2Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb4::R`](R) reader structure"] +impl crate::Readable for Data2Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb4::W`](W) writer structure"] +impl crate::Writable for Data2Cmb4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB4 to value 0"] +impl crate::Resettable for Data2Cmb4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb5.rs b/va416xx/src/can0/data2_cmb5.rs new file mode 100644 index 0000000..1a94329 --- /dev/null +++ b/va416xx/src/can0/data2_cmb5.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb5Spec; +impl crate::RegisterSpec for Data2Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb5::R`](R) reader structure"] +impl crate::Readable for Data2Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb5::W`](W) writer structure"] +impl crate::Writable for Data2Cmb5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB5 to value 0"] +impl crate::Resettable for Data2Cmb5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb6.rs b/va416xx/src/can0/data2_cmb6.rs new file mode 100644 index 0000000..ea2ed85 --- /dev/null +++ b/va416xx/src/can0/data2_cmb6.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb6Spec; +impl crate::RegisterSpec for Data2Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb6::R`](R) reader structure"] +impl crate::Readable for Data2Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb6::W`](W) writer structure"] +impl crate::Writable for Data2Cmb6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB6 to value 0"] +impl crate::Resettable for Data2Cmb6Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb7.rs b/va416xx/src/can0/data2_cmb7.rs new file mode 100644 index 0000000..da5cea5 --- /dev/null +++ b/va416xx/src/can0/data2_cmb7.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb7Spec; +impl crate::RegisterSpec for Data2Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb7::R`](R) reader structure"] +impl crate::Readable for Data2Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb7::W`](W) writer structure"] +impl crate::Writable for Data2Cmb7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB7 to value 0"] +impl crate::Resettable for Data2Cmb7Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb8.rs b/va416xx/src/can0/data2_cmb8.rs new file mode 100644 index 0000000..4c956f6 --- /dev/null +++ b/va416xx/src/can0/data2_cmb8.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb8Spec; +impl crate::RegisterSpec for Data2Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb8::R`](R) reader structure"] +impl crate::Readable for Data2Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb8::W`](W) writer structure"] +impl crate::Writable for Data2Cmb8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB8 to value 0"] +impl crate::Resettable for Data2Cmb8Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_cmb9.rs b/va416xx/src/can0/data2_cmb9.rs new file mode 100644 index 0000000..3076b3e --- /dev/null +++ b/va416xx/src/can0/data2_cmb9.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_cmb9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_cmb9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2Cmb9Spec; +impl crate::RegisterSpec for Data2Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_cmb9::R`](R) reader structure"] +impl crate::Readable for Data2Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`data2_cmb9::W`](W) writer structure"] +impl crate::Writable for Data2Cmb9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_CMB9 to value 0"] +impl crate::Resettable for Data2Cmb9Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data2_hcmb.rs b/va416xx/src/can0/data2_hcmb.rs new file mode 100644 index 0000000..2d43337 --- /dev/null +++ b/va416xx/src/can0/data2_hcmb.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA2_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `DATA2_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE6` reader - Data Byte 6"] +pub type Byte6R = crate::FieldReader; +#[doc = "Field `BYTE6` writer - Data Byte 6"] +pub type Byte6W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE5` reader - Data Byte 5"] +pub type Byte5R = crate::FieldReader; +#[doc = "Field `BYTE5` writer - Data Byte 5"] +pub type Byte5W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + pub fn byte6(&self) -> Byte6R { + Byte6R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + pub fn byte5(&self) -> Byte5R { + Byte5R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 6"] + #[inline(always)] + #[must_use] + pub fn byte6(&mut self) -> Byte6W { + Byte6W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 5"] + #[inline(always)] + #[must_use] + pub fn byte5(&mut self) -> Byte5W { + Byte5W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data2_hcmb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data2_hcmb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data2HcmbSpec; +impl crate::RegisterSpec for Data2HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data2_hcmb::R`](R) reader structure"] +impl crate::Readable for Data2HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`data2_hcmb::W`](W) writer structure"] +impl crate::Writable for Data2HcmbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA2_HCMB to value 0"] +impl crate::Resettable for Data2HcmbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb0.rs b/va416xx/src/can0/data3_cmb0.rs new file mode 100644 index 0000000..5cec7bc --- /dev/null +++ b/va416xx/src/can0/data3_cmb0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb0Spec; +impl crate::RegisterSpec for Data3Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb0::R`](R) reader structure"] +impl crate::Readable for Data3Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb0::W`](W) writer structure"] +impl crate::Writable for Data3Cmb0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB0 to value 0"] +impl crate::Resettable for Data3Cmb0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb1.rs b/va416xx/src/can0/data3_cmb1.rs new file mode 100644 index 0000000..6240a1c --- /dev/null +++ b/va416xx/src/can0/data3_cmb1.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb1Spec; +impl crate::RegisterSpec for Data3Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb1::R`](R) reader structure"] +impl crate::Readable for Data3Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb1::W`](W) writer structure"] +impl crate::Writable for Data3Cmb1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB1 to value 0"] +impl crate::Resettable for Data3Cmb1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb10.rs b/va416xx/src/can0/data3_cmb10.rs new file mode 100644 index 0000000..bc817b6 --- /dev/null +++ b/va416xx/src/can0/data3_cmb10.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb10Spec; +impl crate::RegisterSpec for Data3Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb10::R`](R) reader structure"] +impl crate::Readable for Data3Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb10::W`](W) writer structure"] +impl crate::Writable for Data3Cmb10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB10 to value 0"] +impl crate::Resettable for Data3Cmb10Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb11.rs b/va416xx/src/can0/data3_cmb11.rs new file mode 100644 index 0000000..f5722aa --- /dev/null +++ b/va416xx/src/can0/data3_cmb11.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb11Spec; +impl crate::RegisterSpec for Data3Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb11::R`](R) reader structure"] +impl crate::Readable for Data3Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb11::W`](W) writer structure"] +impl crate::Writable for Data3Cmb11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB11 to value 0"] +impl crate::Resettable for Data3Cmb11Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb12.rs b/va416xx/src/can0/data3_cmb12.rs new file mode 100644 index 0000000..d830d5f --- /dev/null +++ b/va416xx/src/can0/data3_cmb12.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb12Spec; +impl crate::RegisterSpec for Data3Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb12::R`](R) reader structure"] +impl crate::Readable for Data3Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb12::W`](W) writer structure"] +impl crate::Writable for Data3Cmb12Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB12 to value 0"] +impl crate::Resettable for Data3Cmb12Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb13.rs b/va416xx/src/can0/data3_cmb13.rs new file mode 100644 index 0000000..3d3c30c --- /dev/null +++ b/va416xx/src/can0/data3_cmb13.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb13Spec; +impl crate::RegisterSpec for Data3Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb13::R`](R) reader structure"] +impl crate::Readable for Data3Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb13::W`](W) writer structure"] +impl crate::Writable for Data3Cmb13Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB13 to value 0"] +impl crate::Resettable for Data3Cmb13Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb14.rs b/va416xx/src/can0/data3_cmb14.rs new file mode 100644 index 0000000..446f136 --- /dev/null +++ b/va416xx/src/can0/data3_cmb14.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb14Spec; +impl crate::RegisterSpec for Data3Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb14::R`](R) reader structure"] +impl crate::Readable for Data3Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb14::W`](W) writer structure"] +impl crate::Writable for Data3Cmb14Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB14 to value 0"] +impl crate::Resettable for Data3Cmb14Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb2.rs b/va416xx/src/can0/data3_cmb2.rs new file mode 100644 index 0000000..780bd99 --- /dev/null +++ b/va416xx/src/can0/data3_cmb2.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb2Spec; +impl crate::RegisterSpec for Data3Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb2::R`](R) reader structure"] +impl crate::Readable for Data3Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb2::W`](W) writer structure"] +impl crate::Writable for Data3Cmb2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB2 to value 0"] +impl crate::Resettable for Data3Cmb2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb3.rs b/va416xx/src/can0/data3_cmb3.rs new file mode 100644 index 0000000..7d4a05b --- /dev/null +++ b/va416xx/src/can0/data3_cmb3.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb3Spec; +impl crate::RegisterSpec for Data3Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb3::R`](R) reader structure"] +impl crate::Readable for Data3Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb3::W`](W) writer structure"] +impl crate::Writable for Data3Cmb3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB3 to value 0"] +impl crate::Resettable for Data3Cmb3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb4.rs b/va416xx/src/can0/data3_cmb4.rs new file mode 100644 index 0000000..8b09d6b --- /dev/null +++ b/va416xx/src/can0/data3_cmb4.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb4Spec; +impl crate::RegisterSpec for Data3Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb4::R`](R) reader structure"] +impl crate::Readable for Data3Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb4::W`](W) writer structure"] +impl crate::Writable for Data3Cmb4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB4 to value 0"] +impl crate::Resettable for Data3Cmb4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb5.rs b/va416xx/src/can0/data3_cmb5.rs new file mode 100644 index 0000000..b686f5b --- /dev/null +++ b/va416xx/src/can0/data3_cmb5.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb5Spec; +impl crate::RegisterSpec for Data3Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb5::R`](R) reader structure"] +impl crate::Readable for Data3Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb5::W`](W) writer structure"] +impl crate::Writable for Data3Cmb5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB5 to value 0"] +impl crate::Resettable for Data3Cmb5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb6.rs b/va416xx/src/can0/data3_cmb6.rs new file mode 100644 index 0000000..6cfb1b7 --- /dev/null +++ b/va416xx/src/can0/data3_cmb6.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb6Spec; +impl crate::RegisterSpec for Data3Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb6::R`](R) reader structure"] +impl crate::Readable for Data3Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb6::W`](W) writer structure"] +impl crate::Writable for Data3Cmb6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB6 to value 0"] +impl crate::Resettable for Data3Cmb6Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb7.rs b/va416xx/src/can0/data3_cmb7.rs new file mode 100644 index 0000000..2b594bf --- /dev/null +++ b/va416xx/src/can0/data3_cmb7.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb7Spec; +impl crate::RegisterSpec for Data3Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb7::R`](R) reader structure"] +impl crate::Readable for Data3Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb7::W`](W) writer structure"] +impl crate::Writable for Data3Cmb7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB7 to value 0"] +impl crate::Resettable for Data3Cmb7Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb8.rs b/va416xx/src/can0/data3_cmb8.rs new file mode 100644 index 0000000..c2e0ecc --- /dev/null +++ b/va416xx/src/can0/data3_cmb8.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb8Spec; +impl crate::RegisterSpec for Data3Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb8::R`](R) reader structure"] +impl crate::Readable for Data3Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb8::W`](W) writer structure"] +impl crate::Writable for Data3Cmb8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB8 to value 0"] +impl crate::Resettable for Data3Cmb8Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_cmb9.rs b/va416xx/src/can0/data3_cmb9.rs new file mode 100644 index 0000000..716ae39 --- /dev/null +++ b/va416xx/src/can0/data3_cmb9.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_cmb9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_cmb9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3Cmb9Spec; +impl crate::RegisterSpec for Data3Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_cmb9::R`](R) reader structure"] +impl crate::Readable for Data3Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`data3_cmb9::W`](W) writer structure"] +impl crate::Writable for Data3Cmb9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_CMB9 to value 0"] +impl crate::Resettable for Data3Cmb9Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/data3_hcmb.rs b/va416xx/src/can0/data3_hcmb.rs new file mode 100644 index 0000000..856e651 --- /dev/null +++ b/va416xx/src/can0/data3_hcmb.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DATA3_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `DATA3_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `BYTE8` reader - Data Byte 8"] +pub type Byte8R = crate::FieldReader; +#[doc = "Field `BYTE8` writer - Data Byte 8"] +pub type Byte8W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `BYTE7` reader - Data Byte 7"] +pub type Byte7R = crate::FieldReader; +#[doc = "Field `BYTE7` writer - Data Byte 7"] +pub type Byte7W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + pub fn byte8(&self) -> Byte8R { + Byte8R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + pub fn byte7(&self) -> Byte7R { + Byte7R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Data Byte 8"] + #[inline(always)] + #[must_use] + pub fn byte8(&mut self) -> Byte8W { + Byte8W::new(self, 0) + } + #[doc = "Bits 8:15 - Data Byte 7"] + #[inline(always)] + #[must_use] + pub fn byte7(&mut self) -> Byte7W { + Byte7W::new(self, 8) + } +} +#[doc = "CAN Frame Data Word 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data3_hcmb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data3_hcmb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Data3HcmbSpec; +impl crate::RegisterSpec for Data3HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data3_hcmb::R`](R) reader structure"] +impl crate::Readable for Data3HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`data3_hcmb::W`](W) writer structure"] +impl crate::Writable for Data3HcmbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA3_HCMB to value 0"] +impl crate::Resettable for Data3HcmbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/gmskb.rs b/va416xx/src/can0/gmskb.rs new file mode 100644 index 0000000..aa511c5 --- /dev/null +++ b/va416xx/src/can0/gmskb.rs @@ -0,0 +1,105 @@ +#[doc = "Register `GMSKB` reader"] +pub type R = crate::R; +#[doc = "Register `GMSKB` writer"] +pub type W = crate::W; +#[doc = "Field `GM0` reader - GM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] +pub type Gm0R = crate::FieldReader; +#[doc = "Field `GM0` writer - GM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] +pub type Gm0W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IDE` reader - Identifier Extension Bit"] +pub type IdeR = crate::BitReader; +#[doc = "Field `IDE` writer - Identifier Extension Bit"] +pub type IdeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTR` reader - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub type RtrR = crate::BitReader; +#[doc = "Field `RTR` writer - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] +pub type RtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GM1` reader - GM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] +pub type Gm1R = crate::FieldReader; +#[doc = "Field `GM1` writer - GM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] +pub type Gm1W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +impl R { + #[doc = "Bits 0:2 - GM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] + #[inline(always)] + pub fn gm0(&self) -> Gm0R { + Gm0R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + pub fn ide(&self) -> IdeR { + IdeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + pub fn rtr(&self) -> RtrR { + RtrR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:15 - GM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] + #[inline(always)] + pub fn gm1(&self) -> Gm1R { + Gm1R::new(((self.bits >> 5) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - GM\\[17:15\\] +- Unused in standard, ID\\[17:15\\] +in extended"] + #[inline(always)] + #[must_use] + pub fn gm0(&mut self) -> Gm0W { + Gm0W::new(self, 0) + } + #[doc = "Bit 3 - Identifier Extension Bit"] + #[inline(always)] + #[must_use] + pub fn ide(&mut self) -> IdeW { + IdeW::new(self, 3) + } + #[doc = "Bit 4 - Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended"] + #[inline(always)] + #[must_use] + pub fn rtr(&mut self) -> RtrW { + RtrW::new(self, 4) + } + #[doc = "Bits 5:15 - GM\\[28:18\\] +- ID\\[10:0\\] +in standard, ID\\[28:18\\] +in extended"] + #[inline(always)] + #[must_use] + pub fn gm1(&mut self) -> Gm1W { + Gm1W::new(self, 5) + } +} +#[doc = "CAN Global Mask Base\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmskb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmskb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GmskbSpec; +impl crate::RegisterSpec for GmskbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmskb::R`](R) reader structure"] +impl crate::Readable for GmskbSpec {} +#[doc = "`write(|w| ..)` method takes [`gmskb::W`](W) writer structure"] +impl crate::Writable for GmskbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GMSKB to value 0"] +impl crate::Resettable for GmskbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/gmskx.rs b/va416xx/src/can0/gmskx.rs new file mode 100644 index 0000000..073346a --- /dev/null +++ b/va416xx/src/can0/gmskx.rs @@ -0,0 +1,63 @@ +#[doc = "Register `GMSKX` reader"] +pub type R = crate::R; +#[doc = "Register `GMSKX` writer"] +pub type W = crate::W; +#[doc = "Field `XRTR` reader - Extended Remote transmission Request Bit"] +pub type XrtrR = crate::BitReader; +#[doc = "Field `XRTR` writer - Extended Remote transmission Request Bit"] +pub type XrtrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GM` reader - GM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] +pub type GmR = crate::FieldReader; +#[doc = "Field `GM` writer - GM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] +pub type GmW<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>; +impl R { + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + pub fn xrtr(&self) -> XrtrR { + XrtrR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:15 - GM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] + #[inline(always)] + pub fn gm(&self) -> GmR { + GmR::new(((self.bits >> 1) & 0x7fff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Extended Remote transmission Request Bit"] + #[inline(always)] + #[must_use] + pub fn xrtr(&mut self) -> XrtrW { + XrtrW::new(self, 0) + } + #[doc = "Bits 1:15 - GM\\[14:0\\] +used when an extended frame is received. ID\\[14:0\\] +in extended, unused standard"] + #[inline(always)] + #[must_use] + pub fn gm(&mut self) -> GmW { + GmW::new(self, 1) + } +} +#[doc = "CAN Global Mask Extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gmskx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gmskx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct GmskxSpec; +impl crate::RegisterSpec for GmskxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`gmskx::R`](R) reader structure"] +impl crate::Readable for GmskxSpec {} +#[doc = "`write(|w| ..)` method takes [`gmskx::W`](W) writer structure"] +impl crate::Writable for GmskxSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets GMSKX to value 0"] +impl crate::Resettable for GmskxSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb0.rs b/va416xx/src/can0/id0_cmb0.rs new file mode 100644 index 0000000..23d87ab --- /dev/null +++ b/va416xx/src/can0/id0_cmb0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb0Spec; +impl crate::RegisterSpec for Id0Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb0::R`](R) reader structure"] +impl crate::Readable for Id0Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb0::W`](W) writer structure"] +impl crate::Writable for Id0Cmb0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB0 to value 0"] +impl crate::Resettable for Id0Cmb0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb1.rs b/va416xx/src/can0/id0_cmb1.rs new file mode 100644 index 0000000..5cc65f9 --- /dev/null +++ b/va416xx/src/can0/id0_cmb1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb1Spec; +impl crate::RegisterSpec for Id0Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb1::R`](R) reader structure"] +impl crate::Readable for Id0Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb1::W`](W) writer structure"] +impl crate::Writable for Id0Cmb1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB1 to value 0"] +impl crate::Resettable for Id0Cmb1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb10.rs b/va416xx/src/can0/id0_cmb10.rs new file mode 100644 index 0000000..b62d30a --- /dev/null +++ b/va416xx/src/can0/id0_cmb10.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb10Spec; +impl crate::RegisterSpec for Id0Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb10::R`](R) reader structure"] +impl crate::Readable for Id0Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb10::W`](W) writer structure"] +impl crate::Writable for Id0Cmb10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB10 to value 0"] +impl crate::Resettable for Id0Cmb10Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb11.rs b/va416xx/src/can0/id0_cmb11.rs new file mode 100644 index 0000000..4f27d5a --- /dev/null +++ b/va416xx/src/can0/id0_cmb11.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb11Spec; +impl crate::RegisterSpec for Id0Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb11::R`](R) reader structure"] +impl crate::Readable for Id0Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb11::W`](W) writer structure"] +impl crate::Writable for Id0Cmb11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB11 to value 0"] +impl crate::Resettable for Id0Cmb11Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb12.rs b/va416xx/src/can0/id0_cmb12.rs new file mode 100644 index 0000000..af7eeee --- /dev/null +++ b/va416xx/src/can0/id0_cmb12.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb12Spec; +impl crate::RegisterSpec for Id0Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb12::R`](R) reader structure"] +impl crate::Readable for Id0Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb12::W`](W) writer structure"] +impl crate::Writable for Id0Cmb12Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB12 to value 0"] +impl crate::Resettable for Id0Cmb12Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb13.rs b/va416xx/src/can0/id0_cmb13.rs new file mode 100644 index 0000000..5d01253 --- /dev/null +++ b/va416xx/src/can0/id0_cmb13.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb13Spec; +impl crate::RegisterSpec for Id0Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb13::R`](R) reader structure"] +impl crate::Readable for Id0Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb13::W`](W) writer structure"] +impl crate::Writable for Id0Cmb13Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB13 to value 0"] +impl crate::Resettable for Id0Cmb13Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb14.rs b/va416xx/src/can0/id0_cmb14.rs new file mode 100644 index 0000000..e9a71e1 --- /dev/null +++ b/va416xx/src/can0/id0_cmb14.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb14Spec; +impl crate::RegisterSpec for Id0Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb14::R`](R) reader structure"] +impl crate::Readable for Id0Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb14::W`](W) writer structure"] +impl crate::Writable for Id0Cmb14Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB14 to value 0"] +impl crate::Resettable for Id0Cmb14Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb2.rs b/va416xx/src/can0/id0_cmb2.rs new file mode 100644 index 0000000..0ed74fe --- /dev/null +++ b/va416xx/src/can0/id0_cmb2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb2Spec; +impl crate::RegisterSpec for Id0Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb2::R`](R) reader structure"] +impl crate::Readable for Id0Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb2::W`](W) writer structure"] +impl crate::Writable for Id0Cmb2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB2 to value 0"] +impl crate::Resettable for Id0Cmb2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb3.rs b/va416xx/src/can0/id0_cmb3.rs new file mode 100644 index 0000000..ac8a485 --- /dev/null +++ b/va416xx/src/can0/id0_cmb3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb3Spec; +impl crate::RegisterSpec for Id0Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb3::R`](R) reader structure"] +impl crate::Readable for Id0Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb3::W`](W) writer structure"] +impl crate::Writable for Id0Cmb3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB3 to value 0"] +impl crate::Resettable for Id0Cmb3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb4.rs b/va416xx/src/can0/id0_cmb4.rs new file mode 100644 index 0000000..2bddfff --- /dev/null +++ b/va416xx/src/can0/id0_cmb4.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb4Spec; +impl crate::RegisterSpec for Id0Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb4::R`](R) reader structure"] +impl crate::Readable for Id0Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb4::W`](W) writer structure"] +impl crate::Writable for Id0Cmb4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB4 to value 0"] +impl crate::Resettable for Id0Cmb4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb5.rs b/va416xx/src/can0/id0_cmb5.rs new file mode 100644 index 0000000..cd231e9 --- /dev/null +++ b/va416xx/src/can0/id0_cmb5.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb5Spec; +impl crate::RegisterSpec for Id0Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb5::R`](R) reader structure"] +impl crate::Readable for Id0Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb5::W`](W) writer structure"] +impl crate::Writable for Id0Cmb5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB5 to value 0"] +impl crate::Resettable for Id0Cmb5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb6.rs b/va416xx/src/can0/id0_cmb6.rs new file mode 100644 index 0000000..68a4c87 --- /dev/null +++ b/va416xx/src/can0/id0_cmb6.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb6Spec; +impl crate::RegisterSpec for Id0Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb6::R`](R) reader structure"] +impl crate::Readable for Id0Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb6::W`](W) writer structure"] +impl crate::Writable for Id0Cmb6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB6 to value 0"] +impl crate::Resettable for Id0Cmb6Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb7.rs b/va416xx/src/can0/id0_cmb7.rs new file mode 100644 index 0000000..4fe879e --- /dev/null +++ b/va416xx/src/can0/id0_cmb7.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb7Spec; +impl crate::RegisterSpec for Id0Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb7::R`](R) reader structure"] +impl crate::Readable for Id0Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb7::W`](W) writer structure"] +impl crate::Writable for Id0Cmb7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB7 to value 0"] +impl crate::Resettable for Id0Cmb7Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb8.rs b/va416xx/src/can0/id0_cmb8.rs new file mode 100644 index 0000000..728ae98 --- /dev/null +++ b/va416xx/src/can0/id0_cmb8.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb8Spec; +impl crate::RegisterSpec for Id0Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb8::R`](R) reader structure"] +impl crate::Readable for Id0Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb8::W`](W) writer structure"] +impl crate::Writable for Id0Cmb8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB8 to value 0"] +impl crate::Resettable for Id0Cmb8Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_cmb9.rs b/va416xx/src/can0/id0_cmb9.rs new file mode 100644 index 0000000..cf74967 --- /dev/null +++ b/va416xx/src/can0/id0_cmb9.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_cmb9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_cmb9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0Cmb9Spec; +impl crate::RegisterSpec for Id0Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_cmb9::R`](R) reader structure"] +impl crate::Readable for Id0Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`id0_cmb9::W`](W) writer structure"] +impl crate::Writable for Id0Cmb9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_CMB9 to value 0"] +impl crate::Resettable for Id0Cmb9Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id0_hcmb.rs b/va416xx/src/can0/id0_hcmb.rs new file mode 100644 index 0000000..23cf589 --- /dev/null +++ b/va416xx/src/can0/id0_hcmb.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID0_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `ID0_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `ID0` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0R = crate::FieldReader; +#[doc = "Field `ID0` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id0W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id0(&self) -> Id0R { + Id0R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id0(&mut self) -> Id0W { + Id0W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id0_hcmb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id0_hcmb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id0HcmbSpec; +impl crate::RegisterSpec for Id0HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id0_hcmb::R`](R) reader structure"] +impl crate::Readable for Id0HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`id0_hcmb::W`](W) writer structure"] +impl crate::Writable for Id0HcmbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID0_HCMB to value 0"] +impl crate::Resettable for Id0HcmbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb0.rs b/va416xx/src/can0/id1_cmb0.rs new file mode 100644 index 0000000..ffa77ae --- /dev/null +++ b/va416xx/src/can0/id1_cmb0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb0Spec; +impl crate::RegisterSpec for Id1Cmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb0::R`](R) reader structure"] +impl crate::Readable for Id1Cmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb0::W`](W) writer structure"] +impl crate::Writable for Id1Cmb0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB0 to value 0"] +impl crate::Resettable for Id1Cmb0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb1.rs b/va416xx/src/can0/id1_cmb1.rs new file mode 100644 index 0000000..0e38078 --- /dev/null +++ b/va416xx/src/can0/id1_cmb1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb1Spec; +impl crate::RegisterSpec for Id1Cmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb1::R`](R) reader structure"] +impl crate::Readable for Id1Cmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb1::W`](W) writer structure"] +impl crate::Writable for Id1Cmb1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB1 to value 0"] +impl crate::Resettable for Id1Cmb1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb10.rs b/va416xx/src/can0/id1_cmb10.rs new file mode 100644 index 0000000..6818e63 --- /dev/null +++ b/va416xx/src/can0/id1_cmb10.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb10Spec; +impl crate::RegisterSpec for Id1Cmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb10::R`](R) reader structure"] +impl crate::Readable for Id1Cmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb10::W`](W) writer structure"] +impl crate::Writable for Id1Cmb10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB10 to value 0"] +impl crate::Resettable for Id1Cmb10Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb11.rs b/va416xx/src/can0/id1_cmb11.rs new file mode 100644 index 0000000..09163cf --- /dev/null +++ b/va416xx/src/can0/id1_cmb11.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb11Spec; +impl crate::RegisterSpec for Id1Cmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb11::R`](R) reader structure"] +impl crate::Readable for Id1Cmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb11::W`](W) writer structure"] +impl crate::Writable for Id1Cmb11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB11 to value 0"] +impl crate::Resettable for Id1Cmb11Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb12.rs b/va416xx/src/can0/id1_cmb12.rs new file mode 100644 index 0000000..39a5596 --- /dev/null +++ b/va416xx/src/can0/id1_cmb12.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb12Spec; +impl crate::RegisterSpec for Id1Cmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb12::R`](R) reader structure"] +impl crate::Readable for Id1Cmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb12::W`](W) writer structure"] +impl crate::Writable for Id1Cmb12Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB12 to value 0"] +impl crate::Resettable for Id1Cmb12Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb13.rs b/va416xx/src/can0/id1_cmb13.rs new file mode 100644 index 0000000..6bba934 --- /dev/null +++ b/va416xx/src/can0/id1_cmb13.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb13Spec; +impl crate::RegisterSpec for Id1Cmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb13::R`](R) reader structure"] +impl crate::Readable for Id1Cmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb13::W`](W) writer structure"] +impl crate::Writable for Id1Cmb13Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB13 to value 0"] +impl crate::Resettable for Id1Cmb13Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb14.rs b/va416xx/src/can0/id1_cmb14.rs new file mode 100644 index 0000000..547d7b3 --- /dev/null +++ b/va416xx/src/can0/id1_cmb14.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb14Spec; +impl crate::RegisterSpec for Id1Cmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb14::R`](R) reader structure"] +impl crate::Readable for Id1Cmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb14::W`](W) writer structure"] +impl crate::Writable for Id1Cmb14Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB14 to value 0"] +impl crate::Resettable for Id1Cmb14Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb2.rs b/va416xx/src/can0/id1_cmb2.rs new file mode 100644 index 0000000..502124b --- /dev/null +++ b/va416xx/src/can0/id1_cmb2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb2Spec; +impl crate::RegisterSpec for Id1Cmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb2::R`](R) reader structure"] +impl crate::Readable for Id1Cmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb2::W`](W) writer structure"] +impl crate::Writable for Id1Cmb2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB2 to value 0"] +impl crate::Resettable for Id1Cmb2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb3.rs b/va416xx/src/can0/id1_cmb3.rs new file mode 100644 index 0000000..318cf16 --- /dev/null +++ b/va416xx/src/can0/id1_cmb3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb3Spec; +impl crate::RegisterSpec for Id1Cmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb3::R`](R) reader structure"] +impl crate::Readable for Id1Cmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb3::W`](W) writer structure"] +impl crate::Writable for Id1Cmb3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB3 to value 0"] +impl crate::Resettable for Id1Cmb3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb4.rs b/va416xx/src/can0/id1_cmb4.rs new file mode 100644 index 0000000..cc20409 --- /dev/null +++ b/va416xx/src/can0/id1_cmb4.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb4Spec; +impl crate::RegisterSpec for Id1Cmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb4::R`](R) reader structure"] +impl crate::Readable for Id1Cmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb4::W`](W) writer structure"] +impl crate::Writable for Id1Cmb4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB4 to value 0"] +impl crate::Resettable for Id1Cmb4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb5.rs b/va416xx/src/can0/id1_cmb5.rs new file mode 100644 index 0000000..bc9f997 --- /dev/null +++ b/va416xx/src/can0/id1_cmb5.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb5Spec; +impl crate::RegisterSpec for Id1Cmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb5::R`](R) reader structure"] +impl crate::Readable for Id1Cmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb5::W`](W) writer structure"] +impl crate::Writable for Id1Cmb5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB5 to value 0"] +impl crate::Resettable for Id1Cmb5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb6.rs b/va416xx/src/can0/id1_cmb6.rs new file mode 100644 index 0000000..4a7f601 --- /dev/null +++ b/va416xx/src/can0/id1_cmb6.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb6Spec; +impl crate::RegisterSpec for Id1Cmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb6::R`](R) reader structure"] +impl crate::Readable for Id1Cmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb6::W`](W) writer structure"] +impl crate::Writable for Id1Cmb6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB6 to value 0"] +impl crate::Resettable for Id1Cmb6Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb7.rs b/va416xx/src/can0/id1_cmb7.rs new file mode 100644 index 0000000..0f96f36 --- /dev/null +++ b/va416xx/src/can0/id1_cmb7.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb7Spec; +impl crate::RegisterSpec for Id1Cmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb7::R`](R) reader structure"] +impl crate::Readable for Id1Cmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb7::W`](W) writer structure"] +impl crate::Writable for Id1Cmb7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB7 to value 0"] +impl crate::Resettable for Id1Cmb7Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb8.rs b/va416xx/src/can0/id1_cmb8.rs new file mode 100644 index 0000000..e6d7ad6 --- /dev/null +++ b/va416xx/src/can0/id1_cmb8.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb8Spec; +impl crate::RegisterSpec for Id1Cmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb8::R`](R) reader structure"] +impl crate::Readable for Id1Cmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb8::W`](W) writer structure"] +impl crate::Writable for Id1Cmb8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB8 to value 0"] +impl crate::Resettable for Id1Cmb8Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_cmb9.rs b/va416xx/src/can0/id1_cmb9.rs new file mode 100644 index 0000000..2a9a3d4 --- /dev/null +++ b/va416xx/src/can0/id1_cmb9.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_cmb9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_cmb9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1Cmb9Spec; +impl crate::RegisterSpec for Id1Cmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_cmb9::R`](R) reader structure"] +impl crate::Readable for Id1Cmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`id1_cmb9::W`](W) writer structure"] +impl crate::Writable for Id1Cmb9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_CMB9 to value 0"] +impl crate::Resettable for Id1Cmb9Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/id1_hcmb.rs b/va416xx/src/can0/id1_hcmb.rs new file mode 100644 index 0000000..ba61e23 --- /dev/null +++ b/va416xx/src/can0/id1_hcmb.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ID1_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `ID1_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `ID1` reader - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1R = crate::FieldReader; +#[doc = "Field `ID1` writer - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] +pub type Id1W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + pub fn id1(&self) -> Id1R { + Id1R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Half of CAN Frame ID. Format Varies for Standard or Extended Frames"] + #[inline(always)] + #[must_use] + pub fn id1(&mut self) -> Id1W { + Id1W::new(self, 0) + } +} +#[doc = "CAN Frame Identifier Word 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`id1_hcmb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`id1_hcmb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Id1HcmbSpec; +impl crate::RegisterSpec for Id1HcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`id1_hcmb::R`](R) reader structure"] +impl crate::Readable for Id1HcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`id1_hcmb::W`](W) writer structure"] +impl crate::Writable for Id1HcmbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ID1_HCMB to value 0"] +impl crate::Resettable for Id1HcmbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb0.rs b/va416xx/src/can0/tstp_cmb0.rs new file mode 100644 index 0000000..eeccb9a --- /dev/null +++ b/va416xx/src/can0/tstp_cmb0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB0` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB0` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb0Spec; +impl crate::RegisterSpec for TstpCmb0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb0::R`](R) reader structure"] +impl crate::Readable for TstpCmb0Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb0::W`](W) writer structure"] +impl crate::Writable for TstpCmb0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB0 to value 0"] +impl crate::Resettable for TstpCmb0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb1.rs b/va416xx/src/can0/tstp_cmb1.rs new file mode 100644 index 0000000..30d5381 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB1` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB1` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb1Spec; +impl crate::RegisterSpec for TstpCmb1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb1::R`](R) reader structure"] +impl crate::Readable for TstpCmb1Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb1::W`](W) writer structure"] +impl crate::Writable for TstpCmb1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB1 to value 0"] +impl crate::Resettable for TstpCmb1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb10.rs b/va416xx/src/can0/tstp_cmb10.rs new file mode 100644 index 0000000..eb337d0 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb10.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB10` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB10` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb10Spec; +impl crate::RegisterSpec for TstpCmb10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb10::R`](R) reader structure"] +impl crate::Readable for TstpCmb10Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb10::W`](W) writer structure"] +impl crate::Writable for TstpCmb10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB10 to value 0"] +impl crate::Resettable for TstpCmb10Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb11.rs b/va416xx/src/can0/tstp_cmb11.rs new file mode 100644 index 0000000..75aee4e --- /dev/null +++ b/va416xx/src/can0/tstp_cmb11.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB11` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB11` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb11::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb11::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb11Spec; +impl crate::RegisterSpec for TstpCmb11Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb11::R`](R) reader structure"] +impl crate::Readable for TstpCmb11Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb11::W`](W) writer structure"] +impl crate::Writable for TstpCmb11Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB11 to value 0"] +impl crate::Resettable for TstpCmb11Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb12.rs b/va416xx/src/can0/tstp_cmb12.rs new file mode 100644 index 0000000..80091b8 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb12.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB12` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB12` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb12::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb12::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb12Spec; +impl crate::RegisterSpec for TstpCmb12Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb12::R`](R) reader structure"] +impl crate::Readable for TstpCmb12Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb12::W`](W) writer structure"] +impl crate::Writable for TstpCmb12Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB12 to value 0"] +impl crate::Resettable for TstpCmb12Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb13.rs b/va416xx/src/can0/tstp_cmb13.rs new file mode 100644 index 0000000..4974938 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb13.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB13` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB13` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb13::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb13::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb13Spec; +impl crate::RegisterSpec for TstpCmb13Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb13::R`](R) reader structure"] +impl crate::Readable for TstpCmb13Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb13::W`](W) writer structure"] +impl crate::Writable for TstpCmb13Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB13 to value 0"] +impl crate::Resettable for TstpCmb13Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb14.rs b/va416xx/src/can0/tstp_cmb14.rs new file mode 100644 index 0000000..29617e8 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb14.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB14` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB14` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb14::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb14::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb14Spec; +impl crate::RegisterSpec for TstpCmb14Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb14::R`](R) reader structure"] +impl crate::Readable for TstpCmb14Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb14::W`](W) writer structure"] +impl crate::Writable for TstpCmb14Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB14 to value 0"] +impl crate::Resettable for TstpCmb14Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb2.rs b/va416xx/src/can0/tstp_cmb2.rs new file mode 100644 index 0000000..a1693c4 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB2` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB2` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb2Spec; +impl crate::RegisterSpec for TstpCmb2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb2::R`](R) reader structure"] +impl crate::Readable for TstpCmb2Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb2::W`](W) writer structure"] +impl crate::Writable for TstpCmb2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB2 to value 0"] +impl crate::Resettable for TstpCmb2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb3.rs b/va416xx/src/can0/tstp_cmb3.rs new file mode 100644 index 0000000..a2be4b0 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB3` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB3` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb3Spec; +impl crate::RegisterSpec for TstpCmb3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb3::R`](R) reader structure"] +impl crate::Readable for TstpCmb3Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb3::W`](W) writer structure"] +impl crate::Writable for TstpCmb3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB3 to value 0"] +impl crate::Resettable for TstpCmb3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb4.rs b/va416xx/src/can0/tstp_cmb4.rs new file mode 100644 index 0000000..8ddf61c --- /dev/null +++ b/va416xx/src/can0/tstp_cmb4.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB4` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB4` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb4Spec; +impl crate::RegisterSpec for TstpCmb4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb4::R`](R) reader structure"] +impl crate::Readable for TstpCmb4Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb4::W`](W) writer structure"] +impl crate::Writable for TstpCmb4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB4 to value 0"] +impl crate::Resettable for TstpCmb4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb5.rs b/va416xx/src/can0/tstp_cmb5.rs new file mode 100644 index 0000000..5680928 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb5.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB5` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB5` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb5Spec; +impl crate::RegisterSpec for TstpCmb5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb5::R`](R) reader structure"] +impl crate::Readable for TstpCmb5Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb5::W`](W) writer structure"] +impl crate::Writable for TstpCmb5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB5 to value 0"] +impl crate::Resettable for TstpCmb5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb6.rs b/va416xx/src/can0/tstp_cmb6.rs new file mode 100644 index 0000000..3571ef6 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb6.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB6` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB6` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb6Spec; +impl crate::RegisterSpec for TstpCmb6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb6::R`](R) reader structure"] +impl crate::Readable for TstpCmb6Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb6::W`](W) writer structure"] +impl crate::Writable for TstpCmb6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB6 to value 0"] +impl crate::Resettable for TstpCmb6Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb7.rs b/va416xx/src/can0/tstp_cmb7.rs new file mode 100644 index 0000000..ff7a103 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb7.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB7` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB7` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb7Spec; +impl crate::RegisterSpec for TstpCmb7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb7::R`](R) reader structure"] +impl crate::Readable for TstpCmb7Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb7::W`](W) writer structure"] +impl crate::Writable for TstpCmb7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB7 to value 0"] +impl crate::Resettable for TstpCmb7Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb8.rs b/va416xx/src/can0/tstp_cmb8.rs new file mode 100644 index 0000000..45c0699 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb8.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB8` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB8` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb8::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb8::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb8Spec; +impl crate::RegisterSpec for TstpCmb8Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb8::R`](R) reader structure"] +impl crate::Readable for TstpCmb8Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb8::W`](W) writer structure"] +impl crate::Writable for TstpCmb8Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB8 to value 0"] +impl crate::Resettable for TstpCmb8Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_cmb9.rs b/va416xx/src/can0/tstp_cmb9.rs new file mode 100644 index 0000000..c527458 --- /dev/null +++ b/va416xx/src/can0/tstp_cmb9.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_CMB9` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_CMB9` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_cmb9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_cmb9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpCmb9Spec; +impl crate::RegisterSpec for TstpCmb9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_cmb9::R`](R) reader structure"] +impl crate::Readable for TstpCmb9Spec {} +#[doc = "`write(|w| ..)` method takes [`tstp_cmb9::W`](W) writer structure"] +impl crate::Writable for TstpCmb9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_CMB9 to value 0"] +impl crate::Resettable for TstpCmb9Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/can0/tstp_hcmb.rs b/va416xx/src/can0/tstp_hcmb.rs new file mode 100644 index 0000000..1629d2b --- /dev/null +++ b/va416xx/src/can0/tstp_hcmb.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TSTP_HCMB` reader"] +pub type R = crate::R; +#[doc = "Register `TSTP_HCMB` writer"] +pub type W = crate::W; +#[doc = "Field `TIMESTAMP` reader - Timestamp"] +pub type TimestampR = crate::FieldReader; +#[doc = "Field `TIMESTAMP` writer - Timestamp"] +pub type TimestampW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + pub fn timestamp(&self) -> TimestampR { + TimestampR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - Timestamp"] + #[inline(always)] + #[must_use] + pub fn timestamp(&mut self) -> TimestampW { + TimestampW::new(self, 0) + } +} +#[doc = "CAN Frame Timestamp\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tstp_hcmb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tstp_hcmb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TstpHcmbSpec; +impl crate::RegisterSpec for TstpHcmbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tstp_hcmb::R`](R) reader structure"] +impl crate::Readable for TstpHcmbSpec {} +#[doc = "`write(|w| ..)` method takes [`tstp_hcmb::W`](W) writer structure"] +impl crate::Writable for TstpHcmbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TSTP_HCMB to value 0"] +impl crate::Resettable for TstpHcmbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/clkgen.rs b/va416xx/src/clkgen.rs new file mode 100644 index 0000000..1a6e589 --- /dev/null +++ b/va416xx/src/clkgen.rs @@ -0,0 +1,42 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl0: Ctrl0, + stat: Stat, + ctrl1: Ctrl1, +} +impl RegisterBlock { + #[doc = "0x00 - Clock Generation Module Control Register 0"] + #[inline(always)] + pub const fn ctrl0(&self) -> &Ctrl0 { + &self.ctrl0 + } + #[doc = "0x04 - Clock Generation Module Status Register"] + #[inline(always)] + pub const fn stat(&self) -> &Stat { + &self.stat + } + #[doc = "0x08 - Clock Generation Module Control Register 1"] + #[inline(always)] + pub const fn ctrl1(&self) -> &Ctrl1 { + &self.ctrl1 + } +} +#[doc = "CTRL0 (rw) register accessor: Clock Generation Module Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] +module"] +#[doc(alias = "CTRL0")] +pub type Ctrl0 = crate::Reg; +#[doc = "Clock Generation Module Control Register 0"] +pub mod ctrl0; +#[doc = "STAT (r) register accessor: Clock Generation Module Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`] +module"] +#[doc(alias = "STAT")] +pub type Stat = crate::Reg; +#[doc = "Clock Generation Module Status Register"] +pub mod stat; +#[doc = "CTRL1 (rw) register accessor: Clock Generation Module Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] +module"] +#[doc(alias = "CTRL1")] +pub type Ctrl1 = crate::Reg; +#[doc = "Clock Generation Module Control Register 1"] +pub mod ctrl1; diff --git a/va416xx/src/clkgen/ctrl0.rs b/va416xx/src/clkgen/ctrl0.rs new file mode 100644 index 0000000..5bb8d9d --- /dev/null +++ b/va416xx/src/clkgen/ctrl0.rs @@ -0,0 +1,220 @@ +#[doc = "Register `CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `REF_CLK_SEL` reader - PLL Reference Clock Select"] +pub type RefClkSelR = crate::FieldReader; +#[doc = "Field `REF_CLK_SEL` writer - PLL Reference Clock Select"] +pub type RefClkSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `CLKSEL_SYS` reader - Input clock select to PLL"] +pub type ClkselSysR = crate::FieldReader; +#[doc = "Field `CLKSEL_SYS` writer - Input clock select to PLL"] +pub type ClkselSysW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PLL_INTFB` reader - PLL Symbol; select internal feedback path when high rather than FCLK"] +pub type PllIntfbR = crate::BitReader; +#[doc = "Field `PLL_INTFB` writer - PLL Symbol; select internal feedback path when high rather than FCLK"] +pub type PllIntfbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_PWDN` reader - PLL Symbol; power down when high"] +pub type PllPwdnR = crate::BitReader; +#[doc = "Field `PLL_PWDN` writer - PLL Symbol; power down when high"] +pub type PllPwdnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_BYPASS` reader - PLL Symbol; reference-to-output bypass when high"] +pub type PllBypassR = crate::BitReader; +#[doc = "Field `PLL_BYPASS` writer - PLL Symbol; reference-to-output bypass when high"] +pub type PllBypassW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_TEST` reader - PLL Symbol; Reference-to-counters-to-output bypass when high"] +pub type PllTestR = crate::BitReader; +#[doc = "Field `PLL_TEST` writer - PLL Symbol; Reference-to-counters-to-output bypass when high"] +pub type PllTestW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_BWADJ` reader - PLL Symbol; selects the values 1-64 for the bandwidth divider"] +pub type PllBwadjR = crate::FieldReader; +#[doc = "Field `PLL_BWADJ` writer - PLL Symbol; selects the values 1-64 for the bandwidth divider"] +pub type PllBwadjW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PLL_CLKOD` reader - PLL Symbol; selects the values 1-16 for the post VCO divider"] +pub type PllClkodR = crate::FieldReader; +#[doc = "Field `PLL_CLKOD` writer - PLL Symbol; selects the values 1-16 for the post VCO divider"] +pub type PllClkodW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `PLL_CLKF` reader - PLL Symbol; selects the values 1-64 for the multiplication factor"] +pub type PllClkfR = crate::FieldReader; +#[doc = "Field `PLL_CLKF` writer - PLL Symbol; selects the values 1-64 for the multiplication factor"] +pub type PllClkfW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PLL_CLKR` reader - PLL Symbol; selects the values 1-16 for the reference divider"] +pub type PllClkrR = crate::FieldReader; +#[doc = "Field `PLL_CLKR` writer - PLL Symbol; selects the values 1-16 for the reference divider"] +pub type PllClkrW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `CLK_DIV_SEL` reader - Selects the PLL out divider to divide by 1/2/4/8"] +pub type ClkDivSelR = crate::FieldReader; +#[doc = "Field `CLK_DIV_SEL` writer - Selects the PLL out divider to divide by 1/2/4/8"] +pub type ClkDivSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `PLL_RESET` reader - Writing this bit to 1 puts the PLL into reset"] +pub type PllResetR = crate::BitReader; +#[doc = "Field `PLL_RESET` writer - Writing this bit to 1 puts the PLL into reset"] +pub type PllResetW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYS_CLK_LOST_DET_EN` reader - Enable the circuit that detects loss of SYS_CLK"] +pub type SysClkLostDetEnR = crate::BitReader; +#[doc = "Field `SYS_CLK_LOST_DET_EN` writer - Enable the circuit that detects loss of SYS_CLK"] +pub type SysClkLostDetEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - PLL Reference Clock Select"] + #[inline(always)] + pub fn ref_clk_sel(&self) -> RefClkSelR { + RefClkSelR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Input clock select to PLL"] + #[inline(always)] + pub fn clksel_sys(&self) -> ClkselSysR { + ClkselSysR::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - PLL Symbol; select internal feedback path when high rather than FCLK"] + #[inline(always)] + pub fn pll_intfb(&self) -> PllIntfbR { + PllIntfbR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - PLL Symbol; power down when high"] + #[inline(always)] + pub fn pll_pwdn(&self) -> PllPwdnR { + PllPwdnR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - PLL Symbol; reference-to-output bypass when high"] + #[inline(always)] + pub fn pll_bypass(&self) -> PllBypassR { + PllBypassR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - PLL Symbol; Reference-to-counters-to-output bypass when high"] + #[inline(always)] + pub fn pll_test(&self) -> PllTestR { + PllTestR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:13 - PLL Symbol; selects the values 1-64 for the bandwidth divider"] + #[inline(always)] + pub fn pll_bwadj(&self) -> PllBwadjR { + PllBwadjR::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 14:17 - PLL Symbol; selects the values 1-16 for the post VCO divider"] + #[inline(always)] + pub fn pll_clkod(&self) -> PllClkodR { + PllClkodR::new(((self.bits >> 14) & 0x0f) as u8) + } + #[doc = "Bits 18:23 - PLL Symbol; selects the values 1-64 for the multiplication factor"] + #[inline(always)] + pub fn pll_clkf(&self) -> PllClkfR { + PllClkfR::new(((self.bits >> 18) & 0x3f) as u8) + } + #[doc = "Bits 24:27 - PLL Symbol; selects the values 1-16 for the reference divider"] + #[inline(always)] + pub fn pll_clkr(&self) -> PllClkrR { + PllClkrR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:29 - Selects the PLL out divider to divide by 1/2/4/8"] + #[inline(always)] + pub fn clk_div_sel(&self) -> ClkDivSelR { + ClkDivSelR::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bit 30 - Writing this bit to 1 puts the PLL into reset"] + #[inline(always)] + pub fn pll_reset(&self) -> PllResetR { + PllResetR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Enable the circuit that detects loss of SYS_CLK"] + #[inline(always)] + pub fn sys_clk_lost_det_en(&self) -> SysClkLostDetEnR { + SysClkLostDetEnR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - PLL Reference Clock Select"] + #[inline(always)] + #[must_use] + pub fn ref_clk_sel(&mut self) -> RefClkSelW { + RefClkSelW::new(self, 0) + } + #[doc = "Bits 2:3 - Input clock select to PLL"] + #[inline(always)] + #[must_use] + pub fn clksel_sys(&mut self) -> ClkselSysW { + ClkselSysW::new(self, 2) + } + #[doc = "Bit 4 - PLL Symbol; select internal feedback path when high rather than FCLK"] + #[inline(always)] + #[must_use] + pub fn pll_intfb(&mut self) -> PllIntfbW { + PllIntfbW::new(self, 4) + } + #[doc = "Bit 5 - PLL Symbol; power down when high"] + #[inline(always)] + #[must_use] + pub fn pll_pwdn(&mut self) -> PllPwdnW { + PllPwdnW::new(self, 5) + } + #[doc = "Bit 6 - PLL Symbol; reference-to-output bypass when high"] + #[inline(always)] + #[must_use] + pub fn pll_bypass(&mut self) -> PllBypassW { + PllBypassW::new(self, 6) + } + #[doc = "Bit 7 - PLL Symbol; Reference-to-counters-to-output bypass when high"] + #[inline(always)] + #[must_use] + pub fn pll_test(&mut self) -> PllTestW { + PllTestW::new(self, 7) + } + #[doc = "Bits 8:13 - PLL Symbol; selects the values 1-64 for the bandwidth divider"] + #[inline(always)] + #[must_use] + pub fn pll_bwadj(&mut self) -> PllBwadjW { + PllBwadjW::new(self, 8) + } + #[doc = "Bits 14:17 - PLL Symbol; selects the values 1-16 for the post VCO divider"] + #[inline(always)] + #[must_use] + pub fn pll_clkod(&mut self) -> PllClkodW { + PllClkodW::new(self, 14) + } + #[doc = "Bits 18:23 - PLL Symbol; selects the values 1-64 for the multiplication factor"] + #[inline(always)] + #[must_use] + pub fn pll_clkf(&mut self) -> PllClkfW { + PllClkfW::new(self, 18) + } + #[doc = "Bits 24:27 - PLL Symbol; selects the values 1-16 for the reference divider"] + #[inline(always)] + #[must_use] + pub fn pll_clkr(&mut self) -> PllClkrW { + PllClkrW::new(self, 24) + } + #[doc = "Bits 28:29 - Selects the PLL out divider to divide by 1/2/4/8"] + #[inline(always)] + #[must_use] + pub fn clk_div_sel(&mut self) -> ClkDivSelW { + ClkDivSelW::new(self, 28) + } + #[doc = "Bit 30 - Writing this bit to 1 puts the PLL into reset"] + #[inline(always)] + #[must_use] + pub fn pll_reset(&mut self) -> PllResetW { + PllResetW::new(self, 30) + } + #[doc = "Bit 31 - Enable the circuit that detects loss of SYS_CLK"] + #[inline(always)] + #[must_use] + pub fn sys_clk_lost_det_en(&mut self) -> SysClkLostDetEnW { + SysClkLostDetEnW::new(self, 31) + } +} +#[doc = "Clock Generation Module Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl0Spec; +impl crate::RegisterSpec for Ctrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"] +impl crate::Readable for Ctrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"] +impl crate::Writable for Ctrl0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL0 to value 0x30"] +impl crate::Resettable for Ctrl0Spec { + const RESET_VALUE: u32 = 0x30; +} diff --git a/va416xx/src/clkgen/ctrl1.rs b/va416xx/src/clkgen/ctrl1.rs new file mode 100644 index 0000000..a9340d9 --- /dev/null +++ b/va416xx/src/clkgen/ctrl1.rs @@ -0,0 +1,115 @@ +#[doc = "Register `CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `SYS_CLK_LOST_DET_REARM` reader - Resets/Rearms the SYS_CLK lost detection feature"] +pub type SysClkLostDetRearmR = crate::BitReader; +#[doc = "Field `SYS_CLK_LOST_DET_REARM` writer - Resets/Rearms the SYS_CLK lost detection feature"] +pub type SysClkLostDetRearmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_LCK_DET_REARM` reader - Resets/Rearms the PLL lock detect circuit"] +pub type PllLckDetRearmR = crate::BitReader; +#[doc = "Field `PLL_LCK_DET_REARM` writer - Resets/Rearms the PLL lock detect circuit"] +pub type PllLckDetRearmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLL_LOST_LOCK_DET_EN` reader - Enables the PLL lock lost detection circuit"] +pub type PllLostLockDetEnR = crate::BitReader; +#[doc = "Field `PLL_LOST_LOCK_DET_EN` writer - Enables the PLL lock lost detection circuit"] +pub type PllLostLockDetEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XTAL_EN` reader - Enables the crystal oscillator"] +pub type XtalEnR = crate::BitReader; +#[doc = "Field `XTAL_EN` writer - Enables the crystal oscillator"] +pub type XtalEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `XTAL_N_EN` reader - Enables XTAL_N output"] +pub type XtalNEnR = crate::BitReader; +#[doc = "Field `XTAL_N_EN` writer - Enables XTAL_N output"] +pub type XtalNEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC_CLK_DIV_SEL` reader - Clock divider select for ADC"] +pub type AdcClkDivSelR = crate::FieldReader; +#[doc = "Field `ADC_CLK_DIV_SEL` writer - Clock divider select for ADC"] +pub type AdcClkDivSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - Resets/Rearms the SYS_CLK lost detection feature"] + #[inline(always)] + pub fn sys_clk_lost_det_rearm(&self) -> SysClkLostDetRearmR { + SysClkLostDetRearmR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Resets/Rearms the PLL lock detect circuit"] + #[inline(always)] + pub fn pll_lck_det_rearm(&self) -> PllLckDetRearmR { + PllLckDetRearmR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables the PLL lock lost detection circuit"] + #[inline(always)] + pub fn pll_lost_lock_det_en(&self) -> PllLostLockDetEnR { + PllLostLockDetEnR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables the crystal oscillator"] + #[inline(always)] + pub fn xtal_en(&self) -> XtalEnR { + XtalEnR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enables XTAL_N output"] + #[inline(always)] + pub fn xtal_n_en(&self) -> XtalNEnR { + XtalNEnR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Clock divider select for ADC"] + #[inline(always)] + pub fn adc_clk_div_sel(&self) -> AdcClkDivSelR { + AdcClkDivSelR::new(((self.bits >> 5) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Resets/Rearms the SYS_CLK lost detection feature"] + #[inline(always)] + #[must_use] + pub fn sys_clk_lost_det_rearm(&mut self) -> SysClkLostDetRearmW { + SysClkLostDetRearmW::new(self, 0) + } + #[doc = "Bit 1 - Resets/Rearms the PLL lock detect circuit"] + #[inline(always)] + #[must_use] + pub fn pll_lck_det_rearm(&mut self) -> PllLckDetRearmW { + PllLckDetRearmW::new(self, 1) + } + #[doc = "Bit 2 - Enables the PLL lock lost detection circuit"] + #[inline(always)] + #[must_use] + pub fn pll_lost_lock_det_en(&mut self) -> PllLostLockDetEnW { + PllLostLockDetEnW::new(self, 2) + } + #[doc = "Bit 3 - Enables the crystal oscillator"] + #[inline(always)] + #[must_use] + pub fn xtal_en(&mut self) -> XtalEnW { + XtalEnW::new(self, 3) + } + #[doc = "Bit 4 - Enables XTAL_N output"] + #[inline(always)] + #[must_use] + pub fn xtal_n_en(&mut self) -> XtalNEnW { + XtalNEnW::new(self, 4) + } + #[doc = "Bits 5:6 - Clock divider select for ADC"] + #[inline(always)] + #[must_use] + pub fn adc_clk_div_sel(&mut self) -> AdcClkDivSelW { + AdcClkDivSelW::new(self, 5) + } +} +#[doc = "Clock Generation Module Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl1Spec; +impl crate::RegisterSpec for Ctrl1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"] +impl crate::Readable for Ctrl1Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"] +impl crate::Writable for Ctrl1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for Ctrl1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/clkgen/stat.rs b/va416xx/src/clkgen/stat.rs new file mode 100644 index 0000000..fb89886 --- /dev/null +++ b/va416xx/src/clkgen/stat.rs @@ -0,0 +1,43 @@ +#[doc = "Register `STAT` reader"] +pub type R = crate::R; +#[doc = "Field `FBSLIP` reader - Feedback cycle slip output (CLKOUT frequency low)"] +pub type FbslipR = crate::BitReader; +#[doc = "Field `RFSLIP` reader - Reference cycle slip output (CLKOUT frequency high)"] +pub type RfslipR = crate::BitReader; +#[doc = "Field `LOCKLOST` reader - LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles"] +pub type LocklostR = crate::BitReader; +#[doc = "Field `SYSCLKLOST` reader - Set when SYS_CLK has dropped to less than 1MHz"] +pub type SysclklostR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Feedback cycle slip output (CLKOUT frequency low)"] + #[inline(always)] + pub fn fbslip(&self) -> FbslipR { + FbslipR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Reference cycle slip output (CLKOUT frequency high)"] + #[inline(always)] + pub fn rfslip(&self) -> RfslipR { + RfslipR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles"] + #[inline(always)] + pub fn locklost(&self) -> LocklostR { + LocklostR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Set when SYS_CLK has dropped to less than 1MHz"] + #[inline(always)] + pub fn sysclklost(&self) -> SysclklostR { + SysclklostR::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Clock Generation Module Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatSpec; +impl crate::RegisterSpec for StatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`stat::R`](R) reader structure"] +impl crate::Readable for StatSpec {} +#[doc = "`reset()` method sets STAT to value 0"] +impl crate::Resettable for StatSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dac0.rs b/va416xx/src/dac0.rs new file mode 100644 index 0000000..8ca0bd1 --- /dev/null +++ b/va416xx/src/dac0.rs @@ -0,0 +1,139 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl0: Ctrl0, + ctrl1: Ctrl1, + fifo_data: FifoData, + status: Status, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + txfifoirqtrg: Txfifoirqtrg, + fifo_clr: FifoClr, + _reserved10: [u8; 0x07d4], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register 0"] + #[inline(always)] + pub const fn ctrl0(&self) -> &Ctrl0 { + &self.ctrl0 + } + #[doc = "0x04 - Control Register 1"] + #[inline(always)] + pub const fn ctrl1(&self) -> &Ctrl1 { + &self.ctrl1 + } + #[doc = "0x08 - FIFO data"] + #[inline(always)] + pub const fn fifo_data(&self) -> &FifoData { + &self.fifo_data + } + #[doc = "0x0c - Status"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x10 - Interrupt Enable"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x14 - Raw Interrupt Status"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x18 - Enabled Interrupt Status"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x1c - Clear Interrupt"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x20 - Receive FIFO Interrupt Trigger Value"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x24 - FIFO Clear"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x7fc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] +module"] +#[doc(alias = "CTRL0")] +pub type Ctrl0 = crate::Reg; +#[doc = "Control Register 0"] +pub mod ctrl0; +#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] +module"] +#[doc(alias = "CTRL1")] +pub type Ctrl1 = crate::Reg; +#[doc = "Control Register 1"] +pub mod ctrl1; +#[doc = "FIFO_DATA (rw) register accessor: FIFO data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_data`] +module"] +#[doc(alias = "FIFO_DATA")] +pub type FifoData = crate::Reg; +#[doc = "FIFO data"] +pub mod fifo_data; +#[doc = "STATUS (r) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] +module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] +module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable"] +pub mod irq_enb; +#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] +module"] +#[doc(alias = "IRQ_RAW")] +pub type IrqRaw = crate::Reg; +#[doc = "Raw Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END (r) register accessor: Enabled Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] +module"] +#[doc(alias = "IRQ_END")] +pub type IrqEnd = crate::Reg; +#[doc = "Enabled Interrupt Status"] +pub mod irq_end; +#[doc = "IRQ_CLR (w) register accessor: Clear Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_clr`] +module"] +#[doc(alias = "IRQ_CLR")] +pub type IrqClr = crate::Reg; +#[doc = "Clear Interrupt"] +pub mod irq_clr; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] +module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Receive FIFO Interrupt Trigger Value"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR (rw) register accessor: FIFO Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] +module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "FIFO Clear"] +pub mod fifo_clr; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/dac0/ctrl0.rs b/va416xx/src/dac0/ctrl0.rs new file mode 100644 index 0000000..ebf18e2 --- /dev/null +++ b/va416xx/src/dac0/ctrl0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `EXT_TRIG_EN` reader - Enables external trigger"] +pub type ExtTrigEnR = crate::BitReader; +#[doc = "Field `EXT_TRIG_EN` writer - Enables external trigger"] +pub type ExtTrigEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MAN_TRIG_EN` reader - Enables manual trigger"] +pub type ManTrigEnR = crate::BitReader; +#[doc = "Field `MAN_TRIG_EN` writer - Enables manual trigger"] +pub type ManTrigEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 10 - Enables external trigger"] + #[inline(always)] + pub fn ext_trig_en(&self) -> ExtTrigEnR { + ExtTrigEnR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enables manual trigger"] + #[inline(always)] + pub fn man_trig_en(&self) -> ManTrigEnR { + ManTrigEnR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 10 - Enables external trigger"] + #[inline(always)] + #[must_use] + pub fn ext_trig_en(&mut self) -> ExtTrigEnW { + ExtTrigEnW::new(self, 10) + } + #[doc = "Bit 11 - Enables manual trigger"] + #[inline(always)] + #[must_use] + pub fn man_trig_en(&mut self) -> ManTrigEnW { + ManTrigEnW::new(self, 11) + } +} +#[doc = "Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl0Spec; +impl crate::RegisterSpec for Ctrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"] +impl crate::Readable for Ctrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"] +impl crate::Writable for Ctrl0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL0 to value 0"] +impl crate::Resettable for Ctrl0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dac0/ctrl1.rs b/va416xx/src/dac0/ctrl1.rs new file mode 100644 index 0000000..0bc3232 --- /dev/null +++ b/va416xx/src/dac0/ctrl1.rs @@ -0,0 +1,55 @@ +#[doc = "Register `CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `DAC_SETTLING` reader - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] +pub type DacSettlingR = crate::FieldReader; +#[doc = "Field `DAC_SETTLING` writer - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] +pub type DacSettlingW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `DAC_EN` reader - Enables the DAC analog block"] +pub type DacEnR = crate::BitReader; +#[doc = "Field `DAC_EN` writer - Enables the DAC analog block"] +pub type DacEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 5:7 - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] + #[inline(always)] + pub fn dac_settling(&self) -> DacSettlingR { + DacSettlingR::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 8 - Enables the DAC analog block"] + #[inline(always)] + pub fn dac_en(&self) -> DacEnR { + DacEnR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bits 5:7 - Sets the the amount of time in microseconds the control FSM waits for the DAC settling time"] + #[inline(always)] + #[must_use] + pub fn dac_settling(&mut self) -> DacSettlingW { + DacSettlingW::new(self, 5) + } + #[doc = "Bit 8 - Enables the DAC analog block"] + #[inline(always)] + #[must_use] + pub fn dac_en(&mut self) -> DacEnW { + DacEnW::new(self, 8) + } +} +#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl1Spec; +impl crate::RegisterSpec for Ctrl1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"] +impl crate::Readable for Ctrl1Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"] +impl crate::Writable for Ctrl1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for Ctrl1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dac0/fifo_clr.rs b/va416xx/src/dac0/fifo_clr.rs new file mode 100644 index 0000000..96ceabc --- /dev/null +++ b/va416xx/src/dac0/fifo_clr.rs @@ -0,0 +1,31 @@ +#[doc = "Register `FIFO_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_CLR` writer - Clears the DAC FIFO. Always reads 0"] +pub type FifoClrW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clears the DAC FIFO. Always reads 0"] + #[inline(always)] + #[must_use] + pub fn fifo_clr(&mut self) -> FifoClrW { + FifoClrW::new(self, 0) + } +} +#[doc = "FIFO Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_clr::R`](R) reader structure"] +impl crate::Readable for FifoClrSpec {} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dac0/fifo_data.rs b/va416xx/src/dac0/fifo_data.rs new file mode 100644 index 0000000..63aeaaa --- /dev/null +++ b/va416xx/src/dac0/fifo_data.rs @@ -0,0 +1,31 @@ +#[doc = "Register `FIFO_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `FIFO_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `DATA` writer - Data for FIFO write"] +pub type DataW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl W { + #[doc = "Bits 0:11 - Data for FIFO write"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DataW { + DataW::new(self, 0) + } +} +#[doc = "FIFO data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoDataSpec; +impl crate::RegisterSpec for FifoDataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`fifo_data::R`](R) reader structure"] +impl crate::Readable for FifoDataSpec {} +#[doc = "`write(|w| ..)` method takes [`fifo_data::W`](W) writer structure"] +impl crate::Writable for FifoDataSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO_DATA to value 0"] +impl crate::Resettable for FifoDataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dac0/irq_clr.rs b/va416xx/src/dac0/irq_clr.rs new file mode 100644 index 0000000..da11188 --- /dev/null +++ b/va416xx/src/dac0/irq_clr.rs @@ -0,0 +1,51 @@ +#[doc = "Register `IRQ_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_OFLOW` writer - Clears the FIFO overflow interrupt status. Always reads 0"] +pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_UFLOW` writer - Clears the FIFO underflow interrupt status. Always reads 0"] +pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DAC_DONE` writer - Clears the DAC done interrupt status. Always reads 0"] +pub type DacDoneW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRIG_ERROR` writer - Clears the trigger error interrupt status. Always reads 0"] +pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clears the FIFO overflow interrupt status. Always reads 0"] + #[inline(always)] + #[must_use] + pub fn fifo_oflow(&mut self) -> FifoOflowW { + FifoOflowW::new(self, 0) + } + #[doc = "Bit 1 - Clears the FIFO underflow interrupt status. Always reads 0"] + #[inline(always)] + #[must_use] + pub fn fifo_uflow(&mut self) -> FifoUflowW { + FifoUflowW::new(self, 1) + } + #[doc = "Bit 2 - Clears the DAC done interrupt status. Always reads 0"] + #[inline(always)] + #[must_use] + pub fn dac_done(&mut self) -> DacDoneW { + DacDoneW::new(self, 2) + } + #[doc = "Bit 3 - Clears the trigger error interrupt status. Always reads 0"] + #[inline(always)] + #[must_use] + pub fn trig_error(&mut self) -> TrigErrorW { + TrigErrorW::new(self, 3) + } +} +#[doc = "Clear Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqClrSpec; +impl crate::RegisterSpec for IrqClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`irq_clr::W`](W) writer structure"] +impl crate::Writable for IrqClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_CLR to value 0"] +impl crate::Resettable for IrqClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dac0/irq_enb.rs b/va416xx/src/dac0/irq_enb.rs new file mode 100644 index 0000000..9c0718e --- /dev/null +++ b/va416xx/src/dac0/irq_enb.rs @@ -0,0 +1,130 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"] +pub type FifoEmptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"] +pub type FifoFullW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"] +pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"] +pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DAC_DONE` reader - Enables the interrupt for a DAC data acquisition completion"] +pub type DacDoneR = crate::BitReader; +#[doc = "Field `DAC_DONE` writer - Enables the interrupt for a DAC data acquisition completion"] +pub type DacDoneW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"] +pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] +pub type FifoDepthTrigR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] +pub type FifoDepthTrigW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Enables the interrupt for a DAC data acquisition completion"] + #[inline(always)] + pub fn dac_done(&self) -> DacDoneR { + DacDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enables the interrupt for FIFO empty"] + #[inline(always)] + #[must_use] + pub fn fifo_empty(&mut self) -> FifoEmptyW { + FifoEmptyW::new(self, 0) + } + #[doc = "Bit 1 - Enables the interrupt for FIFO full"] + #[inline(always)] + #[must_use] + pub fn fifo_full(&mut self) -> FifoFullW { + FifoFullW::new(self, 1) + } + #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"] + #[inline(always)] + #[must_use] + pub fn fifo_oflow(&mut self) -> FifoOflowW { + FifoOflowW::new(self, 2) + } + #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"] + #[inline(always)] + #[must_use] + pub fn fifo_uflow(&mut self) -> FifoUflowW { + FifoUflowW::new(self, 3) + } + #[doc = "Bit 4 - Enables the interrupt for a DAC data acquisition completion"] + #[inline(always)] + #[must_use] + pub fn dac_done(&mut self) -> DacDoneW { + DacDoneW::new(self, 4) + } + #[doc = "Bit 5 - Enables the interrupt for a trigger error"] + #[inline(always)] + #[must_use] + pub fn trig_error(&mut self) -> TrigErrorW { + TrigErrorW::new(self, 5) + } + #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count is less than or equal to the trigger level"] + #[inline(always)] + #[must_use] + pub fn fifo_depth_trig(&mut self) -> FifoDepthTrigW { + FifoDepthTrigW::new(self, 6) + } +} +#[doc = "Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dac0/irq_end.rs b/va416xx/src/dac0/irq_end.rs new file mode 100644 index 0000000..2043fc3 --- /dev/null +++ b/va416xx/src/dac0/irq_end.rs @@ -0,0 +1,64 @@ +#[doc = "Register `IRQ_END` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty and the interrupt is enabled"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full and the interrupt is enabled"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred and the interrupt is enabled"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` reader - Indicates a FIFO underflow occurred and the interrupt is enabled"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `DAC_DONE` reader - Indicates that a DAC conversion is done and the interrupt is enabled"] +pub type DacDoneR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled"] +pub type FifoDepthTrigR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates the FIFO is empty and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates a FIFO underflow occurred and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates that a DAC conversion is done and the interrupt is enabled"] + #[inline(always)] + pub fn dac_done(&self) -> DacDoneR { + DacDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "Enabled Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEndSpec; +impl crate::RegisterSpec for IrqEndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"] +impl crate::Readable for IrqEndSpec {} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IrqEndSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dac0/irq_raw.rs b/va416xx/src/dac0/irq_raw.rs new file mode 100644 index 0000000..91a9e68 --- /dev/null +++ b/va416xx/src/dac0/irq_raw.rs @@ -0,0 +1,64 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty"] +pub type FifoEmptyR = crate::BitReader; +#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full"] +pub type FifoFullR = crate::BitReader; +#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] +pub type FifoOflowR = crate::BitReader; +#[doc = "Field `FIFO_UFLOW` reader - Indicates data was unavailable when a new trigger for DAC update is received"] +pub type FifoUflowR = crate::BitReader; +#[doc = "Field `DAC_DONE` reader - Indicates that a DAC conversion is done"] +pub type DacDoneR = crate::BitReader; +#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion"] +pub type TrigErrorR = crate::BitReader; +#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the FIFO entry count is less than or equal to the trigger level"] +pub type FifoDepthTrigR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates the FIFO is empty"] + #[inline(always)] + pub fn fifo_empty(&self) -> FifoEmptyR { + FifoEmptyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates the FIFO is full"] + #[inline(always)] + pub fn fifo_full(&self) -> FifoFullR { + FifoFullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"] + #[inline(always)] + pub fn fifo_oflow(&self) -> FifoOflowR { + FifoOflowR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates data was unavailable when a new trigger for DAC update is received"] + #[inline(always)] + pub fn fifo_uflow(&self) -> FifoUflowR { + FifoUflowR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Indicates that a DAC conversion is done"] + #[inline(always)] + pub fn dac_done(&self) -> DacDoneR { + DacDoneR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion"] + #[inline(always)] + pub fn trig_error(&self) -> TrigErrorR { + TrigErrorR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Indicates the FIFO entry count is less than or equal to the trigger level"] + #[inline(always)] + pub fn fifo_depth_trig(&self) -> FifoDepthTrigR { + FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqRawSpec; +impl crate::RegisterSpec for IrqRawSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"] +impl crate::Readable for IrqRawSpec {} +#[doc = "`reset()` method sets IRQ_RAW to value 0x41"] +impl crate::Resettable for IrqRawSpec { + const RESET_VALUE: u32 = 0x41; +} diff --git a/va416xx/src/dac0/perid.rs b/va416xx/src/dac0/perid.rs new file mode 100644 index 0000000..a7c25a8 --- /dev/null +++ b/va416xx/src/dac0/perid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0020_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0020_07e9; +} diff --git a/va416xx/src/dac0/status.rs b/va416xx/src/dac0/status.rs new file mode 100644 index 0000000..af7a48d --- /dev/null +++ b/va416xx/src/dac0/status.rs @@ -0,0 +1,29 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `FIFO_ENTRY_CNT` reader - Indicates the number of entries in the FIFO"] +pub type FifoEntryCntR = crate::FieldReader; +#[doc = "Field `DAC_BUSY` reader - Indicates a DAC data acquisition is in process"] +pub type DacBusyR = crate::BitReader; +impl R { + #[doc = "Bits 0:5 - Indicates the number of entries in the FIFO"] + #[inline(always)] + pub fn fifo_entry_cnt(&self) -> FifoEntryCntR { + FifoEntryCntR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bit 7 - Indicates a DAC data acquisition is in process"] + #[inline(always)] + pub fn dac_busy(&self) -> DacBusyR { + DacBusyR::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dac0/txfifoirqtrg.rs b/va416xx/src/dac0/txfifoirqtrg.rs new file mode 100644 index 0000000..167855c --- /dev/null +++ b/va416xx/src/dac0/txfifoirqtrg.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[doc = "Field `LEVEL` reader - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub type LevelR = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] +pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + pub fn level(&self) -> LevelR { + LevelR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"] + #[inline(always)] + #[must_use] + pub fn level(&mut self) -> LevelW { + LevelW::new(self, 0) + } +} +#[doc = "Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0x10"] +impl crate::Resettable for TxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0x10; +} diff --git a/va416xx/src/dma.rs b/va416xx/src/dma.rs new file mode 100644 index 0000000..102edef --- /dev/null +++ b/va416xx/src/dma.rs @@ -0,0 +1,434 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + status: Status, + cfg: Cfg, + ctrl_base_ptr: CtrlBasePtr, + alt_ctrl_base_ptr: AltCtrlBasePtr, + waitonreq_status: WaitonreqStatus, + chnl_sw_request: ChnlSwRequest, + chnl_useburst_set: ChnlUseburstSet, + chnl_useburst_clr: ChnlUseburstClr, + chnl_req_mask_set: ChnlReqMaskSet, + chnl_req_mask_clr: ChnlReqMaskClr, + chnl_enable_set: ChnlEnableSet, + chnl_enable_clr: ChnlEnableClr, + chnl_pri_alt_set: ChnlPriAltSet, + chnl_pri_alt_clr: ChnlPriAltClr, + chnl_priority_set: ChnlPrioritySet, + chnl_priority_clr: ChnlPriorityClr, + _reserved16: [u8; 0x0c], + err_clr: ErrClr, + _reserved17: [u8; 0x0db0], + integration_cfg: IntegrationCfg, + _reserved18: [u8; 0x04], + stall_status: StallStatus, + _reserved19: [u8; 0x04], + dma_req_status: DmaReqStatus, + _reserved20: [u8; 0x04], + dma_sreq_status: DmaSreqStatus, + _reserved21: [u8; 0x04], + dma_done_set: DmaDoneSet, + dma_done_clr: DmaDoneClr, + dma_active_set: DmaActiveSet, + dma_active_clr: DmaActiveClr, + _reserved25: [u8; 0x18], + err_set: ErrSet, + _reserved26: [u8; 0x0184], + periph_id_4: PeriphId4, + _reserved27: [u8; 0x0c], + periph_id_0: PeriphId0, + periph_id_1: PeriphId1, + periph_id_2: PeriphId2, + periph_id_3: PeriphId3, + primecell_id_0: PrimecellId0, + primecell_id_1: PrimecellId1, + primecell_id_2: PrimecellId2, + primecell_id_3: PrimecellId3, +} +impl RegisterBlock { + #[doc = "0x00 - DMA Status"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x04 - DMA Configuration"] + #[inline(always)] + pub const fn cfg(&self) -> &Cfg { + &self.cfg + } + #[doc = "0x08 - Base Pointer for DMA Control Registers"] + #[inline(always)] + pub const fn ctrl_base_ptr(&self) -> &CtrlBasePtr { + &self.ctrl_base_ptr + } + #[doc = "0x0c - DMA Channel alternate control data base pointer"] + #[inline(always)] + pub const fn alt_ctrl_base_ptr(&self) -> &AltCtrlBasePtr { + &self.alt_ctrl_base_ptr + } + #[doc = "0x10 - DMA channel wait on request status"] + #[inline(always)] + pub const fn waitonreq_status(&self) -> &WaitonreqStatus { + &self.waitonreq_status + } + #[doc = "0x14 - DMA channel software request"] + #[inline(always)] + pub const fn chnl_sw_request(&self) -> &ChnlSwRequest { + &self.chnl_sw_request + } + #[doc = "0x18 - DMA channel useburst set"] + #[inline(always)] + pub const fn chnl_useburst_set(&self) -> &ChnlUseburstSet { + &self.chnl_useburst_set + } + #[doc = "0x1c - DMA channel useburst clear"] + #[inline(always)] + pub const fn chnl_useburst_clr(&self) -> &ChnlUseburstClr { + &self.chnl_useburst_clr + } + #[doc = "0x20 - DMA channel request mask set"] + #[inline(always)] + pub const fn chnl_req_mask_set(&self) -> &ChnlReqMaskSet { + &self.chnl_req_mask_set + } + #[doc = "0x24 - DMA channel request mask clear"] + #[inline(always)] + pub const fn chnl_req_mask_clr(&self) -> &ChnlReqMaskClr { + &self.chnl_req_mask_clr + } + #[doc = "0x28 - DMA channel enable set"] + #[inline(always)] + pub const fn chnl_enable_set(&self) -> &ChnlEnableSet { + &self.chnl_enable_set + } + #[doc = "0x2c - DMA channel enable clear"] + #[inline(always)] + pub const fn chnl_enable_clr(&self) -> &ChnlEnableClr { + &self.chnl_enable_clr + } + #[doc = "0x30 - DMA channel primary alternate set"] + #[inline(always)] + pub const fn chnl_pri_alt_set(&self) -> &ChnlPriAltSet { + &self.chnl_pri_alt_set + } + #[doc = "0x34 - DMA channel primary alternate clear"] + #[inline(always)] + pub const fn chnl_pri_alt_clr(&self) -> &ChnlPriAltClr { + &self.chnl_pri_alt_clr + } + #[doc = "0x38 - DMA channel priority set"] + #[inline(always)] + pub const fn chnl_priority_set(&self) -> &ChnlPrioritySet { + &self.chnl_priority_set + } + #[doc = "0x3c - DMA channel priority clear"] + #[inline(always)] + pub const fn chnl_priority_clr(&self) -> &ChnlPriorityClr { + &self.chnl_priority_clr + } + #[doc = "0x4c - DMA bus error clear"] + #[inline(always)] + pub const fn err_clr(&self) -> &ErrClr { + &self.err_clr + } + #[doc = "0xe00 - DMA integration configuration"] + #[inline(always)] + pub const fn integration_cfg(&self) -> &IntegrationCfg { + &self.integration_cfg + } + #[doc = "0xe08 - DMA stall status"] + #[inline(always)] + pub const fn stall_status(&self) -> &StallStatus { + &self.stall_status + } + #[doc = "0xe10 - DMA Configuration"] + #[inline(always)] + pub const fn dma_req_status(&self) -> &DmaReqStatus { + &self.dma_req_status + } + #[doc = "0xe18 - DMA single request status"] + #[inline(always)] + pub const fn dma_sreq_status(&self) -> &DmaSreqStatus { + &self.dma_sreq_status + } + #[doc = "0xe20 - DMA done set"] + #[inline(always)] + pub const fn dma_done_set(&self) -> &DmaDoneSet { + &self.dma_done_set + } + #[doc = "0xe24 - DMA done clear"] + #[inline(always)] + pub const fn dma_done_clr(&self) -> &DmaDoneClr { + &self.dma_done_clr + } + #[doc = "0xe28 - DMA active set"] + #[inline(always)] + pub const fn dma_active_set(&self) -> &DmaActiveSet { + &self.dma_active_set + } + #[doc = "0xe2c - DMA active clear"] + #[inline(always)] + pub const fn dma_active_clr(&self) -> &DmaActiveClr { + &self.dma_active_clr + } + #[doc = "0xe48 - DMA bus error set"] + #[inline(always)] + pub const fn err_set(&self) -> &ErrSet { + &self.err_set + } + #[doc = "0xfd0 - DMA Peripheral ID 4"] + #[inline(always)] + pub const fn periph_id_4(&self) -> &PeriphId4 { + &self.periph_id_4 + } + #[doc = "0xfe0 - DMA Peripheral ID 0"] + #[inline(always)] + pub const fn periph_id_0(&self) -> &PeriphId0 { + &self.periph_id_0 + } + #[doc = "0xfe4 - DMA Peripheral ID 1"] + #[inline(always)] + pub const fn periph_id_1(&self) -> &PeriphId1 { + &self.periph_id_1 + } + #[doc = "0xfe8 - DMA Peripheral ID 2"] + #[inline(always)] + pub const fn periph_id_2(&self) -> &PeriphId2 { + &self.periph_id_2 + } + #[doc = "0xfec - DMA Peripheral ID 3"] + #[inline(always)] + pub const fn periph_id_3(&self) -> &PeriphId3 { + &self.periph_id_3 + } + #[doc = "0xff0 - DMA PrimeCell ID 0"] + #[inline(always)] + pub const fn primecell_id_0(&self) -> &PrimecellId0 { + &self.primecell_id_0 + } + #[doc = "0xff4 - DMA PrimeCell ID 1"] + #[inline(always)] + pub const fn primecell_id_1(&self) -> &PrimecellId1 { + &self.primecell_id_1 + } + #[doc = "0xff8 - DMA PrimeCell ID 2"] + #[inline(always)] + pub const fn primecell_id_2(&self) -> &PrimecellId2 { + &self.primecell_id_2 + } + #[doc = "0xffc - DMA PrimeCell ID 3"] + #[inline(always)] + pub const fn primecell_id_3(&self) -> &PrimecellId3 { + &self.primecell_id_3 + } +} +#[doc = "STATUS (r) register accessor: DMA Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] +module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "DMA Status"] +pub mod status; +#[doc = "CFG (w) register accessor: DMA Configuration\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +#[doc(alias = "CFG")] +pub type Cfg = crate::Reg; +#[doc = "DMA Configuration"] +pub mod cfg; +#[doc = "CTRL_BASE_PTR (rw) register accessor: Base Pointer for DMA Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl_base_ptr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl_base_ptr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl_base_ptr`] +module"] +#[doc(alias = "CTRL_BASE_PTR")] +pub type CtrlBasePtr = crate::Reg; +#[doc = "Base Pointer for DMA Control Registers"] +pub mod ctrl_base_ptr; +#[doc = "ALT_CTRL_BASE_PTR (rw) register accessor: DMA Channel alternate control data base pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`alt_ctrl_base_ptr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alt_ctrl_base_ptr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@alt_ctrl_base_ptr`] +module"] +#[doc(alias = "ALT_CTRL_BASE_PTR")] +pub type AltCtrlBasePtr = crate::Reg; +#[doc = "DMA Channel alternate control data base pointer"] +pub mod alt_ctrl_base_ptr; +#[doc = "WAITONREQ_STATUS (r) register accessor: DMA channel wait on request status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`waitonreq_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@waitonreq_status`] +module"] +#[doc(alias = "WAITONREQ_STATUS")] +pub type WaitonreqStatus = crate::Reg; +#[doc = "DMA channel wait on request status"] +pub mod waitonreq_status; +#[doc = "CHNL_SW_REQUEST (w) register accessor: DMA channel software request\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_sw_request::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_sw_request`] +module"] +#[doc(alias = "CHNL_SW_REQUEST")] +pub type ChnlSwRequest = crate::Reg; +#[doc = "DMA channel software request"] +pub mod chnl_sw_request; +#[doc = "CHNL_USEBURST_SET (rw) register accessor: DMA channel useburst set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_useburst_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_useburst_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_useburst_set`] +module"] +#[doc(alias = "CHNL_USEBURST_SET")] +pub type ChnlUseburstSet = crate::Reg; +#[doc = "DMA channel useburst set"] +pub mod chnl_useburst_set; +#[doc = "CHNL_USEBURST_CLR (rw) register accessor: DMA channel useburst clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_useburst_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_useburst_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_useburst_clr`] +module"] +#[doc(alias = "CHNL_USEBURST_CLR")] +pub type ChnlUseburstClr = crate::Reg; +#[doc = "DMA channel useburst clear"] +pub mod chnl_useburst_clr; +#[doc = "CHNL_REQ_MASK_SET (rw) register accessor: DMA channel request mask set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_req_mask_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_req_mask_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_req_mask_set`] +module"] +#[doc(alias = "CHNL_REQ_MASK_SET")] +pub type ChnlReqMaskSet = crate::Reg; +#[doc = "DMA channel request mask set"] +pub mod chnl_req_mask_set; +#[doc = "CHNL_REQ_MASK_CLR (rw) register accessor: DMA channel request mask clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_req_mask_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_req_mask_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_req_mask_clr`] +module"] +#[doc(alias = "CHNL_REQ_MASK_CLR")] +pub type ChnlReqMaskClr = crate::Reg; +#[doc = "DMA channel request mask clear"] +pub mod chnl_req_mask_clr; +#[doc = "CHNL_ENABLE_SET (rw) register accessor: DMA channel enable set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_enable_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_enable_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_enable_set`] +module"] +#[doc(alias = "CHNL_ENABLE_SET")] +pub type ChnlEnableSet = crate::Reg; +#[doc = "DMA channel enable set"] +pub mod chnl_enable_set; +#[doc = "CHNL_ENABLE_CLR (rw) register accessor: DMA channel enable clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_enable_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_enable_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_enable_clr`] +module"] +#[doc(alias = "CHNL_ENABLE_CLR")] +pub type ChnlEnableClr = crate::Reg; +#[doc = "DMA channel enable clear"] +pub mod chnl_enable_clr; +#[doc = "CHNL_PRI_ALT_SET (rw) register accessor: DMA channel primary alternate set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_pri_alt_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_pri_alt_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_pri_alt_set`] +module"] +#[doc(alias = "CHNL_PRI_ALT_SET")] +pub type ChnlPriAltSet = crate::Reg; +#[doc = "DMA channel primary alternate set"] +pub mod chnl_pri_alt_set; +#[doc = "CHNL_PRI_ALT_CLR (rw) register accessor: DMA channel primary alternate clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_pri_alt_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_pri_alt_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_pri_alt_clr`] +module"] +#[doc(alias = "CHNL_PRI_ALT_CLR")] +pub type ChnlPriAltClr = crate::Reg; +#[doc = "DMA channel primary alternate clear"] +pub mod chnl_pri_alt_clr; +#[doc = "CHNL_PRIORITY_SET (rw) register accessor: DMA channel priority set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_priority_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_priority_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_priority_set`] +module"] +#[doc(alias = "CHNL_PRIORITY_SET")] +pub type ChnlPrioritySet = crate::Reg; +#[doc = "DMA channel priority set"] +pub mod chnl_priority_set; +#[doc = "CHNL_PRIORITY_CLR (w) register accessor: DMA channel priority clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_priority_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@chnl_priority_clr`] +module"] +#[doc(alias = "CHNL_PRIORITY_CLR")] +pub type ChnlPriorityClr = crate::Reg; +#[doc = "DMA channel priority clear"] +pub mod chnl_priority_clr; +#[doc = "ERR_CLR (rw) register accessor: DMA bus error clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_clr`] +module"] +#[doc(alias = "ERR_CLR")] +pub type ErrClr = crate::Reg; +#[doc = "DMA bus error clear"] +pub mod err_clr; +#[doc = "INTEGRATION_CFG (rw) register accessor: DMA integration configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`integration_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`integration_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@integration_cfg`] +module"] +#[doc(alias = "INTEGRATION_CFG")] +pub type IntegrationCfg = crate::Reg; +#[doc = "DMA integration configuration"] +pub mod integration_cfg; +#[doc = "STALL_STATUS (rw) register accessor: DMA stall status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stall_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stall_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stall_status`] +module"] +#[doc(alias = "STALL_STATUS")] +pub type StallStatus = crate::Reg; +#[doc = "DMA stall status"] +pub mod stall_status; +#[doc = "DMA_REQ_STATUS (rw) register accessor: DMA Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_req_status`] +module"] +#[doc(alias = "DMA_REQ_STATUS")] +pub type DmaReqStatus = crate::Reg; +#[doc = "DMA Configuration"] +pub mod dma_req_status; +#[doc = "DMA_SREQ_STATUS (rw) register accessor: DMA single request status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_sreq_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_sreq_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_sreq_status`] +module"] +#[doc(alias = "DMA_SREQ_STATUS")] +pub type DmaSreqStatus = crate::Reg; +#[doc = "DMA single request status"] +pub mod dma_sreq_status; +#[doc = "DMA_DONE_SET (rw) register accessor: DMA done set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_done_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_done_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_done_set`] +module"] +#[doc(alias = "DMA_DONE_SET")] +pub type DmaDoneSet = crate::Reg; +#[doc = "DMA done set"] +pub mod dma_done_set; +#[doc = "DMA_DONE_CLR (rw) register accessor: DMA done clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_done_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_done_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_done_clr`] +module"] +#[doc(alias = "DMA_DONE_CLR")] +pub type DmaDoneClr = crate::Reg; +#[doc = "DMA done clear"] +pub mod dma_done_clr; +#[doc = "DMA_ACTIVE_SET (rw) register accessor: DMA active set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_active_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_active_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_active_set`] +module"] +#[doc(alias = "DMA_ACTIVE_SET")] +pub type DmaActiveSet = crate::Reg; +#[doc = "DMA active set"] +pub mod dma_active_set; +#[doc = "DMA_ACTIVE_CLR (rw) register accessor: DMA active clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_active_clr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_active_clr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_active_clr`] +module"] +#[doc(alias = "DMA_ACTIVE_CLR")] +pub type DmaActiveClr = crate::Reg; +#[doc = "DMA active clear"] +pub mod dma_active_clr; +#[doc = "ERR_SET (rw) register accessor: DMA bus error set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_set::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err_set::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@err_set`] +module"] +#[doc(alias = "ERR_SET")] +pub type ErrSet = crate::Reg; +#[doc = "DMA bus error set"] +pub mod err_set; +#[doc = "PERIPH_ID_4 (rw) register accessor: DMA Peripheral ID 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periph_id_4`] +module"] +#[doc(alias = "PERIPH_ID_4")] +pub type PeriphId4 = crate::Reg; +#[doc = "DMA Peripheral ID 4"] +pub mod periph_id_4; +#[doc = "PERIPH_ID_0 (rw) register accessor: DMA Peripheral ID 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periph_id_0`] +module"] +#[doc(alias = "PERIPH_ID_0")] +pub type PeriphId0 = crate::Reg; +#[doc = "DMA Peripheral ID 0"] +pub mod periph_id_0; +#[doc = "PERIPH_ID_1 (r) register accessor: DMA Peripheral ID 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periph_id_1`] +module"] +#[doc(alias = "PERIPH_ID_1")] +pub type PeriphId1 = crate::Reg; +#[doc = "DMA Peripheral ID 1"] +pub mod periph_id_1; +#[doc = "PERIPH_ID_2 (rw) register accessor: DMA Peripheral ID 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periph_id_2`] +module"] +#[doc(alias = "PERIPH_ID_2")] +pub type PeriphId2 = crate::Reg; +#[doc = "DMA Peripheral ID 2"] +pub mod periph_id_2; +#[doc = "PERIPH_ID_3 (rw) register accessor: DMA Peripheral ID 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@periph_id_3`] +module"] +#[doc(alias = "PERIPH_ID_3")] +pub type PeriphId3 = crate::Reg; +#[doc = "DMA Peripheral ID 3"] +pub mod periph_id_3; +#[doc = "PRIMECELL_ID_0 (rw) register accessor: DMA PrimeCell ID 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@primecell_id_0`] +module"] +#[doc(alias = "PRIMECELL_ID_0")] +pub type PrimecellId0 = crate::Reg; +#[doc = "DMA PrimeCell ID 0"] +pub mod primecell_id_0; +#[doc = "PRIMECELL_ID_1 (rw) register accessor: DMA PrimeCell ID 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@primecell_id_1`] +module"] +#[doc(alias = "PRIMECELL_ID_1")] +pub type PrimecellId1 = crate::Reg; +#[doc = "DMA PrimeCell ID 1"] +pub mod primecell_id_1; +#[doc = "PRIMECELL_ID_2 (rw) register accessor: DMA PrimeCell ID 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@primecell_id_2`] +module"] +#[doc(alias = "PRIMECELL_ID_2")] +pub type PrimecellId2 = crate::Reg; +#[doc = "DMA PrimeCell ID 2"] +pub mod primecell_id_2; +#[doc = "PRIMECELL_ID_3 (rw) register accessor: DMA PrimeCell ID 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@primecell_id_3`] +module"] +#[doc(alias = "PRIMECELL_ID_3")] +pub type PrimecellId3 = crate::Reg; +#[doc = "DMA PrimeCell ID 3"] +pub mod primecell_id_3; diff --git a/va416xx/src/dma/alt_ctrl_base_ptr.rs b/va416xx/src/dma/alt_ctrl_base_ptr.rs new file mode 100644 index 0000000..0ae67d4 --- /dev/null +++ b/va416xx/src/dma/alt_ctrl_base_ptr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ALT_CTRL_BASE_PTR` reader"] +pub type R = crate::R; +#[doc = "Register `ALT_CTRL_BASE_PTR` writer"] +pub type W = crate::W; +#[doc = "Field `ALT_CTRL_BASE_PTR` reader - Base Pointer for Alternate DMA Control Register"] +pub type AltCtrlBasePtrR = crate::FieldReader; +#[doc = "Field `ALT_CTRL_BASE_PTR` writer - Base Pointer for Alternate DMA Control Register"] +pub type AltCtrlBasePtrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Base Pointer for Alternate DMA Control Register"] + #[inline(always)] + pub fn alt_ctrl_base_ptr(&self) -> AltCtrlBasePtrR { + AltCtrlBasePtrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Base Pointer for Alternate DMA Control Register"] + #[inline(always)] + #[must_use] + pub fn alt_ctrl_base_ptr(&mut self) -> AltCtrlBasePtrW { + AltCtrlBasePtrW::new(self, 0) + } +} +#[doc = "DMA Channel alternate control data base pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`alt_ctrl_base_ptr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alt_ctrl_base_ptr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AltCtrlBasePtrSpec; +impl crate::RegisterSpec for AltCtrlBasePtrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`alt_ctrl_base_ptr::R`](R) reader structure"] +impl crate::Readable for AltCtrlBasePtrSpec {} +#[doc = "`write(|w| ..)` method takes [`alt_ctrl_base_ptr::W`](W) writer structure"] +impl crate::Writable for AltCtrlBasePtrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ALT_CTRL_BASE_PTR to value 0"] +impl crate::Resettable for AltCtrlBasePtrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/cfg.rs b/va416xx/src/dma/cfg.rs new file mode 100644 index 0000000..5e537c3 --- /dev/null +++ b/va416xx/src/dma/cfg.rs @@ -0,0 +1,35 @@ +#[doc = "Register `CFG` writer"] +pub type W = crate::W; +#[doc = "Field `MASTER_ENABLE` writer - PLL Symbol; Feedback cycle slip output (CLKOUT frequency low)"] +pub type MasterEnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CHNL_PROT_CTRL` writer - HPROT\\[3:0\\]"] +pub type ChnlProtCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +impl W { + #[doc = "Bit 0 - PLL Symbol; Feedback cycle slip output (CLKOUT frequency low)"] + #[inline(always)] + #[must_use] + pub fn master_enable(&mut self) -> MasterEnableW { + MasterEnableW::new(self, 0) + } + #[doc = "Bits 5:7 - HPROT\\[3:0\\]"] + #[inline(always)] + #[must_use] + pub fn chnl_prot_ctrl(&mut self) -> ChnlProtCtrlW { + ChnlProtCtrlW::new(self, 5) + } +} +#[doc = "DMA Configuration\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CfgSpec; +impl crate::RegisterSpec for CfgSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"] +impl crate::Writable for CfgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CFG to value 0"] +impl crate::Resettable for CfgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_enable_clr.rs b/va416xx/src/dma/chnl_enable_clr.rs new file mode 100644 index 0000000..374fc9e --- /dev/null +++ b/va416xx/src/dma/chnl_enable_clr.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CHNL_ENABLE_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_ENABLE_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel Enable clear"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel Enable clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel Enable clear"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel Enable clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel Enable clear"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel Enable clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel Enable clear"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel Enable clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel Enable clear"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Enable clear"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Enable clear"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel Enable clear"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Enable clear"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel Enable clear"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel Enable clear"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel Enable clear"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel enable clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_enable_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_enable_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlEnableClrSpec; +impl crate::RegisterSpec for ChnlEnableClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_enable_clr::R`](R) reader structure"] +impl crate::Readable for ChnlEnableClrSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_enable_clr::W`](W) writer structure"] +impl crate::Writable for ChnlEnableClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_ENABLE_CLR to value 0"] +impl crate::Resettable for ChnlEnableClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_enable_set.rs b/va416xx/src/dma/chnl_enable_set.rs new file mode 100644 index 0000000..49390d5 --- /dev/null +++ b/va416xx/src/dma/chnl_enable_set.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CHNL_ENABLE_SET` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_ENABLE_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel Enable set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel Enable set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel Enable set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel Enable set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel Enable set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel Enable set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel Enable set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel Enable set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel Enable set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Enable set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Enable set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel Enable set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Enable set"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel Enable set"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel Enable set"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel Enable set"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel enable set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_enable_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_enable_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlEnableSetSpec; +impl crate::RegisterSpec for ChnlEnableSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_enable_set::R`](R) reader structure"] +impl crate::Readable for ChnlEnableSetSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_enable_set::W`](W) writer structure"] +impl crate::Writable for ChnlEnableSetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_ENABLE_SET to value 0"] +impl crate::Resettable for ChnlEnableSetSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_pri_alt_clr.rs b/va416xx/src/dma/chnl_pri_alt_clr.rs new file mode 100644 index 0000000..fbd1c6c --- /dev/null +++ b/va416xx/src/dma/chnl_pri_alt_clr.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CHNL_PRI_ALT_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_PRI_ALT_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel PRI_ALT clear"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel PRI_ALT clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel PRI_ALT clear"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel PRI_ALT clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel PRI_ALT clear"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel PRI_ALT clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel PRI_ALT clear"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel PRI_ALT clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel PRI_ALT clear"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel PRI_ALT clear"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel PRI_ALT clear"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel PRI_ALT clear"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel PRI_ALT clear"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel primary alternate clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_pri_alt_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_pri_alt_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlPriAltClrSpec; +impl crate::RegisterSpec for ChnlPriAltClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_pri_alt_clr::R`](R) reader structure"] +impl crate::Readable for ChnlPriAltClrSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_pri_alt_clr::W`](W) writer structure"] +impl crate::Writable for ChnlPriAltClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_PRI_ALT_CLR to value 0"] +impl crate::Resettable for ChnlPriAltClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_pri_alt_set.rs b/va416xx/src/dma/chnl_pri_alt_set.rs new file mode 100644 index 0000000..99ca91c --- /dev/null +++ b/va416xx/src/dma/chnl_pri_alt_set.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CHNL_PRI_ALT_SET` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_PRI_ALT_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel PRI_ALT set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel PRI_ALT set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel PRI_ALT set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel PRI_ALT set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel PRI_ALT set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel PRI_ALT set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel PRI_ALT set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel PRI_ALT set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel PRI_ALT set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel PRI_ALT set"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel PRI_ALT set"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel PRI_ALT set"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel PRI_ALT set"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel primary alternate set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_pri_alt_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_pri_alt_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlPriAltSetSpec; +impl crate::RegisterSpec for ChnlPriAltSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_pri_alt_set::R`](R) reader structure"] +impl crate::Readable for ChnlPriAltSetSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_pri_alt_set::W`](W) writer structure"] +impl crate::Writable for ChnlPriAltSetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_PRI_ALT_SET to value 0"] +impl crate::Resettable for ChnlPriAltSetSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_priority_clr.rs b/va416xx/src/dma/chnl_priority_clr.rs new file mode 100644 index 0000000..cd8f54c --- /dev/null +++ b/va416xx/src/dma/chnl_priority_clr.rs @@ -0,0 +1,51 @@ +#[doc = "Register `CHNL_PRIORITY_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` writer - Channel PRIORITY clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` writer - Channel PRIORITY clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` writer - Channel PRIORITY clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` writer - Channel PRIORITY clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Channel PRIORITY clear"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel PRIORITY clear"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel PRIORITY clear"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel PRIORITY clear"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel priority clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_priority_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlPriorityClrSpec; +impl crate::RegisterSpec for ChnlPriorityClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`chnl_priority_clr::W`](W) writer structure"] +impl crate::Writable for ChnlPriorityClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_PRIORITY_CLR to value 0"] +impl crate::Resettable for ChnlPriorityClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_priority_set.rs b/va416xx/src/dma/chnl_priority_set.rs new file mode 100644 index 0000000..a92e2ae --- /dev/null +++ b/va416xx/src/dma/chnl_priority_set.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CHNL_PRIORITY_SET` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_PRIORITY_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel PRIORITY set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel PRIORITY set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel PRIORITY set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel PRIORITY set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel PRIORITY set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel PRIORITY set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel PRIORITY set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel PRIORITY set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel PRIORITY set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel PRIORITY set"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel PRIORITY set"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel PRIORITY set"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel PRIORITY set"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel priority set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_priority_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_priority_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlPrioritySetSpec; +impl crate::RegisterSpec for ChnlPrioritySetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_priority_set::R`](R) reader structure"] +impl crate::Readable for ChnlPrioritySetSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_priority_set::W`](W) writer structure"] +impl crate::Writable for ChnlPrioritySetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_PRIORITY_SET to value 0"] +impl crate::Resettable for ChnlPrioritySetSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_req_mask_clr.rs b/va416xx/src/dma/chnl_req_mask_clr.rs new file mode 100644 index 0000000..3074105 --- /dev/null +++ b/va416xx/src/dma/chnl_req_mask_clr.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CHNL_REQ_MASK_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_REQ_MASK_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel Request Mask clear"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel Request Mask clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel Request Mask clear"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel Request Mask clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel Request Mask clear"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel Request Mask clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel Request Mask clear"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel Request Mask clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel Request Mask clear"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Request Mask clear"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel Request Mask clear"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel Request Mask clear"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel Request Mask clear"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel request mask clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_req_mask_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_req_mask_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlReqMaskClrSpec; +impl crate::RegisterSpec for ChnlReqMaskClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_req_mask_clr::R`](R) reader structure"] +impl crate::Readable for ChnlReqMaskClrSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_req_mask_clr::W`](W) writer structure"] +impl crate::Writable for ChnlReqMaskClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_REQ_MASK_CLR to value 0"] +impl crate::Resettable for ChnlReqMaskClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_req_mask_set.rs b/va416xx/src/dma/chnl_req_mask_set.rs new file mode 100644 index 0000000..ded1e6a --- /dev/null +++ b/va416xx/src/dma/chnl_req_mask_set.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CHNL_REQ_MASK_SET` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_REQ_MASK_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel Request Mask set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel Request Mask set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel Request Mask set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel Request Mask set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel Request Mask set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel Request Mask set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel Request Mask set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel Request Mask set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel Request Mask set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Request Mask set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Request Mask set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel Request Mask set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Request Mask set"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel Request Mask set"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel Request Mask set"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel Request Mask set"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel request mask set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_req_mask_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_req_mask_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlReqMaskSetSpec; +impl crate::RegisterSpec for ChnlReqMaskSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_req_mask_set::R`](R) reader structure"] +impl crate::Readable for ChnlReqMaskSetSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_req_mask_set::W`](W) writer structure"] +impl crate::Writable for ChnlReqMaskSetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_REQ_MASK_SET to value 0"] +impl crate::Resettable for ChnlReqMaskSetSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_sw_request.rs b/va416xx/src/dma/chnl_sw_request.rs new file mode 100644 index 0000000..4a72688 --- /dev/null +++ b/va416xx/src/dma/chnl_sw_request.rs @@ -0,0 +1,51 @@ +#[doc = "Register `CHNL_SW_REQUEST` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` writer - Channel SW request"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` writer - Channel SW request"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` writer - Channel SW request"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` writer - Channel SW request"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Channel SW request"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel SW request"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel SW request"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel SW request"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel software request\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_sw_request::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlSwRequestSpec; +impl crate::RegisterSpec for ChnlSwRequestSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`chnl_sw_request::W`](W) writer structure"] +impl crate::Writable for ChnlSwRequestSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_SW_REQUEST to value 0"] +impl crate::Resettable for ChnlSwRequestSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_useburst_clr.rs b/va416xx/src/dma/chnl_useburst_clr.rs new file mode 100644 index 0000000..622218d --- /dev/null +++ b/va416xx/src/dma/chnl_useburst_clr.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CHNL_USEBURST_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_USEBURST_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel use burst clear"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel use burst clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel use burst clear"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel use burst clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel use burst clear"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel use burst clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel use burst clear"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel use burst clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel use burst clear"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel use burst clear"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel use burst clear"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel use burst clear"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel use burst clear"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel use burst clear"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel use burst clear"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel use burst clear"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel useburst clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_useburst_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_useburst_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlUseburstClrSpec; +impl crate::RegisterSpec for ChnlUseburstClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_useburst_clr::R`](R) reader structure"] +impl crate::Readable for ChnlUseburstClrSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_useburst_clr::W`](W) writer structure"] +impl crate::Writable for ChnlUseburstClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_USEBURST_CLR to value 0"] +impl crate::Resettable for ChnlUseburstClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/chnl_useburst_set.rs b/va416xx/src/dma/chnl_useburst_set.rs new file mode 100644 index 0000000..432d463 --- /dev/null +++ b/va416xx/src/dma/chnl_useburst_set.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CHNL_USEBURST_SET` reader"] +pub type R = crate::R; +#[doc = "Register `CHNL_USEBURST_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - Channel use burst set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - Channel use burst set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - Channel use burst set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - Channel use burst set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - Channel use burst set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - Channel use burst set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - Channel use burst set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - Channel use burst set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Channel use burst set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel use burst set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel use burst set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel use burst set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel use burst set"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - Channel use burst set"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - Channel use burst set"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - Channel use burst set"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA channel useburst set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_useburst_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_useburst_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ChnlUseburstSetSpec; +impl crate::RegisterSpec for ChnlUseburstSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`chnl_useburst_set::R`](R) reader structure"] +impl crate::Readable for ChnlUseburstSetSpec {} +#[doc = "`write(|w| ..)` method takes [`chnl_useburst_set::W`](W) writer structure"] +impl crate::Writable for ChnlUseburstSetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CHNL_USEBURST_SET to value 0"] +impl crate::Resettable for ChnlUseburstSetSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/ctrl_base_ptr.rs b/va416xx/src/dma/ctrl_base_ptr.rs new file mode 100644 index 0000000..810ddc6 --- /dev/null +++ b/va416xx/src/dma/ctrl_base_ptr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `CTRL_BASE_PTR` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL_BASE_PTR` writer"] +pub type W = crate::W; +#[doc = "Field `CTRL_BASE_PTR` reader - Base Pointer for DMA Control Registers"] +pub type CtrlBasePtrR = crate::FieldReader; +#[doc = "Field `CTRL_BASE_PTR` writer - Base Pointer for DMA Control Registers"] +pub type CtrlBasePtrW<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>; +impl R { + #[doc = "Bits 7:31 - Base Pointer for DMA Control Registers"] + #[inline(always)] + pub fn ctrl_base_ptr(&self) -> CtrlBasePtrR { + CtrlBasePtrR::new((self.bits >> 7) & 0x01ff_ffff) + } +} +impl W { + #[doc = "Bits 7:31 - Base Pointer for DMA Control Registers"] + #[inline(always)] + #[must_use] + pub fn ctrl_base_ptr(&mut self) -> CtrlBasePtrW { + CtrlBasePtrW::new(self, 7) + } +} +#[doc = "Base Pointer for DMA Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl_base_ptr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl_base_ptr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlBasePtrSpec; +impl crate::RegisterSpec for CtrlBasePtrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl_base_ptr::R`](R) reader structure"] +impl crate::Readable for CtrlBasePtrSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl_base_ptr::W`](W) writer structure"] +impl crate::Writable for CtrlBasePtrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL_BASE_PTR to value 0"] +impl crate::Resettable for CtrlBasePtrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/dma_active_clr.rs b/va416xx/src/dma/dma_active_clr.rs new file mode 100644 index 0000000..0c962e3 --- /dev/null +++ b/va416xx/src/dma/dma_active_clr.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DMA_ACTIVE_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_ACTIVE_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA Active clear"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA Active clear"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA Active clear"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA Active clear"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA Active clear"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA Active clear"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA Active clear"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA Active clear"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA Active clear"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Active clear"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Active clear"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA Active clear"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Active clear"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA Active clear"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA Active clear"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA Active clear"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA active clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_active_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_active_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaActiveClrSpec; +impl crate::RegisterSpec for DmaActiveClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_active_clr::R`](R) reader structure"] +impl crate::Readable for DmaActiveClrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_active_clr::W`](W) writer structure"] +impl crate::Writable for DmaActiveClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_ACTIVE_CLR to value 0"] +impl crate::Resettable for DmaActiveClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/dma_active_set.rs b/va416xx/src/dma/dma_active_set.rs new file mode 100644 index 0000000..55f9f8e --- /dev/null +++ b/va416xx/src/dma/dma_active_set.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DMA_ACTIVE_SET` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_ACTIVE_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA Active Set"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA Active Set"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA Active Set"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA Active Set"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA Active Set"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA Active Set"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA Active Set"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA Active Set"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA Active Set"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Active Set"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Active Set"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA Active Set"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Active Set"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA Active Set"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA Active Set"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA Active Set"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA active set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_active_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_active_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaActiveSetSpec; +impl crate::RegisterSpec for DmaActiveSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_active_set::R`](R) reader structure"] +impl crate::Readable for DmaActiveSetSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_active_set::W`](W) writer structure"] +impl crate::Writable for DmaActiveSetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_ACTIVE_SET to value 0"] +impl crate::Resettable for DmaActiveSetSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/dma_done_clr.rs b/va416xx/src/dma/dma_done_clr.rs new file mode 100644 index 0000000..2a1091d --- /dev/null +++ b/va416xx/src/dma/dma_done_clr.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DMA_DONE_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_DONE_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA Done clear for this CH"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA Done clear for this CH"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA Done clear for this CH"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA Done clear for this CH"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA Done clear for this CH"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA Done clear for this CH"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA Done clear for this CH"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA Done clear for this CH"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA Done clear for this CH"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Done clear for this CH"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA Done clear for this CH"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA Done clear for this CH"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA Done clear for this CH"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA done clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_done_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_done_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaDoneClrSpec; +impl crate::RegisterSpec for DmaDoneClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_done_clr::R`](R) reader structure"] +impl crate::Readable for DmaDoneClrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_done_clr::W`](W) writer structure"] +impl crate::Writable for DmaDoneClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_DONE_CLR to value 0"] +impl crate::Resettable for DmaDoneClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/dma_done_set.rs b/va416xx/src/dma/dma_done_set.rs new file mode 100644 index 0000000..632ac90 --- /dev/null +++ b/va416xx/src/dma/dma_done_set.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DMA_DONE_SET` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_DONE_SET` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA Done Set for this CH"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA Done Set for this CH"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA Done Set for this CH"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA Done Set for this CH"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA Done Set for this CH"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA Done Set for this CH"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA Done Set for this CH"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA Done Set for this CH"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA Done Set for this CH"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Done Set for this CH"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA Done Set for this CH"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA Done Set for this CH"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA Done Set for this CH"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA done set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_done_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_done_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaDoneSetSpec; +impl crate::RegisterSpec for DmaDoneSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_done_set::R`](R) reader structure"] +impl crate::Readable for DmaDoneSetSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_done_set::W`](W) writer structure"] +impl crate::Writable for DmaDoneSetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_DONE_SET to value 0"] +impl crate::Resettable for DmaDoneSetSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/dma_req_status.rs b/va416xx/src/dma/dma_req_status.rs new file mode 100644 index 0000000..b93aeeb --- /dev/null +++ b/va416xx/src/dma/dma_req_status.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DMA_REQ_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_REQ_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA Request Status for this CH"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA Request Status for this CH"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA Request Status for this CH"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA Request Status for this CH"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA Request Status for this CH"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA Request Status for this CH"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA Request Status for this CH"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA Request Status for this CH"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA Request Status for this CH"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA Request Status for this CH"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA Request Status for this CH"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA Request Status for this CH"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA Request Status for this CH"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaReqStatusSpec; +impl crate::RegisterSpec for DmaReqStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_req_status::R`](R) reader structure"] +impl crate::Readable for DmaReqStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_req_status::W`](W) writer structure"] +impl crate::Writable for DmaReqStatusSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_REQ_STATUS to value 0"] +impl crate::Resettable for DmaReqStatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/dma_sreq_status.rs b/va416xx/src/dma/dma_sreq_status.rs new file mode 100644 index 0000000..a091bfb --- /dev/null +++ b/va416xx/src/dma/dma_sreq_status.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DMA_SREQ_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_SREQ_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `CH0` reader - DMA SRequest Status for this CH"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH0` writer - DMA SRequest Status for this CH"] +pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH1` reader - DMA SRequest Status for this CH"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH1` writer - DMA SRequest Status for this CH"] +pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH2` reader - DMA SRequest Status for this CH"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH2` writer - DMA SRequest Status for this CH"] +pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CH3` reader - DMA SRequest Status for this CH"] +pub type Ch3R = crate::BitReader; +#[doc = "Field `CH3` writer - DMA SRequest Status for this CH"] +pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA SRequest Status for this CH"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - DMA SRequest Status for this CH"] + #[inline(always)] + #[must_use] + pub fn ch0(&mut self) -> Ch0W { + Ch0W::new(self, 0) + } + #[doc = "Bit 1 - DMA SRequest Status for this CH"] + #[inline(always)] + #[must_use] + pub fn ch1(&mut self) -> Ch1W { + Ch1W::new(self, 1) + } + #[doc = "Bit 2 - DMA SRequest Status for this CH"] + #[inline(always)] + #[must_use] + pub fn ch2(&mut self) -> Ch2W { + Ch2W::new(self, 2) + } + #[doc = "Bit 3 - DMA SRequest Status for this CH"] + #[inline(always)] + #[must_use] + pub fn ch3(&mut self) -> Ch3W { + Ch3W::new(self, 3) + } +} +#[doc = "DMA single request status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_sreq_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_sreq_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaSreqStatusSpec; +impl crate::RegisterSpec for DmaSreqStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_sreq_status::R`](R) reader structure"] +impl crate::Readable for DmaSreqStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_sreq_status::W`](W) writer structure"] +impl crate::Writable for DmaSreqStatusSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_SREQ_STATUS to value 0"] +impl crate::Resettable for DmaSreqStatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/err_clr.rs b/va416xx/src/dma/err_clr.rs new file mode 100644 index 0000000..aecfeea --- /dev/null +++ b/va416xx/src/dma/err_clr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ERR_CLR` reader"] +pub type R = crate::R; +#[doc = "Register `ERR_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `ERR_CLR` reader - Error Clear"] +pub type ErrClrR = crate::BitReader; +#[doc = "Field `ERR_CLR` writer - Error Clear"] +pub type ErrClrW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + pub fn err_clr(&self) -> ErrClrR { + ErrClrR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + #[must_use] + pub fn err_clr(&mut self) -> ErrClrW { + ErrClrW::new(self, 0) + } +} +#[doc = "DMA bus error clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ErrClrSpec; +impl crate::RegisterSpec for ErrClrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`err_clr::R`](R) reader structure"] +impl crate::Readable for ErrClrSpec {} +#[doc = "`write(|w| ..)` method takes [`err_clr::W`](W) writer structure"] +impl crate::Writable for ErrClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ERR_CLR to value 0"] +impl crate::Resettable for ErrClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/err_set.rs b/va416xx/src/dma/err_set.rs new file mode 100644 index 0000000..02b3c6b --- /dev/null +++ b/va416xx/src/dma/err_set.rs @@ -0,0 +1,31 @@ +#[doc = "Register `ERR_SET` reader"] +pub type R = crate::R; +#[doc = "Register `ERR_SET` writer"] +pub type W = crate::W; +#[doc = "Field `ERR_SET` reader - Set Error"] +pub type ErrSetR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Set Error"] + #[inline(always)] + pub fn err_set(&self) -> ErrSetR { + ErrSetR::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "DMA bus error set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_set::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ErrSetSpec; +impl crate::RegisterSpec for ErrSetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`err_set::R`](R) reader structure"] +impl crate::Readable for ErrSetSpec {} +#[doc = "`write(|w| ..)` method takes [`err_set::W`](W) writer structure"] +impl crate::Writable for ErrSetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ERR_SET to value 0"] +impl crate::Resettable for ErrSetSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/integration_cfg.rs b/va416xx/src/dma/integration_cfg.rs new file mode 100644 index 0000000..cc131c1 --- /dev/null +++ b/va416xx/src/dma/integration_cfg.rs @@ -0,0 +1,40 @@ +#[doc = "Register `INTEGRATION_CFG` reader"] +pub type R = crate::R; +#[doc = "Register `INTEGRATION_CFG` writer"] +pub type W = crate::W; +#[doc = "Field `INT_TEST_EN` reader - Error Clear"] +pub type IntTestEnR = crate::BitReader; +#[doc = "Field `INT_TEST_EN` writer - Error Clear"] +pub type IntTestEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + pub fn int_test_en(&self) -> IntTestEnR { + IntTestEnR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Error Clear"] + #[inline(always)] + #[must_use] + pub fn int_test_en(&mut self) -> IntTestEnW { + IntTestEnW::new(self, 0) + } +} +#[doc = "DMA integration configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`integration_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`integration_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IntegrationCfgSpec; +impl crate::RegisterSpec for IntegrationCfgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`integration_cfg::R`](R) reader structure"] +impl crate::Readable for IntegrationCfgSpec {} +#[doc = "`write(|w| ..)` method takes [`integration_cfg::W`](W) writer structure"] +impl crate::Writable for IntegrationCfgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets INTEGRATION_CFG to value 0"] +impl crate::Resettable for IntegrationCfgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/periph_id_0.rs b/va416xx/src/dma/periph_id_0.rs new file mode 100644 index 0000000..b54baa4 --- /dev/null +++ b/va416xx/src/dma/periph_id_0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PERIPH_ID_0` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPH_ID_0` writer"] +pub type W = crate::W; +#[doc = "Field `PART_NUMBER_0` reader - Part Number"] +pub type PartNumber0R = crate::FieldReader; +#[doc = "Field `PART_NUMBER_0` writer - Part Number"] +pub type PartNumber0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Part Number"] + #[inline(always)] + pub fn part_number_0(&self) -> PartNumber0R { + PartNumber0R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Part Number"] + #[inline(always)] + #[must_use] + pub fn part_number_0(&mut self) -> PartNumber0W { + PartNumber0W::new(self, 0) + } +} +#[doc = "DMA Peripheral ID 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeriphId0Spec; +impl crate::RegisterSpec for PeriphId0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`periph_id_0::R`](R) reader structure"] +impl crate::Readable for PeriphId0Spec {} +#[doc = "`write(|w| ..)` method takes [`periph_id_0::W`](W) writer structure"] +impl crate::Writable for PeriphId0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERIPH_ID_0 to value 0x30"] +impl crate::Resettable for PeriphId0Spec { + const RESET_VALUE: u32 = 0x30; +} diff --git a/va416xx/src/dma/periph_id_1.rs b/va416xx/src/dma/periph_id_1.rs new file mode 100644 index 0000000..e8cef83 --- /dev/null +++ b/va416xx/src/dma/periph_id_1.rs @@ -0,0 +1,29 @@ +#[doc = "Register `PERIPH_ID_1` reader"] +pub type R = crate::R; +#[doc = "Field `PART_NUMBER_1` reader - Part Number 1"] +pub type PartNumber1R = crate::FieldReader; +#[doc = "Field `JEP106_ID_3_0` reader - Indentity Code"] +pub type Jep106Id3_0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Part Number 1"] + #[inline(always)] + pub fn part_number_1(&self) -> PartNumber1R { + PartNumber1R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Indentity Code"] + #[inline(always)] + pub fn jep106_id_3_0(&self) -> Jep106Id3_0R { + Jep106Id3_0R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "DMA Peripheral ID 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeriphId1Spec; +impl crate::RegisterSpec for PeriphId1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`periph_id_1::R`](R) reader structure"] +impl crate::Readable for PeriphId1Spec {} +#[doc = "`reset()` method sets PERIPH_ID_1 to value 0xb2"] +impl crate::Resettable for PeriphId1Spec { + const RESET_VALUE: u32 = 0xb2; +} diff --git a/va416xx/src/dma/periph_id_2.rs b/va416xx/src/dma/periph_id_2.rs new file mode 100644 index 0000000..8f7bcf2 --- /dev/null +++ b/va416xx/src/dma/periph_id_2.rs @@ -0,0 +1,70 @@ +#[doc = "Register `PERIPH_ID_2` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPH_ID_2` writer"] +pub type W = crate::W; +#[doc = "Field `JEP106_ID_6_4` reader - JEP106"] +pub type Jep106Id6_4R = crate::FieldReader; +#[doc = "Field `JEP106_ID_6_4` writer - JEP106"] +pub type Jep106Id6_4W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `JEDEC_USED` reader - JEDEC"] +pub type JedecUsedR = crate::BitReader; +#[doc = "Field `JEDEC_USED` writer - JEDEC"] +pub type JedecUsedW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REVISION` reader - Revision"] +pub type RevisionR = crate::FieldReader; +#[doc = "Field `REVISION` writer - Revision"] +pub type RevisionW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:2 - JEP106"] + #[inline(always)] + pub fn jep106_id_6_4(&self) -> Jep106Id6_4R { + Jep106Id6_4R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - JEDEC"] + #[inline(always)] + pub fn jedec_used(&self) -> JedecUsedR { + JedecUsedR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - Revision"] + #[inline(always)] + pub fn revision(&self) -> RevisionR { + RevisionR::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - JEP106"] + #[inline(always)] + #[must_use] + pub fn jep106_id_6_4(&mut self) -> Jep106Id6_4W { + Jep106Id6_4W::new(self, 0) + } + #[doc = "Bit 3 - JEDEC"] + #[inline(always)] + #[must_use] + pub fn jedec_used(&mut self) -> JedecUsedW { + JedecUsedW::new(self, 3) + } + #[doc = "Bits 4:7 - Revision"] + #[inline(always)] + #[must_use] + pub fn revision(&mut self) -> RevisionW { + RevisionW::new(self, 4) + } +} +#[doc = "DMA Peripheral ID 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeriphId2Spec; +impl crate::RegisterSpec for PeriphId2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`periph_id_2::R`](R) reader structure"] +impl crate::Readable for PeriphId2Spec {} +#[doc = "`write(|w| ..)` method takes [`periph_id_2::W`](W) writer structure"] +impl crate::Writable for PeriphId2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERIPH_ID_2 to value 0xbc"] +impl crate::Resettable for PeriphId2Spec { + const RESET_VALUE: u32 = 0xbc; +} diff --git a/va416xx/src/dma/periph_id_3.rs b/va416xx/src/dma/periph_id_3.rs new file mode 100644 index 0000000..94d92ce --- /dev/null +++ b/va416xx/src/dma/periph_id_3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PERIPH_ID_3` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPH_ID_3` writer"] +pub type W = crate::W; +#[doc = "Field `MOD_NUMBER` reader - Controller Modifications"] +pub type ModNumberR = crate::FieldReader; +#[doc = "Field `MOD_NUMBER` writer - Controller Modifications"] +pub type ModNumberW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - Controller Modifications"] + #[inline(always)] + pub fn mod_number(&self) -> ModNumberR { + ModNumberR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Controller Modifications"] + #[inline(always)] + #[must_use] + pub fn mod_number(&mut self) -> ModNumberW { + ModNumberW::new(self, 0) + } +} +#[doc = "DMA Peripheral ID 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeriphId3Spec; +impl crate::RegisterSpec for PeriphId3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`periph_id_3::R`](R) reader structure"] +impl crate::Readable for PeriphId3Spec {} +#[doc = "`write(|w| ..)` method takes [`periph_id_3::W`](W) writer structure"] +impl crate::Writable for PeriphId3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERIPH_ID_3 to value 0"] +impl crate::Resettable for PeriphId3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/periph_id_4.rs b/va416xx/src/dma/periph_id_4.rs new file mode 100644 index 0000000..215d604 --- /dev/null +++ b/va416xx/src/dma/periph_id_4.rs @@ -0,0 +1,55 @@ +#[doc = "Register `PERIPH_ID_4` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPH_ID_4` writer"] +pub type W = crate::W; +#[doc = "Field `JEP106_C_CODE` reader - JEP106"] +pub type Jep106CCodeR = crate::FieldReader; +#[doc = "Field `JEP106_C_CODE` writer - JEP106"] +pub type Jep106CCodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `BLOCK_COUNT` reader - The Number of 4k Address Blocks Required"] +pub type BlockCountR = crate::FieldReader; +#[doc = "Field `BLOCK_COUNT` writer - The Number of 4k Address Blocks Required"] +pub type BlockCountW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - JEP106"] + #[inline(always)] + pub fn jep106_c_code(&self) -> Jep106CCodeR { + Jep106CCodeR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - The Number of 4k Address Blocks Required"] + #[inline(always)] + pub fn block_count(&self) -> BlockCountR { + BlockCountR::new(((self.bits >> 4) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - JEP106"] + #[inline(always)] + #[must_use] + pub fn jep106_c_code(&mut self) -> Jep106CCodeW { + Jep106CCodeW::new(self, 0) + } + #[doc = "Bits 4:7 - The Number of 4k Address Blocks Required"] + #[inline(always)] + #[must_use] + pub fn block_count(&mut self) -> BlockCountW { + BlockCountW::new(self, 4) + } +} +#[doc = "DMA Peripheral ID 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeriphId4Spec; +impl crate::RegisterSpec for PeriphId4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`periph_id_4::R`](R) reader structure"] +impl crate::Readable for PeriphId4Spec {} +#[doc = "`write(|w| ..)` method takes [`periph_id_4::W`](W) writer structure"] +impl crate::Writable for PeriphId4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERIPH_ID_4 to value 0x04"] +impl crate::Resettable for PeriphId4Spec { + const RESET_VALUE: u32 = 0x04; +} diff --git a/va416xx/src/dma/primecell_id_0.rs b/va416xx/src/dma/primecell_id_0.rs new file mode 100644 index 0000000..21fa74f --- /dev/null +++ b/va416xx/src/dma/primecell_id_0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PRIMECELL_ID_0` reader"] +pub type R = crate::R; +#[doc = "Register `PRIMECELL_ID_0` writer"] +pub type W = crate::W; +#[doc = "Field `PRIMECELL_ID_0` reader - PrimeCell Identification"] +pub type PrimecellId0R = crate::FieldReader; +#[doc = "Field `PRIMECELL_ID_0` writer - PrimeCell Identification"] +pub type PrimecellId0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_0(&self) -> PrimecellId0R { + PrimecellId0R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + #[must_use] + pub fn primecell_id_0(&mut self) -> PrimecellId0W { + PrimecellId0W::new(self, 0) + } +} +#[doc = "DMA PrimeCell ID 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrimecellId0Spec; +impl crate::RegisterSpec for PrimecellId0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`primecell_id_0::R`](R) reader structure"] +impl crate::Readable for PrimecellId0Spec {} +#[doc = "`write(|w| ..)` method takes [`primecell_id_0::W`](W) writer structure"] +impl crate::Writable for PrimecellId0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PRIMECELL_ID_0 to value 0x0d"] +impl crate::Resettable for PrimecellId0Spec { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/va416xx/src/dma/primecell_id_1.rs b/va416xx/src/dma/primecell_id_1.rs new file mode 100644 index 0000000..7afe1c7 --- /dev/null +++ b/va416xx/src/dma/primecell_id_1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PRIMECELL_ID_1` reader"] +pub type R = crate::R; +#[doc = "Register `PRIMECELL_ID_1` writer"] +pub type W = crate::W; +#[doc = "Field `PRIMECELL_ID_1` reader - PrimeCell Identification"] +pub type PrimecellId1R = crate::FieldReader; +#[doc = "Field `PRIMECELL_ID_1` writer - PrimeCell Identification"] +pub type PrimecellId1W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_1(&self) -> PrimecellId1R { + PrimecellId1R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + #[must_use] + pub fn primecell_id_1(&mut self) -> PrimecellId1W { + PrimecellId1W::new(self, 0) + } +} +#[doc = "DMA PrimeCell ID 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrimecellId1Spec; +impl crate::RegisterSpec for PrimecellId1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`primecell_id_1::R`](R) reader structure"] +impl crate::Readable for PrimecellId1Spec {} +#[doc = "`write(|w| ..)` method takes [`primecell_id_1::W`](W) writer structure"] +impl crate::Writable for PrimecellId1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PRIMECELL_ID_1 to value 0xf0"] +impl crate::Resettable for PrimecellId1Spec { + const RESET_VALUE: u32 = 0xf0; +} diff --git a/va416xx/src/dma/primecell_id_2.rs b/va416xx/src/dma/primecell_id_2.rs new file mode 100644 index 0000000..9f593e2 --- /dev/null +++ b/va416xx/src/dma/primecell_id_2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PRIMECELL_ID_2` reader"] +pub type R = crate::R; +#[doc = "Register `PRIMECELL_ID_2` writer"] +pub type W = crate::W; +#[doc = "Field `PRIMECELL_ID_2` reader - PrimeCell Identification"] +pub type PrimecellId2R = crate::FieldReader; +#[doc = "Field `PRIMECELL_ID_2` writer - PrimeCell Identification"] +pub type PrimecellId2W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_2(&self) -> PrimecellId2R { + PrimecellId2R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + #[must_use] + pub fn primecell_id_2(&mut self) -> PrimecellId2W { + PrimecellId2W::new(self, 0) + } +} +#[doc = "DMA PrimeCell ID 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrimecellId2Spec; +impl crate::RegisterSpec for PrimecellId2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`primecell_id_2::R`](R) reader structure"] +impl crate::Readable for PrimecellId2Spec {} +#[doc = "`write(|w| ..)` method takes [`primecell_id_2::W`](W) writer structure"] +impl crate::Writable for PrimecellId2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PRIMECELL_ID_2 to value 0x05"] +impl crate::Resettable for PrimecellId2Spec { + const RESET_VALUE: u32 = 0x05; +} diff --git a/va416xx/src/dma/primecell_id_3.rs b/va416xx/src/dma/primecell_id_3.rs new file mode 100644 index 0000000..36e5875 --- /dev/null +++ b/va416xx/src/dma/primecell_id_3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PRIMECELL_ID_3` reader"] +pub type R = crate::R; +#[doc = "Register `PRIMECELL_ID_3` writer"] +pub type W = crate::W; +#[doc = "Field `PRIMECELL_ID_3` reader - PrimeCell Identification"] +pub type PrimecellId3R = crate::FieldReader; +#[doc = "Field `PRIMECELL_ID_3` writer - PrimeCell Identification"] +pub type PrimecellId3W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + pub fn primecell_id_3(&self) -> PrimecellId3R { + PrimecellId3R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - PrimeCell Identification"] + #[inline(always)] + #[must_use] + pub fn primecell_id_3(&mut self) -> PrimecellId3W { + PrimecellId3W::new(self, 0) + } +} +#[doc = "DMA PrimeCell ID 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PrimecellId3Spec; +impl crate::RegisterSpec for PrimecellId3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`primecell_id_3::R`](R) reader structure"] +impl crate::Readable for PrimecellId3Spec {} +#[doc = "`write(|w| ..)` method takes [`primecell_id_3::W`](W) writer structure"] +impl crate::Writable for PrimecellId3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PRIMECELL_ID_3 to value 0xb1"] +impl crate::Resettable for PrimecellId3Spec { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/va416xx/src/dma/stall_status.rs b/va416xx/src/dma/stall_status.rs new file mode 100644 index 0000000..067c1ae --- /dev/null +++ b/va416xx/src/dma/stall_status.rs @@ -0,0 +1,31 @@ +#[doc = "Register `STALL_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `STALL_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `STALL_STATUS` reader - DMA is stalled"] +pub type StallStatusR = crate::BitReader; +impl R { + #[doc = "Bit 0 - DMA is stalled"] + #[inline(always)] + pub fn stall_status(&self) -> StallStatusR { + StallStatusR::new((self.bits & 1) != 0) + } +} +impl W {} +#[doc = "DMA stall status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stall_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stall_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StallStatusSpec; +impl crate::RegisterSpec for StallStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`stall_status::R`](R) reader structure"] +impl crate::Readable for StallStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`stall_status::W`](W) writer structure"] +impl crate::Writable for StallStatusSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STALL_STATUS to value 0"] +impl crate::Resettable for StallStatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/status.rs b/va416xx/src/dma/status.rs new file mode 100644 index 0000000..65dfd07 --- /dev/null +++ b/va416xx/src/dma/status.rs @@ -0,0 +1,43 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `MASTER_ENABLE` reader - Enable status of the controller"] +pub type MasterEnableR = crate::BitReader; +#[doc = "Field `STATE` reader - Current State of the control state machine"] +pub type StateR = crate::FieldReader; +#[doc = "Field `CHNLS_MINUS1` reader - Number of Available Channels Minus 1"] +pub type ChnlsMinus1R = crate::FieldReader; +#[doc = "Field `TEST_STATUS` reader - Test Status Logic Included"] +pub type TestStatusR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Enable status of the controller"] + #[inline(always)] + pub fn master_enable(&self) -> MasterEnableR { + MasterEnableR::new((self.bits & 1) != 0) + } + #[doc = "Bits 4:7 - Current State of the control state machine"] + #[inline(always)] + pub fn state(&self) -> StateR { + StateR::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 16:20 - Number of Available Channels Minus 1"] + #[inline(always)] + pub fn chnls_minus1(&self) -> ChnlsMinus1R { + ChnlsMinus1R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Test Status Logic Included"] + #[inline(always)] + pub fn test_status(&self) -> TestStatusR { + TestStatusR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "DMA Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/dma/waitonreq_status.rs b/va416xx/src/dma/waitonreq_status.rs new file mode 100644 index 0000000..a5cdb49 --- /dev/null +++ b/va416xx/src/dma/waitonreq_status.rs @@ -0,0 +1,43 @@ +#[doc = "Register `WAITONREQ_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `CH0` reader - DMA wait on request"] +pub type Ch0R = crate::BitReader; +#[doc = "Field `CH1` reader - DMA wait on request"] +pub type Ch1R = crate::BitReader; +#[doc = "Field `CH2` reader - DMA wait on request"] +pub type Ch2R = crate::BitReader; +#[doc = "Field `CH3` reader - DMA wait on request"] +pub type Ch3R = crate::BitReader; +impl R { + #[doc = "Bit 0 - DMA wait on request"] + #[inline(always)] + pub fn ch0(&self) -> Ch0R { + Ch0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA wait on request"] + #[inline(always)] + pub fn ch1(&self) -> Ch1R { + Ch1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DMA wait on request"] + #[inline(always)] + pub fn ch2(&self) -> Ch2R { + Ch2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMA wait on request"] + #[inline(always)] + pub fn ch3(&self) -> Ch3R { + Ch3R::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "DMA channel wait on request status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`waitonreq_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WaitonreqStatusSpec; +impl crate::RegisterSpec for WaitonreqStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`waitonreq_status::R`](R) reader structure"] +impl crate::Readable for WaitonreqStatusSpec {} +#[doc = "`reset()` method sets WAITONREQ_STATUS to value 0"] +impl crate::Resettable for WaitonreqStatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth.rs b/va416xx/src/eth.rs new file mode 100644 index 0000000..d547318 --- /dev/null +++ b/va416xx/src/eth.rs @@ -0,0 +1,1157 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + mac_config: MacConfig, + mac_frame_fltr: MacFrameFltr, + _reserved2: [u8; 0x08], + mac_gmii_addr: MacGmiiAddr, + mac_gmii_data: MacGmiiData, + mac_flow_ctrl: MacFlowCtrl, + mac_vlan_tag: MacVlanTag, + _reserved6: [u8; 0x04], + mac_debug: MacDebug, + _reserved7: [u8; 0x10], + mac_intr_stat: MacIntrStat, + mac_intr_mask: MacIntrMask, + mac_addr_h: MacAddrH, + mac_addr_l: MacAddrL, + _reserved11: [u8; 0x94], + mac_wdog_to: MacWdogTo, + _reserved12: [u8; 0x20], + mmc_cntrl: MmcCntrl, + mmc_intr_rx: MmcIntrRx, + mmc_intr_tx: MmcIntrTx, + mmc_intr_mask_rx: MmcIntrMaskRx, + mmc_intr_mask_tx: MmcIntrMaskTx, + txoctetcount_gb: TxoctetcountGb, + txframecount_gb: TxframecountGb, + txbcastframes_g: TxbcastframesG, + txmcastframes_g: TxmcastframesG, + tx64oct_gb: Tx64octGb, + tx65to127oct_gb: Tx65to127octGb, + tx128to255oct_gb: Tx128to255octGb, + tx256to511oct_gb: Tx256to511octGb, + tx512to1023oct_gb: Tx512to1023octGb, + tx1024maxoct_gb: Tx1024maxoctGb, + txucastframe_gb: TxucastframeGb, + txmcastframe_gb: TxmcastframeGb, + txbcastframe_gb: TxbcastframeGb, + txundererr: Txundererr, + txsinglecol_g: TxsinglecolG, + txmulticol_g: TxmulticolG, + txdeferred: Txdeferred, + txlatecol: Txlatecol, + txexesscol: Txexesscol, + txcarriererror: Txcarriererror, + txoctetcount_g: TxoctetcountG, + txframecount_g: TxframecountG, + txexcessdef: Txexcessdef, + txpauseframes: Txpauseframes, + txlanframes_g: TxlanframesG, + txoversize_g: TxoversizeG, + _reserved43: [u8; 0x04], + rxframecount_gb: RxframecountGb, + rxoctetcount_gb: RxoctetcountGb, + rxoctetcount_g: RxoctetcountG, + rxbcastframes_g: RxbcastframesG, + rxmcastframes_g: RxmcastframesG, + rxcrcerror: Rxcrcerror, + rxalignerror: Rxalignerror, + rxrunterror: Rxrunterror, + rxjabbererror: Rxjabbererror, + rxundersize_g: RxundersizeG, + rxoversize_g: RxoversizeG, + rx64octets_gb: Rx64octetsGb, + rx65to127oct_gb: Rx65to127octGb, + rx128to255oct_gb: Rx128to255octGb, + rx256to511oct_gb: Rx256to511octGb, + rx512to1023oct_gb: Rx512to1023octGb, + rx1024maxoct_gb: Rx1024maxoctGb, + rxucastframes_g: RxucastframesG, + rxlengtherror: Rxlengtherror, + rxoutrangetype: Rxoutrangetype, + rxpauseframes: Rxpauseframes, + rxfifooverflow: Rxfifooverflow, + rxvlanframes_gb: RxvlanframesGb, + rxwdogerror: Rxwdogerror, + rxrcverror: Rxrcverror, + rxctrlframes_g: RxctrlframesG, + _reserved69: [u8; 0x039c], + vlan_increplace: VlanIncreplace, + vlan_hashtable: VlanHashtable, + _reserved71: [u8; 0x0174], + timestamp_ctrl: TimestampCtrl, + subsec_inc: SubsecInc, + systime_seconds: SystimeSeconds, + systime_nanosec: SystimeNanosec, + systime_secsupdat: SystimeSecsupdat, + systime_nsecup: SystimeNsecup, + timestampaddend: Timestampaddend, + target_time_secs: TargetTimeSecs, + target_time_nsec: TargetTimeNsec, + _reserved80: [u8; 0x08dc], + dma_bus_mode: DmaBusMode, + dma_tx_poll_demand: DmaTxPollDemand, + dma_rx_poll_demand: DmaRxPollDemand, + dma_rx_desc_list_addr: DmaRxDescListAddr, + dma_tx_desc_list_addr: DmaTxDescListAddr, + dma_status: DmaStatus, + dma_oper_mode: DmaOperMode, + dma_intr_en: DmaIntrEn, + dma_miss_over_counter: DmaMissOverCounter, + dma_rx_intr_wdog_timer: DmaRxIntrWdogTimer, + _reserved90: [u8; 0x04], + dma_ahb_status: DmaAhbStatus, + _reserved91: [u8; 0x18], + dma_curr_tx_desc: DmaCurrTxDesc, + dma_curr_rx_desc: DmaCurrRxDesc, + dma_curr_tx_bufr_addr: DmaCurrTxBufrAddr, + dma_curr_rx_bufr_addr: DmaCurrRxBufrAddr, +} +impl RegisterBlock { + #[doc = "0x00 - Operation mode register for the MAC"] + #[inline(always)] + pub const fn mac_config(&self) -> &MacConfig { + &self.mac_config + } + #[doc = "0x04 - Contains the frame filtering controls"] + #[inline(always)] + pub const fn mac_frame_fltr(&self) -> &MacFrameFltr { + &self.mac_frame_fltr + } + #[doc = "0x10 - Controls the management cycles to an external PHY"] + #[inline(always)] + pub const fn mac_gmii_addr(&self) -> &MacGmiiAddr { + &self.mac_gmii_addr + } + #[doc = "0x14 - Contains the data to be written to or read from the PHY register"] + #[inline(always)] + pub const fn mac_gmii_data(&self) -> &MacGmiiData { + &self.mac_gmii_data + } + #[doc = "0x18 - Controls the generation of control frames"] + #[inline(always)] + pub const fn mac_flow_ctrl(&self) -> &MacFlowCtrl { + &self.mac_flow_ctrl + } + #[doc = "0x1c - Identifies IEEE 802.1Q VLAN type frames"] + #[inline(always)] + pub const fn mac_vlan_tag(&self) -> &MacVlanTag { + &self.mac_vlan_tag + } + #[doc = "0x24 - Gives the status of the various internal blocks for debugging"] + #[inline(always)] + pub const fn mac_debug(&self) -> &MacDebug { + &self.mac_debug + } + #[doc = "0x38 - Contains the interrupt status"] + #[inline(always)] + pub const fn mac_intr_stat(&self) -> &MacIntrStat { + &self.mac_intr_stat + } + #[doc = "0x3c - Contains the masks for generating interrupt"] + #[inline(always)] + pub const fn mac_intr_mask(&self) -> &MacIntrMask { + &self.mac_intr_mask + } + #[doc = "0x40 - Contains the high 16-bits of the first MAC Address"] + #[inline(always)] + pub const fn mac_addr_h(&self) -> &MacAddrH { + &self.mac_addr_h + } + #[doc = "0x44 - Contains the Low 32-bits of the first MAC Address"] + #[inline(always)] + pub const fn mac_addr_l(&self) -> &MacAddrL { + &self.mac_addr_l + } + #[doc = "0xdc - Controls the watchdog time-out for received frames"] + #[inline(always)] + pub const fn mac_wdog_to(&self) -> &MacWdogTo { + &self.mac_wdog_to + } + #[doc = "0x100 - MMC Control Register"] + #[inline(always)] + pub const fn mmc_cntrl(&self) -> &MmcCntrl { + &self.mmc_cntrl + } + #[doc = "0x104 - MMC Receive Interrupt Register"] + #[inline(always)] + pub const fn mmc_intr_rx(&self) -> &MmcIntrRx { + &self.mmc_intr_rx + } + #[doc = "0x108 - MMC Transmit Interrupt Register"] + #[inline(always)] + pub const fn mmc_intr_tx(&self) -> &MmcIntrTx { + &self.mmc_intr_tx + } + #[doc = "0x10c - MMC Receive Interrupt Mask Register"] + #[inline(always)] + pub const fn mmc_intr_mask_rx(&self) -> &MmcIntrMaskRx { + &self.mmc_intr_mask_rx + } + #[doc = "0x110 - MMC Transmit Interrupt Mask Register"] + #[inline(always)] + pub const fn mmc_intr_mask_tx(&self) -> &MmcIntrMaskTx { + &self.mmc_intr_mask_tx + } + #[doc = "0x114 - MMC Transmit Count"] + #[inline(always)] + pub const fn txoctetcount_gb(&self) -> &TxoctetcountGb { + &self.txoctetcount_gb + } + #[doc = "0x118 - MMC Frame Count Register"] + #[inline(always)] + pub const fn txframecount_gb(&self) -> &TxframecountGb { + &self.txframecount_gb + } + #[doc = "0x11c - MMC Good Broadcast Frames Register"] + #[inline(always)] + pub const fn txbcastframes_g(&self) -> &TxbcastframesG { + &self.txbcastframes_g + } + #[doc = "0x120 - MMC Good Multicast Frames Register"] + #[inline(always)] + pub const fn txmcastframes_g(&self) -> &TxmcastframesG { + &self.txmcastframes_g + } + #[doc = "0x124 - MMC Good and bad Frames transmitted with length 64"] + #[inline(always)] + pub const fn tx64oct_gb(&self) -> &Tx64octGb { + &self.tx64oct_gb + } + #[doc = "0x128 - MMC Good and bad Frames transmitted with length 65 to 127"] + #[inline(always)] + pub const fn tx65to127oct_gb(&self) -> &Tx65to127octGb { + &self.tx65to127oct_gb + } + #[doc = "0x12c - MMC Good and bad Frames transmitted with length 128 to 255"] + #[inline(always)] + pub const fn tx128to255oct_gb(&self) -> &Tx128to255octGb { + &self.tx128to255oct_gb + } + #[doc = "0x130 - MMC Good and bad Frames transmitted with length 256 to 511"] + #[inline(always)] + pub const fn tx256to511oct_gb(&self) -> &Tx256to511octGb { + &self.tx256to511oct_gb + } + #[doc = "0x134 - MMC Good and bad Frames transmitted with length 512 to 1023"] + #[inline(always)] + pub const fn tx512to1023oct_gb(&self) -> &Tx512to1023octGb { + &self.tx512to1023oct_gb + } + #[doc = "0x138 - MMC Good and bad Frames transmitted with length 1024 to max bytes"] + #[inline(always)] + pub const fn tx1024maxoct_gb(&self) -> &Tx1024maxoctGb { + &self.tx1024maxoct_gb + } + #[doc = "0x13c - MMC number of good and bad unicast frames transmitted"] + #[inline(always)] + pub const fn txucastframe_gb(&self) -> &TxucastframeGb { + &self.txucastframe_gb + } + #[doc = "0x140 - MMC number of good and bad MULTIcast frames transmitted"] + #[inline(always)] + pub const fn txmcastframe_gb(&self) -> &TxmcastframeGb { + &self.txmcastframe_gb + } + #[doc = "0x144 - MMC number of good and bad broadcast frames transmitted"] + #[inline(always)] + pub const fn txbcastframe_gb(&self) -> &TxbcastframeGb { + &self.txbcastframe_gb + } + #[doc = "0x148 - MMC number of frames aborted because of frame underflow error"] + #[inline(always)] + pub const fn txundererr(&self) -> &Txundererr { + &self.txundererr + } + #[doc = "0x14c - MMC Number of successfully transmitted frames after a single collision"] + #[inline(always)] + pub const fn txsinglecol_g(&self) -> &TxsinglecolG { + &self.txsinglecol_g + } + #[doc = "0x150 - MMC Number of successfully transmitted frames after multiple collisions"] + #[inline(always)] + pub const fn txmulticol_g(&self) -> &TxmulticolG { + &self.txmulticol_g + } + #[doc = "0x154 - MMC Number of successfully transmitted frames after a deferral"] + #[inline(always)] + pub const fn txdeferred(&self) -> &Txdeferred { + &self.txdeferred + } + #[doc = "0x158 - MMC Number of aborted frames because of late collision error"] + #[inline(always)] + pub const fn txlatecol(&self) -> &Txlatecol { + &self.txlatecol + } + #[doc = "0x15c - MMC Number of aborted frames because of excessive collision errors"] + #[inline(always)] + pub const fn txexesscol(&self) -> &Txexesscol { + &self.txexesscol + } + #[doc = "0x160 - MMC Number of aborted frames because of carrier sense error"] + #[inline(always)] + pub const fn txcarriererror(&self) -> &Txcarriererror { + &self.txcarriererror + } + #[doc = "0x164 - MMC Number of bytes transmitted frames only in good frames"] + #[inline(always)] + pub const fn txoctetcount_g(&self) -> &TxoctetcountG { + &self.txoctetcount_g + } + #[doc = "0x168 - MMC Number of good frames transmitted"] + #[inline(always)] + pub const fn txframecount_g(&self) -> &TxframecountG { + &self.txframecount_g + } + #[doc = "0x16c - MMC Number of frames aborted because of excessive deferral error"] + #[inline(always)] + pub const fn txexcessdef(&self) -> &Txexcessdef { + &self.txexcessdef + } + #[doc = "0x170 - MMC Number of good pause frames transmitted"] + #[inline(always)] + pub const fn txpauseframes(&self) -> &Txpauseframes { + &self.txpauseframes + } + #[doc = "0x174 - MMC Number of good VLAN frames transmitted"] + #[inline(always)] + pub const fn txlanframes_g(&self) -> &TxlanframesG { + &self.txlanframes_g + } + #[doc = "0x178 - MMC Number of frames transmitted without errors"] + #[inline(always)] + pub const fn txoversize_g(&self) -> &TxoversizeG { + &self.txoversize_g + } + #[doc = "0x180 - MMC Number of good and bad frames received"] + #[inline(always)] + pub const fn rxframecount_gb(&self) -> &RxframecountGb { + &self.rxframecount_gb + } + #[doc = "0x184 - MMC Number of bytes received in good and bad frames"] + #[inline(always)] + pub const fn rxoctetcount_gb(&self) -> &RxoctetcountGb { + &self.rxoctetcount_gb + } + #[doc = "0x188 - MMC Number of bytes received in good frames only"] + #[inline(always)] + pub const fn rxoctetcount_g(&self) -> &RxoctetcountG { + &self.rxoctetcount_g + } + #[doc = "0x18c - MMC Number of good broadcast frames received"] + #[inline(always)] + pub const fn rxbcastframes_g(&self) -> &RxbcastframesG { + &self.rxbcastframes_g + } + #[doc = "0x190 - MMC Number of good multicast frames received"] + #[inline(always)] + pub const fn rxmcastframes_g(&self) -> &RxmcastframesG { + &self.rxmcastframes_g + } + #[doc = "0x194 - MMC Number of frames received with CRC error"] + #[inline(always)] + pub const fn rxcrcerror(&self) -> &Rxcrcerror { + &self.rxcrcerror + } + #[doc = "0x198 - MMC Number of frames received with alignment error"] + #[inline(always)] + pub const fn rxalignerror(&self) -> &Rxalignerror { + &self.rxalignerror + } + #[doc = "0x19c - MMC Number of frames received with runt error"] + #[inline(always)] + pub const fn rxrunterror(&self) -> &Rxrunterror { + &self.rxrunterror + } + #[doc = "0x1a0 - MMC Number of giant frames received with length greater than 1518 bytes and with CRC error"] + #[inline(always)] + pub const fn rxjabbererror(&self) -> &Rxjabbererror { + &self.rxjabbererror + } + #[doc = "0x1a4 - MMC Number of frames received with length less than 64 bytes"] + #[inline(always)] + pub const fn rxundersize_g(&self) -> &RxundersizeG { + &self.rxundersize_g + } + #[doc = "0x1a8 - MMC Number of frames received without errors with length greater than the max size"] + #[inline(always)] + pub const fn rxoversize_g(&self) -> &RxoversizeG { + &self.rxoversize_g + } + #[doc = "0x1ac - MMC Number of good and bad frames received with length 64 bytes"] + #[inline(always)] + pub const fn rx64octets_gb(&self) -> &Rx64octetsGb { + &self.rx64octets_gb + } + #[doc = "0x1b0 - MMC Number of good and bad frames received with length between 65 and 127 bytes"] + #[inline(always)] + pub const fn rx65to127oct_gb(&self) -> &Rx65to127octGb { + &self.rx65to127oct_gb + } + #[doc = "0x1b4 - MMC Number of good and bad frames received with length between 128 and 255 bytes"] + #[inline(always)] + pub const fn rx128to255oct_gb(&self) -> &Rx128to255octGb { + &self.rx128to255oct_gb + } + #[doc = "0x1b8 - MMC Number of good and bad frames received with length between 256 and 511 bytes"] + #[inline(always)] + pub const fn rx256to511oct_gb(&self) -> &Rx256to511octGb { + &self.rx256to511oct_gb + } + #[doc = "0x1bc - MMC Number of good and bad frames received with length between 512 and 1023 bytes"] + #[inline(always)] + pub const fn rx512to1023oct_gb(&self) -> &Rx512to1023octGb { + &self.rx512to1023oct_gb + } + #[doc = "0x1c0 - MMC Number of good and bad frames received with length between 1024 and max size bytes"] + #[inline(always)] + pub const fn rx1024maxoct_gb(&self) -> &Rx1024maxoctGb { + &self.rx1024maxoct_gb + } + #[doc = "0x1c4 - MMC Number of received good unicast frames"] + #[inline(always)] + pub const fn rxucastframes_g(&self) -> &RxucastframesG { + &self.rxucastframes_g + } + #[doc = "0x1c8 - MMC Number of frames received with length error"] + #[inline(always)] + pub const fn rxlengtherror(&self) -> &Rxlengtherror { + &self.rxlengtherror + } + #[doc = "0x1cc - MMC Number of frames received with length field not equal to the valid frame size"] + #[inline(always)] + pub const fn rxoutrangetype(&self) -> &Rxoutrangetype { + &self.rxoutrangetype + } + #[doc = "0x1d0 - MMC Number of good and valid Pause frames received"] + #[inline(always)] + pub const fn rxpauseframes(&self) -> &Rxpauseframes { + &self.rxpauseframes + } + #[doc = "0x1d4 - MMC Number of missed received frames because of FIFO overflow"] + #[inline(always)] + pub const fn rxfifooverflow(&self) -> &Rxfifooverflow { + &self.rxfifooverflow + } + #[doc = "0x1d8 - MMC Number of good and bad VLAN frames received"] + #[inline(always)] + pub const fn rxvlanframes_gb(&self) -> &RxvlanframesGb { + &self.rxvlanframes_gb + } + #[doc = "0x1dc - MMC Number of frames received with error because of watchdog timeout error"] + #[inline(always)] + pub const fn rxwdogerror(&self) -> &Rxwdogerror { + &self.rxwdogerror + } + #[doc = "0x1e0 - MMC Number of frames received with Receive error or Frame Extension error"] + #[inline(always)] + pub const fn rxrcverror(&self) -> &Rxrcverror { + &self.rxrcverror + } + #[doc = "0x1e4 - MMC Number of received good control frames"] + #[inline(always)] + pub const fn rxctrlframes_g(&self) -> &RxctrlframesG { + &self.rxctrlframes_g + } + #[doc = "0x584 - Holds the VLAN Tag for insertion into or replacement in the transmit frames"] + #[inline(always)] + pub const fn vlan_increplace(&self) -> &VlanIncreplace { + &self.vlan_increplace + } + #[doc = "0x588 - Holds the VLAN Hash Table"] + #[inline(always)] + pub const fn vlan_hashtable(&self) -> &VlanHashtable { + &self.vlan_hashtable + } + #[doc = "0x700 - Controls the IEEE 1588 timestamp generation and update logic"] + #[inline(always)] + pub const fn timestamp_ctrl(&self) -> &TimestampCtrl { + &self.timestamp_ctrl + } + #[doc = "0x704 - Holds the 8-bit value by which the Sub-Second register is incremented"] + #[inline(always)] + pub const fn subsec_inc(&self) -> &SubsecInc { + &self.subsec_inc + } + #[doc = "0x708 - Holds the lower 32 bits of the second field of the system time"] + #[inline(always)] + pub const fn systime_seconds(&self) -> &SystimeSeconds { + &self.systime_seconds + } + #[doc = "0x70c - Holds 32 bits of the nano-second field of the system time"] + #[inline(always)] + pub const fn systime_nanosec(&self) -> &SystimeNanosec { + &self.systime_nanosec + } + #[doc = "0x710 - Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value"] + #[inline(always)] + pub const fn systime_secsupdat(&self) -> &SystimeSecsupdat { + &self.systime_secsupdat + } + #[doc = "0x714 - Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value"] + #[inline(always)] + pub const fn systime_nsecup(&self) -> &SystimeNsecup { + &self.systime_nsecup + } + #[doc = "0x718 - This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency"] + #[inline(always)] + pub const fn timestampaddend(&self) -> &Timestampaddend { + &self.timestampaddend + } + #[doc = "0x71c - Holds the high 32-bits of time to be compared with the system time"] + #[inline(always)] + pub const fn target_time_secs(&self) -> &TargetTimeSecs { + &self.target_time_secs + } + #[doc = "0x720 - Holds the lower 32-bits of time to be compared with the system time"] + #[inline(always)] + pub const fn target_time_nsec(&self) -> &TargetTimeNsec { + &self.target_time_nsec + } + #[doc = "0x1000 - Controls the DMA Host Interface Mode"] + #[inline(always)] + pub const fn dma_bus_mode(&self) -> &DmaBusMode { + &self.dma_bus_mode + } + #[doc = "0x1004 - Used by the host to instruct the DMA to poll the transmit Descriptor list"] + #[inline(always)] + pub const fn dma_tx_poll_demand(&self) -> &DmaTxPollDemand { + &self.dma_tx_poll_demand + } + #[doc = "0x1008 - Used by the host to instruct the DMA to poll the Receive Descriptor list"] + #[inline(always)] + pub const fn dma_rx_poll_demand(&self) -> &DmaRxPollDemand { + &self.dma_rx_poll_demand + } + #[doc = "0x100c - Points the DMA to the start of the Receive Descriptor list"] + #[inline(always)] + pub const fn dma_rx_desc_list_addr(&self) -> &DmaRxDescListAddr { + &self.dma_rx_desc_list_addr + } + #[doc = "0x1010 - Points the DMA to the start of the Transmit Descriptor list"] + #[inline(always)] + pub const fn dma_tx_desc_list_addr(&self) -> &DmaTxDescListAddr { + &self.dma_tx_desc_list_addr + } + #[doc = "0x1014 - Used to determine the status of the DMA"] + #[inline(always)] + pub const fn dma_status(&self) -> &DmaStatus { + &self.dma_status + } + #[doc = "0x1018 - Sets the Receive and Transmit operation mode and command"] + #[inline(always)] + pub const fn dma_oper_mode(&self) -> &DmaOperMode { + &self.dma_oper_mode + } + #[doc = "0x101c - Enables the interrupts reported in the status register"] + #[inline(always)] + pub const fn dma_intr_en(&self) -> &DmaIntrEn { + &self.dma_intr_en + } + #[doc = "0x1020 - Contains the counters for discarded frames because no Receive Descriptor is available"] + #[inline(always)] + pub const fn dma_miss_over_counter(&self) -> &DmaMissOverCounter { + &self.dma_miss_over_counter + } + #[doc = "0x1024 - Watchdog timeout for Receive Interrupt from DMA"] + #[inline(always)] + pub const fn dma_rx_intr_wdog_timer(&self) -> &DmaRxIntrWdogTimer { + &self.dma_rx_intr_wdog_timer + } + #[doc = "0x102c - Provides the active status of the read and write channels of the AHB master interface"] + #[inline(always)] + pub const fn dma_ahb_status(&self) -> &DmaAhbStatus { + &self.dma_ahb_status + } + #[doc = "0x1048 - Contains the start address of the current Transmit Descriptor read by the DMA"] + #[inline(always)] + pub const fn dma_curr_tx_desc(&self) -> &DmaCurrTxDesc { + &self.dma_curr_tx_desc + } + #[doc = "0x104c - Contains the start address of the current Receive Descriptor read by the DMA"] + #[inline(always)] + pub const fn dma_curr_rx_desc(&self) -> &DmaCurrRxDesc { + &self.dma_curr_rx_desc + } + #[doc = "0x1050 - Contains the start address of the current Receive Descriptor read by the DMA"] + #[inline(always)] + pub const fn dma_curr_tx_bufr_addr(&self) -> &DmaCurrTxBufrAddr { + &self.dma_curr_tx_bufr_addr + } + #[doc = "0x1054 - Contains the current Receive Buffer address read by the DMA"] + #[inline(always)] + pub const fn dma_curr_rx_bufr_addr(&self) -> &DmaCurrRxBufrAddr { + &self.dma_curr_rx_bufr_addr + } +} +#[doc = "MAC_CONFIG (rw) register accessor: Operation mode register for the MAC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_config`] +module"] +#[doc(alias = "MAC_CONFIG")] +pub type MacConfig = crate::Reg; +#[doc = "Operation mode register for the MAC"] +pub mod mac_config; +#[doc = "MAC_FRAME_FLTR (rw) register accessor: Contains the frame filtering controls\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_frame_fltr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_frame_fltr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_frame_fltr`] +module"] +#[doc(alias = "MAC_FRAME_FLTR")] +pub type MacFrameFltr = crate::Reg; +#[doc = "Contains the frame filtering controls"] +pub mod mac_frame_fltr; +#[doc = "MAC_GMII_ADDR (rw) register accessor: Controls the management cycles to an external PHY\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_gmii_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_gmii_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_gmii_addr`] +module"] +#[doc(alias = "MAC_GMII_ADDR")] +pub type MacGmiiAddr = crate::Reg; +#[doc = "Controls the management cycles to an external PHY"] +pub mod mac_gmii_addr; +#[doc = "MAC_GMII_DATA (rw) register accessor: Contains the data to be written to or read from the PHY register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_gmii_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_gmii_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_gmii_data`] +module"] +#[doc(alias = "MAC_GMII_DATA")] +pub type MacGmiiData = crate::Reg; +#[doc = "Contains the data to be written to or read from the PHY register"] +pub mod mac_gmii_data; +#[doc = "MAC_FLOW_CTRL (rw) register accessor: Controls the generation of control frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_flow_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_flow_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_flow_ctrl`] +module"] +#[doc(alias = "MAC_FLOW_CTRL")] +pub type MacFlowCtrl = crate::Reg; +#[doc = "Controls the generation of control frames"] +pub mod mac_flow_ctrl; +#[doc = "MAC_VLAN_TAG (rw) register accessor: Identifies IEEE 802.1Q VLAN type frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_vlan_tag::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_vlan_tag::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_vlan_tag`] +module"] +#[doc(alias = "MAC_VLAN_TAG")] +pub type MacVlanTag = crate::Reg; +#[doc = "Identifies IEEE 802.1Q VLAN type frames"] +pub mod mac_vlan_tag; +#[doc = "MAC_DEBUG (r) register accessor: Gives the status of the various internal blocks for debugging\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_debug::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_debug`] +module"] +#[doc(alias = "MAC_DEBUG")] +pub type MacDebug = crate::Reg; +#[doc = "Gives the status of the various internal blocks for debugging"] +pub mod mac_debug; +#[doc = "MAC_INTR_STAT (r) register accessor: Contains the interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_intr_stat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_intr_stat`] +module"] +#[doc(alias = "MAC_INTR_STAT")] +pub type MacIntrStat = crate::Reg; +#[doc = "Contains the interrupt status"] +pub mod mac_intr_stat; +#[doc = "MAC_INTR_MASK (rw) register accessor: Contains the masks for generating interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_intr_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_intr_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_intr_mask`] +module"] +#[doc(alias = "MAC_INTR_MASK")] +pub type MacIntrMask = crate::Reg; +#[doc = "Contains the masks for generating interrupt"] +pub mod mac_intr_mask; +#[doc = "MAC_ADDR_H (rw) register accessor: Contains the high 16-bits of the first MAC Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_addr_h::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_addr_h::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_addr_h`] +module"] +#[doc(alias = "MAC_ADDR_H")] +pub type MacAddrH = crate::Reg; +#[doc = "Contains the high 16-bits of the first MAC Address"] +pub mod mac_addr_h; +#[doc = "MAC_ADDR_L (rw) register accessor: Contains the Low 32-bits of the first MAC Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_addr_l::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_addr_l::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_addr_l`] +module"] +#[doc(alias = "MAC_ADDR_L")] +pub type MacAddrL = crate::Reg; +#[doc = "Contains the Low 32-bits of the first MAC Address"] +pub mod mac_addr_l; +#[doc = "MAC_WDOG_TO (rw) register accessor: Controls the watchdog time-out for received frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_wdog_to::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_wdog_to::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_wdog_to`] +module"] +#[doc(alias = "MAC_WDOG_TO")] +pub type MacWdogTo = crate::Reg; +#[doc = "Controls the watchdog time-out for received frames"] +pub mod mac_wdog_to; +#[doc = "MMC_CNTRL (rw) register accessor: MMC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmc_cntrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmc_cntrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmc_cntrl`] +module"] +#[doc(alias = "MMC_CNTRL")] +pub type MmcCntrl = crate::Reg; +#[doc = "MMC Control Register"] +pub mod mmc_cntrl; +#[doc = "MMC_INTR_RX (rw) register accessor: MMC Receive Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmc_intr_rx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmc_intr_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmc_intr_rx`] +module"] +#[doc(alias = "MMC_INTR_RX")] +pub type MmcIntrRx = crate::Reg; +#[doc = "MMC Receive Interrupt Register"] +pub mod mmc_intr_rx; +#[doc = "MMC_INTR_TX (rw) register accessor: MMC Transmit Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmc_intr_tx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmc_intr_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmc_intr_tx`] +module"] +#[doc(alias = "MMC_INTR_TX")] +pub type MmcIntrTx = crate::Reg; +#[doc = "MMC Transmit Interrupt Register"] +pub mod mmc_intr_tx; +#[doc = "MMC_INTR_MASK_RX (rw) register accessor: MMC Receive Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmc_intr_mask_rx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmc_intr_mask_rx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmc_intr_mask_rx`] +module"] +#[doc(alias = "MMC_INTR_MASK_RX")] +pub type MmcIntrMaskRx = crate::Reg; +#[doc = "MMC Receive Interrupt Mask Register"] +pub mod mmc_intr_mask_rx; +#[doc = "MMC_INTR_MASK_TX (rw) register accessor: MMC Transmit Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmc_intr_mask_tx::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmc_intr_mask_tx::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mmc_intr_mask_tx`] +module"] +#[doc(alias = "MMC_INTR_MASK_TX")] +pub type MmcIntrMaskTx = crate::Reg; +#[doc = "MMC Transmit Interrupt Mask Register"] +pub mod mmc_intr_mask_tx; +#[doc = "TXOCTETCOUNT_GB (r) register accessor: MMC Transmit Count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txoctetcount_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txoctetcount_gb`] +module"] +#[doc(alias = "TXOCTETCOUNT_GB")] +pub type TxoctetcountGb = crate::Reg; +#[doc = "MMC Transmit Count"] +pub mod txoctetcount_gb; +#[doc = "TXFRAMECOUNT_GB (r) register accessor: MMC Frame Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txframecount_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txframecount_gb`] +module"] +#[doc(alias = "TXFRAMECOUNT_GB")] +pub type TxframecountGb = crate::Reg; +#[doc = "MMC Frame Count Register"] +pub mod txframecount_gb; +#[doc = "TXBCASTFRAMES_G (r) register accessor: MMC Good Broadcast Frames Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcastframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbcastframes_g`] +module"] +#[doc(alias = "TXBCASTFRAMES_G")] +pub type TxbcastframesG = crate::Reg; +#[doc = "MMC Good Broadcast Frames Register"] +pub mod txbcastframes_g; +#[doc = "TXMCASTFRAMES_G (r) register accessor: MMC Good Multicast Frames Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txmcastframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txmcastframes_g`] +module"] +#[doc(alias = "TXMCASTFRAMES_G")] +pub type TxmcastframesG = crate::Reg; +#[doc = "MMC Good Multicast Frames Register"] +pub mod txmcastframes_g; +#[doc = "TX64OCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx64oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx64oct_gb`] +module"] +#[doc(alias = "TX64OCT_GB")] +pub type Tx64octGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 64"] +pub mod tx64oct_gb; +#[doc = "TX65TO127OCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 65 to 127\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx65to127oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx65to127oct_gb`] +module"] +#[doc(alias = "TX65TO127OCT_GB")] +pub type Tx65to127octGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 65 to 127"] +pub mod tx65to127oct_gb; +#[doc = "TX128TO255OCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 128 to 255\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx128to255oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx128to255oct_gb`] +module"] +#[doc(alias = "TX128TO255OCT_GB")] +pub type Tx128to255octGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 128 to 255"] +pub mod tx128to255oct_gb; +#[doc = "TX256TO511OCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 256 to 511\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx256to511oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx256to511oct_gb`] +module"] +#[doc(alias = "TX256TO511OCT_GB")] +pub type Tx256to511octGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 256 to 511"] +pub mod tx256to511oct_gb; +#[doc = "TX512TO1023OCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 512 to 1023\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx512to1023oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx512to1023oct_gb`] +module"] +#[doc(alias = "TX512TO1023OCT_GB")] +pub type Tx512to1023octGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 512 to 1023"] +pub mod tx512to1023oct_gb; +#[doc = "TX1024MAXOCT_GB (r) register accessor: MMC Good and bad Frames transmitted with length 1024 to max bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx1024maxoct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tx1024maxoct_gb`] +module"] +#[doc(alias = "TX1024MAXOCT_GB")] +pub type Tx1024maxoctGb = crate::Reg; +#[doc = "MMC Good and bad Frames transmitted with length 1024 to max bytes"] +pub mod tx1024maxoct_gb; +#[doc = "TXUCASTFRAME_GB (r) register accessor: MMC number of good and bad unicast frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txucastframe_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txucastframe_gb`] +module"] +#[doc(alias = "TXUCASTFRAME_GB")] +pub type TxucastframeGb = crate::Reg; +#[doc = "MMC number of good and bad unicast frames transmitted"] +pub mod txucastframe_gb; +#[doc = "TXMCASTFRAME_GB (r) register accessor: MMC number of good and bad MULTIcast frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txmcastframe_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txmcastframe_gb`] +module"] +#[doc(alias = "TXMCASTFRAME_GB")] +pub type TxmcastframeGb = crate::Reg; +#[doc = "MMC number of good and bad MULTIcast frames transmitted"] +pub mod txmcastframe_gb; +#[doc = "TXBCASTFRAME_GB (r) register accessor: MMC number of good and bad broadcast frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcastframe_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbcastframe_gb`] +module"] +#[doc(alias = "TXBCASTFRAME_GB")] +pub type TxbcastframeGb = crate::Reg; +#[doc = "MMC number of good and bad broadcast frames transmitted"] +pub mod txbcastframe_gb; +#[doc = "TXUNDERERR (r) register accessor: MMC number of frames aborted because of frame underflow error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txundererr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txundererr`] +module"] +#[doc(alias = "TXUNDERERR")] +pub type Txundererr = crate::Reg; +#[doc = "MMC number of frames aborted because of frame underflow error"] +pub mod txundererr; +#[doc = "TXSINGLECOL_G (r) register accessor: MMC Number of successfully transmitted frames after a single collision\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txsinglecol_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txsinglecol_g`] +module"] +#[doc(alias = "TXSINGLECOL_G")] +pub type TxsinglecolG = crate::Reg; +#[doc = "MMC Number of successfully transmitted frames after a single collision"] +pub mod txsinglecol_g; +#[doc = "TXMULTICOL_G (r) register accessor: MMC Number of successfully transmitted frames after multiple collisions\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txmulticol_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txmulticol_g`] +module"] +#[doc(alias = "TXMULTICOL_G")] +pub type TxmulticolG = crate::Reg; +#[doc = "MMC Number of successfully transmitted frames after multiple collisions"] +pub mod txmulticol_g; +#[doc = "TXDEFERRED (r) register accessor: MMC Number of successfully transmitted frames after a deferral\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txdeferred::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txdeferred`] +module"] +#[doc(alias = "TXDEFERRED")] +pub type Txdeferred = crate::Reg; +#[doc = "MMC Number of successfully transmitted frames after a deferral"] +pub mod txdeferred; +#[doc = "TXLATECOL (r) register accessor: MMC Number of aborted frames because of late collision error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txlatecol::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txlatecol`] +module"] +#[doc(alias = "TXLATECOL")] +pub type Txlatecol = crate::Reg; +#[doc = "MMC Number of aborted frames because of late collision error"] +pub mod txlatecol; +#[doc = "TXEXESSCOL (r) register accessor: MMC Number of aborted frames because of excessive collision errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txexesscol::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txexesscol`] +module"] +#[doc(alias = "TXEXESSCOL")] +pub type Txexesscol = crate::Reg; +#[doc = "MMC Number of aborted frames because of excessive collision errors"] +pub mod txexesscol; +#[doc = "TXCARRIERERROR (r) register accessor: MMC Number of aborted frames because of carrier sense error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcarriererror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcarriererror`] +module"] +#[doc(alias = "TXCARRIERERROR")] +pub type Txcarriererror = crate::Reg; +#[doc = "MMC Number of aborted frames because of carrier sense error"] +pub mod txcarriererror; +#[doc = "TXOCTETCOUNT_G (r) register accessor: MMC Number of bytes transmitted frames only in good frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txoctetcount_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txoctetcount_g`] +module"] +#[doc(alias = "TXOCTETCOUNT_G")] +pub type TxoctetcountG = crate::Reg; +#[doc = "MMC Number of bytes transmitted frames only in good frames"] +pub mod txoctetcount_g; +#[doc = "TXFRAMECOUNT_G (r) register accessor: MMC Number of good frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txframecount_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txframecount_g`] +module"] +#[doc(alias = "TXFRAMECOUNT_G")] +pub type TxframecountG = crate::Reg; +#[doc = "MMC Number of good frames transmitted"] +pub mod txframecount_g; +#[doc = "TXEXCESSDEF (r) register accessor: MMC Number of frames aborted because of excessive deferral error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txexcessdef::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txexcessdef`] +module"] +#[doc(alias = "TXEXCESSDEF")] +pub type Txexcessdef = crate::Reg; +#[doc = "MMC Number of frames aborted because of excessive deferral error"] +pub mod txexcessdef; +#[doc = "TXPAUSEFRAMES (r) register accessor: MMC Number of good pause frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txpauseframes::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txpauseframes`] +module"] +#[doc(alias = "TXPAUSEFRAMES")] +pub type Txpauseframes = crate::Reg; +#[doc = "MMC Number of good pause frames transmitted"] +pub mod txpauseframes; +#[doc = "TXLANFRAMES_G (r) register accessor: MMC Number of good VLAN frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txlanframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txlanframes_g`] +module"] +#[doc(alias = "TXLANFRAMES_G")] +pub type TxlanframesG = crate::Reg; +#[doc = "MMC Number of good VLAN frames transmitted"] +pub mod txlanframes_g; +#[doc = "TXOVERSIZE_G (r) register accessor: MMC Number of frames transmitted without errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txoversize_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txoversize_g`] +module"] +#[doc(alias = "TXOVERSIZE_G")] +pub type TxoversizeG = crate::Reg; +#[doc = "MMC Number of frames transmitted without errors"] +pub mod txoversize_g; +#[doc = "RXFRAMECOUNT_GB (r) register accessor: MMC Number of good and bad frames received\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxframecount_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxframecount_gb`] +module"] +#[doc(alias = "RXFRAMECOUNT_GB")] +pub type RxframecountGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received"] +pub mod rxframecount_gb; +#[doc = "RXOCTETCOUNT_GB (r) register accessor: MMC Number of bytes received in good and bad frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxoctetcount_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxoctetcount_gb`] +module"] +#[doc(alias = "RXOCTETCOUNT_GB")] +pub type RxoctetcountGb = crate::Reg; +#[doc = "MMC Number of bytes received in good and bad frames"] +pub mod rxoctetcount_gb; +#[doc = "RXOCTETCOUNT_G (r) register accessor: MMC Number of bytes received in good frames only\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxoctetcount_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxoctetcount_g`] +module"] +#[doc(alias = "RXOCTETCOUNT_G")] +pub type RxoctetcountG = crate::Reg; +#[doc = "MMC Number of bytes received in good frames only"] +pub mod rxoctetcount_g; +#[doc = "RXBCASTFRAMES_G (r) register accessor: MMC Number of good broadcast frames received\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxbcastframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxbcastframes_g`] +module"] +#[doc(alias = "RXBCASTFRAMES_G")] +pub type RxbcastframesG = crate::Reg; +#[doc = "MMC Number of good broadcast frames received"] +pub mod rxbcastframes_g; +#[doc = "RXMCASTFRAMES_G (r) register accessor: MMC Number of good multicast frames received\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxmcastframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxmcastframes_g`] +module"] +#[doc(alias = "RXMCASTFRAMES_G")] +pub type RxmcastframesG = crate::Reg; +#[doc = "MMC Number of good multicast frames received"] +pub mod rxmcastframes_g; +#[doc = "RXCRCERROR (r) register accessor: MMC Number of frames received with CRC error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcrcerror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcrcerror`] +module"] +#[doc(alias = "RXCRCERROR")] +pub type Rxcrcerror = crate::Reg; +#[doc = "MMC Number of frames received with CRC error"] +pub mod rxcrcerror; +#[doc = "RXALIGNERROR (r) register accessor: MMC Number of frames received with alignment error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxalignerror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxalignerror`] +module"] +#[doc(alias = "RXALIGNERROR")] +pub type Rxalignerror = crate::Reg; +#[doc = "MMC Number of frames received with alignment error"] +pub mod rxalignerror; +#[doc = "RXRUNTERROR (r) register accessor: MMC Number of frames received with runt error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxrunterror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxrunterror`] +module"] +#[doc(alias = "RXRUNTERROR")] +pub type Rxrunterror = crate::Reg; +#[doc = "MMC Number of frames received with runt error"] +pub mod rxrunterror; +#[doc = "RXJABBERERROR (r) register accessor: MMC Number of giant frames received with length greater than 1518 bytes and with CRC error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxjabbererror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxjabbererror`] +module"] +#[doc(alias = "RXJABBERERROR")] +pub type Rxjabbererror = crate::Reg; +#[doc = "MMC Number of giant frames received with length greater than 1518 bytes and with CRC error"] +pub mod rxjabbererror; +#[doc = "RXUNDERSIZE_G (r) register accessor: MMC Number of frames received with length less than 64 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxundersize_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxundersize_g`] +module"] +#[doc(alias = "RXUNDERSIZE_G")] +pub type RxundersizeG = crate::Reg; +#[doc = "MMC Number of frames received with length less than 64 bytes"] +pub mod rxundersize_g; +#[doc = "RXOVERSIZE_G (r) register accessor: MMC Number of frames received without errors with length greater than the max size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxoversize_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxoversize_g`] +module"] +#[doc(alias = "RXOVERSIZE_G")] +pub type RxoversizeG = crate::Reg; +#[doc = "MMC Number of frames received without errors with length greater than the max size"] +pub mod rxoversize_g; +#[doc = "RX64OCTETS_GB (r) register accessor: MMC Number of good and bad frames received with length 64 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx64octets_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx64octets_gb`] +module"] +#[doc(alias = "RX64OCTETS_GB")] +pub type Rx64octetsGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length 64 bytes"] +pub mod rx64octets_gb; +#[doc = "RX65TO127OCT_GB (r) register accessor: MMC Number of good and bad frames received with length between 65 and 127 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx65to127oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx65to127oct_gb`] +module"] +#[doc(alias = "RX65TO127OCT_GB")] +pub type Rx65to127octGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 65 and 127 bytes"] +pub mod rx65to127oct_gb; +#[doc = "RX128TO255OCT_GB (r) register accessor: MMC Number of good and bad frames received with length between 128 and 255 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx128to255oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx128to255oct_gb`] +module"] +#[doc(alias = "RX128TO255OCT_GB")] +pub type Rx128to255octGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 128 and 255 bytes"] +pub mod rx128to255oct_gb; +#[doc = "RX256TO511OCT_GB (r) register accessor: MMC Number of good and bad frames received with length between 256 and 511 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx256to511oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx256to511oct_gb`] +module"] +#[doc(alias = "RX256TO511OCT_GB")] +pub type Rx256to511octGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 256 and 511 bytes"] +pub mod rx256to511oct_gb; +#[doc = "RX512TO1023OCT_GB (r) register accessor: MMC Number of good and bad frames received with length between 512 and 1023 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx512to1023oct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx512to1023oct_gb`] +module"] +#[doc(alias = "RX512TO1023OCT_GB")] +pub type Rx512to1023octGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 512 and 1023 bytes"] +pub mod rx512to1023oct_gb; +#[doc = "RX1024MAXOCT_GB (r) register accessor: MMC Number of good and bad frames received with length between 1024 and max size bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx1024maxoct_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx1024maxoct_gb`] +module"] +#[doc(alias = "RX1024MAXOCT_GB")] +pub type Rx1024maxoctGb = crate::Reg; +#[doc = "MMC Number of good and bad frames received with length between 1024 and max size bytes"] +pub mod rx1024maxoct_gb; +#[doc = "RXUCASTFRAMES_G (r) register accessor: MMC Number of received good unicast frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxucastframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxucastframes_g`] +module"] +#[doc(alias = "RXUCASTFRAMES_G")] +pub type RxucastframesG = crate::Reg; +#[doc = "MMC Number of received good unicast frames"] +pub mod rxucastframes_g; +#[doc = "RXLENGTHERROR (r) register accessor: MMC Number of frames received with length error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxlengtherror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxlengtherror`] +module"] +#[doc(alias = "RXLENGTHERROR")] +pub type Rxlengtherror = crate::Reg; +#[doc = "MMC Number of frames received with length error"] +pub mod rxlengtherror; +#[doc = "RXOUTRANGETYPE (r) register accessor: MMC Number of frames received with length field not equal to the valid frame size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxoutrangetype::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxoutrangetype`] +module"] +#[doc(alias = "RXOUTRANGETYPE")] +pub type Rxoutrangetype = crate::Reg; +#[doc = "MMC Number of frames received with length field not equal to the valid frame size"] +pub mod rxoutrangetype; +#[doc = "RXPAUSEFRAMES (r) register accessor: MMC Number of good and valid Pause frames received\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxpauseframes::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxpauseframes`] +module"] +#[doc(alias = "RXPAUSEFRAMES")] +pub type Rxpauseframes = crate::Reg; +#[doc = "MMC Number of good and valid Pause frames received"] +pub mod rxpauseframes; +#[doc = "RXFIFOOVERFLOW (r) register accessor: MMC Number of missed received frames because of FIFO overflow\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifooverflow::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifooverflow`] +module"] +#[doc(alias = "RXFIFOOVERFLOW")] +pub type Rxfifooverflow = crate::Reg; +#[doc = "MMC Number of missed received frames because of FIFO overflow"] +pub mod rxfifooverflow; +#[doc = "RXVLANFRAMES_GB (r) register accessor: MMC Number of good and bad VLAN frames received\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxvlanframes_gb::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxvlanframes_gb`] +module"] +#[doc(alias = "RXVLANFRAMES_GB")] +pub type RxvlanframesGb = crate::Reg; +#[doc = "MMC Number of good and bad VLAN frames received"] +pub mod rxvlanframes_gb; +#[doc = "RXWDOGERROR (r) register accessor: MMC Number of frames received with error because of watchdog timeout error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxwdogerror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxwdogerror`] +module"] +#[doc(alias = "RXWDOGERROR")] +pub type Rxwdogerror = crate::Reg; +#[doc = "MMC Number of frames received with error because of watchdog timeout error"] +pub mod rxwdogerror; +#[doc = "RXRCVERROR (r) register accessor: MMC Number of frames received with Receive error or Frame Extension error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxrcverror::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxrcverror`] +module"] +#[doc(alias = "RXRCVERROR")] +pub type Rxrcverror = crate::Reg; +#[doc = "MMC Number of frames received with Receive error or Frame Extension error"] +pub mod rxrcverror; +#[doc = "RXCTRLFRAMES_G (r) register accessor: MMC Number of received good control frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxctrlframes_g::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxctrlframes_g`] +module"] +#[doc(alias = "RXCTRLFRAMES_G")] +pub type RxctrlframesG = crate::Reg; +#[doc = "MMC Number of received good control frames"] +pub mod rxctrlframes_g; +#[doc = "VLAN_INCREPLACE (rw) register accessor: Holds the VLAN Tag for insertion into or replacement in the transmit frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vlan_increplace::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vlan_increplace::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vlan_increplace`] +module"] +#[doc(alias = "VLAN_INCREPLACE")] +pub type VlanIncreplace = crate::Reg; +#[doc = "Holds the VLAN Tag for insertion into or replacement in the transmit frames"] +pub mod vlan_increplace; +#[doc = "VLAN_HASHTABLE (rw) register accessor: Holds the VLAN Hash Table\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vlan_hashtable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vlan_hashtable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@vlan_hashtable`] +module"] +#[doc(alias = "VLAN_HASHTABLE")] +pub type VlanHashtable = crate::Reg; +#[doc = "Holds the VLAN Hash Table"] +pub mod vlan_hashtable; +#[doc = "TIMESTAMP_CTRL (rw) register accessor: Controls the IEEE 1588 timestamp generation and update logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timestamp_ctrl`] +module"] +#[doc(alias = "TIMESTAMP_CTRL")] +pub type TimestampCtrl = crate::Reg; +#[doc = "Controls the IEEE 1588 timestamp generation and update logic"] +pub mod timestamp_ctrl; +#[doc = "SUBSEC_INC (rw) register accessor: Holds the 8-bit value by which the Sub-Second register is incremented\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`subsec_inc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`subsec_inc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@subsec_inc`] +module"] +#[doc(alias = "SUBSEC_INC")] +pub type SubsecInc = crate::Reg; +#[doc = "Holds the 8-bit value by which the Sub-Second register is incremented"] +pub mod subsec_inc; +#[doc = "SYSTIME_SECONDS (r) register accessor: Holds the lower 32 bits of the second field of the system time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systime_seconds::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systime_seconds`] +module"] +#[doc(alias = "SYSTIME_SECONDS")] +pub type SystimeSeconds = crate::Reg; +#[doc = "Holds the lower 32 bits of the second field of the system time"] +pub mod systime_seconds; +#[doc = "SYSTIME_NANOSEC (r) register accessor: Holds 32 bits of the nano-second field of the system time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systime_nanosec::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systime_nanosec`] +module"] +#[doc(alias = "SYSTIME_NANOSEC")] +pub type SystimeNanosec = crate::Reg; +#[doc = "Holds 32 bits of the nano-second field of the system time"] +pub mod systime_nanosec; +#[doc = "SYSTIME_SECSUPDAT (rw) register accessor: Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systime_secsupdat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systime_secsupdat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systime_secsupdat`] +module"] +#[doc(alias = "SYSTIME_SECSUPDAT")] +pub type SystimeSecsupdat = crate::Reg; +#[doc = "Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value"] +pub mod systime_secsupdat; +#[doc = "SYSTIME_NSECUP (rw) register accessor: Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systime_nsecup::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systime_nsecup::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systime_nsecup`] +module"] +#[doc(alias = "SYSTIME_NSECUP")] +pub type SystimeNsecup = crate::Reg; +#[doc = "Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value"] +pub mod systime_nsecup; +#[doc = "TIMESTAMPADDEND (rw) register accessor: This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestampaddend::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestampaddend::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timestampaddend`] +module"] +#[doc(alias = "TIMESTAMPADDEND")] +pub type Timestampaddend = crate::Reg; +#[doc = "This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency"] +pub mod timestampaddend; +#[doc = "TARGET_TIME_SECS (rw) register accessor: Holds the high 32-bits of time to be compared with the system time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target_time_secs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target_time_secs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target_time_secs`] +module"] +#[doc(alias = "TARGET_TIME_SECS")] +pub type TargetTimeSecs = crate::Reg; +#[doc = "Holds the high 32-bits of time to be compared with the system time"] +pub mod target_time_secs; +#[doc = "TARGET_TIME_NSEC (rw) register accessor: Holds the lower 32-bits of time to be compared with the system time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target_time_nsec::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target_time_nsec::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@target_time_nsec`] +module"] +#[doc(alias = "TARGET_TIME_NSEC")] +pub type TargetTimeNsec = crate::Reg; +#[doc = "Holds the lower 32-bits of time to be compared with the system time"] +pub mod target_time_nsec; +#[doc = "DMA_BUS_MODE (rw) register accessor: Controls the DMA Host Interface Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_bus_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_bus_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_bus_mode`] +module"] +#[doc(alias = "DMA_BUS_MODE")] +pub type DmaBusMode = crate::Reg; +#[doc = "Controls the DMA Host Interface Mode"] +pub mod dma_bus_mode; +#[doc = "DMA_TX_POLL_DEMAND (rw) register accessor: Used by the host to instruct the DMA to poll the transmit Descriptor list\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_tx_poll_demand::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_tx_poll_demand::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_tx_poll_demand`] +module"] +#[doc(alias = "DMA_TX_POLL_DEMAND")] +pub type DmaTxPollDemand = crate::Reg; +#[doc = "Used by the host to instruct the DMA to poll the transmit Descriptor list"] +pub mod dma_tx_poll_demand; +#[doc = "DMA_RX_POLL_DEMAND (rw) register accessor: Used by the host to instruct the DMA to poll the Receive Descriptor list\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_rx_poll_demand::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_rx_poll_demand::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_rx_poll_demand`] +module"] +#[doc(alias = "DMA_RX_POLL_DEMAND")] +pub type DmaRxPollDemand = crate::Reg; +#[doc = "Used by the host to instruct the DMA to poll the Receive Descriptor list"] +pub mod dma_rx_poll_demand; +#[doc = "DMA_RX_DESC_LIST_ADDR (rw) register accessor: Points the DMA to the start of the Receive Descriptor list\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_rx_desc_list_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_rx_desc_list_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_rx_desc_list_addr`] +module"] +#[doc(alias = "DMA_RX_DESC_LIST_ADDR")] +pub type DmaRxDescListAddr = crate::Reg; +#[doc = "Points the DMA to the start of the Receive Descriptor list"] +pub mod dma_rx_desc_list_addr; +#[doc = "DMA_TX_DESC_LIST_ADDR (rw) register accessor: Points the DMA to the start of the Transmit Descriptor list\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_tx_desc_list_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_tx_desc_list_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_tx_desc_list_addr`] +module"] +#[doc(alias = "DMA_TX_DESC_LIST_ADDR")] +pub type DmaTxDescListAddr = crate::Reg; +#[doc = "Points the DMA to the start of the Transmit Descriptor list"] +pub mod dma_tx_desc_list_addr; +#[doc = "DMA_STATUS (r) register accessor: Used to determine the status of the DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_status`] +module"] +#[doc(alias = "DMA_STATUS")] +pub type DmaStatus = crate::Reg; +#[doc = "Used to determine the status of the DMA"] +pub mod dma_status; +#[doc = "DMA_OPER_MODE (rw) register accessor: Sets the Receive and Transmit operation mode and command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_oper_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_oper_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_oper_mode`] +module"] +#[doc(alias = "DMA_OPER_MODE")] +pub type DmaOperMode = crate::Reg; +#[doc = "Sets the Receive and Transmit operation mode and command"] +pub mod dma_oper_mode; +#[doc = "DMA_INTR_EN (rw) register accessor: Enables the interrupts reported in the status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_intr_en::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_intr_en::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_intr_en`] +module"] +#[doc(alias = "DMA_INTR_EN")] +pub type DmaIntrEn = crate::Reg; +#[doc = "Enables the interrupts reported in the status register"] +pub mod dma_intr_en; +#[doc = "DMA_MISS_OVER_COUNTER (rw) register accessor: Contains the counters for discarded frames because no Receive Descriptor is available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_miss_over_counter::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_miss_over_counter::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_miss_over_counter`] +module"] +#[doc(alias = "DMA_MISS_OVER_COUNTER")] +pub type DmaMissOverCounter = crate::Reg; +#[doc = "Contains the counters for discarded frames because no Receive Descriptor is available"] +pub mod dma_miss_over_counter; +#[doc = "DMA_RX_INTR_WDOG_TIMER (rw) register accessor: Watchdog timeout for Receive Interrupt from DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_rx_intr_wdog_timer::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_rx_intr_wdog_timer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_rx_intr_wdog_timer`] +module"] +#[doc(alias = "DMA_RX_INTR_WDOG_TIMER")] +pub type DmaRxIntrWdogTimer = crate::Reg; +#[doc = "Watchdog timeout for Receive Interrupt from DMA"] +pub mod dma_rx_intr_wdog_timer; +#[doc = "DMA_AHB_STATUS (rw) register accessor: Provides the active status of the read and write channels of the AHB master interface\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_ahb_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_ahb_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_ahb_status`] +module"] +#[doc(alias = "DMA_AHB_STATUS")] +pub type DmaAhbStatus = crate::Reg; +#[doc = "Provides the active status of the read and write channels of the AHB master interface"] +pub mod dma_ahb_status; +#[doc = "DMA_CURR_TX_DESC (rw) register accessor: Contains the start address of the current Transmit Descriptor read by the DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_curr_tx_desc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_curr_tx_desc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_curr_tx_desc`] +module"] +#[doc(alias = "DMA_CURR_TX_DESC")] +pub type DmaCurrTxDesc = crate::Reg; +#[doc = "Contains the start address of the current Transmit Descriptor read by the DMA"] +pub mod dma_curr_tx_desc; +#[doc = "DMA_CURR_RX_DESC (rw) register accessor: Contains the start address of the current Receive Descriptor read by the DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_curr_rx_desc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_curr_rx_desc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_curr_rx_desc`] +module"] +#[doc(alias = "DMA_CURR_RX_DESC")] +pub type DmaCurrRxDesc = crate::Reg; +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA"] +pub mod dma_curr_rx_desc; +#[doc = "DMA_CURR_TX_BUFR_ADDR (rw) register accessor: Contains the start address of the current Receive Descriptor read by the DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_curr_tx_bufr_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_curr_tx_bufr_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_curr_tx_bufr_addr`] +module"] +#[doc(alias = "DMA_CURR_TX_BUFR_ADDR")] +pub type DmaCurrTxBufrAddr = crate::Reg; +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA"] +pub mod dma_curr_tx_bufr_addr; +#[doc = "DMA_CURR_RX_BUFR_ADDR (rw) register accessor: Contains the current Receive Buffer address read by the DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_curr_rx_bufr_addr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_curr_rx_bufr_addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_curr_rx_bufr_addr`] +module"] +#[doc(alias = "DMA_CURR_RX_BUFR_ADDR")] +pub type DmaCurrRxBufrAddr = crate::Reg; +#[doc = "Contains the current Receive Buffer address read by the DMA"] +pub mod dma_curr_rx_bufr_addr; diff --git a/va416xx/src/eth/dma_ahb_status.rs b/va416xx/src/eth/dma_ahb_status.rs new file mode 100644 index 0000000..bb66213 --- /dev/null +++ b/va416xx/src/eth/dma_ahb_status.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMA_AHB_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_AHB_STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `AHBMASTRSTS` reader - When high, indicates that the AHB master interface FSMs are in the non-idle state"] +pub type AhbmastrstsR = crate::BitReader; +#[doc = "Field `AHBMASTRSTS` writer - When high, indicates that the AHB master interface FSMs are in the non-idle state"] +pub type AhbmastrstsW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - When high, indicates that the AHB master interface FSMs are in the non-idle state"] + #[inline(always)] + pub fn ahbmastrsts(&self) -> AhbmastrstsR { + AhbmastrstsR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - When high, indicates that the AHB master interface FSMs are in the non-idle state"] + #[inline(always)] + #[must_use] + pub fn ahbmastrsts(&mut self) -> AhbmastrstsW { + AhbmastrstsW::new(self, 0) + } +} +#[doc = "Provides the active status of the read and write channels of the AHB master interface\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_ahb_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_ahb_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaAhbStatusSpec; +impl crate::RegisterSpec for DmaAhbStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_ahb_status::R`](R) reader structure"] +impl crate::Readable for DmaAhbStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_ahb_status::W`](W) writer structure"] +impl crate::Writable for DmaAhbStatusSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_AHB_STATUS to value 0"] +impl crate::Resettable for DmaAhbStatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_bus_mode.rs b/va416xx/src/eth/dma_bus_mode.rs new file mode 100644 index 0000000..73f8249 --- /dev/null +++ b/va416xx/src/eth/dma_bus_mode.rs @@ -0,0 +1,235 @@ +#[doc = "Register `DMA_BUS_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_BUS_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SWR` reader - Software Reset (Read, Write Set, and Self Clear)"] +pub type SwrR = crate::BitReader; +#[doc = "Field `SWR` writer - Software Reset (Read, Write Set, and Self Clear)"] +pub type SwrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DA` reader - DMA Arbitration Scheme"] +pub type DaR = crate::BitReader; +#[doc = "Field `DA` writer - DMA Arbitration Scheme"] +pub type DaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DSL` reader - Descriptor Skip Length"] +pub type DslR = crate::FieldReader; +#[doc = "Field `DSL` writer - Descriptor Skip Length"] +pub type DslW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PBL` reader - Programmable Burst Lengthe"] +pub type PblR = crate::FieldReader; +#[doc = "Field `PBL` writer - Programmable Burst Lengthe"] +pub type PblW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `PR` reader - Priority Ratio"] +pub type PrR = crate::FieldReader; +#[doc = "Field `PR` writer - Priority Ratio"] +pub type PrW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `FB` reader - Fixed Burste"] +pub type FbR = crate::BitReader; +#[doc = "Field `FB` writer - Fixed Burste"] +pub type FbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RPBL` reader - Rx DMA PBL"] +pub type RpblR = crate::FieldReader; +#[doc = "Field `RPBL` writer - Rx DMA PBL"] +pub type RpblW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `USP` reader - Use Separate PBL"] +pub type UspR = crate::BitReader; +#[doc = "Field `USP` writer - Use Separate PBL"] +pub type UspW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PBLx8` reader - PBLx8 Mode"] +pub type Pblx8R = crate::BitReader; +#[doc = "Field `PBLx8` writer - PBLx8 Mode"] +pub type Pblx8W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AAL` reader - Address-Aligned Beats"] +pub type AalR = crate::BitReader; +#[doc = "Field `AAL` writer - Address-Aligned Beats"] +pub type AalW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MB` reader - Mixed Burst"] +pub type MbR = crate::BitReader; +#[doc = "Field `MB` writer - Mixed Burst"] +pub type MbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXPR` reader - Transmit Priority"] +pub type TxprR = crate::BitReader; +#[doc = "Field `TXPR` writer - Transmit Priority"] +pub type TxprW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PRWG` reader - Channel Priority Weights"] +pub type PrwgR = crate::FieldReader; +#[doc = "Field `PRWG` writer - Channel Priority Weights"] +pub type PrwgW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RIB` reader - Rebuild INCRx Burst"] +pub type RibR = crate::BitReader; +#[doc = "Field `RIB` writer - Rebuild INCRx Burst"] +pub type RibW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Software Reset (Read, Write Set, and Self Clear)"] + #[inline(always)] + pub fn swr(&self) -> SwrR { + SwrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Arbitration Scheme"] + #[inline(always)] + pub fn da(&self) -> DaR { + DaR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:6 - Descriptor Skip Length"] + #[inline(always)] + pub fn dsl(&self) -> DslR { + DslR::new(((self.bits >> 2) & 0x1f) as u8) + } + #[doc = "Bits 8:13 - Programmable Burst Lengthe"] + #[inline(always)] + pub fn pbl(&self) -> PblR { + PblR::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 14:15 - Priority Ratio"] + #[inline(always)] + pub fn pr(&self) -> PrR { + PrR::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 16 - Fixed Burste"] + #[inline(always)] + pub fn fb(&self) -> FbR { + FbR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:22 - Rx DMA PBL"] + #[inline(always)] + pub fn rpbl(&self) -> RpblR { + RpblR::new(((self.bits >> 17) & 0x3f) as u8) + } + #[doc = "Bit 23 - Use Separate PBL"] + #[inline(always)] + pub fn usp(&self) -> UspR { + UspR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - PBLx8 Mode"] + #[inline(always)] + pub fn pblx8(&self) -> Pblx8R { + Pblx8R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Address-Aligned Beats"] + #[inline(always)] + pub fn aal(&self) -> AalR { + AalR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Mixed Burst"] + #[inline(always)] + pub fn mb(&self) -> MbR { + MbR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Transmit Priority"] + #[inline(always)] + pub fn txpr(&self) -> TxprR { + TxprR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:29 - Channel Priority Weights"] + #[inline(always)] + pub fn prwg(&self) -> PrwgR { + PrwgR::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bit 31 - Rebuild INCRx Burst"] + #[inline(always)] + pub fn rib(&self) -> RibR { + RibR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset (Read, Write Set, and Self Clear)"] + #[inline(always)] + #[must_use] + pub fn swr(&mut self) -> SwrW { + SwrW::new(self, 0) + } + #[doc = "Bit 1 - DMA Arbitration Scheme"] + #[inline(always)] + #[must_use] + pub fn da(&mut self) -> DaW { + DaW::new(self, 1) + } + #[doc = "Bits 2:6 - Descriptor Skip Length"] + #[inline(always)] + #[must_use] + pub fn dsl(&mut self) -> DslW { + DslW::new(self, 2) + } + #[doc = "Bits 8:13 - Programmable Burst Lengthe"] + #[inline(always)] + #[must_use] + pub fn pbl(&mut self) -> PblW { + PblW::new(self, 8) + } + #[doc = "Bits 14:15 - Priority Ratio"] + #[inline(always)] + #[must_use] + pub fn pr(&mut self) -> PrW { + PrW::new(self, 14) + } + #[doc = "Bit 16 - Fixed Burste"] + #[inline(always)] + #[must_use] + pub fn fb(&mut self) -> FbW { + FbW::new(self, 16) + } + #[doc = "Bits 17:22 - Rx DMA PBL"] + #[inline(always)] + #[must_use] + pub fn rpbl(&mut self) -> RpblW { + RpblW::new(self, 17) + } + #[doc = "Bit 23 - Use Separate PBL"] + #[inline(always)] + #[must_use] + pub fn usp(&mut self) -> UspW { + UspW::new(self, 23) + } + #[doc = "Bit 24 - PBLx8 Mode"] + #[inline(always)] + #[must_use] + pub fn pblx8(&mut self) -> Pblx8W { + Pblx8W::new(self, 24) + } + #[doc = "Bit 25 - Address-Aligned Beats"] + #[inline(always)] + #[must_use] + pub fn aal(&mut self) -> AalW { + AalW::new(self, 25) + } + #[doc = "Bit 26 - Mixed Burst"] + #[inline(always)] + #[must_use] + pub fn mb(&mut self) -> MbW { + MbW::new(self, 26) + } + #[doc = "Bit 27 - Transmit Priority"] + #[inline(always)] + #[must_use] + pub fn txpr(&mut self) -> TxprW { + TxprW::new(self, 27) + } + #[doc = "Bits 28:29 - Channel Priority Weights"] + #[inline(always)] + #[must_use] + pub fn prwg(&mut self) -> PrwgW { + PrwgW::new(self, 28) + } + #[doc = "Bit 31 - Rebuild INCRx Burst"] + #[inline(always)] + #[must_use] + pub fn rib(&mut self) -> RibW { + RibW::new(self, 31) + } +} +#[doc = "Controls the DMA Host Interface Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_bus_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_bus_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaBusModeSpec; +impl crate::RegisterSpec for DmaBusModeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_bus_mode::R`](R) reader structure"] +impl crate::Readable for DmaBusModeSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_bus_mode::W`](W) writer structure"] +impl crate::Writable for DmaBusModeSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_BUS_MODE to value 0x0002_0101"] +impl crate::Resettable for DmaBusModeSpec { + const RESET_VALUE: u32 = 0x0002_0101; +} diff --git a/va416xx/src/eth/dma_curr_rx_bufr_addr.rs b/va416xx/src/eth/dma_curr_rx_bufr_addr.rs new file mode 100644 index 0000000..7d24d1c --- /dev/null +++ b/va416xx/src/eth/dma_curr_rx_bufr_addr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMA_CURR_RX_BUFR_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_CURR_RX_BUFR_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `CURTBUFAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtbufaptrR = crate::FieldReader; +#[doc = "Field `CURTBUFAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtbufaptrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtbufaptr(&self) -> CurtbufaptrR { + CurtbufaptrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + #[must_use] + pub fn curtbufaptr(&mut self) -> CurtbufaptrW { + CurtbufaptrW::new(self, 0) + } +} +#[doc = "Contains the current Receive Buffer address read by the DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_curr_rx_bufr_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_curr_rx_bufr_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaCurrRxBufrAddrSpec; +impl crate::RegisterSpec for DmaCurrRxBufrAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_curr_rx_bufr_addr::R`](R) reader structure"] +impl crate::Readable for DmaCurrRxBufrAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_curr_rx_bufr_addr::W`](W) writer structure"] +impl crate::Writable for DmaCurrRxBufrAddrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_CURR_RX_BUFR_ADDR to value 0"] +impl crate::Resettable for DmaCurrRxBufrAddrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_curr_rx_desc.rs b/va416xx/src/eth/dma_curr_rx_desc.rs new file mode 100644 index 0000000..5eb5692 --- /dev/null +++ b/va416xx/src/eth/dma_curr_rx_desc.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMA_CURR_RX_DESC` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_CURR_RX_DESC` writer"] +pub type W = crate::W; +#[doc = "Field `CURRDESAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurrdesaptrR = crate::FieldReader; +#[doc = "Field `CURRDESAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurrdesaptrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn currdesaptr(&self) -> CurrdesaptrR { + CurrdesaptrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + #[must_use] + pub fn currdesaptr(&mut self) -> CurrdesaptrW { + CurrdesaptrW::new(self, 0) + } +} +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_curr_rx_desc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_curr_rx_desc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaCurrRxDescSpec; +impl crate::RegisterSpec for DmaCurrRxDescSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_curr_rx_desc::R`](R) reader structure"] +impl crate::Readable for DmaCurrRxDescSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_curr_rx_desc::W`](W) writer structure"] +impl crate::Writable for DmaCurrRxDescSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_CURR_RX_DESC to value 0"] +impl crate::Resettable for DmaCurrRxDescSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_curr_tx_bufr_addr.rs b/va416xx/src/eth/dma_curr_tx_bufr_addr.rs new file mode 100644 index 0000000..9734955 --- /dev/null +++ b/va416xx/src/eth/dma_curr_tx_bufr_addr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMA_CURR_TX_BUFR_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_CURR_TX_BUFR_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `CURTBUFAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtbufaptrR = crate::FieldReader; +#[doc = "Field `CURTBUFAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtbufaptrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtbufaptr(&self) -> CurtbufaptrR { + CurtbufaptrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + #[must_use] + pub fn curtbufaptr(&mut self) -> CurtbufaptrW { + CurtbufaptrW::new(self, 0) + } +} +#[doc = "Contains the start address of the current Receive Descriptor read by the DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_curr_tx_bufr_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_curr_tx_bufr_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaCurrTxBufrAddrSpec; +impl crate::RegisterSpec for DmaCurrTxBufrAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_curr_tx_bufr_addr::R`](R) reader structure"] +impl crate::Readable for DmaCurrTxBufrAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_curr_tx_bufr_addr::W`](W) writer structure"] +impl crate::Writable for DmaCurrTxBufrAddrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_CURR_TX_BUFR_ADDR to value 0"] +impl crate::Resettable for DmaCurrTxBufrAddrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_curr_tx_desc.rs b/va416xx/src/eth/dma_curr_tx_desc.rs new file mode 100644 index 0000000..940e775 --- /dev/null +++ b/va416xx/src/eth/dma_curr_tx_desc.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMA_CURR_TX_DESC` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_CURR_TX_DESC` writer"] +pub type W = crate::W; +#[doc = "Field `CURTDESAPTR` reader - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtdesaptrR = crate::FieldReader; +#[doc = "Field `CURTDESAPTR` writer - Cleared on Reset. Pointer updated by the DMA during operation."] +pub type CurtdesaptrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + pub fn curtdesaptr(&self) -> CurtdesaptrR { + CurtdesaptrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Cleared on Reset. Pointer updated by the DMA during operation."] + #[inline(always)] + #[must_use] + pub fn curtdesaptr(&mut self) -> CurtdesaptrW { + CurtdesaptrW::new(self, 0) + } +} +#[doc = "Contains the start address of the current Transmit Descriptor read by the DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_curr_tx_desc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_curr_tx_desc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaCurrTxDescSpec; +impl crate::RegisterSpec for DmaCurrTxDescSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_curr_tx_desc::R`](R) reader structure"] +impl crate::Readable for DmaCurrTxDescSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_curr_tx_desc::W`](W) writer structure"] +impl crate::Writable for DmaCurrTxDescSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_CURR_TX_DESC to value 0"] +impl crate::Resettable for DmaCurrTxDescSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_intr_en.rs b/va416xx/src/eth/dma_intr_en.rs new file mode 100644 index 0000000..ae6834d --- /dev/null +++ b/va416xx/src/eth/dma_intr_en.rs @@ -0,0 +1,250 @@ +#[doc = "Register `DMA_INTR_EN` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_INTR_EN` writer"] +pub type W = crate::W; +#[doc = "Field `TIE` reader - Transmit Interrupt Enable"] +pub type TieR = crate::BitReader; +#[doc = "Field `TIE` writer - Transmit Interrupt Enable"] +pub type TieW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSE` reader - Transmit Stopped Enable"] +pub type TseR = crate::BitReader; +#[doc = "Field `TSE` writer - Transmit Stopped Enable"] +pub type TseW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TUE` reader - Transmit Buffer Unavailable Enable"] +pub type TueR = crate::BitReader; +#[doc = "Field `TUE` writer - Transmit Buffer Unavailable Enable"] +pub type TueW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `THE` reader - Transmit Jabber Timeout Enable"] +pub type TheR = crate::BitReader; +#[doc = "Field `THE` writer - Transmit Jabber Timeout Enable"] +pub type TheW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVE` reader - Overflow Interrupt Enable"] +pub type OveR = crate::BitReader; +#[doc = "Field `OVE` writer - Overflow Interrupt Enable"] +pub type OveW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UNE` reader - Underflow Interrupt Enable"] +pub type UneR = crate::BitReader; +#[doc = "Field `UNE` writer - Underflow Interrupt Enable"] +pub type UneW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RIE` reader - Receive Interrupt Enable"] +pub type RieR = crate::BitReader; +#[doc = "Field `RIE` writer - Receive Interrupt Enable"] +pub type RieW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RUE` reader - Receive Buffer Unavailable Enable"] +pub type RueR = crate::BitReader; +#[doc = "Field `RUE` writer - Receive Buffer Unavailable Enable"] +pub type RueW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSE` reader - Receive Stopped Enable"] +pub type RseR = crate::BitReader; +#[doc = "Field `RSE` writer - Receive Stopped Enable"] +pub type RseW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RWE` reader - Receive Watchdog Timeout Enable"] +pub type RweR = crate::BitReader; +#[doc = "Field `RWE` writer - Receive Watchdog Timeout Enable"] +pub type RweW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETE` reader - Early Transmit Interrupt Enable"] +pub type EteR = crate::BitReader; +#[doc = "Field `ETE` writer - Early Transmit Interrupt Enable"] +pub type EteW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FBE` reader - Fatal Bus Error Enable"] +pub type FbeR = crate::BitReader; +#[doc = "Field `FBE` writer - Fatal Bus Error Enable"] +pub type FbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ERE` reader - Early Receive Interrupt Enable"] +pub type EreR = crate::BitReader; +#[doc = "Field `ERE` writer - Early Receive Interrupt Enable"] +pub type EreW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AIE` reader - Abnormal Interrupt Summary Enable"] +pub type AieR = crate::BitReader; +#[doc = "Field `AIE` writer - Abnormal Interrupt Summary Enable"] +pub type AieW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NIE` reader - Normal Interrupt Summary Enable"] +pub type NieR = crate::BitReader; +#[doc = "Field `NIE` writer - Normal Interrupt Summary Enable"] +pub type NieW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Transmit Interrupt Enable"] + #[inline(always)] + pub fn tie(&self) -> TieR { + TieR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Stopped Enable"] + #[inline(always)] + pub fn tse(&self) -> TseR { + TseR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transmit Buffer Unavailable Enable"] + #[inline(always)] + pub fn tue(&self) -> TueR { + TueR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmit Jabber Timeout Enable"] + #[inline(always)] + pub fn the(&self) -> TheR { + TheR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ove(&self) -> OveR { + OveR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Underflow Interrupt Enable"] + #[inline(always)] + pub fn une(&self) -> UneR { + UneR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Receive Interrupt Enable"] + #[inline(always)] + pub fn rie(&self) -> RieR { + RieR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Receive Buffer Unavailable Enable"] + #[inline(always)] + pub fn rue(&self) -> RueR { + RueR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Receive Stopped Enable"] + #[inline(always)] + pub fn rse(&self) -> RseR { + RseR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Receive Watchdog Timeout Enable"] + #[inline(always)] + pub fn rwe(&self) -> RweR { + RweR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Early Transmit Interrupt Enable"] + #[inline(always)] + pub fn ete(&self) -> EteR { + EteR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 13 - Fatal Bus Error Enable"] + #[inline(always)] + pub fn fbe(&self) -> FbeR { + FbeR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Early Receive Interrupt Enable"] + #[inline(always)] + pub fn ere(&self) -> EreR { + EreR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Abnormal Interrupt Summary Enable"] + #[inline(always)] + pub fn aie(&self) -> AieR { + AieR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Normal Interrupt Summary Enable"] + #[inline(always)] + pub fn nie(&self) -> NieR { + NieR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transmit Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn tie(&mut self) -> TieW { + TieW::new(self, 0) + } + #[doc = "Bit 1 - Transmit Stopped Enable"] + #[inline(always)] + #[must_use] + pub fn tse(&mut self) -> TseW { + TseW::new(self, 1) + } + #[doc = "Bit 2 - Transmit Buffer Unavailable Enable"] + #[inline(always)] + #[must_use] + pub fn tue(&mut self) -> TueW { + TueW::new(self, 2) + } + #[doc = "Bit 3 - Transmit Jabber Timeout Enable"] + #[inline(always)] + #[must_use] + pub fn the(&mut self) -> TheW { + TheW::new(self, 3) + } + #[doc = "Bit 4 - Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ove(&mut self) -> OveW { + OveW::new(self, 4) + } + #[doc = "Bit 5 - Underflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn une(&mut self) -> UneW { + UneW::new(self, 5) + } + #[doc = "Bit 6 - Receive Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn rie(&mut self) -> RieW { + RieW::new(self, 6) + } + #[doc = "Bit 7 - Receive Buffer Unavailable Enable"] + #[inline(always)] + #[must_use] + pub fn rue(&mut self) -> RueW { + RueW::new(self, 7) + } + #[doc = "Bit 8 - Receive Stopped Enable"] + #[inline(always)] + #[must_use] + pub fn rse(&mut self) -> RseW { + RseW::new(self, 8) + } + #[doc = "Bit 9 - Receive Watchdog Timeout Enable"] + #[inline(always)] + #[must_use] + pub fn rwe(&mut self) -> RweW { + RweW::new(self, 9) + } + #[doc = "Bit 10 - Early Transmit Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ete(&mut self) -> EteW { + EteW::new(self, 10) + } + #[doc = "Bit 13 - Fatal Bus Error Enable"] + #[inline(always)] + #[must_use] + pub fn fbe(&mut self) -> FbeW { + FbeW::new(self, 13) + } + #[doc = "Bit 14 - Early Receive Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ere(&mut self) -> EreW { + EreW::new(self, 14) + } + #[doc = "Bit 15 - Abnormal Interrupt Summary Enable"] + #[inline(always)] + #[must_use] + pub fn aie(&mut self) -> AieW { + AieW::new(self, 15) + } + #[doc = "Bit 16 - Normal Interrupt Summary Enable"] + #[inline(always)] + #[must_use] + pub fn nie(&mut self) -> NieW { + NieW::new(self, 16) + } +} +#[doc = "Enables the interrupts reported in the status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_intr_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_intr_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaIntrEnSpec; +impl crate::RegisterSpec for DmaIntrEnSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_intr_en::R`](R) reader structure"] +impl crate::Readable for DmaIntrEnSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_intr_en::W`](W) writer structure"] +impl crate::Writable for DmaIntrEnSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_INTR_EN to value 0"] +impl crate::Resettable for DmaIntrEnSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_miss_over_counter.rs b/va416xx/src/eth/dma_miss_over_counter.rs new file mode 100644 index 0000000..14f5065 --- /dev/null +++ b/va416xx/src/eth/dma_miss_over_counter.rs @@ -0,0 +1,85 @@ +#[doc = "Register `DMA_MISS_OVER_COUNTER` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_MISS_OVER_COUNTER` writer"] +pub type W = crate::W; +#[doc = "Field `MISFRMCNT` reader - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] +pub type MisfrmcntR = crate::FieldReader; +#[doc = "Field `MISFRMCNT` writer - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] +pub type MisfrmcntW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `MISCNTOVF` reader - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] +pub type MiscntovfR = crate::BitReader; +#[doc = "Field `MISCNTOVF` writer - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] +pub type MiscntovfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OVFFRMCNT` reader - This field indicates the number of frames missed by the application"] +pub type OvffrmcntR = crate::FieldReader; +#[doc = "Field `OVFFRMCNT` writer - This field indicates the number of frames missed by the application"] +pub type OvffrmcntW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `OVFCNTOVF` reader - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] +pub type OvfcntovfR = crate::BitReader; +#[doc = "Field `OVFCNTOVF` writer - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] +pub type OvfcntovfW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] + #[inline(always)] + pub fn misfrmcnt(&self) -> MisfrmcntR { + MisfrmcntR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] + #[inline(always)] + pub fn miscntovf(&self) -> MiscntovfR { + MiscntovfR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:27 - This field indicates the number of frames missed by the application"] + #[inline(always)] + pub fn ovffrmcnt(&self) -> OvffrmcntR { + OvffrmcntR::new(((self.bits >> 17) & 0x07ff) as u16) + } + #[doc = "Bit 28 - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] + #[inline(always)] + pub fn ovfcntovf(&self) -> OvfcntovfR { + OvfcntovfR::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable."] + #[inline(always)] + #[must_use] + pub fn misfrmcnt(&mut self) -> MisfrmcntW { + MisfrmcntW::new(self, 0) + } + #[doc = "Bit 16 - This bit is set every time Missed Frame Counter (Bits\\[15:0\\]) overflows"] + #[inline(always)] + #[must_use] + pub fn miscntovf(&mut self) -> MiscntovfW { + MiscntovfW::new(self, 16) + } + #[doc = "Bits 17:27 - This field indicates the number of frames missed by the application"] + #[inline(always)] + #[must_use] + pub fn ovffrmcnt(&mut self) -> OvffrmcntW { + OvffrmcntW::new(self, 17) + } + #[doc = "Bit 28 - This bit is set every time the Overflow Frame Counter (Bits\\[27:17\\])overflows"] + #[inline(always)] + #[must_use] + pub fn ovfcntovf(&mut self) -> OvfcntovfW { + OvfcntovfW::new(self, 28) + } +} +#[doc = "Contains the counters for discarded frames because no Receive Descriptor is available\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_miss_over_counter::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_miss_over_counter::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaMissOverCounterSpec; +impl crate::RegisterSpec for DmaMissOverCounterSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_miss_over_counter::R`](R) reader structure"] +impl crate::Readable for DmaMissOverCounterSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_miss_over_counter::W`](W) writer structure"] +impl crate::Writable for DmaMissOverCounterSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_MISS_OVER_COUNTER to value 0"] +impl crate::Resettable for DmaMissOverCounterSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_oper_mode.rs b/va416xx/src/eth/dma_oper_mode.rs new file mode 100644 index 0000000..8830bd5 --- /dev/null +++ b/va416xx/src/eth/dma_oper_mode.rs @@ -0,0 +1,250 @@ +#[doc = "Register `DMA_OPER_MODE` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_OPER_MODE` writer"] +pub type W = crate::W; +#[doc = "Field `SR` reader - Start or Stop Receive"] +pub type SrR = crate::BitReader; +#[doc = "Field `SR` writer - Start or Stop Receive"] +pub type SrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OSF` reader - Operate on Second Frame"] +pub type OsfR = crate::BitReader; +#[doc = "Field `OSF` writer - Operate on Second Frame"] +pub type OsfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTC` reader - Receive Threshold Control"] +pub type RtcR = crate::FieldReader; +#[doc = "Field `RTC` writer - Receive Threshold Control"] +pub type RtcW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DGF` reader - Drop Giant Frames"] +pub type DgfR = crate::BitReader; +#[doc = "Field `DGF` writer - Drop Giant Frames"] +pub type DgfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FUF` reader - Forward Undersized Good Frames"] +pub type FufR = crate::BitReader; +#[doc = "Field `FUF` writer - Forward Undersized Good Frames"] +pub type FufW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FEF` reader - Forward Error Frames"] +pub type FefR = crate::BitReader; +#[doc = "Field `FEF` writer - Forward Error Frames"] +pub type FefW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RFA` reader - Threshold for Activating Flow Control"] +pub type RfaR = crate::FieldReader; +#[doc = "Field `RFA` writer - Threshold for Activating Flow Control"] +pub type RfaW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RFD` reader - Threshold for Deactivating Flow Control"] +pub type RfdR = crate::FieldReader; +#[doc = "Field `RFD` writer - Threshold for Deactivating Flow Control"] +pub type RfdW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ST` reader - Start or Stop Transmission Command"] +pub type StR = crate::BitReader; +#[doc = "Field `ST` writer - Start or Stop Transmission Command"] +pub type StW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TTC` reader - Transmit Threshold Control"] +pub type TtcR = crate::FieldReader; +#[doc = "Field `TTC` writer - Transmit Threshold Control"] +pub type TtcW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `FTF` reader - Flush Transmit FIFO"] +pub type FtfR = crate::BitReader; +#[doc = "Field `FTF` writer - Flush Transmit FIFO"] +pub type FtfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSF` reader - Transmit Store and Forward"] +pub type TsfR = crate::BitReader; +#[doc = "Field `TSF` writer - Transmit Store and Forward"] +pub type TsfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DFF` reader - Disable Flushing of Received Frames"] +pub type DffR = crate::BitReader; +#[doc = "Field `DFF` writer - Disable Flushing of Received Frames"] +pub type DffW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSF` reader - Receive Store and Forward"] +pub type RsfR = crate::BitReader; +#[doc = "Field `RSF` writer - Receive Store and Forward"] +pub type RsfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DT` reader - Disable Dropping of TCP/IP Checksum Error Frames"] +pub type DtR = crate::BitReader; +#[doc = "Field `DT` writer - Disable Dropping of TCP/IP Checksum Error Frames"] +pub type DtW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - Start or Stop Receive"] + #[inline(always)] + pub fn sr(&self) -> SrR { + SrR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Operate on Second Frame"] + #[inline(always)] + pub fn osf(&self) -> OsfR { + OsfR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - Receive Threshold Control"] + #[inline(always)] + pub fn rtc(&self) -> RtcR { + RtcR::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Drop Giant Frames"] + #[inline(always)] + pub fn dgf(&self) -> DgfR { + DgfR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Forward Undersized Good Frames"] + #[inline(always)] + pub fn fuf(&self) -> FufR { + FufR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Forward Error Frames"] + #[inline(always)] + pub fn fef(&self) -> FefR { + FefR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 9:10 - Threshold for Activating Flow Control"] + #[inline(always)] + pub fn rfa(&self) -> RfaR { + RfaR::new(((self.bits >> 9) & 3) as u8) + } + #[doc = "Bits 11:12 - Threshold for Deactivating Flow Control"] + #[inline(always)] + pub fn rfd(&self) -> RfdR { + RfdR::new(((self.bits >> 11) & 3) as u8) + } + #[doc = "Bit 13 - Start or Stop Transmission Command"] + #[inline(always)] + pub fn st(&self) -> StR { + StR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:16 - Transmit Threshold Control"] + #[inline(always)] + pub fn ttc(&self) -> TtcR { + TtcR::new(((self.bits >> 14) & 7) as u8) + } + #[doc = "Bit 20 - Flush Transmit FIFO"] + #[inline(always)] + pub fn ftf(&self) -> FtfR { + FtfR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Transmit Store and Forward"] + #[inline(always)] + pub fn tsf(&self) -> TsfR { + TsfR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 24 - Disable Flushing of Received Frames"] + #[inline(always)] + pub fn dff(&self) -> DffR { + DffR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Receive Store and Forward"] + #[inline(always)] + pub fn rsf(&self) -> RsfR { + RsfR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Disable Dropping of TCP/IP Checksum Error Frames"] + #[inline(always)] + pub fn dt(&self) -> DtR { + DtR::new(((self.bits >> 26) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Start or Stop Receive"] + #[inline(always)] + #[must_use] + pub fn sr(&mut self) -> SrW { + SrW::new(self, 1) + } + #[doc = "Bit 2 - Operate on Second Frame"] + #[inline(always)] + #[must_use] + pub fn osf(&mut self) -> OsfW { + OsfW::new(self, 2) + } + #[doc = "Bits 3:4 - Receive Threshold Control"] + #[inline(always)] + #[must_use] + pub fn rtc(&mut self) -> RtcW { + RtcW::new(self, 3) + } + #[doc = "Bit 5 - Drop Giant Frames"] + #[inline(always)] + #[must_use] + pub fn dgf(&mut self) -> DgfW { + DgfW::new(self, 5) + } + #[doc = "Bit 6 - Forward Undersized Good Frames"] + #[inline(always)] + #[must_use] + pub fn fuf(&mut self) -> FufW { + FufW::new(self, 6) + } + #[doc = "Bit 7 - Forward Error Frames"] + #[inline(always)] + #[must_use] + pub fn fef(&mut self) -> FefW { + FefW::new(self, 7) + } + #[doc = "Bits 9:10 - Threshold for Activating Flow Control"] + #[inline(always)] + #[must_use] + pub fn rfa(&mut self) -> RfaW { + RfaW::new(self, 9) + } + #[doc = "Bits 11:12 - Threshold for Deactivating Flow Control"] + #[inline(always)] + #[must_use] + pub fn rfd(&mut self) -> RfdW { + RfdW::new(self, 11) + } + #[doc = "Bit 13 - Start or Stop Transmission Command"] + #[inline(always)] + #[must_use] + pub fn st(&mut self) -> StW { + StW::new(self, 13) + } + #[doc = "Bits 14:16 - Transmit Threshold Control"] + #[inline(always)] + #[must_use] + pub fn ttc(&mut self) -> TtcW { + TtcW::new(self, 14) + } + #[doc = "Bit 20 - Flush Transmit FIFO"] + #[inline(always)] + #[must_use] + pub fn ftf(&mut self) -> FtfW { + FtfW::new(self, 20) + } + #[doc = "Bit 21 - Transmit Store and Forward"] + #[inline(always)] + #[must_use] + pub fn tsf(&mut self) -> TsfW { + TsfW::new(self, 21) + } + #[doc = "Bit 24 - Disable Flushing of Received Frames"] + #[inline(always)] + #[must_use] + pub fn dff(&mut self) -> DffW { + DffW::new(self, 24) + } + #[doc = "Bit 25 - Receive Store and Forward"] + #[inline(always)] + #[must_use] + pub fn rsf(&mut self) -> RsfW { + RsfW::new(self, 25) + } + #[doc = "Bit 26 - Disable Dropping of TCP/IP Checksum Error Frames"] + #[inline(always)] + #[must_use] + pub fn dt(&mut self) -> DtW { + DtW::new(self, 26) + } +} +#[doc = "Sets the Receive and Transmit operation mode and command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_oper_mode::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_oper_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaOperModeSpec; +impl crate::RegisterSpec for DmaOperModeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_oper_mode::R`](R) reader structure"] +impl crate::Readable for DmaOperModeSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_oper_mode::W`](W) writer structure"] +impl crate::Writable for DmaOperModeSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_OPER_MODE to value 0"] +impl crate::Resettable for DmaOperModeSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_rx_desc_list_addr.rs b/va416xx/src/eth/dma_rx_desc_list_addr.rs new file mode 100644 index 0000000..124dc86 --- /dev/null +++ b/va416xx/src/eth/dma_rx_desc_list_addr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMA_RX_DESC_LIST_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_RX_DESC_LIST_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `RDESLA` reader - Start of Receive List"] +pub type RdeslaR = crate::FieldReader; +#[doc = "Field `RDESLA` writer - Start of Receive List"] +pub type RdeslaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Start of Receive List"] + #[inline(always)] + pub fn rdesla(&self) -> RdeslaR { + RdeslaR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Start of Receive List"] + #[inline(always)] + #[must_use] + pub fn rdesla(&mut self) -> RdeslaW { + RdeslaW::new(self, 0) + } +} +#[doc = "Points the DMA to the start of the Receive Descriptor list\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_rx_desc_list_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_rx_desc_list_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaRxDescListAddrSpec; +impl crate::RegisterSpec for DmaRxDescListAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_rx_desc_list_addr::R`](R) reader structure"] +impl crate::Readable for DmaRxDescListAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_rx_desc_list_addr::W`](W) writer structure"] +impl crate::Writable for DmaRxDescListAddrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_RX_DESC_LIST_ADDR to value 0"] +impl crate::Resettable for DmaRxDescListAddrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_rx_intr_wdog_timer.rs b/va416xx/src/eth/dma_rx_intr_wdog_timer.rs new file mode 100644 index 0000000..d4ef2f0 --- /dev/null +++ b/va416xx/src/eth/dma_rx_intr_wdog_timer.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMA_RX_INTR_WDOG_TIMER` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_RX_INTR_WDOG_TIMER` writer"] +pub type W = crate::W; +#[doc = "Field `RIWT` reader - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] +pub type RiwtR = crate::FieldReader; +#[doc = "Field `RIWT` writer - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] +pub type RiwtW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] + #[inline(always)] + pub fn riwt(&self) -> RiwtR { + RiwtR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set."] + #[inline(always)] + #[must_use] + pub fn riwt(&mut self) -> RiwtW { + RiwtW::new(self, 0) + } +} +#[doc = "Watchdog timeout for Receive Interrupt from DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_rx_intr_wdog_timer::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_rx_intr_wdog_timer::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaRxIntrWdogTimerSpec; +impl crate::RegisterSpec for DmaRxIntrWdogTimerSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_rx_intr_wdog_timer::R`](R) reader structure"] +impl crate::Readable for DmaRxIntrWdogTimerSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_rx_intr_wdog_timer::W`](W) writer structure"] +impl crate::Writable for DmaRxIntrWdogTimerSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_RX_INTR_WDOG_TIMER to value 0"] +impl crate::Resettable for DmaRxIntrWdogTimerSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_rx_poll_demand.rs b/va416xx/src/eth/dma_rx_poll_demand.rs new file mode 100644 index 0000000..df87347 --- /dev/null +++ b/va416xx/src/eth/dma_rx_poll_demand.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMA_RX_POLL_DEMAND` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_RX_POLL_DEMAND` writer"] +pub type W = crate::W; +#[doc = "Field `RPD` reader - Receive Poll Demand (Read Only and Write Trigger)"] +pub type RpdR = crate::FieldReader; +#[doc = "Field `RPD` writer - Receive Poll Demand (Read Only and Write Trigger)"] +pub type RpdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Receive Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + pub fn rpd(&self) -> RpdR { + RpdR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Receive Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + #[must_use] + pub fn rpd(&mut self) -> RpdW { + RpdW::new(self, 0) + } +} +#[doc = "Used by the host to instruct the DMA to poll the Receive Descriptor list\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_rx_poll_demand::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_rx_poll_demand::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaRxPollDemandSpec; +impl crate::RegisterSpec for DmaRxPollDemandSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_rx_poll_demand::R`](R) reader structure"] +impl crate::Readable for DmaRxPollDemandSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_rx_poll_demand::W`](W) writer structure"] +impl crate::Writable for DmaRxPollDemandSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_RX_POLL_DEMAND to value 0"] +impl crate::Resettable for DmaRxPollDemandSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_status.rs b/va416xx/src/eth/dma_status.rs new file mode 100644 index 0000000..cc4d93d --- /dev/null +++ b/va416xx/src/eth/dma_status.rs @@ -0,0 +1,155 @@ +#[doc = "Register `DMA_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TI` reader - Transmit Interrupt"] +pub type TiR = crate::BitReader; +#[doc = "Field `TPS` reader - Transmit Process Stopped"] +pub type TpsR = crate::BitReader; +#[doc = "Field `TU` reader - Transmit Buffer Unavailable"] +pub type TuR = crate::BitReader; +#[doc = "Field `TJT` reader - Transmit Jabber Timeout"] +pub type TjtR = crate::BitReader; +#[doc = "Field `OVF` reader - Receive Underflow"] +pub type OvfR = crate::BitReader; +#[doc = "Field `UNF` reader - Transmit Underflow"] +pub type UnfR = crate::BitReader; +#[doc = "Field `RI` reader - Receive Interrupt"] +pub type RiR = crate::BitReader; +#[doc = "Field `RU` reader - Receive Buffer Unavailable"] +pub type RuR = crate::BitReader; +#[doc = "Field `RPS` reader - Receive Process Stopped"] +pub type RpsR = crate::BitReader; +#[doc = "Field `RWT` reader - Receive Watchdog Timeout"] +pub type RwtR = crate::BitReader; +#[doc = "Field `ETI` reader - Early Transmit Interrupt"] +pub type EtiR = crate::BitReader; +#[doc = "Field `FBI` reader - Fatal Bus Error Interruptble"] +pub type FbiR = crate::BitReader; +#[doc = "Field `ERI` reader - Early Receive Interrupt"] +pub type EriR = crate::BitReader; +#[doc = "Field `AIS` reader - Abnormal Interrupt Summary"] +pub type AisR = crate::BitReader; +#[doc = "Field `NIS` reader - Normal Interrupt Summary"] +pub type NisR = crate::BitReader; +#[doc = "Field `RS` reader - Receive Process State"] +pub type RsR = crate::FieldReader; +#[doc = "Field `TS` reader - Transmit Process State"] +pub type TsR = crate::FieldReader; +#[doc = "Field `EB` reader - Error Bits"] +pub type EbR = crate::FieldReader; +#[doc = "Field `GMI` reader - GMAC MMC Interrupt"] +pub type GmiR = crate::BitReader; +#[doc = "Field `TTI` reader - Timestamp Trigger Interrupt"] +pub type TtiR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit Interrupt"] + #[inline(always)] + pub fn ti(&self) -> TiR { + TiR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Process Stopped"] + #[inline(always)] + pub fn tps(&self) -> TpsR { + TpsR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Transmit Buffer Unavailable"] + #[inline(always)] + pub fn tu(&self) -> TuR { + TuR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmit Jabber Timeout"] + #[inline(always)] + pub fn tjt(&self) -> TjtR { + TjtR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Receive Underflow"] + #[inline(always)] + pub fn ovf(&self) -> OvfR { + OvfR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Transmit Underflow"] + #[inline(always)] + pub fn unf(&self) -> UnfR { + UnfR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Receive Interrupt"] + #[inline(always)] + pub fn ri(&self) -> RiR { + RiR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Receive Buffer Unavailable"] + #[inline(always)] + pub fn ru(&self) -> RuR { + RuR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Receive Process Stopped"] + #[inline(always)] + pub fn rps(&self) -> RpsR { + RpsR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Receive Watchdog Timeout"] + #[inline(always)] + pub fn rwt(&self) -> RwtR { + RwtR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Early Transmit Interrupt"] + #[inline(always)] + pub fn eti(&self) -> EtiR { + EtiR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 13 - Fatal Bus Error Interruptble"] + #[inline(always)] + pub fn fbi(&self) -> FbiR { + FbiR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Early Receive Interrupt"] + #[inline(always)] + pub fn eri(&self) -> EriR { + EriR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Abnormal Interrupt Summary"] + #[inline(always)] + pub fn ais(&self) -> AisR { + AisR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Normal Interrupt Summary"] + #[inline(always)] + pub fn nis(&self) -> NisR { + NisR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - Receive Process State"] + #[inline(always)] + pub fn rs(&self) -> RsR { + RsR::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bits 20:22 - Transmit Process State"] + #[inline(always)] + pub fn ts(&self) -> TsR { + TsR::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bits 23:25 - Error Bits"] + #[inline(always)] + pub fn eb(&self) -> EbR { + EbR::new(((self.bits >> 23) & 7) as u8) + } + #[doc = "Bit 27 - GMAC MMC Interrupt"] + #[inline(always)] + pub fn gmi(&self) -> GmiR { + GmiR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 29 - Timestamp Trigger Interrupt"] + #[inline(always)] + pub fn tti(&self) -> TtiR { + TtiR::new(((self.bits >> 29) & 1) != 0) + } +} +#[doc = "Used to determine the status of the DMA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaStatusSpec; +impl crate::RegisterSpec for DmaStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_status::R`](R) reader structure"] +impl crate::Readable for DmaStatusSpec {} +#[doc = "`reset()` method sets DMA_STATUS to value 0"] +impl crate::Resettable for DmaStatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_tx_desc_list_addr.rs b/va416xx/src/eth/dma_tx_desc_list_addr.rs new file mode 100644 index 0000000..123386b --- /dev/null +++ b/va416xx/src/eth/dma_tx_desc_list_addr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMA_TX_DESC_LIST_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_TX_DESC_LIST_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `TDESLA` reader - Start of Transmit List"] +pub type TdeslaR = crate::FieldReader; +#[doc = "Field `TDESLA` writer - Start of Transmit List"] +pub type TdeslaW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Start of Transmit List"] + #[inline(always)] + pub fn tdesla(&self) -> TdeslaR { + TdeslaR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Start of Transmit List"] + #[inline(always)] + #[must_use] + pub fn tdesla(&mut self) -> TdeslaW { + TdeslaW::new(self, 0) + } +} +#[doc = "Points the DMA to the start of the Transmit Descriptor list\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_tx_desc_list_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_tx_desc_list_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaTxDescListAddrSpec; +impl crate::RegisterSpec for DmaTxDescListAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_tx_desc_list_addr::R`](R) reader structure"] +impl crate::Readable for DmaTxDescListAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_tx_desc_list_addr::W`](W) writer structure"] +impl crate::Writable for DmaTxDescListAddrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_TX_DESC_LIST_ADDR to value 0"] +impl crate::Resettable for DmaTxDescListAddrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/dma_tx_poll_demand.rs b/va416xx/src/eth/dma_tx_poll_demand.rs new file mode 100644 index 0000000..b5d9b31 --- /dev/null +++ b/va416xx/src/eth/dma_tx_poll_demand.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMA_TX_POLL_DEMAND` reader"] +pub type R = crate::R; +#[doc = "Register `DMA_TX_POLL_DEMAND` writer"] +pub type W = crate::W; +#[doc = "Field `TPD` reader - Transmit Poll Demand (Read Only and Write Trigger)"] +pub type TpdR = crate::FieldReader; +#[doc = "Field `TPD` writer - Transmit Poll Demand (Read Only and Write Trigger)"] +pub type TpdW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Transmit Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + pub fn tpd(&self) -> TpdR { + TpdR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Transmit Poll Demand (Read Only and Write Trigger)"] + #[inline(always)] + #[must_use] + pub fn tpd(&mut self) -> TpdW { + TpdW::new(self, 0) + } +} +#[doc = "Used by the host to instruct the DMA to poll the transmit Descriptor list\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_tx_poll_demand::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_tx_poll_demand::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmaTxPollDemandSpec; +impl crate::RegisterSpec for DmaTxPollDemandSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dma_tx_poll_demand::R`](R) reader structure"] +impl crate::Readable for DmaTxPollDemandSpec {} +#[doc = "`write(|w| ..)` method takes [`dma_tx_poll_demand::W`](W) writer structure"] +impl crate::Writable for DmaTxPollDemandSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMA_TX_POLL_DEMAND to value 0"] +impl crate::Resettable for DmaTxPollDemandSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mac_addr_h.rs b/va416xx/src/eth/mac_addr_h.rs new file mode 100644 index 0000000..45fd510 --- /dev/null +++ b/va416xx/src/eth/mac_addr_h.rs @@ -0,0 +1,38 @@ +#[doc = "Register `MAC_ADDR_H` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_ADDR_H` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRHI` reader - MAC Address0\\[47:32\\]"] +pub type AddrhiR = crate::FieldReader; +#[doc = "Field `AE` reader - Address Enable, This bit is always set to 1"] +pub type AeR = crate::BitReader; +impl R { + #[doc = "Bits 0:15 - MAC Address0\\[47:32\\]"] + #[inline(always)] + pub fn addrhi(&self) -> AddrhiR { + AddrhiR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 31 - Address Enable, This bit is always set to 1"] + #[inline(always)] + pub fn ae(&self) -> AeR { + AeR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W {} +#[doc = "Contains the high 16-bits of the first MAC Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_addr_h::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_addr_h::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacAddrHSpec; +impl crate::RegisterSpec for MacAddrHSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_addr_h::R`](R) reader structure"] +impl crate::Readable for MacAddrHSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_addr_h::W`](W) writer structure"] +impl crate::Writable for MacAddrHSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAC_ADDR_H to value 0x8000_ffff"] +impl crate::Resettable for MacAddrHSpec { + const RESET_VALUE: u32 = 0x8000_ffff; +} diff --git a/va416xx/src/eth/mac_addr_l.rs b/va416xx/src/eth/mac_addr_l.rs new file mode 100644 index 0000000..7a60fd7 --- /dev/null +++ b/va416xx/src/eth/mac_addr_l.rs @@ -0,0 +1,31 @@ +#[doc = "Register `MAC_ADDR_L` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_ADDR_L` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRLO` reader - MAC Address0\\[31:0\\]"] +pub type AddrloR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - MAC Address0\\[31:0\\]"] + #[inline(always)] + pub fn addrlo(&self) -> AddrloR { + AddrloR::new(self.bits) + } +} +impl W {} +#[doc = "Contains the Low 32-bits of the first MAC Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_addr_l::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_addr_l::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacAddrLSpec; +impl crate::RegisterSpec for MacAddrLSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_addr_l::R`](R) reader structure"] +impl crate::Readable for MacAddrLSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_addr_l::W`](W) writer structure"] +impl crate::Writable for MacAddrLSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAC_ADDR_L to value 0xffff_ffff"] +impl crate::Resettable for MacAddrLSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va416xx/src/eth/mac_config.rs b/va416xx/src/eth/mac_config.rs new file mode 100644 index 0000000..c855b13 --- /dev/null +++ b/va416xx/src/eth/mac_config.rs @@ -0,0 +1,310 @@ +#[doc = "Register `MAC_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `PRELEN` reader - Preamble Length for Transmit frames"] +pub type PrelenR = crate::FieldReader; +#[doc = "Field `PRELEN` writer - Preamble Length for Transmit frames"] +pub type PrelenW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `RE` reader - Receiver Enable"] +pub type ReR = crate::BitReader; +#[doc = "Field `RE` writer - Receiver Enable"] +pub type ReW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TE` reader - Transmitter Enable"] +pub type TeR = crate::BitReader; +#[doc = "Field `TE` writer - Transmitter Enable"] +pub type TeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DC` reader - Deferral Check"] +pub type DcR = crate::BitReader; +#[doc = "Field `DC` writer - Deferral Check"] +pub type DcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BL` reader - Back-Off-Limit"] +pub type BlR = crate::FieldReader; +#[doc = "Field `BL` writer - Back-Off-Limit"] +pub type BlW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ACS` reader - Automatic Pad, or CRC Stripping"] +pub type AcsR = crate::BitReader; +#[doc = "Field `ACS` writer - Automatic Pad, or CRC Stripping"] +pub type AcsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DR` reader - Disable Retry"] +pub type DrR = crate::BitReader; +#[doc = "Field `DR` writer - Disable Retry"] +pub type DrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IPC` reader - Checksum Offload"] +pub type IpcR = crate::BitReader; +#[doc = "Field `IPC` writer - Checksum Offload"] +pub type IpcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DM` reader - Duplex Mode"] +pub type DmR = crate::BitReader; +#[doc = "Field `DM` writer - Duplex Mode"] +pub type DmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LM` reader - Loopback Mode"] +pub type LmR = crate::BitReader; +#[doc = "Field `LM` writer - Loopback Mode"] +pub type LmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DRO` reader - Disable Receive Own"] +pub type DroR = crate::BitReader; +#[doc = "Field `DRO` writer - Disable Receive Own"] +pub type DroW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FES` reader - Speed"] +pub type FesR = crate::BitReader; +#[doc = "Field `FES` writer - Speed"] +pub type FesW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PS` reader - Port Select"] +pub type PsR = crate::BitReader; +#[doc = "Field `PS` writer - Port Select"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCRS` reader - Disable Carrier Sense During Transmission"] +pub type DcrsR = crate::BitReader; +#[doc = "Field `DCRS` writer - Disable Carrier Sense During Transmission"] +pub type DcrsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IFG` reader - Inter-Frame Gap"] +pub type IfgR = crate::FieldReader; +#[doc = "Field `IFG` writer - Inter-Frame Gap"] +pub type IfgW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `JE` reader - Jumbo Frame Enable"] +pub type JeR = crate::BitReader; +#[doc = "Field `JE` writer - Jumbo Frame Enable"] +pub type JeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BE` reader - Frame Burst Enable"] +pub type BeR = crate::BitReader; +#[doc = "Field `BE` writer - Frame Burst Enable"] +pub type BeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JD` reader - Jabber Disable"] +pub type JdR = crate::BitReader; +#[doc = "Field `JD` writer - Jabber Disable"] +pub type JdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WD` reader - Watchdog disable"] +pub type WdR = crate::BitReader; +#[doc = "Field `WD` writer - Watchdog disable"] +pub type WdW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:1 - Preamble Length for Transmit frames"] + #[inline(always)] + pub fn prelen(&self) -> PrelenR { + PrelenR::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Receiver Enable"] + #[inline(always)] + pub fn re(&self) -> ReR { + ReR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Transmitter Enable"] + #[inline(always)] + pub fn te(&self) -> TeR { + TeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Deferral Check"] + #[inline(always)] + pub fn dc(&self) -> DcR { + DcR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Back-Off-Limit"] + #[inline(always)] + pub fn bl(&self) -> BlR { + BlR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Automatic Pad, or CRC Stripping"] + #[inline(always)] + pub fn acs(&self) -> AcsR { + AcsR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Disable Retry"] + #[inline(always)] + pub fn dr(&self) -> DrR { + DrR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Checksum Offload"] + #[inline(always)] + pub fn ipc(&self) -> IpcR { + IpcR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Duplex Mode"] + #[inline(always)] + pub fn dm(&self) -> DmR { + DmR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Loopback Mode"] + #[inline(always)] + pub fn lm(&self) -> LmR { + LmR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Disable Receive Own"] + #[inline(always)] + pub fn dro(&self) -> DroR { + DroR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Speed"] + #[inline(always)] + pub fn fes(&self) -> FesR { + FesR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Port Select"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Disable Carrier Sense During Transmission"] + #[inline(always)] + pub fn dcrs(&self) -> DcrsR { + DcrsR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:19 - Inter-Frame Gap"] + #[inline(always)] + pub fn ifg(&self) -> IfgR { + IfgR::new(((self.bits >> 17) & 7) as u8) + } + #[doc = "Bit 20 - Jumbo Frame Enable"] + #[inline(always)] + pub fn je(&self) -> JeR { + JeR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Frame Burst Enable"] + #[inline(always)] + pub fn be(&self) -> BeR { + BeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Jabber Disable"] + #[inline(always)] + pub fn jd(&self) -> JdR { + JdR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Watchdog disable"] + #[inline(always)] + pub fn wd(&self) -> WdR { + WdR::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Preamble Length for Transmit frames"] + #[inline(always)] + #[must_use] + pub fn prelen(&mut self) -> PrelenW { + PrelenW::new(self, 0) + } + #[doc = "Bit 2 - Receiver Enable"] + #[inline(always)] + #[must_use] + pub fn re(&mut self) -> ReW { + ReW::new(self, 2) + } + #[doc = "Bit 3 - Transmitter Enable"] + #[inline(always)] + #[must_use] + pub fn te(&mut self) -> TeW { + TeW::new(self, 3) + } + #[doc = "Bit 4 - Deferral Check"] + #[inline(always)] + #[must_use] + pub fn dc(&mut self) -> DcW { + DcW::new(self, 4) + } + #[doc = "Bits 5:6 - Back-Off-Limit"] + #[inline(always)] + #[must_use] + pub fn bl(&mut self) -> BlW { + BlW::new(self, 5) + } + #[doc = "Bit 7 - Automatic Pad, or CRC Stripping"] + #[inline(always)] + #[must_use] + pub fn acs(&mut self) -> AcsW { + AcsW::new(self, 7) + } + #[doc = "Bit 9 - Disable Retry"] + #[inline(always)] + #[must_use] + pub fn dr(&mut self) -> DrW { + DrW::new(self, 9) + } + #[doc = "Bit 10 - Checksum Offload"] + #[inline(always)] + #[must_use] + pub fn ipc(&mut self) -> IpcW { + IpcW::new(self, 10) + } + #[doc = "Bit 11 - Duplex Mode"] + #[inline(always)] + #[must_use] + pub fn dm(&mut self) -> DmW { + DmW::new(self, 11) + } + #[doc = "Bit 12 - Loopback Mode"] + #[inline(always)] + #[must_use] + pub fn lm(&mut self) -> LmW { + LmW::new(self, 12) + } + #[doc = "Bit 13 - Disable Receive Own"] + #[inline(always)] + #[must_use] + pub fn dro(&mut self) -> DroW { + DroW::new(self, 13) + } + #[doc = "Bit 14 - Speed"] + #[inline(always)] + #[must_use] + pub fn fes(&mut self) -> FesW { + FesW::new(self, 14) + } + #[doc = "Bit 15 - Port Select"] + #[inline(always)] + #[must_use] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 15) + } + #[doc = "Bit 16 - Disable Carrier Sense During Transmission"] + #[inline(always)] + #[must_use] + pub fn dcrs(&mut self) -> DcrsW { + DcrsW::new(self, 16) + } + #[doc = "Bits 17:19 - Inter-Frame Gap"] + #[inline(always)] + #[must_use] + pub fn ifg(&mut self) -> IfgW { + IfgW::new(self, 17) + } + #[doc = "Bit 20 - Jumbo Frame Enable"] + #[inline(always)] + #[must_use] + pub fn je(&mut self) -> JeW { + JeW::new(self, 20) + } + #[doc = "Bit 21 - Frame Burst Enable"] + #[inline(always)] + #[must_use] + pub fn be(&mut self) -> BeW { + BeW::new(self, 21) + } + #[doc = "Bit 22 - Jabber Disable"] + #[inline(always)] + #[must_use] + pub fn jd(&mut self) -> JdW { + JdW::new(self, 22) + } + #[doc = "Bit 23 - Watchdog disable"] + #[inline(always)] + #[must_use] + pub fn wd(&mut self) -> WdW { + WdW::new(self, 23) + } +} +#[doc = "Operation mode register for the MAC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacConfigSpec; +impl crate::RegisterSpec for MacConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_config::R`](R) reader structure"] +impl crate::Readable for MacConfigSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_config::W`](W) writer structure"] +impl crate::Writable for MacConfigSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAC_CONFIG to value 0"] +impl crate::Resettable for MacConfigSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mac_debug.rs b/va416xx/src/eth/mac_debug.rs new file mode 100644 index 0000000..b95f3d4 --- /dev/null +++ b/va416xx/src/eth/mac_debug.rs @@ -0,0 +1,99 @@ +#[doc = "Register `MAC_DEBUG` reader"] +pub type R = crate::R; +#[doc = "Field `RPESTS` reader - MAC GMII or MII Receive Protocol Engine Status"] +pub type RpestsR = crate::BitReader; +#[doc = "Field `RFCFCSTS` reader - MAC Receive Frame FIFO Controller Status"] +pub type RfcfcstsR = crate::FieldReader; +#[doc = "Field `RWCSTS` reader - MTL Rx FIFO Write Controller Active Status"] +pub type RwcstsR = crate::BitReader; +#[doc = "Field `RRCSTS` reader - MTL RxFIFO Read Controller State"] +pub type RrcstsR = crate::FieldReader; +#[doc = "Field `RXFSTS` reader - MTL RxFIFO Fill-Level Status"] +pub type RxfstsR = crate::FieldReader; +#[doc = "Field `TPESTS` reader - MAC GMII or MII Transmit Protocol Engine Status"] +pub type TpestsR = crate::BitReader; +#[doc = "Field `TFCSTS` reader - PAC Transmit Frame Controller Status"] +pub type TfcstsR = crate::FieldReader; +#[doc = "Field `TXPAUSED` reader - MAC Transmitter in Pause"] +pub type TxpausedR = crate::BitReader; +#[doc = "Field `TRCSTS` reader - MTL Tx FIFO Read Controller Status"] +pub type TrcstsR = crate::FieldReader; +#[doc = "Field `TWCSTS` reader - MTL Tx FIFO Write Controller Status"] +pub type TwcstsR = crate::BitReader; +#[doc = "Field `TXFSTS` reader - MTL Tx FIFO Not Empty Status"] +pub type TxfstsR = crate::BitReader; +#[doc = "Field `TXSTSFSTS` reader - MTL TxStatus FIFO Full Status"] +pub type TxstsfstsR = crate::BitReader; +impl R { + #[doc = "Bit 0 - MAC GMII or MII Receive Protocol Engine Status"] + #[inline(always)] + pub fn rpests(&self) -> RpestsR { + RpestsR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - MAC Receive Frame FIFO Controller Status"] + #[inline(always)] + pub fn rfcfcsts(&self) -> RfcfcstsR { + RfcfcstsR::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bit 4 - MTL Rx FIFO Write Controller Active Status"] + #[inline(always)] + pub fn rwcsts(&self) -> RwcstsR { + RwcstsR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - MTL RxFIFO Read Controller State"] + #[inline(always)] + pub fn rrcsts(&self) -> RrcstsR { + RrcstsR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bits 8:9 - MTL RxFIFO Fill-Level Status"] + #[inline(always)] + pub fn rxfsts(&self) -> RxfstsR { + RxfstsR::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 16 - MAC GMII or MII Transmit Protocol Engine Status"] + #[inline(always)] + pub fn tpests(&self) -> TpestsR { + TpestsR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 17:18 - PAC Transmit Frame Controller Status"] + #[inline(always)] + pub fn tfcsts(&self) -> TfcstsR { + TfcstsR::new(((self.bits >> 17) & 3) as u8) + } + #[doc = "Bit 19 - MAC Transmitter in Pause"] + #[inline(always)] + pub fn txpaused(&self) -> TxpausedR { + TxpausedR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:21 - MTL Tx FIFO Read Controller Status"] + #[inline(always)] + pub fn trcsts(&self) -> TrcstsR { + TrcstsR::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bit 22 - MTL Tx FIFO Write Controller Status"] + #[inline(always)] + pub fn twcsts(&self) -> TwcstsR { + TwcstsR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - MTL Tx FIFO Not Empty Status"] + #[inline(always)] + pub fn txfsts(&self) -> TxfstsR { + TxfstsR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - MTL TxStatus FIFO Full Status"] + #[inline(always)] + pub fn txstsfsts(&self) -> TxstsfstsR { + TxstsfstsR::new(((self.bits >> 25) & 1) != 0) + } +} +#[doc = "Gives the status of the various internal blocks for debugging\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_debug::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacDebugSpec; +impl crate::RegisterSpec for MacDebugSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_debug::R`](R) reader structure"] +impl crate::Readable for MacDebugSpec {} +#[doc = "`reset()` method sets MAC_DEBUG to value 0"] +impl crate::Resettable for MacDebugSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mac_flow_ctrl.rs b/va416xx/src/eth/mac_flow_ctrl.rs new file mode 100644 index 0000000..27f4bd2 --- /dev/null +++ b/va416xx/src/eth/mac_flow_ctrl.rs @@ -0,0 +1,130 @@ +#[doc = "Register `MAC_FLOW_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_FLOW_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `FCB_BPA` reader - Flow Control Busy or Backpressure Activate"] +pub type FcbBpaR = crate::BitReader; +#[doc = "Field `FCB_BPA` writer - Flow Control Busy or Backpressure Activate"] +pub type FcbBpaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TFE` reader - Transmit Flow Control Enable"] +pub type TfeR = crate::BitReader; +#[doc = "Field `TFE` writer - Transmit Flow Control Enable"] +pub type TfeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RFE` reader - Receive Flow Control Enable"] +pub type RfeR = crate::BitReader; +#[doc = "Field `RFE` writer - Receive Flow Control Enable"] +pub type RfeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UP` reader - Unicast Pause Frame Detect"] +pub type UpR = crate::BitReader; +#[doc = "Field `UP` writer - Unicast Pause Frame Detect"] +pub type UpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLT` reader - Pause Low Threshold"] +pub type PltR = crate::FieldReader; +#[doc = "Field `PLT` writer - Pause Low Threshold"] +pub type PltW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `DZPQ` reader - Disable Zero-Quanta Pause"] +pub type DzpqR = crate::BitReader; +#[doc = "Field `DZPQ` writer - Disable Zero-Quanta Pause"] +pub type DzpqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PT` reader - Pause time"] +pub type PtR = crate::FieldReader; +#[doc = "Field `PT` writer - Pause time"] +pub type PtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bit 0 - Flow Control Busy or Backpressure Activate"] + #[inline(always)] + pub fn fcb_bpa(&self) -> FcbBpaR { + FcbBpaR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Flow Control Enable"] + #[inline(always)] + pub fn tfe(&self) -> TfeR { + TfeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive Flow Control Enable"] + #[inline(always)] + pub fn rfe(&self) -> RfeR { + RfeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Unicast Pause Frame Detect"] + #[inline(always)] + pub fn up(&self) -> UpR { + UpR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Pause Low Threshold"] + #[inline(always)] + pub fn plt(&self) -> PltR { + PltR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 7 - Disable Zero-Quanta Pause"] + #[inline(always)] + pub fn dzpq(&self) -> DzpqR { + DzpqR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 16:31 - Pause time"] + #[inline(always)] + pub fn pt(&self) -> PtR { + PtR::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Flow Control Busy or Backpressure Activate"] + #[inline(always)] + #[must_use] + pub fn fcb_bpa(&mut self) -> FcbBpaW { + FcbBpaW::new(self, 0) + } + #[doc = "Bit 1 - Transmit Flow Control Enable"] + #[inline(always)] + #[must_use] + pub fn tfe(&mut self) -> TfeW { + TfeW::new(self, 1) + } + #[doc = "Bit 2 - Receive Flow Control Enable"] + #[inline(always)] + #[must_use] + pub fn rfe(&mut self) -> RfeW { + RfeW::new(self, 2) + } + #[doc = "Bit 3 - Unicast Pause Frame Detect"] + #[inline(always)] + #[must_use] + pub fn up(&mut self) -> UpW { + UpW::new(self, 3) + } + #[doc = "Bits 4:5 - Pause Low Threshold"] + #[inline(always)] + #[must_use] + pub fn plt(&mut self) -> PltW { + PltW::new(self, 4) + } + #[doc = "Bit 7 - Disable Zero-Quanta Pause"] + #[inline(always)] + #[must_use] + pub fn dzpq(&mut self) -> DzpqW { + DzpqW::new(self, 7) + } + #[doc = "Bits 16:31 - Pause time"] + #[inline(always)] + #[must_use] + pub fn pt(&mut self) -> PtW { + PtW::new(self, 16) + } +} +#[doc = "Controls the generation of control frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_flow_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_flow_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacFlowCtrlSpec; +impl crate::RegisterSpec for MacFlowCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_flow_ctrl::R`](R) reader structure"] +impl crate::Readable for MacFlowCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_flow_ctrl::W`](W) writer structure"] +impl crate::Writable for MacFlowCtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAC_FLOW_CTRL to value 0"] +impl crate::Resettable for MacFlowCtrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mac_frame_fltr.rs b/va416xx/src/eth/mac_frame_fltr.rs new file mode 100644 index 0000000..4ac7cd2 --- /dev/null +++ b/va416xx/src/eth/mac_frame_fltr.rs @@ -0,0 +1,220 @@ +#[doc = "Register `MAC_FRAME_FLTR` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_FRAME_FLTR` writer"] +pub type W = crate::W; +#[doc = "Field `PR` reader - Promiscuous Mode"] +pub type PrR = crate::BitReader; +#[doc = "Field `PR` writer - Promiscuous Mode"] +pub type PrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HUC` reader - Hash Unicast"] +pub type HucR = crate::BitReader; +#[doc = "Field `HUC` writer - Hash Unicast"] +pub type HucW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HMC` reader - Hash Multicast"] +pub type HmcR = crate::BitReader; +#[doc = "Field `HMC` writer - Hash Multicast"] +pub type HmcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DAIF` reader - DA Inverse Filtering"] +pub type DaifR = crate::BitReader; +#[doc = "Field `DAIF` writer - DA Inverse Filtering"] +pub type DaifW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PM` reader - Pass All Multicast"] +pub type PmR = crate::BitReader; +#[doc = "Field `PM` writer - Pass All Multicast"] +pub type PmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DBF` reader - Disable Broadcast Frames"] +pub type DbfR = crate::BitReader; +#[doc = "Field `DBF` writer - Disable Broadcast Frames"] +pub type DbfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PCF` reader - Pass Control Frames"] +pub type PcfR = crate::FieldReader; +#[doc = "Field `PCF` writer - Pass Control Frames"] +pub type PcfW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `SAIF` reader - SA Inverse Filtering"] +pub type SaifR = crate::BitReader; +#[doc = "Field `SAIF` writer - SA Inverse Filtering"] +pub type SaifW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SAF` reader - Source Address Filter Enable"] +pub type SafR = crate::BitReader; +#[doc = "Field `SAF` writer - Source Address Filter Enable"] +pub type SafW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `HDF` reader - Hash or Perfect Filter"] +pub type HdfR = crate::BitReader; +#[doc = "Field `HDF` writer - Hash or Perfect Filter"] +pub type HdfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VFTE` reader - VLAN Tag Filter Enable"] +pub type VfteR = crate::BitReader; +#[doc = "Field `VFTE` writer - VLAN Tag Filter Enable"] +pub type VfteW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DNTU` reader - Drop non TCP/UDP over IP Frames"] +pub type DntuR = crate::BitReader; +#[doc = "Field `DNTU` writer - Drop non TCP/UDP over IP Frames"] +pub type DntuW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RA` reader - Receive All"] +pub type RaR = crate::BitReader; +#[doc = "Field `RA` writer - Receive All"] +pub type RaW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Promiscuous Mode"] + #[inline(always)] + pub fn pr(&self) -> PrR { + PrR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Hash Unicast"] + #[inline(always)] + pub fn huc(&self) -> HucR { + HucR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Hash Multicast"] + #[inline(always)] + pub fn hmc(&self) -> HmcR { + HmcR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DA Inverse Filtering"] + #[inline(always)] + pub fn daif(&self) -> DaifR { + DaifR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pass All Multicast"] + #[inline(always)] + pub fn pm(&self) -> PmR { + PmR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Disable Broadcast Frames"] + #[inline(always)] + pub fn dbf(&self) -> DbfR { + DbfR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bits 6:7 - Pass Control Frames"] + #[inline(always)] + pub fn pcf(&self) -> PcfR { + PcfR::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - SA Inverse Filtering"] + #[inline(always)] + pub fn saif(&self) -> SaifR { + SaifR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Source Address Filter Enable"] + #[inline(always)] + pub fn saf(&self) -> SafR { + SafR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Hash or Perfect Filter"] + #[inline(always)] + pub fn hdf(&self) -> HdfR { + HdfR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 16 - VLAN Tag Filter Enable"] + #[inline(always)] + pub fn vfte(&self) -> VfteR { + VfteR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 21 - Drop non TCP/UDP over IP Frames"] + #[inline(always)] + pub fn dntu(&self) -> DntuR { + DntuR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 31 - Receive All"] + #[inline(always)] + pub fn ra(&self) -> RaR { + RaR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Promiscuous Mode"] + #[inline(always)] + #[must_use] + pub fn pr(&mut self) -> PrW { + PrW::new(self, 0) + } + #[doc = "Bit 1 - Hash Unicast"] + #[inline(always)] + #[must_use] + pub fn huc(&mut self) -> HucW { + HucW::new(self, 1) + } + #[doc = "Bit 2 - Hash Multicast"] + #[inline(always)] + #[must_use] + pub fn hmc(&mut self) -> HmcW { + HmcW::new(self, 2) + } + #[doc = "Bit 3 - DA Inverse Filtering"] + #[inline(always)] + #[must_use] + pub fn daif(&mut self) -> DaifW { + DaifW::new(self, 3) + } + #[doc = "Bit 4 - Pass All Multicast"] + #[inline(always)] + #[must_use] + pub fn pm(&mut self) -> PmW { + PmW::new(self, 4) + } + #[doc = "Bit 5 - Disable Broadcast Frames"] + #[inline(always)] + #[must_use] + pub fn dbf(&mut self) -> DbfW { + DbfW::new(self, 5) + } + #[doc = "Bits 6:7 - Pass Control Frames"] + #[inline(always)] + #[must_use] + pub fn pcf(&mut self) -> PcfW { + PcfW::new(self, 6) + } + #[doc = "Bit 8 - SA Inverse Filtering"] + #[inline(always)] + #[must_use] + pub fn saif(&mut self) -> SaifW { + SaifW::new(self, 8) + } + #[doc = "Bit 9 - Source Address Filter Enable"] + #[inline(always)] + #[must_use] + pub fn saf(&mut self) -> SafW { + SafW::new(self, 9) + } + #[doc = "Bit 10 - Hash or Perfect Filter"] + #[inline(always)] + #[must_use] + pub fn hdf(&mut self) -> HdfW { + HdfW::new(self, 10) + } + #[doc = "Bit 16 - VLAN Tag Filter Enable"] + #[inline(always)] + #[must_use] + pub fn vfte(&mut self) -> VfteW { + VfteW::new(self, 16) + } + #[doc = "Bit 21 - Drop non TCP/UDP over IP Frames"] + #[inline(always)] + #[must_use] + pub fn dntu(&mut self) -> DntuW { + DntuW::new(self, 21) + } + #[doc = "Bit 31 - Receive All"] + #[inline(always)] + #[must_use] + pub fn ra(&mut self) -> RaW { + RaW::new(self, 31) + } +} +#[doc = "Contains the frame filtering controls\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_frame_fltr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_frame_fltr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacFrameFltrSpec; +impl crate::RegisterSpec for MacFrameFltrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_frame_fltr::R`](R) reader structure"] +impl crate::Readable for MacFrameFltrSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_frame_fltr::W`](W) writer structure"] +impl crate::Writable for MacFrameFltrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAC_FRAME_FLTR to value 0"] +impl crate::Resettable for MacFrameFltrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mac_gmii_addr.rs b/va416xx/src/eth/mac_gmii_addr.rs new file mode 100644 index 0000000..3e2ad77 --- /dev/null +++ b/va416xx/src/eth/mac_gmii_addr.rs @@ -0,0 +1,100 @@ +#[doc = "Register `MAC_GMII_ADDR` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_GMII_ADDR` writer"] +pub type W = crate::W; +#[doc = "Field `GB` reader - GMII Busy"] +pub type GbR = crate::BitReader; +#[doc = "Field `GB` writer - GMII Busy"] +pub type GbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `GW` reader - GMII Write/Read"] +pub type GwR = crate::BitReader; +#[doc = "Field `GW` writer - GMII Write/Read"] +pub type GwW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CR` reader - CSR Clock Range"] +pub type CrR = crate::FieldReader; +#[doc = "Field `CR` writer - CSR Clock Range"] +pub type CrW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `GR` reader - GMII Register"] +pub type GrR = crate::FieldReader; +#[doc = "Field `GR` writer - GMII Register"] +pub type GrW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PA` reader - Physical Layer Address"] +pub type PaR = crate::FieldReader; +#[doc = "Field `PA` writer - Physical Layer Address"] +pub type PaW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bit 0 - GMII Busy"] + #[inline(always)] + pub fn gb(&self) -> GbR { + GbR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - GMII Write/Read"] + #[inline(always)] + pub fn gw(&self) -> GwR { + GwR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:5 - CSR Clock Range"] + #[inline(always)] + pub fn cr(&self) -> CrR { + CrR::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bits 6:10 - GMII Register"] + #[inline(always)] + pub fn gr(&self) -> GrR { + GrR::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bits 11:15 - Physical Layer Address"] + #[inline(always)] + pub fn pa(&self) -> PaR { + PaR::new(((self.bits >> 11) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bit 0 - GMII Busy"] + #[inline(always)] + #[must_use] + pub fn gb(&mut self) -> GbW { + GbW::new(self, 0) + } + #[doc = "Bit 1 - GMII Write/Read"] + #[inline(always)] + #[must_use] + pub fn gw(&mut self) -> GwW { + GwW::new(self, 1) + } + #[doc = "Bits 2:5 - CSR Clock Range"] + #[inline(always)] + #[must_use] + pub fn cr(&mut self) -> CrW { + CrW::new(self, 2) + } + #[doc = "Bits 6:10 - GMII Register"] + #[inline(always)] + #[must_use] + pub fn gr(&mut self) -> GrW { + GrW::new(self, 6) + } + #[doc = "Bits 11:15 - Physical Layer Address"] + #[inline(always)] + #[must_use] + pub fn pa(&mut self) -> PaW { + PaW::new(self, 11) + } +} +#[doc = "Controls the management cycles to an external PHY\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_gmii_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_gmii_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacGmiiAddrSpec; +impl crate::RegisterSpec for MacGmiiAddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_gmii_addr::R`](R) reader structure"] +impl crate::Readable for MacGmiiAddrSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_gmii_addr::W`](W) writer structure"] +impl crate::Writable for MacGmiiAddrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAC_GMII_ADDR to value 0"] +impl crate::Resettable for MacGmiiAddrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mac_gmii_data.rs b/va416xx/src/eth/mac_gmii_data.rs new file mode 100644 index 0000000..8fee346 --- /dev/null +++ b/va416xx/src/eth/mac_gmii_data.rs @@ -0,0 +1,40 @@ +#[doc = "Register `MAC_GMII_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_GMII_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `GD` reader - GMII Data"] +pub type GdR = crate::FieldReader; +#[doc = "Field `GD` writer - GMII Data"] +pub type GdW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - GMII Data"] + #[inline(always)] + pub fn gd(&self) -> GdR { + GdR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - GMII Data"] + #[inline(always)] + #[must_use] + pub fn gd(&mut self) -> GdW { + GdW::new(self, 0) + } +} +#[doc = "Contains the data to be written to or read from the PHY register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_gmii_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_gmii_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacGmiiDataSpec; +impl crate::RegisterSpec for MacGmiiDataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_gmii_data::R`](R) reader structure"] +impl crate::Readable for MacGmiiDataSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_gmii_data::W`](W) writer structure"] +impl crate::Writable for MacGmiiDataSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAC_GMII_DATA to value 0"] +impl crate::Resettable for MacGmiiDataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mac_intr_mask.rs b/va416xx/src/eth/mac_intr_mask.rs new file mode 100644 index 0000000..fd3b25b --- /dev/null +++ b/va416xx/src/eth/mac_intr_mask.rs @@ -0,0 +1,40 @@ +#[doc = "Register `MAC_INTR_MASK` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_INTR_MASK` writer"] +pub type W = crate::W; +#[doc = "Field `TSIM` reader - Timestamp Interrupt Mask"] +pub type TsimR = crate::BitReader; +#[doc = "Field `TSIM` writer - Timestamp Interrupt Mask"] +pub type TsimW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 9 - Timestamp Interrupt Mask"] + #[inline(always)] + pub fn tsim(&self) -> TsimR { + TsimR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 9 - Timestamp Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn tsim(&mut self) -> TsimW { + TsimW::new(self, 9) + } +} +#[doc = "Contains the masks for generating interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_intr_mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_intr_mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacIntrMaskSpec; +impl crate::RegisterSpec for MacIntrMaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_intr_mask::R`](R) reader structure"] +impl crate::Readable for MacIntrMaskSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_intr_mask::W`](W) writer structure"] +impl crate::Writable for MacIntrMaskSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAC_INTR_MASK to value 0"] +impl crate::Resettable for MacIntrMaskSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mac_intr_stat.rs b/va416xx/src/eth/mac_intr_stat.rs new file mode 100644 index 0000000..c5289b2 --- /dev/null +++ b/va416xx/src/eth/mac_intr_stat.rs @@ -0,0 +1,50 @@ +#[doc = "Register `MAC_INTR_STAT` reader"] +pub type R = crate::R; +#[doc = "Field `MMCIS` reader - MMC Interrupt Status"] +pub type MmcisR = crate::BitReader; +#[doc = "Field `MMCRXIS` reader - MMC Receive Interrupt Status"] +pub type MmcrxisR = crate::BitReader; +#[doc = "Field `MMCTXIS` reader - MMC Transmit Interrupt Status"] +pub type MmctxisR = crate::BitReader; +#[doc = "Field `MMCRXIPIS` reader - MMC Receive Checksum Offload Interrupt Status"] +pub type MmcrxipisR = crate::BitReader; +#[doc = "Field `TSIS` reader - Timestamp Interrupt Status"] +pub type TsisR = crate::BitReader; +impl R { + #[doc = "Bit 4 - MMC Interrupt Status"] + #[inline(always)] + pub fn mmcis(&self) -> MmcisR { + MmcisR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MMC Receive Interrupt Status"] + #[inline(always)] + pub fn mmcrxis(&self) -> MmcrxisR { + MmcrxisR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - MMC Transmit Interrupt Status"] + #[inline(always)] + pub fn mmctxis(&self) -> MmctxisR { + MmctxisR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - MMC Receive Checksum Offload Interrupt Status"] + #[inline(always)] + pub fn mmcrxipis(&self) -> MmcrxipisR { + MmcrxipisR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Timestamp Interrupt Status"] + #[inline(always)] + pub fn tsis(&self) -> TsisR { + TsisR::new(((self.bits >> 9) & 1) != 0) + } +} +#[doc = "Contains the interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_intr_stat::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacIntrStatSpec; +impl crate::RegisterSpec for MacIntrStatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_intr_stat::R`](R) reader structure"] +impl crate::Readable for MacIntrStatSpec {} +#[doc = "`reset()` method sets MAC_INTR_STAT to value 0"] +impl crate::Resettable for MacIntrStatSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mac_vlan_tag.rs b/va416xx/src/eth/mac_vlan_tag.rs new file mode 100644 index 0000000..ffddabc --- /dev/null +++ b/va416xx/src/eth/mac_vlan_tag.rs @@ -0,0 +1,85 @@ +#[doc = "Register `MAC_VLAN_TAG` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_VLAN_TAG` writer"] +pub type W = crate::W; +#[doc = "Field `VL` reader - VLAN Tag identifier for Receive Frames"] +pub type VlR = crate::FieldReader; +#[doc = "Field `VL` writer - VLAN Tag identifier for Receive Frames"] +pub type VlW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `ETV` reader - Enable 12-Bit VLAN Tag Comparison"] +pub type EtvR = crate::BitReader; +#[doc = "Field `ETV` writer - Enable 12-Bit VLAN Tag Comparison"] +pub type EtvW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VTIM` reader - VLAN Tag Inverse Match Enable"] +pub type VtimR = crate::BitReader; +#[doc = "Field `VTIM` writer - VLAN Tag Inverse Match Enable"] +pub type VtimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ESVL` reader - Enable S-VLAN"] +pub type EsvlR = crate::BitReader; +#[doc = "Field `ESVL` writer - Enable S-VLAN"] +pub type EsvlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - VLAN Tag identifier for Receive Frames"] + #[inline(always)] + pub fn vl(&self) -> VlR { + VlR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - Enable 12-Bit VLAN Tag Comparison"] + #[inline(always)] + pub fn etv(&self) -> EtvR { + EtvR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - VLAN Tag Inverse Match Enable"] + #[inline(always)] + pub fn vtim(&self) -> VtimR { + VtimR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enable S-VLAN"] + #[inline(always)] + pub fn esvl(&self) -> EsvlR { + EsvlR::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - VLAN Tag identifier for Receive Frames"] + #[inline(always)] + #[must_use] + pub fn vl(&mut self) -> VlW { + VlW::new(self, 0) + } + #[doc = "Bit 16 - Enable 12-Bit VLAN Tag Comparison"] + #[inline(always)] + #[must_use] + pub fn etv(&mut self) -> EtvW { + EtvW::new(self, 16) + } + #[doc = "Bit 17 - VLAN Tag Inverse Match Enable"] + #[inline(always)] + #[must_use] + pub fn vtim(&mut self) -> VtimW { + VtimW::new(self, 17) + } + #[doc = "Bit 18 - Enable S-VLAN"] + #[inline(always)] + #[must_use] + pub fn esvl(&mut self) -> EsvlW { + EsvlW::new(self, 18) + } +} +#[doc = "Identifies IEEE 802.1Q VLAN type frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_vlan_tag::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_vlan_tag::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacVlanTagSpec; +impl crate::RegisterSpec for MacVlanTagSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_vlan_tag::R`](R) reader structure"] +impl crate::Readable for MacVlanTagSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_vlan_tag::W`](W) writer structure"] +impl crate::Writable for MacVlanTagSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAC_VLAN_TAG to value 0"] +impl crate::Resettable for MacVlanTagSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mac_wdog_to.rs b/va416xx/src/eth/mac_wdog_to.rs new file mode 100644 index 0000000..a0ba4b0 --- /dev/null +++ b/va416xx/src/eth/mac_wdog_to.rs @@ -0,0 +1,55 @@ +#[doc = "Register `MAC_WDOG_TO` reader"] +pub type R = crate::R; +#[doc = "Register `MAC_WDOG_TO` writer"] +pub type W = crate::W; +#[doc = "Field `WTO` reader - Watchdog Timeout"] +pub type WtoR = crate::FieldReader; +#[doc = "Field `WTO` writer - Watchdog Timeout"] +pub type WtoW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `PWE` reader - Programmable Watchdog Enable"] +pub type PweR = crate::BitReader; +#[doc = "Field `PWE` writer - Programmable Watchdog Enable"] +pub type PweW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:13 - Watchdog Timeout"] + #[inline(always)] + pub fn wto(&self) -> WtoR { + WtoR::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bit 16 - Programmable Watchdog Enable"] + #[inline(always)] + pub fn pwe(&self) -> PweR { + PweR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:13 - Watchdog Timeout"] + #[inline(always)] + #[must_use] + pub fn wto(&mut self) -> WtoW { + WtoW::new(self, 0) + } + #[doc = "Bit 16 - Programmable Watchdog Enable"] + #[inline(always)] + #[must_use] + pub fn pwe(&mut self) -> PweW { + PweW::new(self, 16) + } +} +#[doc = "Controls the watchdog time-out for received frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_wdog_to::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_wdog_to::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MacWdogToSpec; +impl crate::RegisterSpec for MacWdogToSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mac_wdog_to::R`](R) reader structure"] +impl crate::Readable for MacWdogToSpec {} +#[doc = "`write(|w| ..)` method takes [`mac_wdog_to::W`](W) writer structure"] +impl crate::Writable for MacWdogToSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MAC_WDOG_TO to value 0"] +impl crate::Resettable for MacWdogToSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mmc_cntrl.rs b/va416xx/src/eth/mmc_cntrl.rs new file mode 100644 index 0000000..7d4c70a --- /dev/null +++ b/va416xx/src/eth/mmc_cntrl.rs @@ -0,0 +1,130 @@ +#[doc = "Register `MMC_CNTRL` reader"] +pub type R = crate::R; +#[doc = "Register `MMC_CNTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CNTRST` reader - Counters Reset"] +pub type CntrstR = crate::BitReader; +#[doc = "Field `CNTRST` writer - Counters Reset"] +pub type CntrstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNTSTOPRO` reader - Counter Stop Rollover"] +pub type CntstoproR = crate::BitReader; +#[doc = "Field `CNTSTOPRO` writer - Counter Stop Rollover"] +pub type CntstoproW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RSTONRD` reader - Reset on Read"] +pub type RstonrdR = crate::BitReader; +#[doc = "Field `RSTONRD` writer - Reset on Read"] +pub type RstonrdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNTFREEZ` reader - MMC Counter Freeze"] +pub type CntfreezR = crate::BitReader; +#[doc = "Field `CNTFREEZ` writer - MMC Counter Freeze"] +pub type CntfreezW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNTPRST` reader - Counters Preset"] +pub type CntprstR = crate::BitReader; +#[doc = "Field `CNTPRST` writer - Counters Preset"] +pub type CntprstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CNTPRSTLVL` reader - Full-Half Preset"] +pub type CntprstlvlR = crate::BitReader; +#[doc = "Field `CNTPRSTLVL` writer - Full-Half Preset"] +pub type CntprstlvlW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UCDBC` reader - Update MMC Counters for Dropped Broadcast Frames"] +pub type UcdbcR = crate::BitReader; +#[doc = "Field `UCDBC` writer - Update MMC Counters for Dropped Broadcast Frames"] +pub type UcdbcW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Counters Reset"] + #[inline(always)] + pub fn cntrst(&self) -> CntrstR { + CntrstR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Counter Stop Rollover"] + #[inline(always)] + pub fn cntstopro(&self) -> CntstoproR { + CntstoproR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Reset on Read"] + #[inline(always)] + pub fn rstonrd(&self) -> RstonrdR { + RstonrdR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - MMC Counter Freeze"] + #[inline(always)] + pub fn cntfreez(&self) -> CntfreezR { + CntfreezR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Counters Preset"] + #[inline(always)] + pub fn cntprst(&self) -> CntprstR { + CntprstR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Full-Half Preset"] + #[inline(always)] + pub fn cntprstlvl(&self) -> CntprstlvlR { + CntprstlvlR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Update MMC Counters for Dropped Broadcast Frames"] + #[inline(always)] + pub fn ucdbc(&self) -> UcdbcR { + UcdbcR::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counters Reset"] + #[inline(always)] + #[must_use] + pub fn cntrst(&mut self) -> CntrstW { + CntrstW::new(self, 0) + } + #[doc = "Bit 1 - Counter Stop Rollover"] + #[inline(always)] + #[must_use] + pub fn cntstopro(&mut self) -> CntstoproW { + CntstoproW::new(self, 1) + } + #[doc = "Bit 2 - Reset on Read"] + #[inline(always)] + #[must_use] + pub fn rstonrd(&mut self) -> RstonrdW { + RstonrdW::new(self, 2) + } + #[doc = "Bit 3 - MMC Counter Freeze"] + #[inline(always)] + #[must_use] + pub fn cntfreez(&mut self) -> CntfreezW { + CntfreezW::new(self, 3) + } + #[doc = "Bit 4 - Counters Preset"] + #[inline(always)] + #[must_use] + pub fn cntprst(&mut self) -> CntprstW { + CntprstW::new(self, 4) + } + #[doc = "Bit 5 - Full-Half Preset"] + #[inline(always)] + #[must_use] + pub fn cntprstlvl(&mut self) -> CntprstlvlW { + CntprstlvlW::new(self, 5) + } + #[doc = "Bit 8 - Update MMC Counters for Dropped Broadcast Frames"] + #[inline(always)] + #[must_use] + pub fn ucdbc(&mut self) -> UcdbcW { + UcdbcW::new(self, 8) + } +} +#[doc = "MMC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmc_cntrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmc_cntrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmcCntrlSpec; +impl crate::RegisterSpec for MmcCntrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmc_cntrl::R`](R) reader structure"] +impl crate::Readable for MmcCntrlSpec {} +#[doc = "`write(|w| ..)` method takes [`mmc_cntrl::W`](W) writer structure"] +impl crate::Writable for MmcCntrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MMC_CNTRL to value 0"] +impl crate::Resettable for MmcCntrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mmc_intr_mask_rx.rs b/va416xx/src/eth/mmc_intr_mask_rx.rs new file mode 100644 index 0000000..6e771f2 --- /dev/null +++ b/va416xx/src/eth/mmc_intr_mask_rx.rs @@ -0,0 +1,415 @@ +#[doc = "Register `MMC_INTR_MASK_RX` reader"] +pub type R = crate::R; +#[doc = "Register `MMC_INTR_MASK_RX` writer"] +pub type W = crate::W; +#[doc = "Field `RXGBFRMIM` reader - MMC Receive Good Bad Frame Counter Interrupt Mask"] +pub type RxgbfrmimR = crate::BitReader; +#[doc = "Field `RXGBFRMIM` writer - MMC Receive Good Bad Frame Counter Interrupt Mask"] +pub type RxgbfrmimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXGBOCTIM` reader - MMC Receive Good Bad Octet Counter Interrupt Mask."] +pub type RxgboctimR = crate::BitReader; +#[doc = "Field `RXGBOCTIM` writer - MMC Receive Good Bad Octet Counter Interrupt Mask."] +pub type RxgboctimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXGOCTIM` reader - MMC Receive Good Octet Counter Interrupt Mask"] +pub type RxgoctimR = crate::BitReader; +#[doc = "Field `RXGOCTIM` writer - MMC Receive Good Octet Counter Interrupt Mask"] +pub type RxgoctimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXBCGFIM` reader - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] +pub type RxbcgfimR = crate::BitReader; +#[doc = "Field `RXBCGFIM` writer - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] +pub type RxbcgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXMCGFIM` reader - MMC Receive Multicast Good Frame Counter Interrupt Mask"] +pub type RxmcgfimR = crate::BitReader; +#[doc = "Field `RXMCGFIM` writer - MMC Receive Multicast Good Frame Counter Interrupt Mask"] +pub type RxmcgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXCRCERFIM` reader - MMC Receive CRC Error Frame Counter Interrupt Mask"] +pub type RxcrcerfimR = crate::BitReader; +#[doc = "Field `RXCRCERFIM` writer - MMC Receive CRC Error Frame Counter Interrupt Mask"] +pub type RxcrcerfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXALGNERFIM` reader - MMC Receive Alignment Error Frame Counter Interrupt Mask"] +pub type RxalgnerfimR = crate::BitReader; +#[doc = "Field `RXALGNERFIM` writer - MMC Receive Alignment Error Frame Counter Interrupt Mask"] +pub type RxalgnerfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXRUNTFIM` reader - MMC Receive Runt Frame Counter Interrupt Mask"] +pub type RxruntfimR = crate::BitReader; +#[doc = "Field `RXRUNTFIM` writer - MMC Receive Runt Frame Counter Interrupt Mask"] +pub type RxruntfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXJABERFIM` reader - MMC Receive Jabber Error Frame Counter Interrupt Mask"] +pub type RxjaberfimR = crate::BitReader; +#[doc = "Field `RXJABERFIM` writer - MMC Receive Jabber Error Frame Counter Interrupt Mask"] +pub type RxjaberfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXUSIZEGFIM` reader - MMC Receive Undersize Good Frame Counter Interrupt Mask"] +pub type RxusizegfimR = crate::BitReader; +#[doc = "Field `RXUSIZEGFIM` writer - MMC Receive Undersize Good Frame Counter Interrupt Mask"] +pub type RxusizegfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXOSIZEGFIM` reader - MMC Receive Oversize Good Frame Counter Interrupt Mask"] +pub type RxosizegfimR = crate::BitReader; +#[doc = "Field `RXOSIZEGFIM` writer - MMC Receive Oversize Good Frame Counter Interrupt Mask"] +pub type RxosizegfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX64OCTGBFIM` reader - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx64octgbfimR = crate::BitReader; +#[doc = "Field `RX64OCTGBFIM` writer - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx64octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX65T127OCTGBFIM` reader - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx65t127octgbfimR = crate::BitReader; +#[doc = "Field `RX65T127OCTGBFIM` writer - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx65t127octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX128T255OCTGBFIM` reader - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx128t255octgbfimR = crate::BitReader; +#[doc = "Field `RX128T255OCTGBFIM` writer - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx128t255octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX256T511OCTGBFIM` reader - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx256t511octgbfimR = crate::BitReader; +#[doc = "Field `RX256T511OCTGBFIM` writer - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx256t511octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX512T1023OCTGBFIM` reader - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx512t1023octgbfimR = crate::BitReader; +#[doc = "Field `RX512T1023OCTGBFIM` writer - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Rx512t1023octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX1024TMAXOCTGBFIM` reader - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] +pub type Rx1024tmaxoctgbfimR = crate::BitReader; +#[doc = "Field `RX1024TMAXOCTGBFIM` writer - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] +pub type Rx1024tmaxoctgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXUCGFIM` reader - MMC Receive Unicast Good Frame Counter Interrupt Mask"] +pub type RxucgfimR = crate::BitReader; +#[doc = "Field `RXUCGFIM` writer - MMC Receive Unicast Good Frame Counter Interrupt Mask"] +pub type RxucgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXLENERFIM` reader - MMC Receive Length Error Frame Counter Interrupt Mask"] +pub type RxlenerfimR = crate::BitReader; +#[doc = "Field `RXLENERFIM` writer - MMC Receive Length Error Frame Counter Interrupt Mask"] +pub type RxlenerfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXORANGEFIM` reader - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] +pub type RxorangefimR = crate::BitReader; +#[doc = "Field `RXORANGEFIM` writer - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] +pub type RxorangefimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXPAUSFIM` reader - MMC Receive Pause Frame Counter Interrupt Mask"] +pub type RxpausfimR = crate::BitReader; +#[doc = "Field `RXPAUSFIM` writer - MMC Receive Pause Frame Counter Interrupt Mask"] +pub type RxpausfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFOVFIM` reader - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] +pub type RxfovfimR = crate::BitReader; +#[doc = "Field `RXFOVFIM` writer - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] +pub type RxfovfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXVLANGBFIM` reader - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] +pub type RxvlangbfimR = crate::BitReader; +#[doc = "Field `RXVLANGBFIM` writer - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] +pub type RxvlangbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXWDOGFIM` reader - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] +pub type RxwdogfimR = crate::BitReader; +#[doc = "Field `RXWDOGFIM` writer - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] +pub type RxwdogfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXRCVERRFIM` reader - MMC Receive Error Frame Counter Interrupt Mask"] +pub type RxrcverrfimR = crate::BitReader; +#[doc = "Field `RXRCVERRFIM` writer - MMC Receive Error Frame Counter Interrupt Mask"] +pub type RxrcverrfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXCTRLFIM` reader - MMC Receive Control Frame Counter Interrupt Mask"] +pub type RxctrlfimR = crate::BitReader; +#[doc = "Field `RXCTRLFIM` writer - MMC Receive Control Frame Counter Interrupt Mask"] +pub type RxctrlfimW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxgbfrmim(&self) -> RxgbfrmimR { + RxgbfrmimR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Mask."] + #[inline(always)] + pub fn rxgboctim(&self) -> RxgboctimR { + RxgboctimR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn rxgoctim(&self) -> RxgoctimR { + RxgoctimR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxbcgfim(&self) -> RxbcgfimR { + RxbcgfimR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxmcgfim(&self) -> RxmcgfimR { + RxmcgfimR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxcrcerfim(&self) -> RxcrcerfimR { + RxcrcerfimR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxalgnerfim(&self) -> RxalgnerfimR { + RxalgnerfimR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxruntfim(&self) -> RxruntfimR { + RxruntfimR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxjaberfim(&self) -> RxjaberfimR { + RxjaberfimR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxusizegfim(&self) -> RxusizegfimR { + RxusizegfimR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxosizegfim(&self) -> RxosizegfimR { + RxosizegfimR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx64octgbfim(&self) -> Rx64octgbfimR { + Rx64octgbfimR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx65t127octgbfim(&self) -> Rx65t127octgbfimR { + Rx65t127octgbfimR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx128t255octgbfim(&self) -> Rx128t255octgbfimR { + Rx128t255octgbfimR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx256t511octgbfim(&self) -> Rx256t511octgbfimR { + Rx256t511octgbfimR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rx512t1023octgbfim(&self) -> Rx512t1023octgbfimR { + Rx512t1023octgbfimR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] + #[inline(always)] + pub fn rx1024tmaxoctgbfim(&self) -> Rx1024tmaxoctgbfimR { + Rx1024tmaxoctgbfimR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxucgfim(&self) -> RxucgfimR { + RxucgfimR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxlenerfim(&self) -> RxlenerfimR { + RxlenerfimR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxorangefim(&self) -> RxorangefimR { + RxorangefimR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxpausfim(&self) -> RxpausfimR { + RxpausfimR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxfovfim(&self) -> RxfovfimR { + RxfovfimR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxvlangbfim(&self) -> RxvlangbfimR { + RxvlangbfimR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxwdogfim(&self) -> RxwdogfimR { + RxwdogfimR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxrcverrfim(&self) -> RxrcverrfimR { + RxrcverrfimR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn rxctrlfim(&self) -> RxctrlfimR { + RxctrlfimR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxgbfrmim(&mut self) -> RxgbfrmimW { + RxgbfrmimW::new(self, 0) + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Mask."] + #[inline(always)] + #[must_use] + pub fn rxgboctim(&mut self) -> RxgboctimW { + RxgboctimW::new(self, 1) + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxgoctim(&mut self) -> RxgoctimW { + RxgoctimW::new(self, 2) + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxbcgfim(&mut self) -> RxbcgfimW { + RxbcgfimW::new(self, 3) + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxmcgfim(&mut self) -> RxmcgfimW { + RxmcgfimW::new(self, 4) + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxcrcerfim(&mut self) -> RxcrcerfimW { + RxcrcerfimW::new(self, 5) + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxalgnerfim(&mut self) -> RxalgnerfimW { + RxalgnerfimW::new(self, 6) + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxruntfim(&mut self) -> RxruntfimW { + RxruntfimW::new(self, 7) + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxjaberfim(&mut self) -> RxjaberfimW { + RxjaberfimW::new(self, 8) + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxusizegfim(&mut self) -> RxusizegfimW { + RxusizegfimW::new(self, 9) + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxosizegfim(&mut self) -> RxosizegfimW { + RxosizegfimW::new(self, 10) + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rx64octgbfim(&mut self) -> Rx64octgbfimW { + Rx64octgbfimW::new(self, 11) + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rx65t127octgbfim(&mut self) -> Rx65t127octgbfimW { + Rx65t127octgbfimW::new(self, 12) + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rx128t255octgbfim(&mut self) -> Rx128t255octgbfimW { + Rx128t255octgbfimW::new(self, 13) + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rx256t511octgbfim(&mut self) -> Rx256t511octgbfimW { + Rx256t511octgbfimW::new(self, 14) + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rx512t1023octgbfim(&mut self) -> Rx512t1023octgbfimW { + Rx512t1023octgbfimW::new(self, 15) + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask."] + #[inline(always)] + #[must_use] + pub fn rx1024tmaxoctgbfim(&mut self) -> Rx1024tmaxoctgbfimW { + Rx1024tmaxoctgbfimW::new(self, 16) + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxucgfim(&mut self) -> RxucgfimW { + RxucgfimW::new(self, 17) + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxlenerfim(&mut self) -> RxlenerfimW { + RxlenerfimW::new(self, 18) + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxorangefim(&mut self) -> RxorangefimW { + RxorangefimW::new(self, 19) + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxpausfim(&mut self) -> RxpausfimW { + RxpausfimW::new(self, 20) + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxfovfim(&mut self) -> RxfovfimW { + RxfovfimW::new(self, 21) + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxvlangbfim(&mut self) -> RxvlangbfimW { + RxvlangbfimW::new(self, 22) + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxwdogfim(&mut self) -> RxwdogfimW { + RxwdogfimW::new(self, 23) + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxrcverrfim(&mut self) -> RxrcverrfimW { + RxrcverrfimW::new(self, 24) + } + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn rxctrlfim(&mut self) -> RxctrlfimW { + RxctrlfimW::new(self, 25) + } +} +#[doc = "MMC Receive Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmc_intr_mask_rx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmc_intr_mask_rx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmcIntrMaskRxSpec; +impl crate::RegisterSpec for MmcIntrMaskRxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmc_intr_mask_rx::R`](R) reader structure"] +impl crate::Readable for MmcIntrMaskRxSpec {} +#[doc = "`write(|w| ..)` method takes [`mmc_intr_mask_rx::W`](W) writer structure"] +impl crate::Writable for MmcIntrMaskRxSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MMC_INTR_MASK_RX to value 0"] +impl crate::Resettable for MmcIntrMaskRxSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mmc_intr_mask_tx.rs b/va416xx/src/eth/mmc_intr_mask_tx.rs new file mode 100644 index 0000000..4867da8 --- /dev/null +++ b/va416xx/src/eth/mmc_intr_mask_tx.rs @@ -0,0 +1,415 @@ +#[doc = "Register `MMC_INTR_MASK_TX` reader"] +pub type R = crate::R; +#[doc = "Register `MMC_INTR_MASK_TX` writer"] +pub type W = crate::W; +#[doc = "Field `TXGBOCTIM` reader - MMC Transmit Good Bad Octet Counter Interrupt Mask"] +pub type TxgboctimR = crate::BitReader; +#[doc = "Field `TXGBOCTIM` writer - MMC Transmit Good Bad Octet Counter Interrupt Mask"] +pub type TxgboctimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGBFRMIM` reader - MMC Transmit Good Bad Frame Counter Interrupt Mask"] +pub type TxgbfrmimR = crate::BitReader; +#[doc = "Field `TXGBFRMIM` writer - MMC Transmit Good Bad Frame Counter Interrupt Mask"] +pub type TxgbfrmimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXBCGFIM` reader - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] +pub type TxbcgfimR = crate::BitReader; +#[doc = "Field `TXBCGFIM` writer - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] +pub type TxbcgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCGFIM` reader - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] +pub type TxmcgfimR = crate::BitReader; +#[doc = "Field `TXMCGFIM` writer - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] +pub type TxmcgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX64OCTGBFIM` reader - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx64octgbfimR = crate::BitReader; +#[doc = "Field `TX64OCTGBFIM` writer - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx64octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX65T127OCTGBFIM` reader - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx65t127octgbfimR = crate::BitReader; +#[doc = "Field `TX65T127OCTGBFIM` writer - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx65t127octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX128T255OCTGBFIM` reader - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx128t255octgbfimR = crate::BitReader; +#[doc = "Field `TX128T255OCTGBFIM` writer - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx128t255octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX256T511OCTGBFIM` reader - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx256t511octgbfimR = crate::BitReader; +#[doc = "Field `TX256T511OCTGBFIM` writer - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx256t511octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX512T1023OCTGBFIM` reader - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx512t1023octgbfimR = crate::BitReader; +#[doc = "Field `TX512T1023OCTGBFIM` writer - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx512t1023octgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX1024TMAXOCTGBFIM` reader - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx1024tmaxoctgbfimR = crate::BitReader; +#[doc = "Field `TX1024TMAXOCTGBFIM` writer - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] +pub type Tx1024tmaxoctgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUCGBFIM` reader - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] +pub type TxucgbfimR = crate::BitReader; +#[doc = "Field `TXUCGBFIM` writer - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] +pub type TxucgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCGBFIM` reader - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] +pub type TxmcgbfimR = crate::BitReader; +#[doc = "Field `TXMCGBFIM` writer - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] +pub type TxmcgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXBCGBFIM` reader - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] +pub type TxbcgbfimR = crate::BitReader; +#[doc = "Field `TXBCGBFIM` writer - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] +pub type TxbcgbfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUFLOWERFIM` reader - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] +pub type TxuflowerfimR = crate::BitReader; +#[doc = "Field `TXUFLOWERFIM` writer - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] +pub type TxuflowerfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXSCOLGFIM` reader - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] +pub type TxscolgfimR = crate::BitReader; +#[doc = "Field `TXSCOLGFIM` writer - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] +pub type TxscolgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCOLGFIM` reader - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] +pub type TxmcolgfimR = crate::BitReader; +#[doc = "Field `TXMCOLGFIM` writer - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] +pub type TxmcolgfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXDEFFIM` reader - MMC Transmit Deferred Frame Counter Interrupt Mask"] +pub type TxdeffimR = crate::BitReader; +#[doc = "Field `TXDEFFIM` writer - MMC Transmit Deferred Frame Counter Interrupt Mask"] +pub type TxdeffimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXLATCOLFIM` reader - MMC Transmit Late Collision Frame Counter Interrupt Mask"] +pub type TxlatcolfimR = crate::BitReader; +#[doc = "Field `TXLATCOLFIM` writer - MMC Transmit Late Collision Frame Counter Interrupt Mask"] +pub type TxlatcolfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEXCOLFIM` reader - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] +pub type TxexcolfimR = crate::BitReader; +#[doc = "Field `TXEXCOLFIM` writer - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] +pub type TxexcolfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXCARERFIM` reader - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] +pub type TxcarerfimR = crate::BitReader; +#[doc = "Field `TXCARERFIM` writer - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] +pub type TxcarerfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGOCTIM` reader - MMC Transmit Good Octet Counter Interrupt Mask"] +pub type TxgoctimR = crate::BitReader; +#[doc = "Field `TXGOCTIM` writer - MMC Transmit Good Octet Counter Interrupt Mask"] +pub type TxgoctimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGFRMIM` reader - MMC Transmit Good Frame Counter Interrupt Mask"] +pub type TxgfrmimR = crate::BitReader; +#[doc = "Field `TXGFRMIM` writer - MMC Transmit Good Frame Counter Interrupt Mask"] +pub type TxgfrmimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEXDEFFIM` reader - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] +pub type TxexdeffimR = crate::BitReader; +#[doc = "Field `TXEXDEFFIM` writer - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] +pub type TxexdeffimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXPAUSFIM` reader - MMC Transmit Pause Frame Counter Interrupt Mask"] +pub type TxpausfimR = crate::BitReader; +#[doc = "Field `TXPAUSFIM` writer - MMC Transmit Pause Frame Counter Interrupt Mask"] +pub type TxpausfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXVLANGFIM` reader - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] +pub type TxvlangfimR = crate::BitReader; +#[doc = "Field `TXVLANGFIM` writer - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] +pub type TxvlangfimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXOSIZEGFIM` reader - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] +pub type TxosizegfimR = crate::BitReader; +#[doc = "Field `TXOSIZEGFIM` writer - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] +pub type TxosizegfimW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn txgboctim(&self) -> TxgboctimR { + TxgboctimR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txgbfrmim(&self) -> TxgbfrmimR { + TxgbfrmimR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txbcgfim(&self) -> TxbcgfimR { + TxbcgfimR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcgfim(&self) -> TxmcgfimR { + TxmcgfimR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx64octgbfim(&self) -> Tx64octgbfimR { + Tx64octgbfimR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx65t127octgbfim(&self) -> Tx65t127octgbfimR { + Tx65t127octgbfimR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx128t255octgbfim(&self) -> Tx128t255octgbfimR { + Tx128t255octgbfimR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx256t511octgbfim(&self) -> Tx256t511octgbfimR { + Tx256t511octgbfimR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx512t1023octgbfim(&self) -> Tx512t1023octgbfimR { + Tx512t1023octgbfimR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn tx1024tmaxoctgbfim(&self) -> Tx1024tmaxoctgbfimR { + Tx1024tmaxoctgbfimR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txucgbfim(&self) -> TxucgbfimR { + TxucgbfimR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcgbfim(&self) -> TxmcgbfimR { + TxmcgbfimR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txbcgbfim(&self) -> TxbcgbfimR { + TxbcgbfimR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txuflowerfim(&self) -> TxuflowerfimR { + TxuflowerfimR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txscolgfim(&self) -> TxscolgfimR { + TxscolgfimR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txmcolgfim(&self) -> TxmcolgfimR { + TxmcolgfimR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txdeffim(&self) -> TxdeffimR { + TxdeffimR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txlatcolfim(&self) -> TxlatcolfimR { + TxlatcolfimR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txexcolfim(&self) -> TxexcolfimR { + TxexcolfimR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txcarerfim(&self) -> TxcarerfimR { + TxcarerfimR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Mask"] + #[inline(always)] + pub fn txgoctim(&self) -> TxgoctimR { + TxgoctimR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txgfrmim(&self) -> TxgfrmimR { + TxgfrmimR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txexdeffim(&self) -> TxexdeffimR { + TxexdeffimR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txpausfim(&self) -> TxpausfimR { + TxpausfimR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txvlangfim(&self) -> TxvlangfimR { + TxvlangfimR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + pub fn txosizegfim(&self) -> TxosizegfimR { + TxosizegfimR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txgboctim(&mut self) -> TxgboctimW { + TxgboctimW::new(self, 0) + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txgbfrmim(&mut self) -> TxgbfrmimW { + TxgbfrmimW::new(self, 1) + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txbcgfim(&mut self) -> TxbcgfimW { + TxbcgfimW::new(self, 2) + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txmcgfim(&mut self) -> TxmcgfimW { + TxmcgfimW::new(self, 3) + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn tx64octgbfim(&mut self) -> Tx64octgbfimW { + Tx64octgbfimW::new(self, 4) + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn tx65t127octgbfim(&mut self) -> Tx65t127octgbfimW { + Tx65t127octgbfimW::new(self, 5) + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn tx128t255octgbfim(&mut self) -> Tx128t255octgbfimW { + Tx128t255octgbfimW::new(self, 6) + } + #[doc = "Bit 7 - MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn tx256t511octgbfim(&mut self) -> Tx256t511octgbfimW { + Tx256t511octgbfimW::new(self, 7) + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn tx512t1023octgbfim(&mut self) -> Tx512t1023octgbfimW { + Tx512t1023octgbfimW::new(self, 8) + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn tx1024tmaxoctgbfim(&mut self) -> Tx1024tmaxoctgbfimW { + Tx1024tmaxoctgbfimW::new(self, 9) + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txucgbfim(&mut self) -> TxucgbfimW { + TxucgbfimW::new(self, 10) + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txmcgbfim(&mut self) -> TxmcgbfimW { + TxmcgbfimW::new(self, 11) + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txbcgbfim(&mut self) -> TxbcgbfimW { + TxbcgbfimW::new(self, 12) + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txuflowerfim(&mut self) -> TxuflowerfimW { + TxuflowerfimW::new(self, 13) + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txscolgfim(&mut self) -> TxscolgfimW { + TxscolgfimW::new(self, 14) + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txmcolgfim(&mut self) -> TxmcolgfimW { + TxmcolgfimW::new(self, 15) + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txdeffim(&mut self) -> TxdeffimW { + TxdeffimW::new(self, 16) + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txlatcolfim(&mut self) -> TxlatcolfimW { + TxlatcolfimW::new(self, 17) + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txexcolfim(&mut self) -> TxexcolfimW { + TxexcolfimW::new(self, 18) + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txcarerfim(&mut self) -> TxcarerfimW { + TxcarerfimW::new(self, 19) + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txgoctim(&mut self) -> TxgoctimW { + TxgoctimW::new(self, 20) + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txgfrmim(&mut self) -> TxgfrmimW { + TxgfrmimW::new(self, 21) + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txexdeffim(&mut self) -> TxexdeffimW { + TxexdeffimW::new(self, 22) + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txpausfim(&mut self) -> TxpausfimW { + TxpausfimW::new(self, 23) + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txvlangfim(&mut self) -> TxvlangfimW { + TxvlangfimW::new(self, 24) + } + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Mask"] + #[inline(always)] + #[must_use] + pub fn txosizegfim(&mut self) -> TxosizegfimW { + TxosizegfimW::new(self, 25) + } +} +#[doc = "MMC Transmit Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmc_intr_mask_tx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmc_intr_mask_tx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmcIntrMaskTxSpec; +impl crate::RegisterSpec for MmcIntrMaskTxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmc_intr_mask_tx::R`](R) reader structure"] +impl crate::Readable for MmcIntrMaskTxSpec {} +#[doc = "`write(|w| ..)` method takes [`mmc_intr_mask_tx::W`](W) writer structure"] +impl crate::Writable for MmcIntrMaskTxSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MMC_INTR_MASK_TX to value 0"] +impl crate::Resettable for MmcIntrMaskTxSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mmc_intr_rx.rs b/va416xx/src/eth/mmc_intr_rx.rs new file mode 100644 index 0000000..78123ca --- /dev/null +++ b/va416xx/src/eth/mmc_intr_rx.rs @@ -0,0 +1,415 @@ +#[doc = "Register `MMC_INTR_RX` reader"] +pub type R = crate::R; +#[doc = "Register `MMC_INTR_RX` writer"] +pub type W = crate::W; +#[doc = "Field `RXGBFRMIS` reader - MMC Receive Good Bad Frame Counter Interrupt Status"] +pub type RxgbfrmisR = crate::BitReader; +#[doc = "Field `RXGBFRMIS` writer - MMC Receive Good Bad Frame Counter Interrupt Status"] +pub type RxgbfrmisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXGBOCTIS` reader - MMC Receive Good Bad Octet Counter Interrupt Status"] +pub type RxgboctisR = crate::BitReader; +#[doc = "Field `RXGBOCTIS` writer - MMC Receive Good Bad Octet Counter Interrupt Status"] +pub type RxgboctisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXGOCTIS` reader - MMC Receive Good Octet Counter Interrupt Status"] +pub type RxgoctisR = crate::BitReader; +#[doc = "Field `RXGOCTIS` writer - MMC Receive Good Octet Counter Interrupt Status"] +pub type RxgoctisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXBCGFIS` reader - MMC Receive Broadcast Good Frame Counter Interrupt Status"] +pub type RxbcgfisR = crate::BitReader; +#[doc = "Field `RXBCGFIS` writer - MMC Receive Broadcast Good Frame Counter Interrupt Status"] +pub type RxbcgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXMCGFIS` reader - MMC Receive Multicast Good Frame Counter Interrupt Status"] +pub type RxmcgfisR = crate::BitReader; +#[doc = "Field `RXMCGFIS` writer - MMC Receive Multicast Good Frame Counter Interrupt Status"] +pub type RxmcgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXCRCERFIS` reader - MMC Receive CRC Error Frame Counter Interrupt Status"] +pub type RxcrcerfisR = crate::BitReader; +#[doc = "Field `RXCRCERFIS` writer - MMC Receive CRC Error Frame Counter Interrupt Status"] +pub type RxcrcerfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXALGNERFIS` reader - MMC Receive Alignment Error Frame Counter Interrupt Status"] +pub type RxalgnerfisR = crate::BitReader; +#[doc = "Field `RXALGNERFIS` writer - MMC Receive Alignment Error Frame Counter Interrupt Status"] +pub type RxalgnerfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXRUNTFIS` reader - MMC Receive Runt Frame Counter Interrupt Status"] +pub type RxruntfisR = crate::BitReader; +#[doc = "Field `RXRUNTFIS` writer - MMC Receive Runt Frame Counter Interrupt Status"] +pub type RxruntfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXJABERFIS` reader - MMC Receive Jabber Error Frame Counter Interrupt Status"] +pub type RxjaberfisR = crate::BitReader; +#[doc = "Field `RXJABERFIS` writer - MMC Receive Jabber Error Frame Counter Interrupt Status"] +pub type RxjaberfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXUSIZEGFIS` reader - MMC Receive Undersize Good Frame Counter Interrupt Status"] +pub type RxusizegfisR = crate::BitReader; +#[doc = "Field `RXUSIZEGFIS` writer - MMC Receive Undersize Good Frame Counter Interrupt Status"] +pub type RxusizegfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXOSIZEGFIS` reader - MMC Receive Oversize Good Frame Counter Interrupt Status"] +pub type RxosizegfisR = crate::BitReader; +#[doc = "Field `RXOSIZEGFIS` writer - MMC Receive Oversize Good Frame Counter Interrupt Status"] +pub type RxosizegfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX64OCTGBFIS` reader - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx64octgbfisR = crate::BitReader; +#[doc = "Field `RX64OCTGBFIS` writer - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx64octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX65T127OCTGBFIS` reader - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx65t127octgbfisR = crate::BitReader; +#[doc = "Field `RX65T127OCTGBFIS` writer - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx65t127octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX128T255OCTGBFIS` reader - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx128t255octgbfisR = crate::BitReader; +#[doc = "Field `RX128T255OCTGBFIS` writer - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx128t255octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX256T511OCTGBFIS` reader - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx256t511octgbfisR = crate::BitReader; +#[doc = "Field `RX256T511OCTGBFIS` writer - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx256t511octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX512T1023OCTGBFIS` reader - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx512t1023octgbfisR = crate::BitReader; +#[doc = "Field `RX512T1023OCTGBFIS` writer - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub type Rx512t1023octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RX1024TMAXOCTGBFIS` reader - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] +pub type Rx1024tmaxoctgbfisR = crate::BitReader; +#[doc = "Field `RX1024TMAXOCTGBFIS` writer - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] +pub type Rx1024tmaxoctgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXUCGFIS` reader - MMC Receive Unicast Good Frame Counter Interrupt Status"] +pub type RxucgfisR = crate::BitReader; +#[doc = "Field `RXUCGFIS` writer - MMC Receive Unicast Good Frame Counter Interrupt Status"] +pub type RxucgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXLENERFIS` reader - MMC Receive Length Error Frame Counter Interrupt Status"] +pub type RxlenerfisR = crate::BitReader; +#[doc = "Field `RXLENERFIS` writer - MMC Receive Length Error Frame Counter Interrupt Status"] +pub type RxlenerfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXORANGEFIS` reader - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] +pub type RxorangefisR = crate::BitReader; +#[doc = "Field `RXORANGEFIS` writer - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] +pub type RxorangefisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXPAUSFIS` reader - MMC Receive Pause Frame Counter Interrupt Status"] +pub type RxpausfisR = crate::BitReader; +#[doc = "Field `RXPAUSFIS` writer - MMC Receive Pause Frame Counter Interrupt Status"] +pub type RxpausfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFOVFIS` reader - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] +pub type RxfovfisR = crate::BitReader; +#[doc = "Field `RXFOVFIS` writer - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] +pub type RxfovfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXVLANGBFIS` reader - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] +pub type RxvlangbfisR = crate::BitReader; +#[doc = "Field `RXVLANGBFIS` writer - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] +pub type RxvlangbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXWDOGFIS` reader - MMC Receive Watchdog Error Frame Counter Interrupt Status"] +pub type RxwdogfisR = crate::BitReader; +#[doc = "Field `RXWDOGFIS` writer - MMC Receive Watchdog Error Frame Counter Interrupt Status"] +pub type RxwdogfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXRCVERRFIS` reader - MMC Receive Error Frame Counter Interrupt Status"] +pub type RxrcverrfisR = crate::BitReader; +#[doc = "Field `RXRCVERRFIS` writer - MMC Receive Error Frame Counter Interrupt Status"] +pub type RxrcverrfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXCTRLFIS` reader - MMC Receive Control Frame Counter Interrupt Status"] +pub type RxctrlfisR = crate::BitReader; +#[doc = "Field `RXCTRLFIS` writer - MMC Receive Control Frame Counter Interrupt Status"] +pub type RxctrlfisW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxgbfrmis(&self) -> RxgbfrmisR { + RxgbfrmisR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + pub fn rxgboctis(&self) -> RxgboctisR { + RxgboctisR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Status"] + #[inline(always)] + pub fn rxgoctis(&self) -> RxgoctisR { + RxgoctisR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxbcgfis(&self) -> RxbcgfisR { + RxbcgfisR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxmcgfis(&self) -> RxmcgfisR { + RxmcgfisR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxcrcerfis(&self) -> RxcrcerfisR { + RxcrcerfisR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxalgnerfis(&self) -> RxalgnerfisR { + RxalgnerfisR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxruntfis(&self) -> RxruntfisR { + RxruntfisR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxjaberfis(&self) -> RxjaberfisR { + RxjaberfisR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxusizegfis(&self) -> RxusizegfisR { + RxusizegfisR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxosizegfis(&self) -> RxosizegfisR { + RxosizegfisR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx64octgbfis(&self) -> Rx64octgbfisR { + Rx64octgbfisR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx65t127octgbfis(&self) -> Rx65t127octgbfisR { + Rx65t127octgbfisR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx128t255octgbfis(&self) -> Rx128t255octgbfisR { + Rx128t255octgbfisR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx256t511octgbfis(&self) -> Rx256t511octgbfisR { + Rx256t511octgbfisR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rx512t1023octgbfis(&self) -> Rx512t1023octgbfisR { + Rx512t1023octgbfisR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] + #[inline(always)] + pub fn rx1024tmaxoctgbfis(&self) -> Rx1024tmaxoctgbfisR { + Rx1024tmaxoctgbfisR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxucgfis(&self) -> RxucgfisR { + RxucgfisR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxlenerfis(&self) -> RxlenerfisR { + RxlenerfisR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] + #[inline(always)] + pub fn rxorangefis(&self) -> RxorangefisR { + RxorangefisR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxpausfis(&self) -> RxpausfisR { + RxpausfisR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxfovfis(&self) -> RxfovfisR { + RxfovfisR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxvlangbfis(&self) -> RxvlangbfisR { + RxvlangbfisR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxwdogfis(&self) -> RxwdogfisR { + RxwdogfisR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxrcverrfis(&self) -> RxrcverrfisR { + RxrcverrfisR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Status"] + #[inline(always)] + pub fn rxctrlfis(&self) -> RxctrlfisR { + RxctrlfisR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - MMC Receive Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxgbfrmis(&mut self) -> RxgbfrmisW { + RxgbfrmisW::new(self, 0) + } + #[doc = "Bit 1 - MMC Receive Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxgboctis(&mut self) -> RxgboctisW { + RxgboctisW::new(self, 1) + } + #[doc = "Bit 2 - MMC Receive Good Octet Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxgoctis(&mut self) -> RxgoctisW { + RxgoctisW::new(self, 2) + } + #[doc = "Bit 3 - MMC Receive Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxbcgfis(&mut self) -> RxbcgfisW { + RxbcgfisW::new(self, 3) + } + #[doc = "Bit 4 - MMC Receive Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxmcgfis(&mut self) -> RxmcgfisW { + RxmcgfisW::new(self, 4) + } + #[doc = "Bit 5 - MMC Receive CRC Error Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxcrcerfis(&mut self) -> RxcrcerfisW { + RxcrcerfisW::new(self, 5) + } + #[doc = "Bit 6 - MMC Receive Alignment Error Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxalgnerfis(&mut self) -> RxalgnerfisW { + RxalgnerfisW::new(self, 6) + } + #[doc = "Bit 7 - MMC Receive Runt Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxruntfis(&mut self) -> RxruntfisW { + RxruntfisW::new(self, 7) + } + #[doc = "Bit 8 - MMC Receive Jabber Error Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxjaberfis(&mut self) -> RxjaberfisW { + RxjaberfisW::new(self, 8) + } + #[doc = "Bit 9 - MMC Receive Undersize Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxusizegfis(&mut self) -> RxusizegfisW { + RxusizegfisW::new(self, 9) + } + #[doc = "Bit 10 - MMC Receive Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxosizegfis(&mut self) -> RxosizegfisW { + RxosizegfisW::new(self, 10) + } + #[doc = "Bit 11 - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rx64octgbfis(&mut self) -> Rx64octgbfisW { + Rx64octgbfisW::new(self, 11) + } + #[doc = "Bit 12 - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rx65t127octgbfis(&mut self) -> Rx65t127octgbfisW { + Rx65t127octgbfisW::new(self, 12) + } + #[doc = "Bit 13 - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rx128t255octgbfis(&mut self) -> Rx128t255octgbfisW { + Rx128t255octgbfisW::new(self, 13) + } + #[doc = "Bit 14 - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rx256t511octgbfis(&mut self) -> Rx256t511octgbfisW { + Rx256t511octgbfisW::new(self, 14) + } + #[doc = "Bit 15 - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rx512t1023octgbfis(&mut self) -> Rx512t1023octgbfisW { + Rx512t1023octgbfisW::new(self, 15) + } + #[doc = "Bit 16 - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status."] + #[inline(always)] + #[must_use] + pub fn rx1024tmaxoctgbfis(&mut self) -> Rx1024tmaxoctgbfisW { + Rx1024tmaxoctgbfisW::new(self, 16) + } + #[doc = "Bit 17 - MMC Receive Unicast Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxucgfis(&mut self) -> RxucgfisW { + RxucgfisW::new(self, 17) + } + #[doc = "Bit 18 - MMC Receive Length Error Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxlenerfis(&mut self) -> RxlenerfisW { + RxlenerfisW::new(self, 18) + } + #[doc = "Bit 19 - MMC Receive Out Of Range Error Frame Counter Interrupt Status."] + #[inline(always)] + #[must_use] + pub fn rxorangefis(&mut self) -> RxorangefisW { + RxorangefisW::new(self, 19) + } + #[doc = "Bit 20 - MMC Receive Pause Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxpausfis(&mut self) -> RxpausfisW { + RxpausfisW::new(self, 20) + } + #[doc = "Bit 21 - MMC Receive FIFO Overflow Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxfovfis(&mut self) -> RxfovfisW { + RxfovfisW::new(self, 21) + } + #[doc = "Bit 22 - MMC Receive VLAN Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxvlangbfis(&mut self) -> RxvlangbfisW { + RxvlangbfisW::new(self, 22) + } + #[doc = "Bit 23 - MMC Receive Watchdog Error Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxwdogfis(&mut self) -> RxwdogfisW { + RxwdogfisW::new(self, 23) + } + #[doc = "Bit 24 - MMC Receive Error Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxrcverrfis(&mut self) -> RxrcverrfisW { + RxrcverrfisW::new(self, 24) + } + #[doc = "Bit 25 - MMC Receive Control Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn rxctrlfis(&mut self) -> RxctrlfisW { + RxctrlfisW::new(self, 25) + } +} +#[doc = "MMC Receive Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmc_intr_rx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmc_intr_rx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmcIntrRxSpec; +impl crate::RegisterSpec for MmcIntrRxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmc_intr_rx::R`](R) reader structure"] +impl crate::Readable for MmcIntrRxSpec {} +#[doc = "`write(|w| ..)` method takes [`mmc_intr_rx::W`](W) writer structure"] +impl crate::Writable for MmcIntrRxSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MMC_INTR_RX to value 0"] +impl crate::Resettable for MmcIntrRxSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/mmc_intr_tx.rs b/va416xx/src/eth/mmc_intr_tx.rs new file mode 100644 index 0000000..7069df4 --- /dev/null +++ b/va416xx/src/eth/mmc_intr_tx.rs @@ -0,0 +1,415 @@ +#[doc = "Register `MMC_INTR_TX` reader"] +pub type R = crate::R; +#[doc = "Register `MMC_INTR_TX` writer"] +pub type W = crate::W; +#[doc = "Field `TXGBOCTIS` reader - MMC Transmit Good Bad Octet Counter Interrupt Status"] +pub type TxgboctisR = crate::BitReader; +#[doc = "Field `TXGBOCTIS` writer - MMC Transmit Good Bad Octet Counter Interrupt Status"] +pub type TxgboctisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGBFRMIS` reader - MMC Transmit Good Bad Frame Counter Interrupt Status"] +pub type TxgbfrmisR = crate::BitReader; +#[doc = "Field `TXGBFRMIS` writer - MMC Transmit Good Bad Frame Counter Interrupt Status"] +pub type TxgbfrmisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXBCGFIS` reader - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] +pub type TxbcgfisR = crate::BitReader; +#[doc = "Field `TXBCGFIS` writer - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] +pub type TxbcgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCGFIS` reader - MMC Transmit Multicast Good Frame Counter Interrupt Status"] +pub type TxmcgfisR = crate::BitReader; +#[doc = "Field `TXMCGFIS` writer - MMC Transmit Multicast Good Frame Counter Interrupt Status"] +pub type TxmcgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX64OCTGBFIS` reader - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx64octgbfisR = crate::BitReader; +#[doc = "Field `TX64OCTGBFIS` writer - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx64octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX65T127OCTGBFIS` reader - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx65t127octgbfisR = crate::BitReader; +#[doc = "Field `TX65T127OCTGBFIS` writer - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx65t127octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX128T255OCTGBFIS` reader - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx128t255octgbfisR = crate::BitReader; +#[doc = "Field `TX128T255OCTGBFIS` writer - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx128t255octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX256T511OCTGBFIS` reader - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx256t511octgbfisR = crate::BitReader; +#[doc = "Field `TX256T511OCTGBFIS` writer - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx256t511octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX512T1023OCTGBFIS` reader - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx512t1023octgbfisR = crate::BitReader; +#[doc = "Field `TX512T1023OCTGBFIS` writer - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] +pub type Tx512t1023octgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TX1024TMAXOCTGBFIS` reader - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] +pub type Tx1024tmaxoctgbfisR = crate::BitReader; +#[doc = "Field `TX1024TMAXOCTGBFIS` writer - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] +pub type Tx1024tmaxoctgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUCGBFIS` reader - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] +pub type TxucgbfisR = crate::BitReader; +#[doc = "Field `TXUCGBFIS` writer - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] +pub type TxucgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCGBFIS` reader - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] +pub type TxmcgbfisR = crate::BitReader; +#[doc = "Field `TXMCGBFIS` writer - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] +pub type TxmcgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXBCGBFIS` reader - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] +pub type TxbcgbfisR = crate::BitReader; +#[doc = "Field `TXBCGBFIS` writer - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] +pub type TxbcgbfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUFLOWERFIS` reader - MMC Transmit Underflow Error Frame Counter Interrupt Status"] +pub type TxuflowerfisR = crate::BitReader; +#[doc = "Field `TXUFLOWERFIS` writer - MMC Transmit Underflow Error Frame Counter Interrupt Status"] +pub type TxuflowerfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXSCOLGFIS` reader - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] +pub type TxscolgfisR = crate::BitReader; +#[doc = "Field `TXSCOLGFIS` writer - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] +pub type TxscolgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXMCOLGFIS` reader - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] +pub type TxmcolgfisR = crate::BitReader; +#[doc = "Field `TXMCOLGFIS` writer - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] +pub type TxmcolgfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXDEFFIS` reader - MMC Transmit Deferred Frame Counter Interrupt Status"] +pub type TxdeffisR = crate::BitReader; +#[doc = "Field `TXDEFFIS` writer - MMC Transmit Deferred Frame Counter Interrupt Status"] +pub type TxdeffisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXLATCOLFIS` reader - MMC Transmit Late Collision Frame Counter Interrupt Status"] +pub type TxlatcolfisR = crate::BitReader; +#[doc = "Field `TXLATCOLFIS` writer - MMC Transmit Late Collision Frame Counter Interrupt Status"] +pub type TxlatcolfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEXCOLFIS` reader - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] +pub type TxexcolfisR = crate::BitReader; +#[doc = "Field `TXEXCOLFIS` writer - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] +pub type TxexcolfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXCARERFIS` reader - MMC Transmit Carrier Error Frame Counter Interrupt Status"] +pub type TxcarerfisR = crate::BitReader; +#[doc = "Field `TXCARERFIS` writer - MMC Transmit Carrier Error Frame Counter Interrupt Status"] +pub type TxcarerfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGOCTIS` reader - MMC Transmit Good Octet Counter Interrupt Status"] +pub type TxgoctisR = crate::BitReader; +#[doc = "Field `TXGOCTIS` writer - MMC Transmit Good Octet Counter Interrupt Status"] +pub type TxgoctisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXGFRMIS` reader - MMC Transmit Good Frame Counter Interrupt Status"] +pub type TxgfrmisR = crate::BitReader; +#[doc = "Field `TXGFRMIS` writer - MMC Transmit Good Frame Counter Interrupt Status"] +pub type TxgfrmisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEXDEFFIS` reader - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] +pub type TxexdeffisR = crate::BitReader; +#[doc = "Field `TXEXDEFFIS` writer - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] +pub type TxexdeffisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXPAUSFIS` reader - MMC Transmit Pause Frame Counter Interrupt Status"] +pub type TxpausfisR = crate::BitReader; +#[doc = "Field `TXPAUSFIS` writer - MMC Transmit Pause Frame Counter Interrupt Status"] +pub type TxpausfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXVLANGFIS` reader - MMC Transmit VLAN Good Frame Counter Interrupt Status"] +pub type TxvlangfisR = crate::BitReader; +#[doc = "Field `TXVLANGFIS` writer - MMC Transmit VLAN Good Frame Counter Interrupt Status"] +pub type TxvlangfisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXOSIZEGFIS` reader - MMC Transmit Oversize Good Frame Counter Interrupt Status"] +pub type TxosizegfisR = crate::BitReader; +#[doc = "Field `TXOSIZEGFIS` writer - MMC Transmit Oversize Good Frame Counter Interrupt Status"] +pub type TxosizegfisW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + pub fn txgboctis(&self) -> TxgboctisR { + TxgboctisR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txgbfrmis(&self) -> TxgbfrmisR { + TxgbfrmisR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txbcgfis(&self) -> TxbcgfisR { + TxbcgfisR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcgfis(&self) -> TxmcgfisR { + TxmcgfisR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx64octgbfis(&self) -> Tx64octgbfisR { + Tx64octgbfisR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx65t127octgbfis(&self) -> Tx65t127octgbfisR { + Tx65t127octgbfisR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx128t255octgbfis(&self) -> Tx128t255octgbfisR { + Tx128t255octgbfisR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx256t511octgbfis(&self) -> Tx256t511octgbfisR { + Tx256t511octgbfisR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn tx512t1023octgbfis(&self) -> Tx512t1023octgbfisR { + Tx512t1023octgbfisR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] + #[inline(always)] + pub fn tx1024tmaxoctgbfis(&self) -> Tx1024tmaxoctgbfisR { + Tx1024tmaxoctgbfisR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txucgbfis(&self) -> TxucgbfisR { + TxucgbfisR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcgbfis(&self) -> TxmcgbfisR { + TxmcgbfisR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txbcgbfis(&self) -> TxbcgbfisR { + TxbcgbfisR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txuflowerfis(&self) -> TxuflowerfisR { + TxuflowerfisR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txscolgfis(&self) -> TxscolgfisR { + TxscolgfisR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txmcolgfis(&self) -> TxmcolgfisR { + TxmcolgfisR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txdeffis(&self) -> TxdeffisR { + TxdeffisR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txlatcolfis(&self) -> TxlatcolfisR { + TxlatcolfisR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txexcolfis(&self) -> TxexcolfisR { + TxexcolfisR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txcarerfis(&self) -> TxcarerfisR { + TxcarerfisR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Status"] + #[inline(always)] + pub fn txgoctis(&self) -> TxgoctisR { + TxgoctisR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txgfrmis(&self) -> TxgfrmisR { + TxgfrmisR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txexdeffis(&self) -> TxexdeffisR { + TxexdeffisR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txpausfis(&self) -> TxpausfisR { + TxpausfisR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txvlangfis(&self) -> TxvlangfisR { + TxvlangfisR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + pub fn txosizegfis(&self) -> TxosizegfisR { + TxosizegfisR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - MMC Transmit Good Bad Octet Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txgboctis(&mut self) -> TxgboctisW { + TxgboctisW::new(self, 0) + } + #[doc = "Bit 1 - MMC Transmit Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txgbfrmis(&mut self) -> TxgbfrmisW { + TxgbfrmisW::new(self, 1) + } + #[doc = "Bit 2 - MMC Transmit Broadcast Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txbcgfis(&mut self) -> TxbcgfisW { + TxbcgfisW::new(self, 2) + } + #[doc = "Bit 3 - MMC Transmit Multicast Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txmcgfis(&mut self) -> TxmcgfisW { + TxmcgfisW::new(self, 3) + } + #[doc = "Bit 4 - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn tx64octgbfis(&mut self) -> Tx64octgbfisW { + Tx64octgbfisW::new(self, 4) + } + #[doc = "Bit 5 - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn tx65t127octgbfis(&mut self) -> Tx65t127octgbfisW { + Tx65t127octgbfisW::new(self, 5) + } + #[doc = "Bit 6 - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn tx128t255octgbfis(&mut self) -> Tx128t255octgbfisW { + Tx128t255octgbfisW::new(self, 6) + } + #[doc = "Bit 7 - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn tx256t511octgbfis(&mut self) -> Tx256t511octgbfisW { + Tx256t511octgbfisW::new(self, 7) + } + #[doc = "Bit 8 - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn tx512t1023octgbfis(&mut self) -> Tx512t1023octgbfisW { + Tx512t1023octgbfisW::new(self, 8) + } + #[doc = "Bit 9 - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter"] + #[inline(always)] + #[must_use] + pub fn tx1024tmaxoctgbfis(&mut self) -> Tx1024tmaxoctgbfisW { + Tx1024tmaxoctgbfisW::new(self, 9) + } + #[doc = "Bit 10 - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txucgbfis(&mut self) -> TxucgbfisW { + TxucgbfisW::new(self, 10) + } + #[doc = "Bit 11 - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txmcgbfis(&mut self) -> TxmcgbfisW { + TxmcgbfisW::new(self, 11) + } + #[doc = "Bit 12 - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txbcgbfis(&mut self) -> TxbcgbfisW { + TxbcgbfisW::new(self, 12) + } + #[doc = "Bit 13 - MMC Transmit Underflow Error Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txuflowerfis(&mut self) -> TxuflowerfisW { + TxuflowerfisW::new(self, 13) + } + #[doc = "Bit 14 - MMC Transmit Single Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txscolgfis(&mut self) -> TxscolgfisW { + TxscolgfisW::new(self, 14) + } + #[doc = "Bit 15 - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txmcolgfis(&mut self) -> TxmcolgfisW { + TxmcolgfisW::new(self, 15) + } + #[doc = "Bit 16 - MMC Transmit Deferred Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txdeffis(&mut self) -> TxdeffisW { + TxdeffisW::new(self, 16) + } + #[doc = "Bit 17 - MMC Transmit Late Collision Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txlatcolfis(&mut self) -> TxlatcolfisW { + TxlatcolfisW::new(self, 17) + } + #[doc = "Bit 18 - MMC Transmit Excessive Collision Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txexcolfis(&mut self) -> TxexcolfisW { + TxexcolfisW::new(self, 18) + } + #[doc = "Bit 19 - MMC Transmit Carrier Error Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txcarerfis(&mut self) -> TxcarerfisW { + TxcarerfisW::new(self, 19) + } + #[doc = "Bit 20 - MMC Transmit Good Octet Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txgoctis(&mut self) -> TxgoctisW { + TxgoctisW::new(self, 20) + } + #[doc = "Bit 21 - MMC Transmit Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txgfrmis(&mut self) -> TxgfrmisW { + TxgfrmisW::new(self, 21) + } + #[doc = "Bit 22 - MMC Transmit Excessive Deferral Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txexdeffis(&mut self) -> TxexdeffisW { + TxexdeffisW::new(self, 22) + } + #[doc = "Bit 23 - MMC Transmit Pause Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txpausfis(&mut self) -> TxpausfisW { + TxpausfisW::new(self, 23) + } + #[doc = "Bit 24 - MMC Transmit VLAN Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txvlangfis(&mut self) -> TxvlangfisW { + TxvlangfisW::new(self, 24) + } + #[doc = "Bit 25 - MMC Transmit Oversize Good Frame Counter Interrupt Status"] + #[inline(always)] + #[must_use] + pub fn txosizegfis(&mut self) -> TxosizegfisW { + TxosizegfisW::new(self, 25) + } +} +#[doc = "MMC Transmit Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mmc_intr_tx::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mmc_intr_tx::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct MmcIntrTxSpec; +impl crate::RegisterSpec for MmcIntrTxSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`mmc_intr_tx::R`](R) reader structure"] +impl crate::Readable for MmcIntrTxSpec {} +#[doc = "`write(|w| ..)` method takes [`mmc_intr_tx::W`](W) writer structure"] +impl crate::Writable for MmcIntrTxSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets MMC_INTR_TX to value 0"] +impl crate::Resettable for MmcIntrTxSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rx1024maxoct_gb.rs b/va416xx/src/eth/rx1024maxoct_gb.rs new file mode 100644 index 0000000..aed43cc --- /dev/null +++ b/va416xx/src/eth/rx1024maxoct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RX1024MAXOCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length between 1024 and max size bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx1024maxoct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx1024maxoctGbSpec; +impl crate::RegisterSpec for Rx1024maxoctGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx1024maxoct_gb::R`](R) reader structure"] +impl crate::Readable for Rx1024maxoctGbSpec {} +#[doc = "`reset()` method sets RX1024MAXOCT_GB to value 0"] +impl crate::Resettable for Rx1024maxoctGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rx128to255oct_gb.rs b/va416xx/src/eth/rx128to255oct_gb.rs new file mode 100644 index 0000000..570447e --- /dev/null +++ b/va416xx/src/eth/rx128to255oct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RX128TO255OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length between 128 and 255 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx128to255oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx128to255octGbSpec; +impl crate::RegisterSpec for Rx128to255octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx128to255oct_gb::R`](R) reader structure"] +impl crate::Readable for Rx128to255octGbSpec {} +#[doc = "`reset()` method sets RX128TO255OCT_GB to value 0"] +impl crate::Resettable for Rx128to255octGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rx256to511oct_gb.rs b/va416xx/src/eth/rx256to511oct_gb.rs new file mode 100644 index 0000000..298d61c --- /dev/null +++ b/va416xx/src/eth/rx256to511oct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RX256TO511OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length between 256 and 511 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx256to511oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx256to511octGbSpec; +impl crate::RegisterSpec for Rx256to511octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx256to511oct_gb::R`](R) reader structure"] +impl crate::Readable for Rx256to511octGbSpec {} +#[doc = "`reset()` method sets RX256TO511OCT_GB to value 0"] +impl crate::Resettable for Rx256to511octGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rx512to1023oct_gb.rs b/va416xx/src/eth/rx512to1023oct_gb.rs new file mode 100644 index 0000000..a02df66 --- /dev/null +++ b/va416xx/src/eth/rx512to1023oct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RX512TO1023OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length between 512 and 1023 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx512to1023oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx512to1023octGbSpec; +impl crate::RegisterSpec for Rx512to1023octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx512to1023oct_gb::R`](R) reader structure"] +impl crate::Readable for Rx512to1023octGbSpec {} +#[doc = "`reset()` method sets RX512TO1023OCT_GB to value 0"] +impl crate::Resettable for Rx512to1023octGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rx64octets_gb.rs b/va416xx/src/eth/rx64octets_gb.rs new file mode 100644 index 0000000..a5f714d --- /dev/null +++ b/va416xx/src/eth/rx64octets_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RX64OCTETS_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length 64 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx64octets_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx64octetsGbSpec; +impl crate::RegisterSpec for Rx64octetsGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx64octets_gb::R`](R) reader structure"] +impl crate::Readable for Rx64octetsGbSpec {} +#[doc = "`reset()` method sets RX64OCTETS_GB to value 0"] +impl crate::Resettable for Rx64octetsGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rx65to127oct_gb.rs b/va416xx/src/eth/rx65to127oct_gb.rs new file mode 100644 index 0000000..dd691e8 --- /dev/null +++ b/va416xx/src/eth/rx65to127oct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RX65TO127OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received with length between 65 and 127 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx65to127oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Rx65to127octGbSpec; +impl crate::RegisterSpec for Rx65to127octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rx65to127oct_gb::R`](R) reader structure"] +impl crate::Readable for Rx65to127octGbSpec {} +#[doc = "`reset()` method sets RX65TO127OCT_GB to value 0"] +impl crate::Resettable for Rx65to127octGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxalignerror.rs b/va416xx/src/eth/rxalignerror.rs new file mode 100644 index 0000000..433b904 --- /dev/null +++ b/va416xx/src/eth/rxalignerror.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXALIGNERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with alignment error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxalignerror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxalignerrorSpec; +impl crate::RegisterSpec for RxalignerrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxalignerror::R`](R) reader structure"] +impl crate::Readable for RxalignerrorSpec {} +#[doc = "`reset()` method sets RXALIGNERROR to value 0"] +impl crate::Resettable for RxalignerrorSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxbcastframes_g.rs b/va416xx/src/eth/rxbcastframes_g.rs new file mode 100644 index 0000000..2074e5e --- /dev/null +++ b/va416xx/src/eth/rxbcastframes_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXBCASTFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good broadcast frames received\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxbcastframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxbcastframesGSpec; +impl crate::RegisterSpec for RxbcastframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxbcastframes_g::R`](R) reader structure"] +impl crate::Readable for RxbcastframesGSpec {} +#[doc = "`reset()` method sets RXBCASTFRAMES_G to value 0"] +impl crate::Resettable for RxbcastframesGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxcrcerror.rs b/va416xx/src/eth/rxcrcerror.rs new file mode 100644 index 0000000..33d47f1 --- /dev/null +++ b/va416xx/src/eth/rxcrcerror.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXCRCERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with CRC error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcrcerror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxcrcerrorSpec; +impl crate::RegisterSpec for RxcrcerrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxcrcerror::R`](R) reader structure"] +impl crate::Readable for RxcrcerrorSpec {} +#[doc = "`reset()` method sets RXCRCERROR to value 0"] +impl crate::Resettable for RxcrcerrorSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxctrlframes_g.rs b/va416xx/src/eth/rxctrlframes_g.rs new file mode 100644 index 0000000..949f2c9 --- /dev/null +++ b/va416xx/src/eth/rxctrlframes_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXCTRLFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of received good control frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxctrlframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxctrlframesGSpec; +impl crate::RegisterSpec for RxctrlframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxctrlframes_g::R`](R) reader structure"] +impl crate::Readable for RxctrlframesGSpec {} +#[doc = "`reset()` method sets RXCTRLFRAMES_G to value 0"] +impl crate::Resettable for RxctrlframesGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxfifooverflow.rs b/va416xx/src/eth/rxfifooverflow.rs new file mode 100644 index 0000000..e149320 --- /dev/null +++ b/va416xx/src/eth/rxfifooverflow.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXFIFOOVERFLOW` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of missed received frames because of FIFO overflow\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifooverflow::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifooverflowSpec; +impl crate::RegisterSpec for RxfifooverflowSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifooverflow::R`](R) reader structure"] +impl crate::Readable for RxfifooverflowSpec {} +#[doc = "`reset()` method sets RXFIFOOVERFLOW to value 0"] +impl crate::Resettable for RxfifooverflowSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxframecount_gb.rs b/va416xx/src/eth/rxframecount_gb.rs new file mode 100644 index 0000000..0b6cad3 --- /dev/null +++ b/va416xx/src/eth/rxframecount_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXFRAMECOUNT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad frames received\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxframecount_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxframecountGbSpec; +impl crate::RegisterSpec for RxframecountGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxframecount_gb::R`](R) reader structure"] +impl crate::Readable for RxframecountGbSpec {} +#[doc = "`reset()` method sets RXFRAMECOUNT_GB to value 0"] +impl crate::Resettable for RxframecountGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxjabbererror.rs b/va416xx/src/eth/rxjabbererror.rs new file mode 100644 index 0000000..88ba0fe --- /dev/null +++ b/va416xx/src/eth/rxjabbererror.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXJABBERERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of giant frames received with length greater than 1518 bytes and with CRC error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxjabbererror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxjabbererrorSpec; +impl crate::RegisterSpec for RxjabbererrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxjabbererror::R`](R) reader structure"] +impl crate::Readable for RxjabbererrorSpec {} +#[doc = "`reset()` method sets RXJABBERERROR to value 0"] +impl crate::Resettable for RxjabbererrorSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxlengtherror.rs b/va416xx/src/eth/rxlengtherror.rs new file mode 100644 index 0000000..f838621 --- /dev/null +++ b/va416xx/src/eth/rxlengtherror.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXLENGTHERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with length error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxlengtherror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxlengtherrorSpec; +impl crate::RegisterSpec for RxlengtherrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxlengtherror::R`](R) reader structure"] +impl crate::Readable for RxlengtherrorSpec {} +#[doc = "`reset()` method sets RXLENGTHERROR to value 0"] +impl crate::Resettable for RxlengtherrorSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxmcastframes_g.rs b/va416xx/src/eth/rxmcastframes_g.rs new file mode 100644 index 0000000..3c2c4e7 --- /dev/null +++ b/va416xx/src/eth/rxmcastframes_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXMCASTFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good multicast frames received\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxmcastframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxmcastframesGSpec; +impl crate::RegisterSpec for RxmcastframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxmcastframes_g::R`](R) reader structure"] +impl crate::Readable for RxmcastframesGSpec {} +#[doc = "`reset()` method sets RXMCASTFRAMES_G to value 0"] +impl crate::Resettable for RxmcastframesGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxoctetcount_g.rs b/va416xx/src/eth/rxoctetcount_g.rs new file mode 100644 index 0000000..69e5aab --- /dev/null +++ b/va416xx/src/eth/rxoctetcount_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXOCTETCOUNT_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of bytes"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of bytes received in good frames only\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxoctetcount_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxoctetcountGSpec; +impl crate::RegisterSpec for RxoctetcountGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxoctetcount_g::R`](R) reader structure"] +impl crate::Readable for RxoctetcountGSpec {} +#[doc = "`reset()` method sets RXOCTETCOUNT_G to value 0"] +impl crate::Resettable for RxoctetcountGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxoctetcount_gb.rs b/va416xx/src/eth/rxoctetcount_gb.rs new file mode 100644 index 0000000..2673785 --- /dev/null +++ b/va416xx/src/eth/rxoctetcount_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXOCTETCOUNT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of bytes"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of bytes received in good and bad frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxoctetcount_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxoctetcountGbSpec; +impl crate::RegisterSpec for RxoctetcountGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxoctetcount_gb::R`](R) reader structure"] +impl crate::Readable for RxoctetcountGbSpec {} +#[doc = "`reset()` method sets RXOCTETCOUNT_GB to value 0"] +impl crate::Resettable for RxoctetcountGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxoutrangetype.rs b/va416xx/src/eth/rxoutrangetype.rs new file mode 100644 index 0000000..bbf7a57 --- /dev/null +++ b/va416xx/src/eth/rxoutrangetype.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXOUTRANGETYPE` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with length field not equal to the valid frame size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxoutrangetype::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxoutrangetypeSpec; +impl crate::RegisterSpec for RxoutrangetypeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxoutrangetype::R`](R) reader structure"] +impl crate::Readable for RxoutrangetypeSpec {} +#[doc = "`reset()` method sets RXOUTRANGETYPE to value 0"] +impl crate::Resettable for RxoutrangetypeSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxoversize_g.rs b/va416xx/src/eth/rxoversize_g.rs new file mode 100644 index 0000000..5767117 --- /dev/null +++ b/va416xx/src/eth/rxoversize_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXOVERSIZE_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received without errors with length greater than the max size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxoversize_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxoversizeGSpec; +impl crate::RegisterSpec for RxoversizeGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxoversize_g::R`](R) reader structure"] +impl crate::Readable for RxoversizeGSpec {} +#[doc = "`reset()` method sets RXOVERSIZE_G to value 0"] +impl crate::Resettable for RxoversizeGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxpauseframes.rs b/va416xx/src/eth/rxpauseframes.rs new file mode 100644 index 0000000..71376de --- /dev/null +++ b/va416xx/src/eth/rxpauseframes.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXPAUSEFRAMES` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and valid Pause frames received\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxpauseframes::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxpauseframesSpec; +impl crate::RegisterSpec for RxpauseframesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxpauseframes::R`](R) reader structure"] +impl crate::Readable for RxpauseframesSpec {} +#[doc = "`reset()` method sets RXPAUSEFRAMES to value 0"] +impl crate::Resettable for RxpauseframesSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxrcverror.rs b/va416xx/src/eth/rxrcverror.rs new file mode 100644 index 0000000..bc1b9d3 --- /dev/null +++ b/va416xx/src/eth/rxrcverror.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXRCVERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with Receive error or Frame Extension error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxrcverror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxrcverrorSpec; +impl crate::RegisterSpec for RxrcverrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxrcverror::R`](R) reader structure"] +impl crate::Readable for RxrcverrorSpec {} +#[doc = "`reset()` method sets RXRCVERROR to value 0"] +impl crate::Resettable for RxrcverrorSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxrunterror.rs b/va416xx/src/eth/rxrunterror.rs new file mode 100644 index 0000000..383a955 --- /dev/null +++ b/va416xx/src/eth/rxrunterror.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXRUNTERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with runt error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxrunterror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxrunterrorSpec; +impl crate::RegisterSpec for RxrunterrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxrunterror::R`](R) reader structure"] +impl crate::Readable for RxrunterrorSpec {} +#[doc = "`reset()` method sets RXRUNTERROR to value 0"] +impl crate::Resettable for RxrunterrorSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxucastframes_g.rs b/va416xx/src/eth/rxucastframes_g.rs new file mode 100644 index 0000000..3e53f7f --- /dev/null +++ b/va416xx/src/eth/rxucastframes_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXUCASTFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of received good unicast frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxucastframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxucastframesGSpec; +impl crate::RegisterSpec for RxucastframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxucastframes_g::R`](R) reader structure"] +impl crate::Readable for RxucastframesGSpec {} +#[doc = "`reset()` method sets RXUCASTFRAMES_G to value 0"] +impl crate::Resettable for RxucastframesGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxundersize_g.rs b/va416xx/src/eth/rxundersize_g.rs new file mode 100644 index 0000000..4464266 --- /dev/null +++ b/va416xx/src/eth/rxundersize_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXUNDERSIZE_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with length less than 64 bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxundersize_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxundersizeGSpec; +impl crate::RegisterSpec for RxundersizeGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxundersize_g::R`](R) reader structure"] +impl crate::Readable for RxundersizeGSpec {} +#[doc = "`reset()` method sets RXUNDERSIZE_G to value 0"] +impl crate::Resettable for RxundersizeGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxvlanframes_gb.rs b/va416xx/src/eth/rxvlanframes_gb.rs new file mode 100644 index 0000000..81088d7 --- /dev/null +++ b/va416xx/src/eth/rxvlanframes_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXVLANFRAMES_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good and bad VLAN frames received\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxvlanframes_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxvlanframesGbSpec; +impl crate::RegisterSpec for RxvlanframesGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxvlanframes_gb::R`](R) reader structure"] +impl crate::Readable for RxvlanframesGbSpec {} +#[doc = "`reset()` method sets RXVLANFRAMES_GB to value 0"] +impl crate::Resettable for RxvlanframesGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/rxwdogerror.rs b/va416xx/src/eth/rxwdogerror.rs new file mode 100644 index 0000000..6d6d922 --- /dev/null +++ b/va416xx/src/eth/rxwdogerror.rs @@ -0,0 +1,22 @@ +#[doc = "Register `RXWDOGERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames received with error because of watchdog timeout error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxwdogerror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxwdogerrorSpec; +impl crate::RegisterSpec for RxwdogerrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxwdogerror::R`](R) reader structure"] +impl crate::Readable for RxwdogerrorSpec {} +#[doc = "`reset()` method sets RXWDOGERROR to value 0"] +impl crate::Resettable for RxwdogerrorSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/subsec_inc.rs b/va416xx/src/eth/subsec_inc.rs new file mode 100644 index 0000000..02dd4a6 --- /dev/null +++ b/va416xx/src/eth/subsec_inc.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SUBSEC_INC` reader"] +pub type R = crate::R; +#[doc = "Register `SUBSEC_INC` writer"] +pub type W = crate::W; +#[doc = "Field `SSINC` reader - Sub-Second Increment Valuee"] +pub type SsincR = crate::FieldReader; +#[doc = "Field `SSINC` writer - Sub-Second Increment Valuee"] +pub type SsincW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Sub-Second Increment Valuee"] + #[inline(always)] + pub fn ssinc(&self) -> SsincR { + SsincR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Sub-Second Increment Valuee"] + #[inline(always)] + #[must_use] + pub fn ssinc(&mut self) -> SsincW { + SsincW::new(self, 0) + } +} +#[doc = "Holds the 8-bit value by which the Sub-Second register is incremented\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`subsec_inc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`subsec_inc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SubsecIncSpec; +impl crate::RegisterSpec for SubsecIncSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`subsec_inc::R`](R) reader structure"] +impl crate::Readable for SubsecIncSpec {} +#[doc = "`write(|w| ..)` method takes [`subsec_inc::W`](W) writer structure"] +impl crate::Writable for SubsecIncSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SUBSEC_INC to value 0"] +impl crate::Resettable for SubsecIncSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/systime_nanosec.rs b/va416xx/src/eth/systime_nanosec.rs new file mode 100644 index 0000000..0d91afe --- /dev/null +++ b/va416xx/src/eth/systime_nanosec.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SYSTIME_NANOSEC` reader"] +pub type R = crate::R; +#[doc = "Field `TSSS` reader - Timestamp Sub Seconds"] +pub type TsssR = crate::FieldReader; +impl R { + #[doc = "Bits 0:30 - Timestamp Sub Seconds"] + #[inline(always)] + pub fn tsss(&self) -> TsssR { + TsssR::new(self.bits & 0x7fff_ffff) + } +} +#[doc = "Holds 32 bits of the nano-second field of the system time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systime_nanosec::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SystimeNanosecSpec; +impl crate::RegisterSpec for SystimeNanosecSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`systime_nanosec::R`](R) reader structure"] +impl crate::Readable for SystimeNanosecSpec {} +#[doc = "`reset()` method sets SYSTIME_NANOSEC to value 0"] +impl crate::Resettable for SystimeNanosecSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/systime_nsecup.rs b/va416xx/src/eth/systime_nsecup.rs new file mode 100644 index 0000000..f2a86de --- /dev/null +++ b/va416xx/src/eth/systime_nsecup.rs @@ -0,0 +1,55 @@ +#[doc = "Register `SYSTIME_NSECUP` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTIME_NSECUP` writer"] +pub type W = crate::W; +#[doc = "Field `TSSS` reader - Timestamp Sub Seconds"] +pub type TsssR = crate::FieldReader; +#[doc = "Field `TSSS` writer - Timestamp Sub Seconds"] +pub type TsssW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `ADDSUB` reader - Add or Subtract Time"] +pub type AddsubR = crate::BitReader; +#[doc = "Field `ADDSUB` writer - Add or Subtract Time"] +pub type AddsubW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - Timestamp Sub Seconds"] + #[inline(always)] + pub fn tsss(&self) -> TsssR { + TsssR::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - Add or Subtract Time"] + #[inline(always)] + pub fn addsub(&self) -> AddsubR { + AddsubR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:30 - Timestamp Sub Seconds"] + #[inline(always)] + #[must_use] + pub fn tsss(&mut self) -> TsssW { + TsssW::new(self, 0) + } + #[doc = "Bit 31 - Add or Subtract Time"] + #[inline(always)] + #[must_use] + pub fn addsub(&mut self) -> AddsubW { + AddsubW::new(self, 31) + } +} +#[doc = "Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systime_nsecup::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systime_nsecup::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SystimeNsecupSpec; +impl crate::RegisterSpec for SystimeNsecupSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`systime_nsecup::R`](R) reader structure"] +impl crate::Readable for SystimeNsecupSpec {} +#[doc = "`write(|w| ..)` method takes [`systime_nsecup::W`](W) writer structure"] +impl crate::Writable for SystimeNsecupSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSTIME_NSECUP to value 0"] +impl crate::Resettable for SystimeNsecupSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/systime_seconds.rs b/va416xx/src/eth/systime_seconds.rs new file mode 100644 index 0000000..202f06c --- /dev/null +++ b/va416xx/src/eth/systime_seconds.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SYSTIME_SECONDS` reader"] +pub type R = crate::R; +#[doc = "Field `TSS` reader - Timestamp Second"] +pub type TssR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Timestamp Second"] + #[inline(always)] + pub fn tss(&self) -> TssR { + TssR::new(self.bits) + } +} +#[doc = "Holds the lower 32 bits of the second field of the system time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systime_seconds::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SystimeSecondsSpec; +impl crate::RegisterSpec for SystimeSecondsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`systime_seconds::R`](R) reader structure"] +impl crate::Readable for SystimeSecondsSpec {} +#[doc = "`reset()` method sets SYSTIME_SECONDS to value 0"] +impl crate::Resettable for SystimeSecondsSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/systime_secsupdat.rs b/va416xx/src/eth/systime_secsupdat.rs new file mode 100644 index 0000000..30d3328 --- /dev/null +++ b/va416xx/src/eth/systime_secsupdat.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SYSTIME_SECSUPDAT` reader"] +pub type R = crate::R; +#[doc = "Register `SYSTIME_SECSUPDAT` writer"] +pub type W = crate::W; +#[doc = "Field `TSS` reader - Timestamp Second"] +pub type TssR = crate::FieldReader; +#[doc = "Field `TSS` writer - Timestamp Second"] +pub type TssW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Timestamp Second"] + #[inline(always)] + pub fn tss(&self) -> TssR { + TssR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Timestamp Second"] + #[inline(always)] + #[must_use] + pub fn tss(&mut self) -> TssW { + TssW::new(self, 0) + } +} +#[doc = "Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systime_secsupdat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systime_secsupdat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SystimeSecsupdatSpec; +impl crate::RegisterSpec for SystimeSecsupdatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`systime_secsupdat::R`](R) reader structure"] +impl crate::Readable for SystimeSecsupdatSpec {} +#[doc = "`write(|w| ..)` method takes [`systime_secsupdat::W`](W) writer structure"] +impl crate::Writable for SystimeSecsupdatSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYSTIME_SECSUPDAT to value 0"] +impl crate::Resettable for SystimeSecsupdatSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/target_time_nsec.rs b/va416xx/src/eth/target_time_nsec.rs new file mode 100644 index 0000000..4e91ab0 --- /dev/null +++ b/va416xx/src/eth/target_time_nsec.rs @@ -0,0 +1,55 @@ +#[doc = "Register `TARGET_TIME_NSEC` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET_TIME_NSEC` writer"] +pub type W = crate::W; +#[doc = "Field `TTSLO` reader - Target Timestamp Low Register"] +pub type TtsloR = crate::FieldReader; +#[doc = "Field `TTSLO` writer - Target Timestamp Low Register"] +pub type TtsloW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `TRGTBUSY` reader - 32 Bits of Hash Table"] +pub type TrgtbusyR = crate::BitReader; +#[doc = "Field `TRGTBUSY` writer - 32 Bits of Hash Table"] +pub type TrgtbusyW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - Target Timestamp Low Register"] + #[inline(always)] + pub fn ttslo(&self) -> TtsloR { + TtsloR::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - 32 Bits of Hash Table"] + #[inline(always)] + pub fn trgtbusy(&self) -> TrgtbusyR { + TrgtbusyR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:30 - Target Timestamp Low Register"] + #[inline(always)] + #[must_use] + pub fn ttslo(&mut self) -> TtsloW { + TtsloW::new(self, 0) + } + #[doc = "Bit 31 - 32 Bits of Hash Table"] + #[inline(always)] + #[must_use] + pub fn trgtbusy(&mut self) -> TrgtbusyW { + TrgtbusyW::new(self, 31) + } +} +#[doc = "Holds the lower 32-bits of time to be compared with the system time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target_time_nsec::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target_time_nsec::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TargetTimeNsecSpec; +impl crate::RegisterSpec for TargetTimeNsecSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`target_time_nsec::R`](R) reader structure"] +impl crate::Readable for TargetTimeNsecSpec {} +#[doc = "`write(|w| ..)` method takes [`target_time_nsec::W`](W) writer structure"] +impl crate::Writable for TargetTimeNsecSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TARGET_TIME_NSEC to value 0"] +impl crate::Resettable for TargetTimeNsecSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/target_time_secs.rs b/va416xx/src/eth/target_time_secs.rs new file mode 100644 index 0000000..b5d9c4d --- /dev/null +++ b/va416xx/src/eth/target_time_secs.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TARGET_TIME_SECS` reader"] +pub type R = crate::R; +#[doc = "Register `TARGET_TIME_SECS` writer"] +pub type W = crate::W; +#[doc = "Field `TSTR` reader - Target Time Seconds Registe"] +pub type TstrR = crate::FieldReader; +#[doc = "Field `TSTR` writer - Target Time Seconds Registe"] +pub type TstrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Target Time Seconds Registe"] + #[inline(always)] + pub fn tstr(&self) -> TstrR { + TstrR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Target Time Seconds Registe"] + #[inline(always)] + #[must_use] + pub fn tstr(&mut self) -> TstrW { + TstrW::new(self, 0) + } +} +#[doc = "Holds the high 32-bits of time to be compared with the system time\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`target_time_secs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`target_time_secs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TargetTimeSecsSpec; +impl crate::RegisterSpec for TargetTimeSecsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`target_time_secs::R`](R) reader structure"] +impl crate::Readable for TargetTimeSecsSpec {} +#[doc = "`write(|w| ..)` method takes [`target_time_secs::W`](W) writer structure"] +impl crate::Writable for TargetTimeSecsSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TARGET_TIME_SECS to value 0"] +impl crate::Resettable for TargetTimeSecsSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/timestamp_ctrl.rs b/va416xx/src/eth/timestamp_ctrl.rs new file mode 100644 index 0000000..e41dce4 --- /dev/null +++ b/va416xx/src/eth/timestamp_ctrl.rs @@ -0,0 +1,340 @@ +#[doc = "Register `TIMESTAMP_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `TIMESTAMP_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `TSENA` reader - Timestamp Enable"] +pub type TsenaR = crate::BitReader; +#[doc = "Field `TSENA` writer - Timestamp Enable"] +pub type TsenaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSCFUPDT` reader - Timestamp Fine or Coarse Update"] +pub type TscfupdtR = crate::BitReader; +#[doc = "Field `TSCFUPDT` writer - Timestamp Fine or Coarse Update"] +pub type TscfupdtW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSINIT` reader - Timestamp Initialize"] +pub type TsinitR = crate::BitReader; +#[doc = "Field `TSINIT` writer - Timestamp Initialize"] +pub type TsinitW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSUPDT` reader - Timestamp Update"] +pub type TsupdtR = crate::BitReader; +#[doc = "Field `TSUPDT` writer - Timestamp Update"] +pub type TsupdtW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSTRIG` reader - Timestamp Interrupt Trigger Enable"] +pub type TstrigR = crate::BitReader; +#[doc = "Field `TSTRIG` writer - Timestamp Interrupt Trigger Enable"] +pub type TstrigW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSADDRREG` reader - Addend Reg Update"] +pub type TsaddrregR = crate::BitReader; +#[doc = "Field `TSADDRREG` writer - Addend Reg Update"] +pub type TsaddrregW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSENALL` reader - Enable Timestamp for All Frames"] +pub type TsenallR = crate::BitReader; +#[doc = "Field `TSENALL` writer - Enable Timestamp for All Frames"] +pub type TsenallW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSCTRLSSR` reader - Timestamp Digital or Binary Rollover Control"] +pub type TsctrlssrR = crate::BitReader; +#[doc = "Field `TSCTRLSSR` writer - Timestamp Digital or Binary Rollover Control"] +pub type TsctrlssrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSVER2ENA` reader - Enable PTP packet Processing for Version 2 Format"] +pub type Tsver2enaR = crate::BitReader; +#[doc = "Field `TSVER2ENA` writer - Enable PTP packet Processing for Version 2 Format"] +pub type Tsver2enaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSIPENA` reader - Enable Processing of PTP over Ethernet Frames"] +pub type TsipenaR = crate::BitReader; +#[doc = "Field `TSIPENA` writer - Enable Processing of PTP over Ethernet Frames"] +pub type TsipenaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSIPV6ENA` reader - Enable Processing of PTP Frames Sent over IPv6-UDP"] +pub type Tsipv6enaR = crate::BitReader; +#[doc = "Field `TSIPV6ENA` writer - Enable Processing of PTP Frames Sent over IPv6-UDP"] +pub type Tsipv6enaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSIPV4ENA` reader - Enable Processing of PTP Frames Sent over IPv4-UDP"] +pub type Tsipv4enaR = crate::BitReader; +#[doc = "Field `TSIPV4ENA` writer - Enable Processing of PTP Frames Sent over IPv4-UDP"] +pub type Tsipv4enaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSEVNTENA` reader - Enable Timestamp Snapshot for Event Messages"] +pub type TsevntenaR = crate::BitReader; +#[doc = "Field `TSEVNTENA` writer - Enable Timestamp Snapshot for Event Messages"] +pub type TsevntenaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TSMSTRENA` reader - Enable Snapshot for Messages Relevant to Master"] +pub type TsmstrenaR = crate::BitReader; +#[doc = "Field `TSMSTRENA` writer - Enable Snapshot for Messages Relevant to Master"] +pub type TsmstrenaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SNAPTYPSEL` reader - Select PTP packets for Taking Snapshots"] +pub type SnaptypselR = crate::FieldReader; +#[doc = "Field `SNAPTYPSEL` writer - Select PTP packets for Taking Snapshots"] +pub type SnaptypselW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `TSENMACADDR` reader - Enable MAC address for PTP Frame Filtering"] +pub type TsenmacaddrR = crate::BitReader; +#[doc = "Field `TSENMACADDR` writer - Enable MAC address for PTP Frame Filtering"] +pub type TsenmacaddrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATSFC` reader - Auxiliary Snapshot FIFO Clear"] +pub type AtsfcR = crate::BitReader; +#[doc = "Field `ATSFC` writer - Auxiliary Snapshot FIFO Clear"] +pub type AtsfcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATSEN0` reader - Auxiliary Snapshot 0 Enable"] +pub type Atsen0R = crate::BitReader; +#[doc = "Field `ATSEN0` writer - Auxiliary Snapshot 0 Enable"] +pub type Atsen0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATSEN1` reader - Auxiliary Snapshot 1 Enable"] +pub type Atsen1R = crate::BitReader; +#[doc = "Field `ATSEN1` writer - Auxiliary Snapshot 1 Enable"] +pub type Atsen1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATSEN2` reader - Auxiliary Snapshot 2 Enable"] +pub type Atsen2R = crate::BitReader; +#[doc = "Field `ATSEN2` writer - Auxiliary Snapshot 2 Enable"] +pub type Atsen2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ATSEN3` reader - Auxiliary Snapshot 3 Enable"] +pub type Atsen3R = crate::BitReader; +#[doc = "Field `ATSEN3` writer - Auxiliary Snapshot 3 Enable"] +pub type Atsen3W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Timestamp Enable"] + #[inline(always)] + pub fn tsena(&self) -> TsenaR { + TsenaR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Timestamp Fine or Coarse Update"] + #[inline(always)] + pub fn tscfupdt(&self) -> TscfupdtR { + TscfupdtR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Timestamp Initialize"] + #[inline(always)] + pub fn tsinit(&self) -> TsinitR { + TsinitR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Timestamp Update"] + #[inline(always)] + pub fn tsupdt(&self) -> TsupdtR { + TsupdtR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Timestamp Interrupt Trigger Enable"] + #[inline(always)] + pub fn tstrig(&self) -> TstrigR { + TstrigR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Addend Reg Update"] + #[inline(always)] + pub fn tsaddrreg(&self) -> TsaddrregR { + TsaddrregR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Enable Timestamp for All Frames"] + #[inline(always)] + pub fn tsenall(&self) -> TsenallR { + TsenallR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Timestamp Digital or Binary Rollover Control"] + #[inline(always)] + pub fn tsctrlssr(&self) -> TsctrlssrR { + TsctrlssrR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable PTP packet Processing for Version 2 Format"] + #[inline(always)] + pub fn tsver2ena(&self) -> Tsver2enaR { + Tsver2enaR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable Processing of PTP over Ethernet Frames"] + #[inline(always)] + pub fn tsipena(&self) -> TsipenaR { + TsipenaR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable Processing of PTP Frames Sent over IPv6-UDP"] + #[inline(always)] + pub fn tsipv6ena(&self) -> Tsipv6enaR { + Tsipv6enaR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enable Processing of PTP Frames Sent over IPv4-UDP"] + #[inline(always)] + pub fn tsipv4ena(&self) -> Tsipv4enaR { + Tsipv4enaR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Enable Timestamp Snapshot for Event Messages"] + #[inline(always)] + pub fn tsevntena(&self) -> TsevntenaR { + TsevntenaR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Enable Snapshot for Messages Relevant to Master"] + #[inline(always)] + pub fn tsmstrena(&self) -> TsmstrenaR { + TsmstrenaR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:17 - Select PTP packets for Taking Snapshots"] + #[inline(always)] + pub fn snaptypsel(&self) -> SnaptypselR { + SnaptypselR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - Enable MAC address for PTP Frame Filtering"] + #[inline(always)] + pub fn tsenmacaddr(&self) -> TsenmacaddrR { + TsenmacaddrR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 24 - Auxiliary Snapshot FIFO Clear"] + #[inline(always)] + pub fn atsfc(&self) -> AtsfcR { + AtsfcR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Auxiliary Snapshot 0 Enable"] + #[inline(always)] + pub fn atsen0(&self) -> Atsen0R { + Atsen0R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Auxiliary Snapshot 1 Enable"] + #[inline(always)] + pub fn atsen1(&self) -> Atsen1R { + Atsen1R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Auxiliary Snapshot 2 Enable"] + #[inline(always)] + pub fn atsen2(&self) -> Atsen2R { + Atsen2R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Auxiliary Snapshot 3 Enable"] + #[inline(always)] + pub fn atsen3(&self) -> Atsen3R { + Atsen3R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Timestamp Enable"] + #[inline(always)] + #[must_use] + pub fn tsena(&mut self) -> TsenaW { + TsenaW::new(self, 0) + } + #[doc = "Bit 1 - Timestamp Fine or Coarse Update"] + #[inline(always)] + #[must_use] + pub fn tscfupdt(&mut self) -> TscfupdtW { + TscfupdtW::new(self, 1) + } + #[doc = "Bit 2 - Timestamp Initialize"] + #[inline(always)] + #[must_use] + pub fn tsinit(&mut self) -> TsinitW { + TsinitW::new(self, 2) + } + #[doc = "Bit 3 - Timestamp Update"] + #[inline(always)] + #[must_use] + pub fn tsupdt(&mut self) -> TsupdtW { + TsupdtW::new(self, 3) + } + #[doc = "Bit 4 - Timestamp Interrupt Trigger Enable"] + #[inline(always)] + #[must_use] + pub fn tstrig(&mut self) -> TstrigW { + TstrigW::new(self, 4) + } + #[doc = "Bit 5 - Addend Reg Update"] + #[inline(always)] + #[must_use] + pub fn tsaddrreg(&mut self) -> TsaddrregW { + TsaddrregW::new(self, 5) + } + #[doc = "Bit 8 - Enable Timestamp for All Frames"] + #[inline(always)] + #[must_use] + pub fn tsenall(&mut self) -> TsenallW { + TsenallW::new(self, 8) + } + #[doc = "Bit 9 - Timestamp Digital or Binary Rollover Control"] + #[inline(always)] + #[must_use] + pub fn tsctrlssr(&mut self) -> TsctrlssrW { + TsctrlssrW::new(self, 9) + } + #[doc = "Bit 10 - Enable PTP packet Processing for Version 2 Format"] + #[inline(always)] + #[must_use] + pub fn tsver2ena(&mut self) -> Tsver2enaW { + Tsver2enaW::new(self, 10) + } + #[doc = "Bit 11 - Enable Processing of PTP over Ethernet Frames"] + #[inline(always)] + #[must_use] + pub fn tsipena(&mut self) -> TsipenaW { + TsipenaW::new(self, 11) + } + #[doc = "Bit 12 - Enable Processing of PTP Frames Sent over IPv6-UDP"] + #[inline(always)] + #[must_use] + pub fn tsipv6ena(&mut self) -> Tsipv6enaW { + Tsipv6enaW::new(self, 12) + } + #[doc = "Bit 13 - Enable Processing of PTP Frames Sent over IPv4-UDP"] + #[inline(always)] + #[must_use] + pub fn tsipv4ena(&mut self) -> Tsipv4enaW { + Tsipv4enaW::new(self, 13) + } + #[doc = "Bit 14 - Enable Timestamp Snapshot for Event Messages"] + #[inline(always)] + #[must_use] + pub fn tsevntena(&mut self) -> TsevntenaW { + TsevntenaW::new(self, 14) + } + #[doc = "Bit 15 - Enable Snapshot for Messages Relevant to Master"] + #[inline(always)] + #[must_use] + pub fn tsmstrena(&mut self) -> TsmstrenaW { + TsmstrenaW::new(self, 15) + } + #[doc = "Bits 16:17 - Select PTP packets for Taking Snapshots"] + #[inline(always)] + #[must_use] + pub fn snaptypsel(&mut self) -> SnaptypselW { + SnaptypselW::new(self, 16) + } + #[doc = "Bit 18 - Enable MAC address for PTP Frame Filtering"] + #[inline(always)] + #[must_use] + pub fn tsenmacaddr(&mut self) -> TsenmacaddrW { + TsenmacaddrW::new(self, 18) + } + #[doc = "Bit 24 - Auxiliary Snapshot FIFO Clear"] + #[inline(always)] + #[must_use] + pub fn atsfc(&mut self) -> AtsfcW { + AtsfcW::new(self, 24) + } + #[doc = "Bit 25 - Auxiliary Snapshot 0 Enable"] + #[inline(always)] + #[must_use] + pub fn atsen0(&mut self) -> Atsen0W { + Atsen0W::new(self, 25) + } + #[doc = "Bit 26 - Auxiliary Snapshot 1 Enable"] + #[inline(always)] + #[must_use] + pub fn atsen1(&mut self) -> Atsen1W { + Atsen1W::new(self, 26) + } + #[doc = "Bit 27 - Auxiliary Snapshot 2 Enable"] + #[inline(always)] + #[must_use] + pub fn atsen2(&mut self) -> Atsen2W { + Atsen2W::new(self, 27) + } + #[doc = "Bit 28 - Auxiliary Snapshot 3 Enable"] + #[inline(always)] + #[must_use] + pub fn atsen3(&mut self) -> Atsen3W { + Atsen3W::new(self, 28) + } +} +#[doc = "Controls the IEEE 1588 timestamp generation and update logic\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestamp_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestamp_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimestampCtrlSpec; +impl crate::RegisterSpec for TimestampCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timestamp_ctrl::R`](R) reader structure"] +impl crate::Readable for TimestampCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`timestamp_ctrl::W`](W) writer structure"] +impl crate::Writable for TimestampCtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMESTAMP_CTRL to value 0"] +impl crate::Resettable for TimestampCtrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/timestampaddend.rs b/va416xx/src/eth/timestampaddend.rs new file mode 100644 index 0000000..3b76f70 --- /dev/null +++ b/va416xx/src/eth/timestampaddend.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TIMESTAMPADDEND` reader"] +pub type R = crate::R; +#[doc = "Register `TIMESTAMPADDEND` writer"] +pub type W = crate::W; +#[doc = "Field `TSAR` reader - Timestamp Addend Register"] +pub type TsarR = crate::FieldReader; +#[doc = "Field `TSAR` writer - Timestamp Addend Register"] +pub type TsarW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Timestamp Addend Register"] + #[inline(always)] + pub fn tsar(&self) -> TsarR { + TsarR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Timestamp Addend Register"] + #[inline(always)] + #[must_use] + pub fn tsar(&mut self) -> TsarW { + TsarW::new(self, 0) + } +} +#[doc = "This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timestampaddend::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timestampaddend::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimestampaddendSpec; +impl crate::RegisterSpec for TimestampaddendSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`timestampaddend::R`](R) reader structure"] +impl crate::Readable for TimestampaddendSpec {} +#[doc = "`write(|w| ..)` method takes [`timestampaddend::W`](W) writer structure"] +impl crate::Writable for TimestampaddendSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIMESTAMPADDEND to value 0"] +impl crate::Resettable for TimestampaddendSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/tx1024maxoct_gb.rs b/va416xx/src/eth/tx1024maxoct_gb.rs new file mode 100644 index 0000000..6f1c043 --- /dev/null +++ b/va416xx/src/eth/tx1024maxoct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TX1024MAXOCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 1024 to max bytes\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx1024maxoct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx1024maxoctGbSpec; +impl crate::RegisterSpec for Tx1024maxoctGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx1024maxoct_gb::R`](R) reader structure"] +impl crate::Readable for Tx1024maxoctGbSpec {} +#[doc = "`reset()` method sets TX1024MAXOCT_GB to value 0"] +impl crate::Resettable for Tx1024maxoctGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/tx128to255oct_gb.rs b/va416xx/src/eth/tx128to255oct_gb.rs new file mode 100644 index 0000000..021b3d8 --- /dev/null +++ b/va416xx/src/eth/tx128to255oct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TX128TO255OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 128 to 255\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx128to255oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx128to255octGbSpec; +impl crate::RegisterSpec for Tx128to255octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx128to255oct_gb::R`](R) reader structure"] +impl crate::Readable for Tx128to255octGbSpec {} +#[doc = "`reset()` method sets TX128TO255OCT_GB to value 0"] +impl crate::Resettable for Tx128to255octGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/tx256to511oct_gb.rs b/va416xx/src/eth/tx256to511oct_gb.rs new file mode 100644 index 0000000..f131a58 --- /dev/null +++ b/va416xx/src/eth/tx256to511oct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TX256TO511OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 256 to 511\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx256to511oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx256to511octGbSpec; +impl crate::RegisterSpec for Tx256to511octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx256to511oct_gb::R`](R) reader structure"] +impl crate::Readable for Tx256to511octGbSpec {} +#[doc = "`reset()` method sets TX256TO511OCT_GB to value 0"] +impl crate::Resettable for Tx256to511octGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/tx512to1023oct_gb.rs b/va416xx/src/eth/tx512to1023oct_gb.rs new file mode 100644 index 0000000..e0451c5 --- /dev/null +++ b/va416xx/src/eth/tx512to1023oct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TX512TO1023OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 512 to 1023\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx512to1023oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx512to1023octGbSpec; +impl crate::RegisterSpec for Tx512to1023octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx512to1023oct_gb::R`](R) reader structure"] +impl crate::Readable for Tx512to1023octGbSpec {} +#[doc = "`reset()` method sets TX512TO1023OCT_GB to value 0"] +impl crate::Resettable for Tx512to1023octGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/tx64oct_gb.rs b/va416xx/src/eth/tx64oct_gb.rs new file mode 100644 index 0000000..ed2432d --- /dev/null +++ b/va416xx/src/eth/tx64oct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TX64OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 64\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx64oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx64octGbSpec; +impl crate::RegisterSpec for Tx64octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx64oct_gb::R`](R) reader structure"] +impl crate::Readable for Tx64octGbSpec {} +#[doc = "`reset()` method sets TX64OCT_GB to value 0"] +impl crate::Resettable for Tx64octGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/tx65to127oct_gb.rs b/va416xx/src/eth/tx65to127oct_gb.rs new file mode 100644 index 0000000..9a36048 --- /dev/null +++ b/va416xx/src/eth/tx65to127oct_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TX65TO127OCT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good and bad Frames transmitted with length 65 to 127\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tx65to127oct_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Tx65to127octGbSpec; +impl crate::RegisterSpec for Tx65to127octGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tx65to127oct_gb::R`](R) reader structure"] +impl crate::Readable for Tx65to127octGbSpec {} +#[doc = "`reset()` method sets TX65TO127OCT_GB to value 0"] +impl crate::Resettable for Tx65to127octGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txbcastframe_gb.rs b/va416xx/src/eth/txbcastframe_gb.rs new file mode 100644 index 0000000..650735f --- /dev/null +++ b/va416xx/src/eth/txbcastframe_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXBCASTFRAME_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC number of good and bad broadcast frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcastframe_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxbcastframeGbSpec; +impl crate::RegisterSpec for TxbcastframeGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txbcastframe_gb::R`](R) reader structure"] +impl crate::Readable for TxbcastframeGbSpec {} +#[doc = "`reset()` method sets TXBCASTFRAME_GB to value 0"] +impl crate::Resettable for TxbcastframeGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txbcastframes_g.rs b/va416xx/src/eth/txbcastframes_g.rs new file mode 100644 index 0000000..6ad1301 --- /dev/null +++ b/va416xx/src/eth/txbcastframes_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXBCASTFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good Broadcast Frames Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txbcastframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxbcastframesGSpec; +impl crate::RegisterSpec for TxbcastframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txbcastframes_g::R`](R) reader structure"] +impl crate::Readable for TxbcastframesGSpec {} +#[doc = "`reset()` method sets TXBCASTFRAMES_G to value 0"] +impl crate::Resettable for TxbcastframesGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txcarriererror.rs b/va416xx/src/eth/txcarriererror.rs new file mode 100644 index 0000000..48b8c3e --- /dev/null +++ b/va416xx/src/eth/txcarriererror.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXCARRIERERROR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of aborted frames because of carrier sense error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcarriererror::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxcarriererrorSpec; +impl crate::RegisterSpec for TxcarriererrorSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txcarriererror::R`](R) reader structure"] +impl crate::Readable for TxcarriererrorSpec {} +#[doc = "`reset()` method sets TXCARRIERERROR to value 0"] +impl crate::Resettable for TxcarriererrorSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txdeferred.rs b/va416xx/src/eth/txdeferred.rs new file mode 100644 index 0000000..879b8e9 --- /dev/null +++ b/va416xx/src/eth/txdeferred.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXDEFERRED` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of successfully transmitted frames after a deferral\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txdeferred::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxdeferredSpec; +impl crate::RegisterSpec for TxdeferredSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txdeferred::R`](R) reader structure"] +impl crate::Readable for TxdeferredSpec {} +#[doc = "`reset()` method sets TXDEFERRED to value 0"] +impl crate::Resettable for TxdeferredSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txexcessdef.rs b/va416xx/src/eth/txexcessdef.rs new file mode 100644 index 0000000..49dba0b --- /dev/null +++ b/va416xx/src/eth/txexcessdef.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXEXCESSDEF` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames aborted because of excessive deferral error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txexcessdef::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxexcessdefSpec; +impl crate::RegisterSpec for TxexcessdefSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txexcessdef::R`](R) reader structure"] +impl crate::Readable for TxexcessdefSpec {} +#[doc = "`reset()` method sets TXEXCESSDEF to value 0"] +impl crate::Resettable for TxexcessdefSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txexesscol.rs b/va416xx/src/eth/txexesscol.rs new file mode 100644 index 0000000..1fda568 --- /dev/null +++ b/va416xx/src/eth/txexesscol.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXEXESSCOL` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of aborted frames because of excessive collision errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txexesscol::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxexesscolSpec; +impl crate::RegisterSpec for TxexesscolSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txexesscol::R`](R) reader structure"] +impl crate::Readable for TxexesscolSpec {} +#[doc = "`reset()` method sets TXEXESSCOL to value 0"] +impl crate::Resettable for TxexesscolSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txframecount_g.rs b/va416xx/src/eth/txframecount_g.rs new file mode 100644 index 0000000..1828751 --- /dev/null +++ b/va416xx/src/eth/txframecount_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXFRAMECOUNT_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txframecount_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxframecountGSpec; +impl crate::RegisterSpec for TxframecountGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txframecount_g::R`](R) reader structure"] +impl crate::Readable for TxframecountGSpec {} +#[doc = "`reset()` method sets TXFRAMECOUNT_G to value 0"] +impl crate::Resettable for TxframecountGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txframecount_gb.rs b/va416xx/src/eth/txframecount_gb.rs new file mode 100644 index 0000000..7327de5 --- /dev/null +++ b/va416xx/src/eth/txframecount_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXFRAMECOUNT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Frame Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txframecount_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxframecountGbSpec; +impl crate::RegisterSpec for TxframecountGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txframecount_gb::R`](R) reader structure"] +impl crate::Readable for TxframecountGbSpec {} +#[doc = "`reset()` method sets TXFRAMECOUNT_GB to value 0"] +impl crate::Resettable for TxframecountGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txlanframes_g.rs b/va416xx/src/eth/txlanframes_g.rs new file mode 100644 index 0000000..3006719 --- /dev/null +++ b/va416xx/src/eth/txlanframes_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXLANFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good VLAN frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txlanframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxlanframesGSpec; +impl crate::RegisterSpec for TxlanframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txlanframes_g::R`](R) reader structure"] +impl crate::Readable for TxlanframesGSpec {} +#[doc = "`reset()` method sets TXLANFRAMES_G to value 0"] +impl crate::Resettable for TxlanframesGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txlatecol.rs b/va416xx/src/eth/txlatecol.rs new file mode 100644 index 0000000..2041d11 --- /dev/null +++ b/va416xx/src/eth/txlatecol.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXLATECOL` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of aborted frames because of late collision error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txlatecol::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxlatecolSpec; +impl crate::RegisterSpec for TxlatecolSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txlatecol::R`](R) reader structure"] +impl crate::Readable for TxlatecolSpec {} +#[doc = "`reset()` method sets TXLATECOL to value 0"] +impl crate::Resettable for TxlatecolSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txmcastframe_gb.rs b/va416xx/src/eth/txmcastframe_gb.rs new file mode 100644 index 0000000..478ff2c --- /dev/null +++ b/va416xx/src/eth/txmcastframe_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXMCASTFRAME_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC number of good and bad MULTIcast frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txmcastframe_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxmcastframeGbSpec; +impl crate::RegisterSpec for TxmcastframeGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txmcastframe_gb::R`](R) reader structure"] +impl crate::Readable for TxmcastframeGbSpec {} +#[doc = "`reset()` method sets TXMCASTFRAME_GB to value 0"] +impl crate::Resettable for TxmcastframeGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txmcastframes_g.rs b/va416xx/src/eth/txmcastframes_g.rs new file mode 100644 index 0000000..b165a17 --- /dev/null +++ b/va416xx/src/eth/txmcastframes_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXMCASTFRAMES_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Good Multicast Frames Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txmcastframes_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxmcastframesGSpec; +impl crate::RegisterSpec for TxmcastframesGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txmcastframes_g::R`](R) reader structure"] +impl crate::Readable for TxmcastframesGSpec {} +#[doc = "`reset()` method sets TXMCASTFRAMES_G to value 0"] +impl crate::Resettable for TxmcastframesGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txmulticol_g.rs b/va416xx/src/eth/txmulticol_g.rs new file mode 100644 index 0000000..6d1c3a3 --- /dev/null +++ b/va416xx/src/eth/txmulticol_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXMULTICOL_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of successfully transmitted frames after multiple collisions\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txmulticol_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxmulticolGSpec; +impl crate::RegisterSpec for TxmulticolGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txmulticol_g::R`](R) reader structure"] +impl crate::Readable for TxmulticolGSpec {} +#[doc = "`reset()` method sets TXMULTICOL_G to value 0"] +impl crate::Resettable for TxmulticolGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txoctetcount_g.rs b/va416xx/src/eth/txoctetcount_g.rs new file mode 100644 index 0000000..d48556e --- /dev/null +++ b/va416xx/src/eth/txoctetcount_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXOCTETCOUNT_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of bytes"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of bytes transmitted frames only in good frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txoctetcount_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxoctetcountGSpec; +impl crate::RegisterSpec for TxoctetcountGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txoctetcount_g::R`](R) reader structure"] +impl crate::Readable for TxoctetcountGSpec {} +#[doc = "`reset()` method sets TXOCTETCOUNT_G to value 0"] +impl crate::Resettable for TxoctetcountGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txoctetcount_gb.rs b/va416xx/src/eth/txoctetcount_gb.rs new file mode 100644 index 0000000..77d2143 --- /dev/null +++ b/va416xx/src/eth/txoctetcount_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXOCTETCOUNT_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of bytes"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of bytes"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Transmit Count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txoctetcount_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxoctetcountGbSpec; +impl crate::RegisterSpec for TxoctetcountGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txoctetcount_gb::R`](R) reader structure"] +impl crate::Readable for TxoctetcountGbSpec {} +#[doc = "`reset()` method sets TXOCTETCOUNT_GB to value 0"] +impl crate::Resettable for TxoctetcountGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txoversize_g.rs b/va416xx/src/eth/txoversize_g.rs new file mode 100644 index 0000000..df066e9 --- /dev/null +++ b/va416xx/src/eth/txoversize_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXOVERSIZE_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of frames transmitted without errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txoversize_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxoversizeGSpec; +impl crate::RegisterSpec for TxoversizeGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txoversize_g::R`](R) reader structure"] +impl crate::Readable for TxoversizeGSpec {} +#[doc = "`reset()` method sets TXOVERSIZE_G to value 0"] +impl crate::Resettable for TxoversizeGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txpauseframes.rs b/va416xx/src/eth/txpauseframes.rs new file mode 100644 index 0000000..e495689 --- /dev/null +++ b/va416xx/src/eth/txpauseframes.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXPAUSEFRAMES` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of good pause frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txpauseframes::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxpauseframesSpec; +impl crate::RegisterSpec for TxpauseframesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txpauseframes::R`](R) reader structure"] +impl crate::Readable for TxpauseframesSpec {} +#[doc = "`reset()` method sets TXPAUSEFRAMES to value 0"] +impl crate::Resettable for TxpauseframesSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txsinglecol_g.rs b/va416xx/src/eth/txsinglecol_g.rs new file mode 100644 index 0000000..4fc0ccf --- /dev/null +++ b/va416xx/src/eth/txsinglecol_g.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXSINGLECOL_G` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC Number of successfully transmitted frames after a single collision\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txsinglecol_g::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxsinglecolGSpec; +impl crate::RegisterSpec for TxsinglecolGSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txsinglecol_g::R`](R) reader structure"] +impl crate::Readable for TxsinglecolGSpec {} +#[doc = "`reset()` method sets TXSINGLECOL_G to value 0"] +impl crate::Resettable for TxsinglecolGSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txucastframe_gb.rs b/va416xx/src/eth/txucastframe_gb.rs new file mode 100644 index 0000000..951c3d9 --- /dev/null +++ b/va416xx/src/eth/txucastframe_gb.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXUCASTFRAME_GB` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC number of good and bad unicast frames transmitted\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txucastframe_gb::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxucastframeGbSpec; +impl crate::RegisterSpec for TxucastframeGbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txucastframe_gb::R`](R) reader structure"] +impl crate::Readable for TxucastframeGbSpec {} +#[doc = "`reset()` method sets TXUCASTFRAME_GB to value 0"] +impl crate::Resettable for TxucastframeGbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/txundererr.rs b/va416xx/src/eth/txundererr.rs new file mode 100644 index 0000000..03d9c8f --- /dev/null +++ b/va416xx/src/eth/txundererr.rs @@ -0,0 +1,22 @@ +#[doc = "Register `TXUNDERERR` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Number of frames"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Number of frames"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new(self.bits) + } +} +#[doc = "MMC number of frames aborted because of frame underflow error\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txundererr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxundererrSpec; +impl crate::RegisterSpec for TxundererrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txundererr::R`](R) reader structure"] +impl crate::Readable for TxundererrSpec {} +#[doc = "`reset()` method sets TXUNDERERR to value 0"] +impl crate::Resettable for TxundererrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/vlan_hashtable.rs b/va416xx/src/eth/vlan_hashtable.rs new file mode 100644 index 0000000..f6166d5 --- /dev/null +++ b/va416xx/src/eth/vlan_hashtable.rs @@ -0,0 +1,40 @@ +#[doc = "Register `VLAN_HASHTABLE` reader"] +pub type R = crate::R; +#[doc = "Register `VLAN_HASHTABLE` writer"] +pub type W = crate::W; +#[doc = "Field `VLHT` reader - VLAN Hash Table"] +pub type VlhtR = crate::FieldReader; +#[doc = "Field `VLHT` writer - VLAN Hash Table"] +pub type VlhtW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - VLAN Hash Table"] + #[inline(always)] + pub fn vlht(&self) -> VlhtR { + VlhtR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - VLAN Hash Table"] + #[inline(always)] + #[must_use] + pub fn vlht(&mut self) -> VlhtW { + VlhtW::new(self, 0) + } +} +#[doc = "Holds the VLAN Hash Table\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vlan_hashtable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vlan_hashtable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VlanHashtableSpec; +impl crate::RegisterSpec for VlanHashtableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`vlan_hashtable::R`](R) reader structure"] +impl crate::Readable for VlanHashtableSpec {} +#[doc = "`write(|w| ..)` method takes [`vlan_hashtable::W`](W) writer structure"] +impl crate::Writable for VlanHashtableSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets VLAN_HASHTABLE to value 0"] +impl crate::Resettable for VlanHashtableSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/eth/vlan_increplace.rs b/va416xx/src/eth/vlan_increplace.rs new file mode 100644 index 0000000..d733b5a --- /dev/null +++ b/va416xx/src/eth/vlan_increplace.rs @@ -0,0 +1,85 @@ +#[doc = "Register `VLAN_INCREPLACE` reader"] +pub type R = crate::R; +#[doc = "Register `VLAN_INCREPLACE` writer"] +pub type W = crate::W; +#[doc = "Field `VLT` reader - VLAN Tag for Transmit Frames"] +pub type VltR = crate::FieldReader; +#[doc = "Field `VLT` writer - VLAN Tag for Transmit Frames"] +pub type VltW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `VLC` reader - VLAN Tag Control in Transmit Frames"] +pub type VlcR = crate::FieldReader; +#[doc = "Field `VLC` writer - VLAN Tag Control in Transmit Frames"] +pub type VlcW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `VLP` reader - VLAN Priority Control"] +pub type VlpR = crate::BitReader; +#[doc = "Field `VLP` writer - VLAN Priority Control"] +pub type VlpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSVL` reader - C-VLAN or S-VLAN"] +pub type CsvlR = crate::BitReader; +#[doc = "Field `CSVL` writer - C-VLAN or S-VLAN"] +pub type CsvlW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - VLAN Tag for Transmit Frames"] + #[inline(always)] + pub fn vlt(&self) -> VltR { + VltR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:17 - VLAN Tag Control in Transmit Frames"] + #[inline(always)] + pub fn vlc(&self) -> VlcR { + VlcR::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - VLAN Priority Control"] + #[inline(always)] + pub fn vlp(&self) -> VlpR { + VlpR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - C-VLAN or S-VLAN"] + #[inline(always)] + pub fn csvl(&self) -> CsvlR { + CsvlR::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - VLAN Tag for Transmit Frames"] + #[inline(always)] + #[must_use] + pub fn vlt(&mut self) -> VltW { + VltW::new(self, 0) + } + #[doc = "Bits 16:17 - VLAN Tag Control in Transmit Frames"] + #[inline(always)] + #[must_use] + pub fn vlc(&mut self) -> VlcW { + VlcW::new(self, 16) + } + #[doc = "Bit 18 - VLAN Priority Control"] + #[inline(always)] + #[must_use] + pub fn vlp(&mut self) -> VlpW { + VlpW::new(self, 18) + } + #[doc = "Bit 19 - C-VLAN or S-VLAN"] + #[inline(always)] + #[must_use] + pub fn csvl(&mut self) -> CsvlW { + CsvlW::new(self, 19) + } +} +#[doc = "Holds the VLAN Tag for insertion into or replacement in the transmit frames\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vlan_increplace::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vlan_increplace::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct VlanIncreplaceSpec; +impl crate::RegisterSpec for VlanIncreplaceSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`vlan_increplace::R`](R) reader structure"] +impl crate::Readable for VlanIncreplaceSpec {} +#[doc = "`write(|w| ..)` method takes [`vlan_increplace::W`](W) writer structure"] +impl crate::Writable for VlanIncreplaceSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets VLAN_INCREPLACE to value 0"] +impl crate::Resettable for VlanIncreplaceSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/generic.rs b/va416xx/src/generic.rs new file mode 100644 index 0000000..45ebed1 --- /dev/null +++ b/va416xx/src/generic.rs @@ -0,0 +1,618 @@ +use core::marker; +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + Default + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " Mask for bits of width 1"] + fn one() -> Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + #[inline(always)] + fn one() -> Self { + 1 + } + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + impl FieldSpec for $U { + type Ux = $U; + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Raw field type"] +pub trait FieldSpec: Sized { + #[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."] + type Ux: Copy + core::fmt::Debug + PartialEq + From; +} +#[doc = " Marker for fields with fixed values"] +pub trait IsEnum: FieldSpec {} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec {} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Is it safe to write any bits to register"] + type Safety; + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> R { + R { + bits: self.register.get(), + _reg: marker::PhantomData, + } + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }) + .bits, + ); + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut W) -> &mut W, + { + self.register.set( + f(&mut W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + }) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + &R { + bits, + _reg: marker::PhantomData, + }, + &mut W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }, + ) + .bits, + ); + } +} +impl core::fmt::Debug for crate::generic::Reg +where + R: core::fmt::Debug, +{ + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.read(), f) + } +} +#[doc(hidden)] +pub mod raw; +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub type R = raw::R; +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub const fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub type W = raw::W; +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +impl W +where + REG: Writable, +{ + #[doc = " Writes raw bits to the register."] + #[inline(always)] + pub fn set(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = raw::FieldReader; +#[doc = " Bit-wise field reader"] +pub type BitReader = raw::BitReader; +impl FieldReader { + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub const fn bits(&self) -> FI::Ux { + self.bits + } +} +impl core::fmt::Debug for FieldReader { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.bits, f) + } +} +impl PartialEq for FieldReader +where + FI: FieldSpec + Copy, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&FI::Ux::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub const fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub const fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub const fn bit_is_set(&self) -> bool { + self.bit() + } +} +impl core::fmt::Debug for BitReader { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + core::fmt::Debug::fmt(&self.bits, f) + } +} +#[doc = " Marker for register/field writers which can take any value of specified width"] +pub struct Safe; +#[doc = " You should check that value is allowed to pass to register/field writer marked with this"] +pub struct Unsafe; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct Range; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct RangeFrom; +#[doc = " Marker for field writers are safe to write in specified inclusive range"] +pub struct RangeTo; +#[doc = " Write field Proxy"] +pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> = + raw::FieldWriter<'a, REG, WI, FI, Safety>; +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + WI + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W { + self.w.bits &= !(REG::Ux::mask::() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::()) << self.o; + self.w + } +} +impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64> + FieldWriter<'a, REG, WI, FI, Range> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value >= MIN && value <= MAX); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value >= MIN); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, + REG::Ux: From, + u64: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn set(self, value: FI::Ux) -> &'a mut W { + { + let value = u64::from(value); + assert!(value <= MAX); + } + unsafe { self.bits(value) } + } +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: IsEnum, + REG::Ux: From, +{ + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + unsafe { self.bits(FI::Ux::from(variant)) } + } +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>; + impl<'a, REG, FI> $writer<'a, REG, FI> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + #[doc = " Field width"] + #[inline(always)] + pub const fn width(&self) -> u8 { + Self::WIDTH + } + #[doc = " Field offset"] + #[inline(always)] + pub const fn offset(&self) -> u8 { + self.o + } + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut W { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, REG, FI> BitWriter<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1C<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0S<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} +impl<'a, REG, FI> BitWriter1T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits |= REG::Ux::one() << self.o; + self.w + } +} +impl<'a, REG, FI> BitWriter0T<'a, REG, FI> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut W { + self.w.bits &= !(REG::Ux::one() << self.o); + self.w + } +} diff --git a/va416xx/src/generic/raw.rs b/va416xx/src/generic/raw.rs new file mode 100644 index 0000000..81f5779 --- /dev/null +++ b/va416xx/src/generic/raw.rs @@ -0,0 +1,93 @@ +use super::{marker, BitM, FieldSpec, RegisterSpec, Unsafe, Writable}; +pub struct R { + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + pub(super) _reg: marker::PhantomData, +} +pub struct FieldReader +where + FI: FieldSpec, +{ + pub(crate) bits: FI::Ux, + _reg: marker::PhantomData, +} +impl FieldReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: FI::Ux) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct BitReader { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReader { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) const fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, Safety)>, +} +impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety> +where + REG: Writable + RegisterSpec, + FI: FieldSpec, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} +pub struct BitWriter<'a, REG, FI = bool, M = BitM> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut W, + pub(crate) o: u8, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut W, o: u8) -> Self { + Self { + w, + o, + _field: marker::PhantomData, + } + } +} diff --git a/va416xx/src/i2c0.rs b/va416xx/src/i2c0.rs new file mode 100644 index 0000000..2492ae0 --- /dev/null +++ b/va416xx/src/i2c0.rs @@ -0,0 +1,452 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + clkscale: Clkscale, + words: Words, + address: Address, + data: Data, + cmd: Cmd, + status: Status, + state: State, + txcount: Txcount, + rxcount: Rxcount, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + txfifoirqtrg: Txfifoirqtrg, + fifo_clr: FifoClr, + tmconfig: Tmconfig, + clktolimit: Clktolimit, + _reserved19: [u8; 0xb4], + s0_ctrl: S0Ctrl, + s0_maxwords: S0Maxwords, + s0_address: S0Address, + s0_addressmask: S0Addressmask, + s0_data: S0Data, + s0_lastaddress: S0Lastaddress, + s0_status: S0Status, + s0_state: S0State, + s0_txcount: S0Txcount, + s0_rxcount: S0Rxcount, + s0_irq_enb: S0IrqEnb, + s0_irq_raw: S0IrqRaw, + s0_irq_end: S0IrqEnd, + s0_irq_clr: S0IrqClr, + s0_rxfifoirqtrg: S0Rxfifoirqtrg, + s0_txfifoirqtrg: S0Txfifoirqtrg, + s0_fifo_clr: S0FifoClr, + s0_addressb: S0Addressb, + s0_addressmaskb: S0Addressmaskb, + _reserved38: [u8; 0x02b0], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - Clock Scale divide value"] + #[inline(always)] + pub const fn clkscale(&self) -> &Clkscale { + &self.clkscale + } + #[doc = "0x08 - Word Count value"] + #[inline(always)] + pub const fn words(&self) -> &Words { + &self.words + } + #[doc = "0x0c - I2C Address value"] + #[inline(always)] + pub const fn address(&self) -> &Address { + &self.address + } + #[doc = "0x10 - Data Input/Output"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x14 - Command Register"] + #[inline(always)] + pub const fn cmd(&self) -> &Cmd { + &self.cmd + } + #[doc = "0x18 - I2C Controller Status Register"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x1c - Internal STATE of I2C Master Controller"] + #[inline(always)] + pub const fn state(&self) -> &State { + &self.state + } + #[doc = "0x20 - TX Count Register"] + #[inline(always)] + pub const fn txcount(&self) -> &Txcount { + &self.txcount + } + #[doc = "0x24 - RX Count Register"] + #[inline(always)] + pub const fn rxcount(&self) -> &Rxcount { + &self.rxcount + } + #[doc = "0x28 - Interrupt Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x2c - Raw Interrupt Status Register"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x30 - Enabled Interrupt Status Register"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x34 - Clear Interrupt Status Register"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x38 - Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x3c - Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x40 - Clear FIFO Register"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x44 - Timing Config Register"] + #[inline(always)] + pub const fn tmconfig(&self) -> &Tmconfig { + &self.tmconfig + } + #[doc = "0x48 - Clock Low Timeout Limit Register"] + #[inline(always)] + pub const fn clktolimit(&self) -> &Clktolimit { + &self.clktolimit + } + #[doc = "0x100 - Slave Control Register"] + #[inline(always)] + pub const fn s0_ctrl(&self) -> &S0Ctrl { + &self.s0_ctrl + } + #[doc = "0x104 - Slave MaxWords Register"] + #[inline(always)] + pub const fn s0_maxwords(&self) -> &S0Maxwords { + &self.s0_maxwords + } + #[doc = "0x108 - Slave I2C Address Value"] + #[inline(always)] + pub const fn s0_address(&self) -> &S0Address { + &self.s0_address + } + #[doc = "0x10c - Slave I2C Address Mask value"] + #[inline(always)] + pub const fn s0_addressmask(&self) -> &S0Addressmask { + &self.s0_addressmask + } + #[doc = "0x110 - Slave Data Input/Output"] + #[inline(always)] + pub const fn s0_data(&self) -> &S0Data { + &self.s0_data + } + #[doc = "0x114 - Slave I2C Last Address value"] + #[inline(always)] + pub const fn s0_lastaddress(&self) -> &S0Lastaddress { + &self.s0_lastaddress + } + #[doc = "0x118 - Slave I2C Controller Status Register"] + #[inline(always)] + pub const fn s0_status(&self) -> &S0Status { + &self.s0_status + } + #[doc = "0x11c - Internal STATE of I2C Slave Controller"] + #[inline(always)] + pub const fn s0_state(&self) -> &S0State { + &self.s0_state + } + #[doc = "0x120 - Slave TX Count Register"] + #[inline(always)] + pub const fn s0_txcount(&self) -> &S0Txcount { + &self.s0_txcount + } + #[doc = "0x124 - Slave RX Count Register"] + #[inline(always)] + pub const fn s0_rxcount(&self) -> &S0Rxcount { + &self.s0_rxcount + } + #[doc = "0x128 - Slave Interrupt Enable Register"] + #[inline(always)] + pub const fn s0_irq_enb(&self) -> &S0IrqEnb { + &self.s0_irq_enb + } + #[doc = "0x12c - Slave Raw Interrupt Status Register"] + #[inline(always)] + pub const fn s0_irq_raw(&self) -> &S0IrqRaw { + &self.s0_irq_raw + } + #[doc = "0x130 - Slave Enabled Interrupt Status Register"] + #[inline(always)] + pub const fn s0_irq_end(&self) -> &S0IrqEnd { + &self.s0_irq_end + } + #[doc = "0x134 - Slave Clear Interrupt Status Register"] + #[inline(always)] + pub const fn s0_irq_clr(&self) -> &S0IrqClr { + &self.s0_irq_clr + } + #[doc = "0x138 - Slave Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn s0_rxfifoirqtrg(&self) -> &S0Rxfifoirqtrg { + &self.s0_rxfifoirqtrg + } + #[doc = "0x13c - Slave Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn s0_txfifoirqtrg(&self) -> &S0Txfifoirqtrg { + &self.s0_txfifoirqtrg + } + #[doc = "0x140 - Slave Clear FIFO Register"] + #[inline(always)] + pub const fn s0_fifo_clr(&self) -> &S0FifoClr { + &self.s0_fifo_clr + } + #[doc = "0x144 - Slave I2C Address B Value"] + #[inline(always)] + pub const fn s0_addressb(&self) -> &S0Addressb { + &self.s0_addressb + } + #[doc = "0x148 - Slave I2C Address B Mask value"] + #[inline(always)] + pub const fn s0_addressmaskb(&self) -> &S0Addressmaskb { + &self.s0_addressmaskb + } + #[doc = "0x3fc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] +module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] +module"] +#[doc(alias = "CLKSCALE")] +pub type Clkscale = crate::Reg; +#[doc = "Clock Scale divide value"] +pub mod clkscale; +#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`] +module"] +#[doc(alias = "WORDS")] +pub type Words = crate::Reg; +#[doc = "Word Count value"] +pub mod words; +#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`] +module"] +#[doc(alias = "ADDRESS")] +pub type Address = crate::Reg; +#[doc = "I2C Address value"] +pub mod address; +#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] +module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data Input/Output"] +pub mod data; +#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] +module"] +#[doc(alias = "CMD")] +pub type Cmd = crate::Reg; +#[doc = "Command Register"] +pub mod cmd; +#[doc = "STATUS (rw) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] +module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "I2C Controller Status Register"] +pub mod status; +#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] +module"] +#[doc(alias = "STATE")] +pub type State = crate::Reg; +#[doc = "Internal STATE of I2C Master Controller"] +pub mod state; +#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`] +module"] +#[doc(alias = "TXCOUNT")] +pub type Txcount = crate::Reg; +#[doc = "TX Count Register"] +pub mod txcount; +#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`] +module"] +#[doc(alias = "RXCOUNT")] +pub type Rxcount = crate::Reg; +#[doc = "RX Count Register"] +pub mod rxcount; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] +module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] +module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] +module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] +module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`] +module"] +#[doc(alias = "TMCONFIG")] +pub type Tmconfig = crate::Reg; +#[doc = "Timing Config Register"] +pub mod tmconfig; +#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`] +module"] +#[doc(alias = "CLKTOLIMIT")] +pub type Clktolimit = crate::Reg; +#[doc = "Clock Low Timeout Limit Register"] +pub mod clktolimit; +#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`] +module"] +#[doc(alias = "S0_CTRL")] +pub type S0Ctrl = crate::Reg; +#[doc = "Slave Control Register"] +pub mod s0_ctrl; +#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`] +module"] +#[doc(alias = "S0_MAXWORDS")] +pub type S0Maxwords = crate::Reg; +#[doc = "Slave MaxWords Register"] +pub mod s0_maxwords; +#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`] +module"] +#[doc(alias = "S0_ADDRESS")] +pub type S0Address = crate::Reg; +#[doc = "Slave I2C Address Value"] +pub mod s0_address; +#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`] +module"] +#[doc(alias = "S0_ADDRESSMASK")] +pub type S0Addressmask = crate::Reg; +#[doc = "Slave I2C Address Mask value"] +pub mod s0_addressmask; +#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`] +module"] +#[doc(alias = "S0_DATA")] +pub type S0Data = crate::Reg; +#[doc = "Slave Data Input/Output"] +pub mod s0_data; +#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`] +module"] +#[doc(alias = "S0_LASTADDRESS")] +pub type S0Lastaddress = crate::Reg; +#[doc = "Slave I2C Last Address value"] +pub mod s0_lastaddress; +#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`] +module"] +#[doc(alias = "S0_STATUS")] +pub type S0Status = crate::Reg; +#[doc = "Slave I2C Controller Status Register"] +pub mod s0_status; +#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`] +module"] +#[doc(alias = "S0_STATE")] +pub type S0State = crate::Reg; +#[doc = "Internal STATE of I2C Slave Controller"] +pub mod s0_state; +#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`] +module"] +#[doc(alias = "S0_TXCOUNT")] +pub type S0Txcount = crate::Reg; +#[doc = "Slave TX Count Register"] +pub mod s0_txcount; +#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`] +module"] +#[doc(alias = "S0_RXCOUNT")] +pub type S0Rxcount = crate::Reg; +#[doc = "Slave RX Count Register"] +pub mod s0_rxcount; +#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`] +module"] +#[doc(alias = "S0_IRQ_ENB")] +pub type S0IrqEnb = crate::Reg; +#[doc = "Slave Interrupt Enable Register"] +pub mod s0_irq_enb; +pub use s0_irq_enb as s0_irq_raw; +pub use s0_irq_enb as s0_irq_end; +pub use s0_irq_enb as s0_irq_clr; +pub use S0IrqEnb as S0IrqRaw; +pub use S0IrqEnb as S0IrqEnd; +pub use S0IrqEnb as S0IrqClr; +#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`] +module"] +#[doc(alias = "S0_RXFIFOIRQTRG")] +pub type S0Rxfifoirqtrg = crate::Reg; +#[doc = "Slave Rx FIFO IRQ Trigger Level"] +pub mod s0_rxfifoirqtrg; +#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`] +module"] +#[doc(alias = "S0_TXFIFOIRQTRG")] +pub type S0Txfifoirqtrg = crate::Reg; +#[doc = "Slave Tx FIFO IRQ Trigger Level"] +pub mod s0_txfifoirqtrg; +#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`] +module"] +#[doc(alias = "S0_FIFO_CLR")] +pub type S0FifoClr = crate::Reg; +#[doc = "Slave Clear FIFO Register"] +pub mod s0_fifo_clr; +#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`] +module"] +#[doc(alias = "S0_ADDRESSB")] +pub type S0Addressb = crate::Reg; +#[doc = "Slave I2C Address B Value"] +pub mod s0_addressb; +#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`] +module"] +#[doc(alias = "S0_ADDRESSMASKB")] +pub type S0Addressmaskb = crate::Reg; +#[doc = "Slave I2C Address B Mask value"] +pub mod s0_addressmaskb; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/i2c0/address.rs b/va416xx/src/i2c0/address.rs new file mode 100644 index 0000000..4733ce9 --- /dev/null +++ b/va416xx/src/i2c0/address.rs @@ -0,0 +1,27 @@ +#[doc = "Register `ADDRESS` reader"] +pub type R = crate::R; +#[doc = "Register `ADDRESS` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "I2C Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`address::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AddressSpec; +impl crate::RegisterSpec for AddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`address::R`](R) reader structure"] +impl crate::Readable for AddressSpec {} +#[doc = "`write(|w| ..)` method takes [`address::W`](W) writer structure"] +impl crate::Writable for AddressSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ADDRESS to value 0"] +impl crate::Resettable for AddressSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/clkscale.rs b/va416xx/src/i2c0/clkscale.rs new file mode 100644 index 0000000..ad9dbd5 --- /dev/null +++ b/va416xx/src/i2c0/clkscale.rs @@ -0,0 +1,55 @@ +#[doc = "Register `CLKSCALE` reader"] +pub type R = crate::R; +#[doc = "Register `CLKSCALE` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` reader - Enable FastMode"] +pub type ValueR = crate::FieldReader; +#[doc = "Field `VALUE` writer - Enable FastMode"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 31, u32>; +#[doc = "Field `FASTMODE` reader - Enable FastMode"] +pub type FastmodeR = crate::BitReader; +#[doc = "Field `FASTMODE` writer - Enable FastMode"] +pub type FastmodeW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:30 - Enable FastMode"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new(self.bits & 0x7fff_ffff) + } + #[doc = "Bit 31 - Enable FastMode"] + #[inline(always)] + pub fn fastmode(&self) -> FastmodeR { + FastmodeR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:30 - Enable FastMode"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> ValueW { + ValueW::new(self, 0) + } + #[doc = "Bit 31 - Enable FastMode"] + #[inline(always)] + #[must_use] + pub fn fastmode(&mut self) -> FastmodeW { + FastmodeW::new(self, 31) + } +} +#[doc = "Clock Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkscaleSpec; +impl crate::RegisterSpec for ClkscaleSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkscale::R`](R) reader structure"] +impl crate::Readable for ClkscaleSpec {} +#[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"] +impl crate::Writable for ClkscaleSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKSCALE to value 0"] +impl crate::Resettable for ClkscaleSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/clktolimit.rs b/va416xx/src/i2c0/clktolimit.rs new file mode 100644 index 0000000..2c0569d --- /dev/null +++ b/va416xx/src/i2c0/clktolimit.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CLKTOLIMIT` reader"] +pub type R = crate::R; +#[doc = "Register `CLKTOLIMIT` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock Low Timeout Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clktolimit::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clktolimit::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClktolimitSpec; +impl crate::RegisterSpec for ClktolimitSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clktolimit::R`](R) reader structure"] +impl crate::Readable for ClktolimitSpec {} +#[doc = "`write(|w| ..)` method takes [`clktolimit::W`](W) writer structure"] +impl crate::Writable for ClktolimitSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKTOLIMIT to value 0"] +impl crate::Resettable for ClktolimitSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/cmd.rs b/va416xx/src/i2c0/cmd.rs new file mode 100644 index 0000000..aee7ef2 --- /dev/null +++ b/va416xx/src/i2c0/cmd.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CMD` reader"] +pub type R = crate::R; +#[doc = "Register `CMD` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CmdSpec; +impl crate::RegisterSpec for CmdSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cmd::R`](R) reader structure"] +impl crate::Readable for CmdSpec {} +#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"] +impl crate::Writable for CmdSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CMD to value 0"] +impl crate::Resettable for CmdSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/ctrl.rs b/va416xx/src/i2c0/ctrl.rs new file mode 100644 index 0000000..203c9d3 --- /dev/null +++ b/va416xx/src/i2c0/ctrl.rs @@ -0,0 +1,160 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CLKENABLED` reader - I2C CLK Enabled"] +pub type ClkenabledR = crate::BitReader; +#[doc = "Field `CLKENABLED` writer - I2C CLK Enabled"] +pub type ClkenabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - I2C Activated"] +pub type EnabledR = crate::BitReader; +#[doc = "Field `ENABLED` writer - I2C Activated"] +pub type EnabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - I2C Active"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - I2C Active"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"] +pub type TxfemdR = crate::BitReader; +#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"] +pub type TxfemdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"] +pub type RxffmdR = crate::BitReader; +#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"] +pub type RxffmdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ALGFILTER` reader - Enable Input Analog Glitch Filter"] +pub type AlgfilterR = crate::BitReader; +#[doc = "Field `ALGFILTER` writer - Enable Input Analog Glitch Filter"] +pub type AlgfilterW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DLGFILTER` reader - Enable Input Digital Glitch Filter"] +pub type DlgfilterR = crate::BitReader; +#[doc = "Field `DLGFILTER` writer - Enable Input Digital Glitch Filter"] +pub type DlgfilterW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBACK` reader - Enable LoopBack Mode"] +pub type LoopbackR = crate::BitReader; +#[doc = "Field `LOOPBACK` writer - Enable LoopBack Mode"] +pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMCONFIGENB` reader - Enable Timing Config Register"] +pub type TmconfigenbR = crate::BitReader; +#[doc = "Field `TMCONFIGENB` writer - Enable Timing Config Register"] +pub type TmconfigenbW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C CLK Enabled"] + #[inline(always)] + pub fn clkenabled(&self) -> ClkenabledR { + ClkenabledR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&self) -> EnabledR { + EnabledR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&self) -> TxfemdR { + TxfemdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&self) -> RxffmdR { + RxffmdR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable Input Analog Glitch Filter"] + #[inline(always)] + pub fn algfilter(&self) -> AlgfilterR { + AlgfilterR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Enable Input Digital Glitch Filter"] + #[inline(always)] + pub fn dlgfilter(&self) -> DlgfilterR { + DlgfilterR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Enable LoopBack Mode"] + #[inline(always)] + pub fn loopback(&self) -> LoopbackR { + LoopbackR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Enable Timing Config Register"] + #[inline(always)] + pub fn tmconfigenb(&self) -> TmconfigenbR { + TmconfigenbR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C CLK Enabled"] + #[inline(always)] + #[must_use] + pub fn clkenabled(&mut self) -> ClkenabledW { + ClkenabledW::new(self, 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + #[must_use] + pub fn enabled(&mut self) -> EnabledW { + EnabledW::new(self, 1) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 2) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + #[must_use] + pub fn txfemd(&mut self) -> TxfemdW { + TxfemdW::new(self, 3) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + #[must_use] + pub fn rxffmd(&mut self) -> RxffmdW { + RxffmdW::new(self, 4) + } + #[doc = "Bit 5 - Enable Input Analog Glitch Filter"] + #[inline(always)] + #[must_use] + pub fn algfilter(&mut self) -> AlgfilterW { + AlgfilterW::new(self, 5) + } + #[doc = "Bit 6 - Enable Input Digital Glitch Filter"] + #[inline(always)] + #[must_use] + pub fn dlgfilter(&mut self) -> DlgfilterW { + DlgfilterW::new(self, 6) + } + #[doc = "Bit 8 - Enable LoopBack Mode"] + #[inline(always)] + #[must_use] + pub fn loopback(&mut self) -> LoopbackW { + LoopbackW::new(self, 8) + } + #[doc = "Bit 9 - Enable Timing Config Register"] + #[inline(always)] + #[must_use] + pub fn tmconfigenb(&mut self) -> TmconfigenbW { + TmconfigenbW::new(self, 9) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/data.rs b/va416xx/src/i2c0/data.rs new file mode 100644 index 0000000..30b85c9 --- /dev/null +++ b/va416xx/src/i2c0/data.rs @@ -0,0 +1,27 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/fifo_clr.rs b/va416xx/src/i2c0/fifo_clr.rs new file mode 100644 index 0000000..156da87 --- /dev/null +++ b/va416xx/src/i2c0/fifo_clr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + #[must_use] + pub fn rxfifo(&mut self) -> RxfifoW { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + #[must_use] + pub fn txfifo(&mut self) -> TxfifoW { + TxfifoW::new(self, 1) + } +} +#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/irq_enb.rs b/va416xx/src/i2c0/irq_enb.rs new file mode 100644 index 0000000..4eba067 --- /dev/null +++ b/va416xx/src/i2c0/irq_enb.rs @@ -0,0 +1,235 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `I2CIDLE` reader - I2C Bus is Idle"] +pub type I2cidleR = crate::BitReader; +#[doc = "Field `I2CIDLE` writer - I2C Bus is Idle"] +pub type I2cidleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `IDLE` writer - Controller is Idle"] +pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STALLED` reader - Controller is Stalled"] +pub type StalledR = crate::BitReader; +#[doc = "Field `STALLED` writer - Controller is Stalled"] +pub type StalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"] +pub type ArblostR = crate::BitReader; +#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"] +pub type ArblostW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"] +pub type NackaddrR = crate::BitReader; +#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"] +pub type NackaddrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLKLOTO` reader - I2C Clock Low Timeout"] +pub type ClklotoR = crate::BitReader; +#[doc = "Field `CLKLOTO` writer - I2C Clock Low Timeout"] +pub type ClklotoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXOVERFLOW` reader - TX FIFO Overflowed"] +pub type TxoverflowR = crate::BitReader; +#[doc = "Field `TXOVERFLOW` writer - TX FIFO Overflowed"] +pub type TxoverflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub type RxoverflowR = crate::BitReader; +#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"] +pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub type TxreadyR = crate::BitReader; +#[doc = "Field `TXREADY` writer - TX FIFO Ready"] +pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub type RxreadyR = crate::BitReader; +#[doc = "Field `RXREADY` writer - RX FIFO Ready"] +pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"] +pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXFULL` writer - RX FIFO Full"] +pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + pub fn i2cidle(&self) -> I2cidleR { + I2cidleR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&self) -> StalledR { + StalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&self) -> ArblostR { + ArblostR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&self) -> NackaddrR { + NackaddrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + pub fn clkloto(&self) -> ClklotoR { + ClklotoR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + pub fn txoverflow(&self) -> TxoverflowR { + TxoverflowR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RxoverflowR { + RxoverflowR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TxreadyR { + TxreadyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RxreadyR { + RxreadyR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C Bus is Idle"] + #[inline(always)] + #[must_use] + pub fn i2cidle(&mut self) -> I2cidleW { + I2cidleW::new(self, 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + #[must_use] + pub fn idle(&mut self) -> IdleW { + IdleW::new(self, 1) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + #[must_use] + pub fn waiting(&mut self) -> WaitingW { + WaitingW::new(self, 2) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + #[must_use] + pub fn stalled(&mut self) -> StalledW { + StalledW::new(self, 3) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + #[must_use] + pub fn arblost(&mut self) -> ArblostW { + ArblostW::new(self, 4) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + #[must_use] + pub fn nackaddr(&mut self) -> NackaddrW { + NackaddrW::new(self, 5) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + #[must_use] + pub fn nackdata(&mut self) -> NackdataW { + NackdataW::new(self, 6) + } + #[doc = "Bit 7 - I2C Clock Low Timeout"] + #[inline(always)] + #[must_use] + pub fn clkloto(&mut self) -> ClklotoW { + ClklotoW::new(self, 7) + } + #[doc = "Bit 10 - TX FIFO Overflowed"] + #[inline(always)] + #[must_use] + pub fn txoverflow(&mut self) -> TxoverflowW { + TxoverflowW::new(self, 10) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + #[must_use] + pub fn rxoverflow(&mut self) -> RxoverflowW { + RxoverflowW::new(self, 11) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + #[must_use] + pub fn txready(&mut self) -> TxreadyW { + TxreadyW::new(self, 12) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + #[must_use] + pub fn rxready(&mut self) -> RxreadyW { + RxreadyW::new(self, 13) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + #[must_use] + pub fn txempty(&mut self) -> TxemptyW { + TxemptyW::new(self, 14) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + #[must_use] + pub fn rxfull(&mut self) -> RxfullW { + RxfullW::new(self, 15) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/perid.rs b/va416xx/src/i2c0/perid.rs new file mode 100644 index 0000000..832d608 --- /dev/null +++ b/va416xx/src/i2c0/perid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0214_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0214_07e9; +} diff --git a/va416xx/src/i2c0/rxcount.rs b/va416xx/src/i2c0/rxcount.rs new file mode 100644 index 0000000..b7b6d5a --- /dev/null +++ b/va416xx/src/i2c0/rxcount.rs @@ -0,0 +1,18 @@ +#[doc = "Register `RXCOUNT` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxcountSpec; +impl crate::RegisterSpec for RxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxcount::R`](R) reader structure"] +impl crate::Readable for RxcountSpec {} +#[doc = "`reset()` method sets RXCOUNT to value 0"] +impl crate::Resettable for RxcountSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/rxfifoirqtrg.rs b/va416xx/src/i2c0/rxfifoirqtrg.rs new file mode 100644 index 0000000..46124d5 --- /dev/null +++ b/va416xx/src/i2c0/rxfifoirqtrg.rs @@ -0,0 +1,27 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_address.rs b/va416xx/src/i2c0/s0_address.rs new file mode 100644 index 0000000..69d3dbe --- /dev/null +++ b/va416xx/src/i2c0/s0_address.rs @@ -0,0 +1,70 @@ +#[doc = "Register `S0_ADDRESS` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESS` writer"] +pub type W = crate::W; +#[doc = "Field `RW` reader - Read/Write value"] +pub type RwR = crate::BitReader; +#[doc = "Field `RW` writer - Read/Write value"] +pub type RwW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDRESS` reader - Address value"] +pub type AddressR = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - Address value"] +pub type AddressW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `A10MODE` reader - Enable 10b address mode"] +pub type A10modeR = crate::BitReader; +#[doc = "Field `A10MODE` writer - Enable 10b address mode"] +pub type A10modeW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Read/Write value"] + #[inline(always)] + pub fn rw(&self) -> RwR { + RwR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&self) -> AddressR { + AddressR::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Enable 10b address mode"] + #[inline(always)] + pub fn a10mode(&self) -> A10modeR { + A10modeR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Read/Write value"] + #[inline(always)] + #[must_use] + pub fn rw(&mut self) -> RwW { + RwW::new(self, 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + #[must_use] + pub fn address(&mut self) -> AddressW { + AddressW::new(self, 1) + } + #[doc = "Bit 15 - Enable 10b address mode"] + #[inline(always)] + #[must_use] + pub fn a10mode(&mut self) -> A10modeW { + A10modeW::new(self, 15) + } +} +#[doc = "Slave I2C Address Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_address::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressSpec; +impl crate::RegisterSpec for S0AddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_address::R`](R) reader structure"] +impl crate::Readable for S0AddressSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_address::W`](W) writer structure"] +impl crate::Writable for S0AddressSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_ADDRESS to value 0"] +impl crate::Resettable for S0AddressSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_addressb.rs b/va416xx/src/i2c0/s0_addressb.rs new file mode 100644 index 0000000..c82d283 --- /dev/null +++ b/va416xx/src/i2c0/s0_addressb.rs @@ -0,0 +1,70 @@ +#[doc = "Register `S0_ADDRESSB` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESSB` writer"] +pub type W = crate::W; +#[doc = "Field `RW` reader - Read write value"] +pub type RwR = crate::BitReader; +#[doc = "Field `RW` writer - Read write value"] +pub type RwW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDRESS` reader - Address value"] +pub type AddressR = crate::FieldReader; +#[doc = "Field `ADDRESS` writer - Address value"] +pub type AddressW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +#[doc = "Field `ADDRESSBEN` reader - Enable Address B"] +pub type AddressbenR = crate::BitReader; +#[doc = "Field `ADDRESSBEN` writer - Enable Address B"] +pub type AddressbenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Read write value"] + #[inline(always)] + pub fn rw(&self) -> RwR { + RwR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&self) -> AddressR { + AddressR::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Enable Address B"] + #[inline(always)] + pub fn addressben(&self) -> AddressbenR { + AddressbenR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Read write value"] + #[inline(always)] + #[must_use] + pub fn rw(&mut self) -> RwW { + RwW::new(self, 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + #[must_use] + pub fn address(&mut self) -> AddressW { + AddressW::new(self, 1) + } + #[doc = "Bit 15 - Enable Address B"] + #[inline(always)] + #[must_use] + pub fn addressben(&mut self) -> AddressbenW { + AddressbenW::new(self, 15) + } +} +#[doc = "Slave I2C Address B Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressbSpec; +impl crate::RegisterSpec for S0AddressbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_addressb::R`](R) reader structure"] +impl crate::Readable for S0AddressbSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_addressb::W`](W) writer structure"] +impl crate::Writable for S0AddressbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_ADDRESSB to value 0"] +impl crate::Resettable for S0AddressbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_addressmask.rs b/va416xx/src/i2c0/s0_addressmask.rs new file mode 100644 index 0000000..bcc7051 --- /dev/null +++ b/va416xx/src/i2c0/s0_addressmask.rs @@ -0,0 +1,55 @@ +#[doc = "Register `S0_ADDRESSMASK` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESSMASK` writer"] +pub type W = crate::W; +#[doc = "Field `RWMASK` reader - Read/Write mask"] +pub type RwmaskR = crate::BitReader; +#[doc = "Field `RWMASK` writer - Read/Write mask"] +pub type RwmaskW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK` reader - Address mask value"] +pub type MaskR = crate::FieldReader; +#[doc = "Field `MASK` writer - Address mask value"] +pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bit 0 - Read/Write mask"] + #[inline(always)] + pub fn rwmask(&self) -> RwmaskR { + RwmaskR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + pub fn mask(&self) -> MaskR { + MaskR::new(((self.bits >> 1) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Read/Write mask"] + #[inline(always)] + #[must_use] + pub fn rwmask(&mut self) -> RwmaskW { + RwmaskW::new(self, 0) + } + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + #[must_use] + pub fn mask(&mut self) -> MaskW { + MaskW::new(self, 1) + } +} +#[doc = "Slave I2C Address Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressmaskSpec; +impl crate::RegisterSpec for S0AddressmaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_addressmask::R`](R) reader structure"] +impl crate::Readable for S0AddressmaskSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_addressmask::W`](W) writer structure"] +impl crate::Writable for S0AddressmaskSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"] +impl crate::Resettable for S0AddressmaskSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_addressmaskb.rs b/va416xx/src/i2c0/s0_addressmaskb.rs new file mode 100644 index 0000000..a7b22f0 --- /dev/null +++ b/va416xx/src/i2c0/s0_addressmaskb.rs @@ -0,0 +1,55 @@ +#[doc = "Register `S0_ADDRESSMASKB` reader"] +pub type R = crate::R; +#[doc = "Register `S0_ADDRESSMASKB` writer"] +pub type W = crate::W; +#[doc = "Field `RWMASK` reader - Read write mask"] +pub type RwmaskR = crate::BitReader; +#[doc = "Field `RWMASK` writer - Read write mask"] +pub type RwmaskW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MASK` reader - Address mask value"] +pub type MaskR = crate::FieldReader; +#[doc = "Field `MASK` writer - Address mask value"] +pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>; +impl R { + #[doc = "Bit 0 - Read write mask"] + #[inline(always)] + pub fn rwmask(&self) -> RwmaskR { + RwmaskR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + pub fn mask(&self) -> MaskR { + MaskR::new(((self.bits >> 1) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Read write mask"] + #[inline(always)] + #[must_use] + pub fn rwmask(&mut self) -> RwmaskW { + RwmaskW::new(self, 0) + } + #[doc = "Bits 1:10 - Address mask value"] + #[inline(always)] + #[must_use] + pub fn mask(&mut self) -> MaskW { + MaskW::new(self, 1) + } +} +#[doc = "Slave I2C Address B Mask value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_addressmaskb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_addressmaskb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0AddressmaskbSpec; +impl crate::RegisterSpec for S0AddressmaskbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_addressmaskb::R`](R) reader structure"] +impl crate::Readable for S0AddressmaskbSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_addressmaskb::W`](W) writer structure"] +impl crate::Writable for S0AddressmaskbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0x07fe"] +impl crate::Resettable for S0AddressmaskbSpec { + const RESET_VALUE: u32 = 0x07fe; +} diff --git a/va416xx/src/i2c0/s0_ctrl.rs b/va416xx/src/i2c0/s0_ctrl.rs new file mode 100644 index 0000000..c22d6de --- /dev/null +++ b/va416xx/src/i2c0/s0_ctrl.rs @@ -0,0 +1,100 @@ +#[doc = "Register `S0_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `S0_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CLKENABLED` reader - I2C Enabled"] +pub type ClkenabledR = crate::BitReader; +#[doc = "Field `CLKENABLED` writer - I2C Enabled"] +pub type ClkenabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLED` reader - I2C Activated"] +pub type EnabledR = crate::BitReader; +#[doc = "Field `ENABLED` writer - I2C Activated"] +pub type EnabledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - I2C Active"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - I2C Active"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"] +pub type TxfemdR = crate::BitReader; +#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"] +pub type TxfemdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"] +pub type RxffmdR = crate::BitReader; +#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"] +pub type RxffmdW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C Enabled"] + #[inline(always)] + pub fn clkenabled(&self) -> ClkenabledR { + ClkenabledR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + pub fn enabled(&self) -> EnabledR { + EnabledR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + pub fn txfemd(&self) -> TxfemdR { + TxfemdR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + pub fn rxffmd(&self) -> RxffmdR { + RxffmdR::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C Enabled"] + #[inline(always)] + #[must_use] + pub fn clkenabled(&mut self) -> ClkenabledW { + ClkenabledW::new(self, 0) + } + #[doc = "Bit 1 - I2C Activated"] + #[inline(always)] + #[must_use] + pub fn enabled(&mut self) -> EnabledW { + EnabledW::new(self, 1) + } + #[doc = "Bit 2 - I2C Active"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 2) + } + #[doc = "Bit 3 - TX FIFIO Empty Mode"] + #[inline(always)] + #[must_use] + pub fn txfemd(&mut self) -> TxfemdW { + TxfemdW::new(self, 3) + } + #[doc = "Bit 4 - RX FIFO Full Mode"] + #[inline(always)] + #[must_use] + pub fn rxffmd(&mut self) -> RxffmdW { + RxffmdW::new(self, 4) + } +} +#[doc = "Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0CtrlSpec; +impl crate::RegisterSpec for S0CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_ctrl::R`](R) reader structure"] +impl crate::Readable for S0CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_ctrl::W`](W) writer structure"] +impl crate::Writable for S0CtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_CTRL to value 0"] +impl crate::Resettable for S0CtrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_data.rs b/va416xx/src/i2c0/s0_data.rs new file mode 100644 index 0000000..0429280 --- /dev/null +++ b/va416xx/src/i2c0/s0_data.rs @@ -0,0 +1,40 @@ +#[doc = "Register `S0_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `S0_DATA` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` reader - I2C data value"] +pub type ValueR = crate::FieldReader; +#[doc = "Field `VALUE` writer - I2C data value"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - I2C data value"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - I2C data value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> ValueW { + ValueW::new(self, 0) + } +} +#[doc = "Slave Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0DataSpec; +impl crate::RegisterSpec for S0DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_data::R`](R) reader structure"] +impl crate::Readable for S0DataSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_data::W`](W) writer structure"] +impl crate::Writable for S0DataSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_DATA to value 0"] +impl crate::Resettable for S0DataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_fifo_clr.rs b/va416xx/src/i2c0/s0_fifo_clr.rs new file mode 100644 index 0000000..0d5dd60 --- /dev/null +++ b/va416xx/src/i2c0/s0_fifo_clr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `S0_FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + #[must_use] + pub fn rxfifo(&mut self) -> RxfifoW { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + #[must_use] + pub fn txfifo(&mut self) -> TxfifoW { + TxfifoW::new(self, 1) + } +} +#[doc = "Slave Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0FifoClrSpec; +impl crate::RegisterSpec for S0FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`s0_fifo_clr::W`](W) writer structure"] +impl crate::Writable for S0FifoClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_FIFO_CLR to value 0"] +impl crate::Resettable for S0FifoClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_irq_enb.rs b/va416xx/src/i2c0/s0_irq_enb.rs new file mode 100644 index 0000000..a6a30e2 --- /dev/null +++ b/va416xx/src/i2c0/s0_irq_enb.rs @@ -0,0 +1,265 @@ +#[doc = "Register `S0_IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `S0_IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"] +pub type CompletedR = crate::BitReader; +#[doc = "Field `COMPLETED` writer - Controller Complted a Transaction"] +pub type CompletedW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `IDLE` writer - Controller is Idle"] +pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"] +pub type TxstalledR = crate::BitReader; +#[doc = "Field `TXSTALLED` writer - Controller is Tx Stalled"] +pub type TxstalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"] +pub type RxstalledR = crate::BitReader; +#[doc = "Field `RXSTALLED` writer - Controller is Rx Stalled"] +pub type RxstalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"] +pub type AddressmatchR = crate::BitReader; +#[doc = "Field `ADDRESSMATCH` writer - I2C Address Match"] +pub type AddressmatchW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"] +pub type RxdatafirstR = crate::BitReader; +#[doc = "Field `RXDATAFIRST` writer - Pending Data is first Byte following Address"] +pub type RxdatafirstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C_START` reader - I2C Start Condition"] +pub type I2cStartR = crate::BitReader; +#[doc = "Field `I2C_START` writer - I2C Start Condition"] +pub type I2cStartW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C_STOP` reader - I2C Stop Condition"] +pub type I2cStopR = crate::BitReader; +#[doc = "Field `I2C_STOP` writer - I2C Stop Condition"] +pub type I2cStopW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXUNDERFLOW` reader - TX FIFO Underflowed"] +pub type TxunderflowR = crate::BitReader; +#[doc = "Field `TXUNDERFLOW` writer - TX FIFO Underflowed"] +pub type TxunderflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXOVERFLOW` reader - TX FIFO Overflowed"] +pub type RxoverflowR = crate::BitReader; +#[doc = "Field `RXOVERFLOW` writer - TX FIFO Overflowed"] +pub type RxoverflowW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXREADY` reader - TX FIFO Ready"] +pub type TxreadyR = crate::BitReader; +#[doc = "Field `TXREADY` writer - TX FIFO Ready"] +pub type TxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXREADY` reader - RX FIFO Ready"] +pub type RxreadyR = crate::BitReader; +#[doc = "Field `RXREADY` writer - RX FIFO Ready"] +pub type RxreadyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEMPTY` reader - TX FIFO Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXEMPTY` writer - TX FIFO Empty"] +pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFULL` reader - RX FIFO Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXFULL` writer - RX FIFO Full"] +pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&self) -> CompletedR { + CompletedR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&self) -> TxstalledR { + TxstalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&self) -> RxstalledR { + RxstalledR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&self) -> AddressmatchR { + AddressmatchR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RxdatafirstR { + RxdatafirstR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + pub fn i2c_start(&self) -> I2cStartR { + I2cStartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + pub fn i2c_stop(&self) -> I2cStopR { + I2cStopR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + pub fn txunderflow(&self) -> TxunderflowR { + TxunderflowR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + pub fn rxoverflow(&self) -> RxoverflowR { + RxoverflowR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + pub fn txready(&self) -> TxreadyR { + TxreadyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + pub fn rxready(&self) -> RxreadyR { + RxreadyR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + #[must_use] + pub fn completed(&mut self) -> CompletedW { + CompletedW::new(self, 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + #[must_use] + pub fn idle(&mut self) -> IdleW { + IdleW::new(self, 1) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + #[must_use] + pub fn waiting(&mut self) -> WaitingW { + WaitingW::new(self, 2) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + #[must_use] + pub fn txstalled(&mut self) -> TxstalledW { + TxstalledW::new(self, 3) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + #[must_use] + pub fn rxstalled(&mut self) -> RxstalledW { + RxstalledW::new(self, 4) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + #[must_use] + pub fn addressmatch(&mut self) -> AddressmatchW { + AddressmatchW::new(self, 5) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + #[must_use] + pub fn nackdata(&mut self) -> NackdataW { + NackdataW::new(self, 6) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + #[must_use] + pub fn rxdatafirst(&mut self) -> RxdatafirstW { + RxdatafirstW::new(self, 7) + } + #[doc = "Bit 8 - I2C Start Condition"] + #[inline(always)] + #[must_use] + pub fn i2c_start(&mut self) -> I2cStartW { + I2cStartW::new(self, 8) + } + #[doc = "Bit 9 - I2C Stop Condition"] + #[inline(always)] + #[must_use] + pub fn i2c_stop(&mut self) -> I2cStopW { + I2cStopW::new(self, 9) + } + #[doc = "Bit 10 - TX FIFO Underflowed"] + #[inline(always)] + #[must_use] + pub fn txunderflow(&mut self) -> TxunderflowW { + TxunderflowW::new(self, 10) + } + #[doc = "Bit 11 - TX FIFO Overflowed"] + #[inline(always)] + #[must_use] + pub fn rxoverflow(&mut self) -> RxoverflowW { + RxoverflowW::new(self, 11) + } + #[doc = "Bit 12 - TX FIFO Ready"] + #[inline(always)] + #[must_use] + pub fn txready(&mut self) -> TxreadyW { + TxreadyW::new(self, 12) + } + #[doc = "Bit 13 - RX FIFO Ready"] + #[inline(always)] + #[must_use] + pub fn rxready(&mut self) -> RxreadyW { + RxreadyW::new(self, 13) + } + #[doc = "Bit 14 - TX FIFO Empty"] + #[inline(always)] + #[must_use] + pub fn txempty(&mut self) -> TxemptyW { + TxemptyW::new(self, 14) + } + #[doc = "Bit 15 - RX FIFO Full"] + #[inline(always)] + #[must_use] + pub fn rxfull(&mut self) -> RxfullW { + RxfullW::new(self, 15) + } +} +#[doc = "Slave Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0IrqEnbSpec; +impl crate::RegisterSpec for S0IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_irq_enb::R`](R) reader structure"] +impl crate::Readable for S0IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_irq_enb::W`](W) writer structure"] +impl crate::Writable for S0IrqEnbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_IRQ_ENB to value 0"] +impl crate::Resettable for S0IrqEnbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_lastaddress.rs b/va416xx/src/i2c0/s0_lastaddress.rs new file mode 100644 index 0000000..98ac58d --- /dev/null +++ b/va416xx/src/i2c0/s0_lastaddress.rs @@ -0,0 +1,29 @@ +#[doc = "Register `S0_LASTADDRESS` reader"] +pub type R = crate::R; +#[doc = "Field `DIRECTION` reader - Transaction direction 0=master send, 1=master receive"] +pub type DirectionR = crate::BitReader; +#[doc = "Field `ADDRESS` reader - Address value"] +pub type AddressR = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Transaction direction 0=master send, 1=master receive"] + #[inline(always)] + pub fn direction(&self) -> DirectionR { + DirectionR::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address value"] + #[inline(always)] + pub fn address(&self) -> AddressR { + AddressR::new(((self.bits >> 1) & 0x03ff) as u16) + } +} +#[doc = "Slave I2C Last Address value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_lastaddress::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0LastaddressSpec; +impl crate::RegisterSpec for S0LastaddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_lastaddress::R`](R) reader structure"] +impl crate::Readable for S0LastaddressSpec {} +#[doc = "`reset()` method sets S0_LASTADDRESS to value 0"] +impl crate::Resettable for S0LastaddressSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_maxwords.rs b/va416xx/src/i2c0/s0_maxwords.rs new file mode 100644 index 0000000..e5fbd32 --- /dev/null +++ b/va416xx/src/i2c0/s0_maxwords.rs @@ -0,0 +1,55 @@ +#[doc = "Register `S0_MAXWORDS` reader"] +pub type R = crate::R; +#[doc = "Register `S0_MAXWORDS` writer"] +pub type W = crate::W; +#[doc = "Field `MAXWORD` reader - Max Word Count"] +pub type MaxwordR = crate::FieldReader; +#[doc = "Field `MAXWORD` writer - Max Word Count"] +pub type MaxwordW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>; +#[doc = "Field `ENABLE` reader - Enables the max word count"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enables the max word count"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:10 - Max Word Count"] + #[inline(always)] + pub fn maxword(&self) -> MaxwordR { + MaxwordR::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 31 - Enables the max word count"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:10 - Max Word Count"] + #[inline(always)] + #[must_use] + pub fn maxword(&mut self) -> MaxwordW { + MaxwordW::new(self, 0) + } + #[doc = "Bit 31 - Enables the max word count"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 31) + } +} +#[doc = "Slave MaxWords Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_maxwords::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_maxwords::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0MaxwordsSpec; +impl crate::RegisterSpec for S0MaxwordsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_maxwords::R`](R) reader structure"] +impl crate::Readable for S0MaxwordsSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_maxwords::W`](W) writer structure"] +impl crate::Writable for S0MaxwordsSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_MAXWORDS to value 0"] +impl crate::Resettable for S0MaxwordsSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_rxcount.rs b/va416xx/src/i2c0/s0_rxcount.rs new file mode 100644 index 0000000..b01fd37 --- /dev/null +++ b/va416xx/src/i2c0/s0_rxcount.rs @@ -0,0 +1,22 @@ +#[doc = "Register `S0_RXCOUNT` reader"] +pub type R = crate::R; +#[doc = "Field `VALUE` reader - Count value"] +pub type ValueR = crate::FieldReader; +impl R { + #[doc = "Bits 0:10 - Count value"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new((self.bits & 0x07ff) as u16) + } +} +#[doc = "Slave RX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0RxcountSpec; +impl crate::RegisterSpec for S0RxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_rxcount::R`](R) reader structure"] +impl crate::Readable for S0RxcountSpec {} +#[doc = "`reset()` method sets S0_RXCOUNT to value 0"] +impl crate::Resettable for S0RxcountSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_rxfifoirqtrg.rs b/va416xx/src/i2c0/s0_rxfifoirqtrg.rs new file mode 100644 index 0000000..2c8f823 --- /dev/null +++ b/va416xx/src/i2c0/s0_rxfifoirqtrg.rs @@ -0,0 +1,40 @@ +#[doc = "Register `S0_RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `S0_RXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[doc = "Field `LEVEL` reader - Half full level for the Rx FIFO"] +pub type LevelR = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Half full level for the Rx FIFO"] +pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + pub fn level(&self) -> LevelR { + LevelR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + #[must_use] + pub fn level(&mut self) -> LevelW { + LevelW::new(self, 0) + } +} +#[doc = "Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0RxfifoirqtrgSpec; +impl crate::RegisterSpec for S0RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for S0RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for S0RxfifoirqtrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"] +impl crate::Resettable for S0RxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_state.rs b/va416xx/src/i2c0/s0_state.rs new file mode 100644 index 0000000..473fd77 --- /dev/null +++ b/va416xx/src/i2c0/s0_state.rs @@ -0,0 +1,18 @@ +#[doc = "Register `S0_STATE` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0StateSpec; +impl crate::RegisterSpec for S0StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_state::R`](R) reader structure"] +impl crate::Readable for S0StateSpec {} +#[doc = "`reset()` method sets S0_STATE to value 0"] +impl crate::Resettable for S0StateSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_status.rs b/va416xx/src/i2c0/s0_status.rs new file mode 100644 index 0000000..1a79596 --- /dev/null +++ b/va416xx/src/i2c0/s0_status.rs @@ -0,0 +1,134 @@ +#[doc = "Register `S0_STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `COMPLETED` reader - Controller Complted a Transaction"] +pub type CompletedR = crate::BitReader; +#[doc = "Field `IDLE` reader - Controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `TXSTALLED` reader - Controller is Tx Stalled"] +pub type TxstalledR = crate::BitReader; +#[doc = "Field `RXSTALLED` reader - Controller is Rx Stalled"] +pub type RxstalledR = crate::BitReader; +#[doc = "Field `ADDRESSMATCH` reader - I2C Address Match"] +pub type AddressmatchR = crate::BitReader; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte following Address"] +pub type RxdatafirstR = crate::BitReader; +#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"] +pub type RxnemptyR = crate::BitReader; +#[doc = "Field `RXFULL` reader - RX FIFO is Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub type RxtriggerR = crate::BitReader; +#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXNFULL` reader - TX FIFO is Full"] +pub type TxnfullR = crate::BitReader; +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub type TxtriggerR = crate::BitReader; +#[doc = "Field `RAW_BUSY` reader - I2C Raw Busy value"] +pub type RawBusyR = crate::BitReader; +#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"] +pub type RawSdaR = crate::BitReader; +#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"] +pub type RawSclR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Controller Complted a Transaction"] + #[inline(always)] + pub fn completed(&self) -> CompletedR { + CompletedR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Tx Stalled"] + #[inline(always)] + pub fn txstalled(&self) -> TxstalledR { + TxstalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Controller is Rx Stalled"] + #[inline(always)] + pub fn rxstalled(&self) -> RxstalledR { + RxstalledR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address Match"] + #[inline(always)] + pub fn addressmatch(&self) -> AddressmatchR { + AddressmatchR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pending Data is first Byte following Address"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RxdatafirstR { + RxdatafirstR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + pub fn rxnempty(&self) -> RxnemptyR { + RxnemptyR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RxtriggerR { + RxtriggerR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + pub fn txnfull(&self) -> TxnfullR { + TxnfullR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TxtriggerR { + TxtriggerR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 29 - I2C Raw Busy value"] + #[inline(always)] + pub fn raw_busy(&self) -> RawBusyR { + RawBusyR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + pub fn raw_sda(&self) -> RawSdaR { + RawSdaR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + pub fn raw_scl(&self) -> RawSclR { + RawSclR::new(((self.bits >> 31) & 1) != 0) + } +} +#[doc = "Slave I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0StatusSpec; +impl crate::RegisterSpec for S0StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_status::R`](R) reader structure"] +impl crate::Readable for S0StatusSpec {} +#[doc = "`reset()` method sets S0_STATUS to value 0"] +impl crate::Resettable for S0StatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_txcount.rs b/va416xx/src/i2c0/s0_txcount.rs new file mode 100644 index 0000000..43bdd00 --- /dev/null +++ b/va416xx/src/i2c0/s0_txcount.rs @@ -0,0 +1,22 @@ +#[doc = "Register `S0_TXCOUNT` reader"] +pub type R = crate::R; +#[doc = "Field `VALUE` reader - Count value"] +pub type ValueR = crate::FieldReader; +impl R { + #[doc = "Bits 0:10 - Count value"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new((self.bits & 0x07ff) as u16) + } +} +#[doc = "Slave TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0TxcountSpec; +impl crate::RegisterSpec for S0TxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_txcount::R`](R) reader structure"] +impl crate::Readable for S0TxcountSpec {} +#[doc = "`reset()` method sets S0_TXCOUNT to value 0"] +impl crate::Resettable for S0TxcountSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/s0_txfifoirqtrg.rs b/va416xx/src/i2c0/s0_txfifoirqtrg.rs new file mode 100644 index 0000000..2d8881a --- /dev/null +++ b/va416xx/src/i2c0/s0_txfifoirqtrg.rs @@ -0,0 +1,40 @@ +#[doc = "Register `S0_TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `S0_TXFIFOIRQTRG` writer"] +pub type W = crate::W; +#[doc = "Field `LEVEL` reader - Half full level for the Rx FIFO"] +pub type LevelR = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Half full level for the Rx FIFO"] +pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + pub fn level(&self) -> LevelR { + LevelR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Half full level for the Rx FIFO"] + #[inline(always)] + #[must_use] + pub fn level(&mut self) -> LevelW { + LevelW::new(self, 0) + } +} +#[doc = "Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`s0_txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct S0TxfifoirqtrgSpec; +impl crate::RegisterSpec for S0TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`s0_txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for S0TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`s0_txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for S0TxfifoirqtrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0x08"] +impl crate::Resettable for S0TxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0x08; +} diff --git a/va416xx/src/i2c0/state.rs b/va416xx/src/i2c0/state.rs new file mode 100644 index 0000000..fe3c04e --- /dev/null +++ b/va416xx/src/i2c0/state.rs @@ -0,0 +1,18 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StateSpec; +impl crate::RegisterSpec for StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for StateSpec {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for StateSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/status.rs b/va416xx/src/i2c0/status.rs new file mode 100644 index 0000000..2735cab --- /dev/null +++ b/va416xx/src/i2c0/status.rs @@ -0,0 +1,250 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `STATUS` writer"] +pub type W = crate::W; +#[doc = "Field `I2CIDLE` reader - I2C bus is idle"] +pub type I2cidleR = crate::BitReader; +#[doc = "Field `I2CIDLE` writer - I2C bus is idle"] +pub type I2cidleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IDLE` reader - I2C controller is Idle"] +pub type IdleR = crate::BitReader; +#[doc = "Field `IDLE` writer - I2C controller is Idle"] +pub type IdleW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WAITING` reader - Controller is Waiting"] +pub type WaitingR = crate::BitReader; +#[doc = "Field `WAITING` writer - Controller is Waiting"] +pub type WaitingW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STALLED` reader - Controller is Stalled"] +pub type StalledR = crate::BitReader; +#[doc = "Field `STALLED` writer - Controller is Stalled"] +pub type StalledW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"] +pub type ArblostR = crate::BitReader; +#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"] +pub type ArblostW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"] +pub type NackaddrR = crate::BitReader; +#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"] +pub type NackaddrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"] +pub type NackdataR = crate::BitReader; +#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"] +pub type NackdataW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"] +pub type RxnemptyR = crate::BitReader; +#[doc = "Field `RXNEMPTY` writer - RX FIFO is Not Empty"] +pub type RxnemptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXFULL` reader - RX FIFO is Full"] +pub type RxfullR = crate::BitReader; +#[doc = "Field `RXFULL` writer - RX FIFO is Full"] +pub type RxfullW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub type RxtriggerR = crate::BitReader; +#[doc = "Field `RXTRIGGER` writer - RX FIFO Above Trigger Level"] +pub type RxtriggerW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"] +pub type TxemptyR = crate::BitReader; +#[doc = "Field `TXEMPTY` writer - TX FIFO is Empty"] +pub type TxemptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXNFULL` reader - TX FIFO is Full"] +pub type TxnfullR = crate::BitReader; +#[doc = "Field `TXNFULL` writer - TX FIFO is Full"] +pub type TxnfullW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub type TxtriggerR = crate::BitReader; +#[doc = "Field `TXTRIGGER` writer - TX FIFO Below Trigger Level"] +pub type TxtriggerW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"] +pub type RawSdaR = crate::BitReader; +#[doc = "Field `RAW_SDA` writer - I2C Raw SDA value"] +pub type RawSdaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"] +pub type RawSclR = crate::BitReader; +#[doc = "Field `RAW_SCL` writer - I2C Raw SCL value"] +pub type RawSclW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - I2C bus is idle"] + #[inline(always)] + pub fn i2cidle(&self) -> I2cidleR { + I2cidleR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - I2C controller is Idle"] + #[inline(always)] + pub fn idle(&self) -> IdleR { + IdleR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + pub fn waiting(&self) -> WaitingR { + WaitingR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + pub fn stalled(&self) -> StalledR { + StalledR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + pub fn arblost(&self) -> ArblostR { + ArblostR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + pub fn nackaddr(&self) -> NackaddrR { + NackaddrR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + pub fn nackdata(&self) -> NackdataR { + NackdataR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + pub fn rxnempty(&self) -> RxnemptyR { + RxnemptyR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + pub fn rxfull(&self) -> RxfullR { + RxfullR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RxtriggerR { + RxtriggerR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + pub fn txempty(&self) -> TxemptyR { + TxemptyR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + pub fn txnfull(&self) -> TxnfullR { + TxnfullR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TxtriggerR { + TxtriggerR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + pub fn raw_sda(&self) -> RawSdaR { + RawSdaR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + pub fn raw_scl(&self) -> RawSclR { + RawSclR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - I2C bus is idle"] + #[inline(always)] + #[must_use] + pub fn i2cidle(&mut self) -> I2cidleW { + I2cidleW::new(self, 0) + } + #[doc = "Bit 1 - I2C controller is Idle"] + #[inline(always)] + #[must_use] + pub fn idle(&mut self) -> IdleW { + IdleW::new(self, 1) + } + #[doc = "Bit 2 - Controller is Waiting"] + #[inline(always)] + #[must_use] + pub fn waiting(&mut self) -> WaitingW { + WaitingW::new(self, 2) + } + #[doc = "Bit 3 - Controller is Stalled"] + #[inline(always)] + #[must_use] + pub fn stalled(&mut self) -> StalledW { + StalledW::new(self, 3) + } + #[doc = "Bit 4 - I2C Arbitration was lost"] + #[inline(always)] + #[must_use] + pub fn arblost(&mut self) -> ArblostW { + ArblostW::new(self, 4) + } + #[doc = "Bit 5 - I2C Address was not Acknowledged"] + #[inline(always)] + #[must_use] + pub fn nackaddr(&mut self) -> NackaddrW { + NackaddrW::new(self, 5) + } + #[doc = "Bit 6 - I2C Data was not Acknowledged"] + #[inline(always)] + #[must_use] + pub fn nackdata(&mut self) -> NackdataW { + NackdataW::new(self, 6) + } + #[doc = "Bit 8 - RX FIFO is Not Empty"] + #[inline(always)] + #[must_use] + pub fn rxnempty(&mut self) -> RxnemptyW { + RxnemptyW::new(self, 8) + } + #[doc = "Bit 9 - RX FIFO is Full"] + #[inline(always)] + #[must_use] + pub fn rxfull(&mut self) -> RxfullW { + RxfullW::new(self, 9) + } + #[doc = "Bit 11 - RX FIFO Above Trigger Level"] + #[inline(always)] + #[must_use] + pub fn rxtrigger(&mut self) -> RxtriggerW { + RxtriggerW::new(self, 11) + } + #[doc = "Bit 12 - TX FIFO is Empty"] + #[inline(always)] + #[must_use] + pub fn txempty(&mut self) -> TxemptyW { + TxemptyW::new(self, 12) + } + #[doc = "Bit 13 - TX FIFO is Full"] + #[inline(always)] + #[must_use] + pub fn txnfull(&mut self) -> TxnfullW { + TxnfullW::new(self, 13) + } + #[doc = "Bit 15 - TX FIFO Below Trigger Level"] + #[inline(always)] + #[must_use] + pub fn txtrigger(&mut self) -> TxtriggerW { + TxtriggerW::new(self, 15) + } + #[doc = "Bit 30 - I2C Raw SDA value"] + #[inline(always)] + #[must_use] + pub fn raw_sda(&mut self) -> RawSdaW { + RawSdaW::new(self, 30) + } + #[doc = "Bit 31 - I2C Raw SCL value"] + #[inline(always)] + #[must_use] + pub fn raw_scl(&mut self) -> RawSclW { + RawSclW::new(self, 31) + } +} +#[doc = "I2C Controller Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`write(|w| ..)` method takes [`status::W`](W) writer structure"] +impl crate::Writable for StatusSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/tmconfig.rs b/va416xx/src/i2c0/tmconfig.rs new file mode 100644 index 0000000..2d0e025 --- /dev/null +++ b/va416xx/src/i2c0/tmconfig.rs @@ -0,0 +1,27 @@ +#[doc = "Register `TMCONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `TMCONFIG` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Timing Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tmconfig::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tmconfig::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TmconfigSpec; +impl crate::RegisterSpec for TmconfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tmconfig::R`](R) reader structure"] +impl crate::Readable for TmconfigSpec {} +#[doc = "`write(|w| ..)` method takes [`tmconfig::W`](W) writer structure"] +impl crate::Writable for TmconfigSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TMCONFIG to value 0"] +impl crate::Resettable for TmconfigSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/txcount.rs b/va416xx/src/i2c0/txcount.rs new file mode 100644 index 0000000..ae64e43 --- /dev/null +++ b/va416xx/src/i2c0/txcount.rs @@ -0,0 +1,18 @@ +#[doc = "Register `TXCOUNT` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "TX Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txcount::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxcountSpec; +impl crate::RegisterSpec for TxcountSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txcount::R`](R) reader structure"] +impl crate::Readable for TxcountSpec {} +#[doc = "`reset()` method sets TXCOUNT to value 0"] +impl crate::Resettable for TxcountSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/txfifoirqtrg.rs b/va416xx/src/i2c0/txfifoirqtrg.rs new file mode 100644 index 0000000..0d13e54 --- /dev/null +++ b/va416xx/src/i2c0/txfifoirqtrg.rs @@ -0,0 +1,27 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/i2c0/words.rs b/va416xx/src/i2c0/words.rs new file mode 100644 index 0000000..9aedb52 --- /dev/null +++ b/va416xx/src/i2c0/words.rs @@ -0,0 +1,27 @@ +#[doc = "Register `WORDS` reader"] +pub type R = crate::R; +#[doc = "Register `WORDS` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Word Count value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`words::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`words::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WordsSpec; +impl crate::RegisterSpec for WordsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`words::R`](R) reader structure"] +impl crate::Readable for WordsSpec {} +#[doc = "`write(|w| ..)` method takes [`words::W`](W) writer structure"] +impl crate::Writable for WordsSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WORDS to value 0"] +impl crate::Resettable for WordsSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/ioconfig.rs b/va416xx/src/ioconfig.rs new file mode 100644 index 0000000..b6a329e --- /dev/null +++ b/va416xx/src/ioconfig.rs @@ -0,0 +1,218 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + porta: [Porta; 16], + portb0: [Portb; 16], + portc0: [Portc; 16], + portd0: [Portd; 16], + porte0: [Porte; 16], + portf0: [Portf; 16], + portg0: [Portg; 8], + _reserved7: [u8; 0x20], + clkdiv0: Clkdiv0, + clkdiv1: Clkdiv1, + clkdiv2: Clkdiv2, + clkdiv3: Clkdiv3, + clkdiv4: Clkdiv4, + clkdiv5: Clkdiv5, + clkdiv6: Clkdiv6, + clkdiv7: Clkdiv7, + _reserved15: [u8; 0x0e1c], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00..0x40 - PORTA Pin Configuration Register"] + #[inline(always)] + pub const fn porta(&self, n: usize) -> &Porta { + &self.porta[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x00..0x40 - PORTA Pin Configuration Register"] + #[inline(always)] + pub fn porta_iter(&self) -> impl Iterator { + self.porta.iter() + } + #[doc = "0x40..0x80 - PORTB Pin Configuration Register"] + #[inline(always)] + pub const fn portb0(&self, n: usize) -> &Portb { + &self.portb0[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x40..0x80 - PORTB Pin Configuration Register"] + #[inline(always)] + pub fn portb0_iter(&self) -> impl Iterator { + self.portb0.iter() + } + #[doc = "0x80..0xc0 - PORTC Pin Configuration Register"] + #[inline(always)] + pub const fn portc0(&self, n: usize) -> &Portc { + &self.portc0[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x80..0xc0 - PORTC Pin Configuration Register"] + #[inline(always)] + pub fn portc0_iter(&self) -> impl Iterator { + self.portc0.iter() + } + #[doc = "0xc0..0x100 - PORTD Pin Configuration Register"] + #[inline(always)] + pub const fn portd0(&self, n: usize) -> &Portd { + &self.portd0[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0xc0..0x100 - PORTD Pin Configuration Register"] + #[inline(always)] + pub fn portd0_iter(&self) -> impl Iterator { + self.portd0.iter() + } + #[doc = "0x100..0x140 - PORTE Pin Configuration Register"] + #[inline(always)] + pub const fn porte0(&self, n: usize) -> &Porte { + &self.porte0[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x100..0x140 - PORTE Pin Configuration Register"] + #[inline(always)] + pub fn porte0_iter(&self) -> impl Iterator { + self.porte0.iter() + } + #[doc = "0x140..0x180 - PORTF Pin Configuration Register"] + #[inline(always)] + pub const fn portf0(&self, n: usize) -> &Portf { + &self.portf0[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x140..0x180 - PORTF Pin Configuration Register"] + #[inline(always)] + pub fn portf0_iter(&self) -> impl Iterator { + self.portf0.iter() + } + #[doc = "0x180..0x1a0 - PORTG Pin Configuration Register"] + #[inline(always)] + pub const fn portg0(&self, n: usize) -> &Portg { + &self.portg0[n] + } + #[doc = "Iterator for array of:"] + #[doc = "0x180..0x1a0 - PORTG Pin Configuration Register"] + #[inline(always)] + pub fn portg0_iter(&self) -> impl Iterator { + self.portg0.iter() + } + #[doc = "0x1c0 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv0(&self) -> &Clkdiv0 { + &self.clkdiv0 + } + #[doc = "0x1c4 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv1(&self) -> &Clkdiv1 { + &self.clkdiv1 + } + #[doc = "0x1c8 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv2(&self) -> &Clkdiv2 { + &self.clkdiv2 + } + #[doc = "0x1cc - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv3(&self) -> &Clkdiv3 { + &self.clkdiv3 + } + #[doc = "0x1d0 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv4(&self) -> &Clkdiv4 { + &self.clkdiv4 + } + #[doc = "0x1d4 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv5(&self) -> &Clkdiv5 { + &self.clkdiv5 + } + #[doc = "0x1d8 - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv6(&self) -> &Clkdiv6 { + &self.clkdiv6 + } + #[doc = "0x1dc - Clock divide value. 0 will disable the clock"] + #[inline(always)] + pub const fn clkdiv7(&self) -> &Clkdiv7 { + &self.clkdiv7 + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`] +module"] +#[doc(alias = "PORTA")] +pub type Porta = crate::Reg; +#[doc = "PORTA Pin Configuration Register"] +pub mod porta; +pub use porta as portb; +pub use porta as portc; +pub use porta as portd; +pub use porta as porte; +pub use porta as portf; +pub use porta as portg; +pub use Porta as Portb; +pub use Porta as Portc; +pub use Porta as Portd; +pub use Porta as Porte; +pub use Porta as Portf; +pub use Porta as Portg; +#[doc = "CLKDIV0 (r) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv0`] +module"] +#[doc(alias = "CLKDIV0")] +pub type Clkdiv0 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv0; +#[doc = "CLKDIV1 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv1`] +module"] +#[doc(alias = "CLKDIV1")] +pub type Clkdiv1 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv1; +#[doc = "CLKDIV2 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv2`] +module"] +#[doc(alias = "CLKDIV2")] +pub type Clkdiv2 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv2; +#[doc = "CLKDIV3 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv3`] +module"] +#[doc(alias = "CLKDIV3")] +pub type Clkdiv3 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv3; +#[doc = "CLKDIV4 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv4::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv4::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv4`] +module"] +#[doc(alias = "CLKDIV4")] +pub type Clkdiv4 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv4; +#[doc = "CLKDIV5 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv5::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv5::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv5`] +module"] +#[doc(alias = "CLKDIV5")] +pub type Clkdiv5 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv5; +#[doc = "CLKDIV6 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv6::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv6::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv6`] +module"] +#[doc(alias = "CLKDIV6")] +pub type Clkdiv6 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv6; +#[doc = "CLKDIV7 (rw) register accessor: Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv7::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv7::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv7`] +module"] +#[doc(alias = "CLKDIV7")] +pub type Clkdiv7 = crate::Reg; +#[doc = "Clock divide value. 0 will disable the clock"] +pub mod clkdiv7; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/ioconfig/clkdiv0.rs b/va416xx/src/ioconfig/clkdiv0.rs new file mode 100644 index 0000000..387ae41 --- /dev/null +++ b/va416xx/src/ioconfig/clkdiv0.rs @@ -0,0 +1,18 @@ +#[doc = "Register `CLKDIV0` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv0Spec; +impl crate::RegisterSpec for Clkdiv0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv0::R`](R) reader structure"] +impl crate::Readable for Clkdiv0Spec {} +#[doc = "`reset()` method sets CLKDIV0 to value 0"] +impl crate::Resettable for Clkdiv0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/ioconfig/clkdiv1.rs b/va416xx/src/ioconfig/clkdiv1.rs new file mode 100644 index 0000000..3bc2701 --- /dev/null +++ b/va416xx/src/ioconfig/clkdiv1.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CLKDIV1` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV1` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv1Spec; +impl crate::RegisterSpec for Clkdiv1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv1::R`](R) reader structure"] +impl crate::Readable for Clkdiv1Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv1::W`](W) writer structure"] +impl crate::Writable for Clkdiv1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKDIV1 to value 0"] +impl crate::Resettable for Clkdiv1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/ioconfig/clkdiv2.rs b/va416xx/src/ioconfig/clkdiv2.rs new file mode 100644 index 0000000..80e2943 --- /dev/null +++ b/va416xx/src/ioconfig/clkdiv2.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CLKDIV2` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV2` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv2Spec; +impl crate::RegisterSpec for Clkdiv2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv2::R`](R) reader structure"] +impl crate::Readable for Clkdiv2Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv2::W`](W) writer structure"] +impl crate::Writable for Clkdiv2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKDIV2 to value 0"] +impl crate::Resettable for Clkdiv2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/ioconfig/clkdiv3.rs b/va416xx/src/ioconfig/clkdiv3.rs new file mode 100644 index 0000000..d7ed7d0 --- /dev/null +++ b/va416xx/src/ioconfig/clkdiv3.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CLKDIV3` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV3` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv3Spec; +impl crate::RegisterSpec for Clkdiv3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv3::R`](R) reader structure"] +impl crate::Readable for Clkdiv3Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv3::W`](W) writer structure"] +impl crate::Writable for Clkdiv3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKDIV3 to value 0"] +impl crate::Resettable for Clkdiv3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/ioconfig/clkdiv4.rs b/va416xx/src/ioconfig/clkdiv4.rs new file mode 100644 index 0000000..72ccd13 --- /dev/null +++ b/va416xx/src/ioconfig/clkdiv4.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CLKDIV4` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV4` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv4Spec; +impl crate::RegisterSpec for Clkdiv4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv4::R`](R) reader structure"] +impl crate::Readable for Clkdiv4Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv4::W`](W) writer structure"] +impl crate::Writable for Clkdiv4Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKDIV4 to value 0"] +impl crate::Resettable for Clkdiv4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/ioconfig/clkdiv5.rs b/va416xx/src/ioconfig/clkdiv5.rs new file mode 100644 index 0000000..2481bef --- /dev/null +++ b/va416xx/src/ioconfig/clkdiv5.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CLKDIV5` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV5` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv5Spec; +impl crate::RegisterSpec for Clkdiv5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv5::R`](R) reader structure"] +impl crate::Readable for Clkdiv5Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv5::W`](W) writer structure"] +impl crate::Writable for Clkdiv5Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKDIV5 to value 0"] +impl crate::Resettable for Clkdiv5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/ioconfig/clkdiv6.rs b/va416xx/src/ioconfig/clkdiv6.rs new file mode 100644 index 0000000..cbd5c0a --- /dev/null +++ b/va416xx/src/ioconfig/clkdiv6.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CLKDIV6` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV6` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv6Spec; +impl crate::RegisterSpec for Clkdiv6Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv6::R`](R) reader structure"] +impl crate::Readable for Clkdiv6Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv6::W`](W) writer structure"] +impl crate::Writable for Clkdiv6Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKDIV6 to value 0"] +impl crate::Resettable for Clkdiv6Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/ioconfig/clkdiv7.rs b/va416xx/src/ioconfig/clkdiv7.rs new file mode 100644 index 0000000..f461430 --- /dev/null +++ b/va416xx/src/ioconfig/clkdiv7.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CLKDIV7` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV7` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Clkdiv7Spec; +impl crate::RegisterSpec for Clkdiv7Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv7::R`](R) reader structure"] +impl crate::Readable for Clkdiv7Spec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv7::W`](W) writer structure"] +impl crate::Writable for Clkdiv7Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKDIV7 to value 0"] +impl crate::Resettable for Clkdiv7Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/ioconfig/perid.rs b/va416xx/src/ioconfig/perid.rs new file mode 100644 index 0000000..6966c57 --- /dev/null +++ b/va416xx/src/ioconfig/perid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0282_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0282_07e9; +} diff --git a/va416xx/src/ioconfig/porta.rs b/va416xx/src/ioconfig/porta.rs new file mode 100644 index 0000000..b068faa --- /dev/null +++ b/va416xx/src/ioconfig/porta.rs @@ -0,0 +1,299 @@ +#[doc = "Register `PORTA[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `PORTA[%s]` writer"] +pub type W = crate::W; +#[doc = "Input Filter Selectoin\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum Flttype { + #[doc = "0: Synchronize to system clock"] + Sync = 0, + #[doc = "1: Direct input, no synchronization"] + Direct = 1, + #[doc = "2: Require 2 samples to have the same value"] + Filter1 = 2, + #[doc = "3: Require 3 samples to have the same value"] + Filter2 = 3, + #[doc = "4: Require 4 samples to have the same value"] + Filter3 = 4, + #[doc = "5: Require 5 samples to have the same value"] + Filter4 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: Flttype) -> Self { + variant as _ + } +} +impl crate::FieldSpec for Flttype { + type Ux = u8; +} +impl crate::IsEnum for Flttype {} +#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"] +pub type FlttypeR = crate::FieldReader; +impl FlttypeR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(Flttype::Sync), + 1 => Some(Flttype::Direct), + 2 => Some(Flttype::Filter1), + 3 => Some(Flttype::Filter2), + 4 => Some(Flttype::Filter3), + 5 => Some(Flttype::Filter4), + _ => None, + } + } + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + *self == Flttype::Sync + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn is_direct(&self) -> bool { + *self == Flttype::Direct + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn is_filter1(&self) -> bool { + *self == Flttype::Filter1 + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn is_filter2(&self) -> bool { + *self == Flttype::Filter2 + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn is_filter3(&self) -> bool { + *self == Flttype::Filter3 + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn is_filter4(&self) -> bool { + *self == Flttype::Filter4 + } +} +#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"] +pub type FlttypeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Flttype>; +impl<'a, REG> FlttypeW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Synchronize to system clock"] + #[inline(always)] + pub fn sync(self) -> &'a mut crate::W { + self.variant(Flttype::Sync) + } + #[doc = "Direct input, no synchronization"] + #[inline(always)] + pub fn direct(self) -> &'a mut crate::W { + self.variant(Flttype::Direct) + } + #[doc = "Require 2 samples to have the same value"] + #[inline(always)] + pub fn filter1(self) -> &'a mut crate::W { + self.variant(Flttype::Filter1) + } + #[doc = "Require 3 samples to have the same value"] + #[inline(always)] + pub fn filter2(self) -> &'a mut crate::W { + self.variant(Flttype::Filter2) + } + #[doc = "Require 4 samples to have the same value"] + #[inline(always)] + pub fn filter3(self) -> &'a mut crate::W { + self.variant(Flttype::Filter3) + } + #[doc = "Require 5 samples to have the same value"] + #[inline(always)] + pub fn filter4(self) -> &'a mut crate::W { + self.variant(Flttype::Filter4) + } +} +#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"] +pub type FltclkR = crate::FieldReader; +#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"] +pub type FltclkW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `INVINP` reader - Input Invert Selection"] +pub type InvinpR = crate::BitReader; +#[doc = "Field `INVINP` writer - Input Invert Selection"] +pub type InvinpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IEWO` reader - Input Enable While Output enabled"] +pub type IewoR = crate::BitReader; +#[doc = "Field `IEWO` writer - Input Enable While Output enabled"] +pub type IewoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"] +pub type OpendrnR = crate::BitReader; +#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"] +pub type OpendrnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INVOUT` reader - Output Invert Selection"] +pub type InvoutR = crate::BitReader; +#[doc = "Field `INVOUT` writer - Output Invert Selection"] +pub type InvoutW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"] +pub type PlevelR = crate::BitReader; +#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"] +pub type PlevelW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PEN` reader - Enable Internal Pull up/down"] +pub type PenR = crate::BitReader; +#[doc = "Field `PEN` writer - Enable Internal Pull up/down"] +pub type PenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PWOA` reader - Enable Pull when output active"] +pub type PwoaR = crate::BitReader; +#[doc = "Field `PWOA` writer - Enable Pull when output active"] +pub type PwoaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `FUNSEL` reader - Pin Function Selection"] +pub type FunselR = crate::FieldReader; +#[doc = "Field `FUNSEL` writer - Pin Function Selection"] +pub type FunselW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `IODIS` reader - IO Pin Disable"] +pub type IodisR = crate::BitReader; +#[doc = "Field `IODIS` writer - IO Pin Disable"] +pub type IodisW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + pub fn flttype(&self) -> FlttypeR { + FlttypeR::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + pub fn fltclk(&self) -> FltclkR { + FltclkR::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + pub fn invinp(&self) -> InvinpR { + InvinpR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + pub fn iewo(&self) -> IewoR { + IewoR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + pub fn opendrn(&self) -> OpendrnR { + OpendrnR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + pub fn invout(&self) -> InvoutR { + InvoutR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + pub fn plevel(&self) -> PlevelR { + PlevelR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + pub fn pen(&self) -> PenR { + PenR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + pub fn pwoa(&self) -> PwoaR { + PwoaR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + pub fn funsel(&self) -> FunselR { + FunselR::new(((self.bits >> 13) & 7) as u8) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + pub fn iodis(&self) -> IodisR { + IodisR::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Filter Selectoin"] + #[inline(always)] + #[must_use] + pub fn flttype(&mut self) -> FlttypeW { + FlttypeW::new(self, 0) + } + #[doc = "Bits 3:5 - Input Filter Clock Selection"] + #[inline(always)] + #[must_use] + pub fn fltclk(&mut self) -> FltclkW { + FltclkW::new(self, 3) + } + #[doc = "Bit 6 - Input Invert Selection"] + #[inline(always)] + #[must_use] + pub fn invinp(&mut self) -> InvinpW { + InvinpW::new(self, 6) + } + #[doc = "Bit 7 - Input Enable While Output enabled"] + #[inline(always)] + #[must_use] + pub fn iewo(&mut self) -> IewoW { + IewoW::new(self, 7) + } + #[doc = "Bit 8 - Output Open Drain Mode"] + #[inline(always)] + #[must_use] + pub fn opendrn(&mut self) -> OpendrnW { + OpendrnW::new(self, 8) + } + #[doc = "Bit 9 - Output Invert Selection"] + #[inline(always)] + #[must_use] + pub fn invout(&mut self) -> InvoutW { + InvoutW::new(self, 9) + } + #[doc = "Bit 10 - Internal Pull up/down level"] + #[inline(always)] + #[must_use] + pub fn plevel(&mut self) -> PlevelW { + PlevelW::new(self, 10) + } + #[doc = "Bit 11 - Enable Internal Pull up/down"] + #[inline(always)] + #[must_use] + pub fn pen(&mut self) -> PenW { + PenW::new(self, 11) + } + #[doc = "Bit 12 - Enable Pull when output active"] + #[inline(always)] + #[must_use] + pub fn pwoa(&mut self) -> PwoaW { + PwoaW::new(self, 12) + } + #[doc = "Bits 13:15 - Pin Function Selection"] + #[inline(always)] + #[must_use] + pub fn funsel(&mut self) -> FunselW { + FunselW::new(self, 13) + } + #[doc = "Bit 16 - IO Pin Disable"] + #[inline(always)] + #[must_use] + pub fn iodis(&mut self) -> IodisW { + IodisW::new(self, 16) + } +} +#[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PortaSpec; +impl crate::RegisterSpec for PortaSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`porta::R`](R) reader structure"] +impl crate::Readable for PortaSpec {} +#[doc = "`write(|w| ..)` method takes [`porta::W`](W) writer structure"] +impl crate::Writable for PortaSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PORTA[%s] +to value 0"] +impl crate::Resettable for PortaSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/irq_router.rs b/va416xx/src/irq_router.rs new file mode 100644 index 0000000..af90499 --- /dev/null +++ b/va416xx/src/irq_router.rs @@ -0,0 +1,187 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + dmasel0: Dmasel0, + dmasel1: Dmasel1, + dmasel2: Dmasel2, + dmasel3: Dmasel3, + dmattsel: Dmattsel, + adcsel: Adcsel, + dacsel0: Dacsel0, + dacsel1: Dacsel1, + irq_out0: IrqOut0, + irq_out1: IrqOut1, + irq_out2: IrqOut2, + irq_out3: IrqOut3, + irq_out4: IrqOut4, + irq_out5: IrqOut5, + _reserved14: [u8; 0x0fc4], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Interrupt select for DMA channel 0"] + #[inline(always)] + pub const fn dmasel0(&self) -> &Dmasel0 { + &self.dmasel0 + } + #[doc = "0x04 - Interrupt select for DMA channel 1"] + #[inline(always)] + pub const fn dmasel1(&self) -> &Dmasel1 { + &self.dmasel1 + } + #[doc = "0x08 - Interrupt select for DMA channel 2"] + #[inline(always)] + pub const fn dmasel2(&self) -> &Dmasel2 { + &self.dmasel2 + } + #[doc = "0x0c - Interrupt select for DMA channel 3"] + #[inline(always)] + pub const fn dmasel3(&self) -> &Dmasel3 { + &self.dmasel3 + } + #[doc = "0x10 - Trigger select for the DMA channels"] + #[inline(always)] + pub const fn dmattsel(&self) -> &Dmattsel { + &self.dmattsel + } + #[doc = "0x14 - Interrupt select for ADC"] + #[inline(always)] + pub const fn adcsel(&self) -> &Adcsel { + &self.adcsel + } + #[doc = "0x18 - Interrupt select for DAC0"] + #[inline(always)] + pub const fn dacsel0(&self) -> &Dacsel0 { + &self.dacsel0 + } + #[doc = "0x1c - Interrupt select for DAC1"] + #[inline(always)] + pub const fn dacsel1(&self) -> &Dacsel1 { + &self.dacsel1 + } + #[doc = "0x20 - DEBUG IRQ_OUT\\[31:0\\]"] + #[inline(always)] + pub const fn irq_out0(&self) -> &IrqOut0 { + &self.irq_out0 + } + #[doc = "0x24 - DEBUG IRQ_OUT\\[63:32\\]"] + #[inline(always)] + pub const fn irq_out1(&self) -> &IrqOut1 { + &self.irq_out1 + } + #[doc = "0x28 - DEBUG IRQ_OUT\\[95:64\\]"] + #[inline(always)] + pub const fn irq_out2(&self) -> &IrqOut2 { + &self.irq_out2 + } + #[doc = "0x2c - DEBUG IRQ_OUT\\[127:96\\]"] + #[inline(always)] + pub const fn irq_out3(&self) -> &IrqOut3 { + &self.irq_out3 + } + #[doc = "0x30 - DEBUG IRQ_OUT\\[159:128\\]"] + #[inline(always)] + pub const fn irq_out4(&self) -> &IrqOut4 { + &self.irq_out4 + } + #[doc = "0x34 - DEBUG IRQ_OUT\\[179:160\\]"] + #[inline(always)] + pub const fn irq_out5(&self) -> &IrqOut5 { + &self.irq_out5 + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "DMASEL0 (rw) register accessor: Interrupt select for DMA channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasel0`] +module"] +#[doc(alias = "DMASEL0")] +pub type Dmasel0 = crate::Reg; +#[doc = "Interrupt select for DMA channel 0"] +pub mod dmasel0; +#[doc = "DMASEL1 (rw) register accessor: Interrupt select for DMA channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasel1`] +module"] +#[doc(alias = "DMASEL1")] +pub type Dmasel1 = crate::Reg; +#[doc = "Interrupt select for DMA channel 1"] +pub mod dmasel1; +#[doc = "DMASEL2 (rw) register accessor: Interrupt select for DMA channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasel2`] +module"] +#[doc(alias = "DMASEL2")] +pub type Dmasel2 = crate::Reg; +#[doc = "Interrupt select for DMA channel 2"] +pub mod dmasel2; +#[doc = "DMASEL3 (rw) register accessor: Interrupt select for DMA channel 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel3::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasel3`] +module"] +#[doc(alias = "DMASEL3")] +pub type Dmasel3 = crate::Reg; +#[doc = "Interrupt select for DMA channel 3"] +pub mod dmasel3; +#[doc = "DMATTSEL (rw) register accessor: Trigger select for the DMA channels\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmattsel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmattsel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmattsel`] +module"] +#[doc(alias = "DMATTSEL")] +pub type Dmattsel = crate::Reg; +#[doc = "Trigger select for the DMA channels"] +pub mod dmattsel; +#[doc = "ADCSEL (rw) register accessor: Interrupt select for ADC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcsel::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcsel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adcsel`] +module"] +#[doc(alias = "ADCSEL")] +pub type Adcsel = crate::Reg; +#[doc = "Interrupt select for ADC"] +pub mod adcsel; +#[doc = "DACSEL0 (rw) register accessor: Interrupt select for DAC0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dacsel0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dacsel0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dacsel0`] +module"] +#[doc(alias = "DACSEL0")] +pub type Dacsel0 = crate::Reg; +#[doc = "Interrupt select for DAC0"] +pub mod dacsel0; +#[doc = "DACSEL1 (rw) register accessor: Interrupt select for DAC1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dacsel1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dacsel1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dacsel1`] +module"] +#[doc(alias = "DACSEL1")] +pub type Dacsel1 = crate::Reg; +#[doc = "Interrupt select for DAC1"] +pub mod dacsel1; +#[doc = "IRQ_OUT0 (r) register accessor: DEBUG IRQ_OUT\\[31:0\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out0`] +module"] +#[doc(alias = "IRQ_OUT0")] +pub type IrqOut0 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[31:0\\]"] +pub mod irq_out0; +#[doc = "IRQ_OUT1 (r) register accessor: DEBUG IRQ_OUT\\[63:32\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out1`] +module"] +#[doc(alias = "IRQ_OUT1")] +pub type IrqOut1 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[63:32\\]"] +pub mod irq_out1; +#[doc = "IRQ_OUT2 (r) register accessor: DEBUG IRQ_OUT\\[95:64\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out2`] +module"] +#[doc(alias = "IRQ_OUT2")] +pub type IrqOut2 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[95:64\\]"] +pub mod irq_out2; +#[doc = "IRQ_OUT3 (r) register accessor: DEBUG IRQ_OUT\\[127:96\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out3`] +module"] +#[doc(alias = "IRQ_OUT3")] +pub type IrqOut3 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[127:96\\]"] +pub mod irq_out3; +#[doc = "IRQ_OUT4 (r) register accessor: DEBUG IRQ_OUT\\[159:128\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out4::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out4`] +module"] +#[doc(alias = "IRQ_OUT4")] +pub type IrqOut4 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[159:128\\]"] +pub mod irq_out4; +#[doc = "IRQ_OUT5 (r) register accessor: DEBUG IRQ_OUT\\[179:160\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out5::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_out5`] +module"] +#[doc(alias = "IRQ_OUT5")] +pub type IrqOut5 = crate::Reg; +#[doc = "DEBUG IRQ_OUT\\[179:160\\]"] +pub mod irq_out5; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/irq_router/adcsel.rs b/va416xx/src/irq_router/adcsel.rs new file mode 100644 index 0000000..849fcdd --- /dev/null +++ b/va416xx/src/irq_router/adcsel.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ADCSEL` reader"] +pub type R = crate::R; +#[doc = "Register `ADCSEL` writer"] +pub type W = crate::W; +#[doc = "Field `ADCSEL` reader - ADC trigger source selection value"] +pub type AdcselR = crate::FieldReader; +#[doc = "Field `ADCSEL` writer - ADC trigger source selection value"] +pub type AdcselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - ADC trigger source selection value"] + #[inline(always)] + pub fn adcsel(&self) -> AdcselR { + AdcselR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - ADC trigger source selection value"] + #[inline(always)] + #[must_use] + pub fn adcsel(&mut self) -> AdcselW { + AdcselW::new(self, 0) + } +} +#[doc = "Interrupt select for ADC\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adcsel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adcsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AdcselSpec; +impl crate::RegisterSpec for AdcselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`adcsel::R`](R) reader structure"] +impl crate::Readable for AdcselSpec {} +#[doc = "`write(|w| ..)` method takes [`adcsel::W`](W) writer structure"] +impl crate::Writable for AdcselSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ADCSEL to value 0x1f"] +impl crate::Resettable for AdcselSpec { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/va416xx/src/irq_router/dacsel0.rs b/va416xx/src/irq_router/dacsel0.rs new file mode 100644 index 0000000..4ca1863 --- /dev/null +++ b/va416xx/src/irq_router/dacsel0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DACSEL0` reader"] +pub type R = crate::R; +#[doc = "Register `DACSEL0` writer"] +pub type W = crate::W; +#[doc = "Field `DACSEL` reader - DAC trigger source selection value"] +pub type DacselR = crate::FieldReader; +#[doc = "Field `DACSEL` writer - DAC trigger source selection value"] +pub type DacselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + pub fn dacsel(&self) -> DacselR { + DacselR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + #[must_use] + pub fn dacsel(&mut self) -> DacselW { + DacselW::new(self, 0) + } +} +#[doc = "Interrupt select for DAC0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dacsel0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dacsel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dacsel0Spec; +impl crate::RegisterSpec for Dacsel0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dacsel0::R`](R) reader structure"] +impl crate::Readable for Dacsel0Spec {} +#[doc = "`write(|w| ..)` method takes [`dacsel0::W`](W) writer structure"] +impl crate::Writable for Dacsel0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DACSEL0 to value 0x1f"] +impl crate::Resettable for Dacsel0Spec { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/va416xx/src/irq_router/dacsel1.rs b/va416xx/src/irq_router/dacsel1.rs new file mode 100644 index 0000000..7142161 --- /dev/null +++ b/va416xx/src/irq_router/dacsel1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DACSEL1` reader"] +pub type R = crate::R; +#[doc = "Register `DACSEL1` writer"] +pub type W = crate::W; +#[doc = "Field `DACSEL` reader - DAC trigger source selection value"] +pub type DacselR = crate::FieldReader; +#[doc = "Field `DACSEL` writer - DAC trigger source selection value"] +pub type DacselW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +impl R { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + pub fn dacsel(&self) -> DacselR { + DacselR::new((self.bits & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - DAC trigger source selection value"] + #[inline(always)] + #[must_use] + pub fn dacsel(&mut self) -> DacselW { + DacselW::new(self, 0) + } +} +#[doc = "Interrupt select for DAC1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dacsel1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dacsel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dacsel1Spec; +impl crate::RegisterSpec for Dacsel1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dacsel1::R`](R) reader structure"] +impl crate::Readable for Dacsel1Spec {} +#[doc = "`write(|w| ..)` method takes [`dacsel1::W`](W) writer structure"] +impl crate::Writable for Dacsel1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DACSEL1 to value 0x1f"] +impl crate::Resettable for Dacsel1Spec { + const RESET_VALUE: u32 = 0x1f; +} diff --git a/va416xx/src/irq_router/dmasel0.rs b/va416xx/src/irq_router/dmasel0.rs new file mode 100644 index 0000000..870f94e --- /dev/null +++ b/va416xx/src/irq_router/dmasel0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMASEL0` reader"] +pub type R = crate::R; +#[doc = "Register `DMASEL0` writer"] +pub type W = crate::W; +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub type DmaselR = crate::FieldReader; +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub type DmaselW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DmaselR { + DmaselR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + #[must_use] + pub fn dmasel(&mut self) -> DmaselW { + DmaselW::new(self, 0) + } +} +#[doc = "Interrupt select for DMA channel 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmasel0Spec; +impl crate::RegisterSpec for Dmasel0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmasel0::R`](R) reader structure"] +impl crate::Readable for Dmasel0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmasel0::W`](W) writer structure"] +impl crate::Writable for Dmasel0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMASEL0 to value 0x7f"] +impl crate::Resettable for Dmasel0Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/va416xx/src/irq_router/dmasel1.rs b/va416xx/src/irq_router/dmasel1.rs new file mode 100644 index 0000000..e9c43c3 --- /dev/null +++ b/va416xx/src/irq_router/dmasel1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMASEL1` reader"] +pub type R = crate::R; +#[doc = "Register `DMASEL1` writer"] +pub type W = crate::W; +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub type DmaselR = crate::FieldReader; +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub type DmaselW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DmaselR { + DmaselR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + #[must_use] + pub fn dmasel(&mut self) -> DmaselW { + DmaselW::new(self, 0) + } +} +#[doc = "Interrupt select for DMA channel 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmasel1Spec; +impl crate::RegisterSpec for Dmasel1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmasel1::R`](R) reader structure"] +impl crate::Readable for Dmasel1Spec {} +#[doc = "`write(|w| ..)` method takes [`dmasel1::W`](W) writer structure"] +impl crate::Writable for Dmasel1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMASEL1 to value 0x7f"] +impl crate::Resettable for Dmasel1Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/va416xx/src/irq_router/dmasel2.rs b/va416xx/src/irq_router/dmasel2.rs new file mode 100644 index 0000000..02285a2 --- /dev/null +++ b/va416xx/src/irq_router/dmasel2.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMASEL2` reader"] +pub type R = crate::R; +#[doc = "Register `DMASEL2` writer"] +pub type W = crate::W; +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub type DmaselR = crate::FieldReader; +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub type DmaselW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DmaselR { + DmaselR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + #[must_use] + pub fn dmasel(&mut self) -> DmaselW { + DmaselW::new(self, 0) + } +} +#[doc = "Interrupt select for DMA channel 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmasel2Spec; +impl crate::RegisterSpec for Dmasel2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmasel2::R`](R) reader structure"] +impl crate::Readable for Dmasel2Spec {} +#[doc = "`write(|w| ..)` method takes [`dmasel2::W`](W) writer structure"] +impl crate::Writable for Dmasel2Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMASEL2 to value 0x7f"] +impl crate::Resettable for Dmasel2Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/va416xx/src/irq_router/dmasel3.rs b/va416xx/src/irq_router/dmasel3.rs new file mode 100644 index 0000000..2d4d1e8 --- /dev/null +++ b/va416xx/src/irq_router/dmasel3.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMASEL3` reader"] +pub type R = crate::R; +#[doc = "Register `DMASEL3` writer"] +pub type W = crate::W; +#[doc = "Field `DMASEL` reader - DMA trigger source selection value"] +pub type DmaselR = crate::FieldReader; +#[doc = "Field `DMASEL` writer - DMA trigger source selection value"] +pub type DmaselW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +impl R { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + pub fn dmasel(&self) -> DmaselR { + DmaselR::new((self.bits & 0x7f) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - DMA trigger source selection value"] + #[inline(always)] + #[must_use] + pub fn dmasel(&mut self) -> DmaselW { + DmaselW::new(self, 0) + } +} +#[doc = "Interrupt select for DMA channel 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasel3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasel3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmasel3Spec; +impl crate::RegisterSpec for Dmasel3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmasel3::R`](R) reader structure"] +impl crate::Readable for Dmasel3Spec {} +#[doc = "`write(|w| ..)` method takes [`dmasel3::W`](W) writer structure"] +impl crate::Writable for Dmasel3Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMASEL3 to value 0x7f"] +impl crate::Resettable for Dmasel3Spec { + const RESET_VALUE: u32 = 0x7f; +} diff --git a/va416xx/src/irq_router/dmattsel.rs b/va416xx/src/irq_router/dmattsel.rs new file mode 100644 index 0000000..76e73c4 --- /dev/null +++ b/va416xx/src/irq_router/dmattsel.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMATTSEL` reader"] +pub type R = crate::R; +#[doc = "Register `DMATTSEL` writer"] +pub type W = crate::W; +#[doc = "Field `DMATTSEL` reader - DMA trigger type selection value"] +pub type DmattselR = crate::FieldReader; +#[doc = "Field `DMATTSEL` writer - DMA trigger type selection value"] +pub type DmattselW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +impl R { + #[doc = "Bits 0:3 - DMA trigger type selection value"] + #[inline(always)] + pub fn dmattsel(&self) -> DmattselR { + DmattselR::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - DMA trigger type selection value"] + #[inline(always)] + #[must_use] + pub fn dmattsel(&mut self) -> DmattselW { + DmattselW::new(self, 0) + } +} +#[doc = "Trigger select for the DMA channels\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmattsel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmattsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DmattselSpec; +impl crate::RegisterSpec for DmattselSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmattsel::R`](R) reader structure"] +impl crate::Readable for DmattselSpec {} +#[doc = "`write(|w| ..)` method takes [`dmattsel::W`](W) writer structure"] +impl crate::Writable for DmattselSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMATTSEL to value 0"] +impl crate::Resettable for DmattselSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/irq_router/irq_out0.rs b/va416xx/src/irq_router/irq_out0.rs new file mode 100644 index 0000000..2fbde74 --- /dev/null +++ b/va416xx/src/irq_router/irq_out0.rs @@ -0,0 +1,22 @@ +#[doc = "Register `IRQ_OUT0` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT0` reader - IRQ_OUT\\[31:0\\]"] +pub type IrqOut0R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[31:0\\]"] + #[inline(always)] + pub fn irq_out0(&self) -> IrqOut0R { + IrqOut0R::new(self.bits) + } +} +#[doc = "DEBUG IRQ_OUT\\[31:0\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut0Spec; +impl crate::RegisterSpec for IrqOut0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out0::R`](R) reader structure"] +impl crate::Readable for IrqOut0Spec {} +#[doc = "`reset()` method sets IRQ_OUT0 to value 0"] +impl crate::Resettable for IrqOut0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/irq_router/irq_out1.rs b/va416xx/src/irq_router/irq_out1.rs new file mode 100644 index 0000000..aff0f39 --- /dev/null +++ b/va416xx/src/irq_router/irq_out1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `IRQ_OUT1` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT1` reader - IRQ_OUT\\[63:32\\]"] +pub type IrqOut1R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[63:32\\]"] + #[inline(always)] + pub fn irq_out1(&self) -> IrqOut1R { + IrqOut1R::new(self.bits) + } +} +#[doc = "DEBUG IRQ_OUT\\[63:32\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut1Spec; +impl crate::RegisterSpec for IrqOut1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out1::R`](R) reader structure"] +impl crate::Readable for IrqOut1Spec {} +#[doc = "`reset()` method sets IRQ_OUT1 to value 0"] +impl crate::Resettable for IrqOut1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/irq_router/irq_out2.rs b/va416xx/src/irq_router/irq_out2.rs new file mode 100644 index 0000000..4f3275c --- /dev/null +++ b/va416xx/src/irq_router/irq_out2.rs @@ -0,0 +1,22 @@ +#[doc = "Register `IRQ_OUT2` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT2` reader - IRQ_OUT\\[95:64\\]"] +pub type IrqOut2R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[95:64\\]"] + #[inline(always)] + pub fn irq_out2(&self) -> IrqOut2R { + IrqOut2R::new(self.bits) + } +} +#[doc = "DEBUG IRQ_OUT\\[95:64\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut2Spec; +impl crate::RegisterSpec for IrqOut2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out2::R`](R) reader structure"] +impl crate::Readable for IrqOut2Spec {} +#[doc = "`reset()` method sets IRQ_OUT2 to value 0"] +impl crate::Resettable for IrqOut2Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/irq_router/irq_out3.rs b/va416xx/src/irq_router/irq_out3.rs new file mode 100644 index 0000000..adb5998 --- /dev/null +++ b/va416xx/src/irq_router/irq_out3.rs @@ -0,0 +1,22 @@ +#[doc = "Register `IRQ_OUT3` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT3` reader - IRQ_OUT\\[127:96\\]"] +pub type IrqOut3R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[127:96\\]"] + #[inline(always)] + pub fn irq_out3(&self) -> IrqOut3R { + IrqOut3R::new(self.bits) + } +} +#[doc = "DEBUG IRQ_OUT\\[127:96\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut3Spec; +impl crate::RegisterSpec for IrqOut3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out3::R`](R) reader structure"] +impl crate::Readable for IrqOut3Spec {} +#[doc = "`reset()` method sets IRQ_OUT3 to value 0"] +impl crate::Resettable for IrqOut3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/irq_router/irq_out4.rs b/va416xx/src/irq_router/irq_out4.rs new file mode 100644 index 0000000..2fd418a --- /dev/null +++ b/va416xx/src/irq_router/irq_out4.rs @@ -0,0 +1,22 @@ +#[doc = "Register `IRQ_OUT4` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT4` reader - IRQ_OUT\\[159:128\\]"] +pub type IrqOut4R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - IRQ_OUT\\[159:128\\]"] + #[inline(always)] + pub fn irq_out4(&self) -> IrqOut4R { + IrqOut4R::new(self.bits) + } +} +#[doc = "DEBUG IRQ_OUT\\[159:128\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out4::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut4Spec; +impl crate::RegisterSpec for IrqOut4Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out4::R`](R) reader structure"] +impl crate::Readable for IrqOut4Spec {} +#[doc = "`reset()` method sets IRQ_OUT4 to value 0"] +impl crate::Resettable for IrqOut4Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/irq_router/irq_out5.rs b/va416xx/src/irq_router/irq_out5.rs new file mode 100644 index 0000000..efb2f8c --- /dev/null +++ b/va416xx/src/irq_router/irq_out5.rs @@ -0,0 +1,22 @@ +#[doc = "Register `IRQ_OUT5` reader"] +pub type R = crate::R; +#[doc = "Field `IRQ_OUT5` reader - IRQ_OUT\\[179:160\\]"] +pub type IrqOut5R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - IRQ_OUT\\[179:160\\]"] + #[inline(always)] + pub fn irq_out5(&self) -> IrqOut5R { + IrqOut5R::new(self.bits & 0x000f_ffff) + } +} +#[doc = "DEBUG IRQ_OUT\\[179:160\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_out5::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqOut5Spec; +impl crate::RegisterSpec for IrqOut5Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_out5::R`](R) reader structure"] +impl crate::Readable for IrqOut5Spec {} +#[doc = "`reset()` method sets IRQ_OUT5 to value 0"] +impl crate::Resettable for IrqOut5Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/irq_router/perid.rs b/va416xx/src/irq_router/perid.rs new file mode 100644 index 0000000..4ad66bc --- /dev/null +++ b/va416xx/src/irq_router/perid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0281_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0281_07e9; +} diff --git a/va416xx/src/lib.rs b/va416xx/src/lib.rs new file mode 100644 index 0000000..aed7d6d --- /dev/null +++ b/va416xx/src/lib.rs @@ -0,0 +1,3757 @@ +#![doc = "Peripheral access API for VA416XX microcontrollers (generated using svd2rust v0.33.3 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.33.3/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +// Manually inserted. +#![cfg_attr(docsrs, feature(doc_auto_cfg))] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 4; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn U0(); + fn U1(); + fn U2(); + fn U3(); + fn U4(); + fn U5(); + fn U6(); + fn U7(); + fn U8(); + fn U9(); + fn U10(); + fn U11(); + fn U12(); + fn U13(); + fn U14(); + fn U15(); + fn SPI0_TX(); + fn SPI0_RX(); + fn SPI1_TX(); + fn SPI1_RX(); + fn SPI2_TX(); + fn SPI2_RX(); + fn SPI3_TX(); + fn SPI3_RX(); + fn UART0_TX(); + fn UART0_RX(); + fn UART1_TX(); + fn UART1_RX(); + fn UART2_TX(); + fn UART2_RX(); + fn I2C0_MS(); + fn I2C0_SL(); + fn I2C1_MS(); + fn I2C1_SL(); + fn I2C2_MS(); + fn I2C2_SL(); + fn Ethernet(); + fn U37(); + fn SpW(); + fn U39(); + fn DAC0(); + fn DAC1(); + fn TRNG(); + fn DMA_ERROR(); + fn ADC(); + fn LoCLK(); + fn LVD(); + fn WATCHDOG(); + fn TIM0(); + fn TIM1(); + fn TIM2(); + fn TIM3(); + fn TIM4(); + fn TIM5(); + fn TIM6(); + fn TIM7(); + fn TIM8(); + fn TIM9(); + fn TIM10(); + fn TIM11(); + fn TIM12(); + fn TIM13(); + fn TIM14(); + fn TIM15(); + fn TIM16(); + fn TIM17(); + fn TIM18(); + fn TIM19(); + fn TIM20(); + fn TIM21(); + fn TIM22(); + fn TIM23(); + fn CAN0(); + fn U73(); + fn CAN1(); + fn U75(); + fn EDAC_MBE(); + fn EDAC_SBE(); + fn PORTA0(); + fn PORTA1(); + fn PORTA2(); + fn PORTA3(); + fn PORTA4(); + fn PORTA5(); + fn PORTA6(); + fn PORTA7(); + fn PORTA8(); + fn PORTA9(); + fn PORTA10(); + fn PORTA11(); + fn PORTA12(); + fn PORTA13(); + fn PORTA14(); + fn PORTA15(); + fn PORTB0(); + fn PORTB1(); + fn PORTB2(); + fn PORTB3(); + fn PORTB4(); + fn PORTB5(); + fn PORTB6(); + fn PORTB7(); + fn PORTB8(); + fn PORTB9(); + fn PORTB10(); + fn PORTB11(); + fn PORTB12(); + fn PORTB13(); + fn PORTB14(); + fn PORTB15(); + fn PORTC0(); + fn PORTC1(); + fn PORTC2(); + fn PORTC3(); + fn PORTC4(); + fn PORTC5(); + fn PORTC6(); + fn PORTC7(); + fn PORTC8(); + fn PORTC9(); + fn PORTC10(); + fn PORTC11(); + fn PORTC12(); + fn PORTC13(); + fn PORTC14(); + fn PORTC15(); + fn PORTD0(); + fn PORTD1(); + fn PORTD2(); + fn PORTD3(); + fn PORTD4(); + fn PORTD5(); + fn PORTD6(); + fn PORTD7(); + fn PORTD8(); + fn PORTD9(); + fn PORTD10(); + fn PORTD11(); + fn PORTD12(); + fn PORTD13(); + fn PORTD14(); + fn PORTD15(); + fn PORTE0(); + fn PORTE1(); + fn PORTE2(); + fn PORTE3(); + fn PORTE4(); + fn PORTE5(); + fn PORTE6(); + fn PORTE7(); + fn PORTE8(); + fn PORTE9(); + fn PORTE10(); + fn PORTE11(); + fn PORTE12(); + fn PORTE13(); + fn PORTE14(); + fn PORTE15(); + fn PORTF0(); + fn PORTF1(); + fn PORTF2(); + fn PORTF3(); + fn PORTF4(); + fn PORTF5(); + fn PORTF6(); + fn PORTF7(); + fn PORTF8(); + fn PORTF9(); + fn PORTF10(); + fn PORTF11(); + fn PORTF12(); + fn PORTF13(); + fn PORTF14(); + fn PORTF15(); + fn DMA_ACTIVE0(); + fn DMA_ACTIVE1(); + fn DMA_ACTIVE2(); + fn DMA_ACTIVE3(); + fn DMA_DONE0(); + fn DMA_DONE1(); + fn DMA_DONE2(); + fn DMA_DONE3(); + fn I2C0_MS_RX(); + fn I2C0_MS_TX(); + fn I2C0_SL_RX(); + fn I2C0_SL_TX(); + fn I2C1_MS_RX(); + fn I2C1_MS_TX(); + fn I2C1_SL_RX(); + fn I2C1_SL_TX(); + fn I2C2_MS_RX(); + fn I2C2_MS_TX(); + fn I2C2_SL_RX(); + fn I2C2_SL_TX(); + fn FPU(); + fn TXEV(); +} +#[doc(hidden)] +#[repr(C)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 196] = [ + Vector { _handler: U0 }, + Vector { _handler: U1 }, + Vector { _handler: U2 }, + Vector { _handler: U3 }, + Vector { _handler: U4 }, + Vector { _handler: U5 }, + Vector { _handler: U6 }, + Vector { _handler: U7 }, + Vector { _handler: U8 }, + Vector { _handler: U9 }, + Vector { _handler: U10 }, + Vector { _handler: U11 }, + Vector { _handler: U12 }, + Vector { _handler: U13 }, + Vector { _handler: U14 }, + Vector { _handler: U15 }, + Vector { _handler: SPI0_TX }, + Vector { _handler: SPI0_RX }, + Vector { _handler: SPI1_TX }, + Vector { _handler: SPI1_RX }, + Vector { _handler: SPI2_TX }, + Vector { _handler: SPI2_RX }, + Vector { _handler: SPI3_TX }, + Vector { _handler: SPI3_RX }, + Vector { _handler: UART0_TX }, + Vector { _handler: UART0_RX }, + Vector { _handler: UART1_TX }, + Vector { _handler: UART1_RX }, + Vector { _handler: UART2_TX }, + Vector { _handler: UART2_RX }, + Vector { _handler: I2C0_MS }, + Vector { _handler: I2C0_SL }, + Vector { _handler: I2C1_MS }, + Vector { _handler: I2C1_SL }, + Vector { _handler: I2C2_MS }, + Vector { _handler: I2C2_SL }, + Vector { _handler: Ethernet }, + Vector { _handler: U37 }, + Vector { _handler: SpW }, + Vector { _handler: U39 }, + Vector { _handler: DAC0 }, + Vector { _handler: DAC1 }, + Vector { _handler: TRNG }, + Vector { + _handler: DMA_ERROR, + }, + Vector { _handler: ADC }, + Vector { _handler: LoCLK }, + Vector { _handler: LVD }, + Vector { _handler: WATCHDOG }, + Vector { _handler: TIM0 }, + Vector { _handler: TIM1 }, + Vector { _handler: TIM2 }, + Vector { _handler: TIM3 }, + Vector { _handler: TIM4 }, + Vector { _handler: TIM5 }, + Vector { _handler: TIM6 }, + Vector { _handler: TIM7 }, + Vector { _handler: TIM8 }, + Vector { _handler: TIM9 }, + Vector { _handler: TIM10 }, + Vector { _handler: TIM11 }, + Vector { _handler: TIM12 }, + Vector { _handler: TIM13 }, + Vector { _handler: TIM14 }, + Vector { _handler: TIM15 }, + Vector { _handler: TIM16 }, + Vector { _handler: TIM17 }, + Vector { _handler: TIM18 }, + Vector { _handler: TIM19 }, + Vector { _handler: TIM20 }, + Vector { _handler: TIM21 }, + Vector { _handler: TIM22 }, + Vector { _handler: TIM23 }, + Vector { _handler: CAN0 }, + Vector { _handler: U73 }, + Vector { _handler: CAN1 }, + Vector { _handler: U75 }, + Vector { _handler: EDAC_MBE }, + Vector { _handler: EDAC_SBE }, + Vector { _handler: PORTA0 }, + Vector { _handler: PORTA1 }, + Vector { _handler: PORTA2 }, + Vector { _handler: PORTA3 }, + Vector { _handler: PORTA4 }, + Vector { _handler: PORTA5 }, + Vector { _handler: PORTA6 }, + Vector { _handler: PORTA7 }, + Vector { _handler: PORTA8 }, + Vector { _handler: PORTA9 }, + Vector { _handler: PORTA10 }, + Vector { _handler: PORTA11 }, + Vector { _handler: PORTA12 }, + Vector { _handler: PORTA13 }, + Vector { _handler: PORTA14 }, + Vector { _handler: PORTA15 }, + Vector { _handler: PORTB0 }, + Vector { _handler: PORTB1 }, + Vector { _handler: PORTB2 }, + Vector { _handler: PORTB3 }, + Vector { _handler: PORTB4 }, + Vector { _handler: PORTB5 }, + Vector { _handler: PORTB6 }, + Vector { _handler: PORTB7 }, + Vector { _handler: PORTB8 }, + Vector { _handler: PORTB9 }, + Vector { _handler: PORTB10 }, + Vector { _handler: PORTB11 }, + Vector { _handler: PORTB12 }, + Vector { _handler: PORTB13 }, + Vector { _handler: PORTB14 }, + Vector { _handler: PORTB15 }, + Vector { _handler: PORTC0 }, + Vector { _handler: PORTC1 }, + Vector { _handler: PORTC2 }, + Vector { _handler: PORTC3 }, + Vector { _handler: PORTC4 }, + Vector { _handler: PORTC5 }, + Vector { _handler: PORTC6 }, + Vector { _handler: PORTC7 }, + Vector { _handler: PORTC8 }, + Vector { _handler: PORTC9 }, + Vector { _handler: PORTC10 }, + Vector { _handler: PORTC11 }, + Vector { _handler: PORTC12 }, + Vector { _handler: PORTC13 }, + Vector { _handler: PORTC14 }, + Vector { _handler: PORTC15 }, + Vector { _handler: PORTD0 }, + Vector { _handler: PORTD1 }, + Vector { _handler: PORTD2 }, + Vector { _handler: PORTD3 }, + Vector { _handler: PORTD4 }, + Vector { _handler: PORTD5 }, + Vector { _handler: PORTD6 }, + Vector { _handler: PORTD7 }, + Vector { _handler: PORTD8 }, + Vector { _handler: PORTD9 }, + Vector { _handler: PORTD10 }, + Vector { _handler: PORTD11 }, + Vector { _handler: PORTD12 }, + Vector { _handler: PORTD13 }, + Vector { _handler: PORTD14 }, + Vector { _handler: PORTD15 }, + Vector { _handler: PORTE0 }, + Vector { _handler: PORTE1 }, + Vector { _handler: PORTE2 }, + Vector { _handler: PORTE3 }, + Vector { _handler: PORTE4 }, + Vector { _handler: PORTE5 }, + Vector { _handler: PORTE6 }, + Vector { _handler: PORTE7 }, + Vector { _handler: PORTE8 }, + Vector { _handler: PORTE9 }, + Vector { _handler: PORTE10 }, + Vector { _handler: PORTE11 }, + Vector { _handler: PORTE12 }, + Vector { _handler: PORTE13 }, + Vector { _handler: PORTE14 }, + Vector { _handler: PORTE15 }, + Vector { _handler: PORTF0 }, + Vector { _handler: PORTF1 }, + Vector { _handler: PORTF2 }, + Vector { _handler: PORTF3 }, + Vector { _handler: PORTF4 }, + Vector { _handler: PORTF5 }, + Vector { _handler: PORTF6 }, + Vector { _handler: PORTF7 }, + Vector { _handler: PORTF8 }, + Vector { _handler: PORTF9 }, + Vector { _handler: PORTF10 }, + Vector { _handler: PORTF11 }, + Vector { _handler: PORTF12 }, + Vector { _handler: PORTF13 }, + Vector { _handler: PORTF14 }, + Vector { _handler: PORTF15 }, + Vector { + _handler: DMA_ACTIVE0, + }, + Vector { + _handler: DMA_ACTIVE1, + }, + Vector { + _handler: DMA_ACTIVE2, + }, + Vector { + _handler: DMA_ACTIVE3, + }, + Vector { + _handler: DMA_DONE0, + }, + Vector { + _handler: DMA_DONE1, + }, + Vector { + _handler: DMA_DONE2, + }, + Vector { + _handler: DMA_DONE3, + }, + Vector { + _handler: I2C0_MS_RX, + }, + Vector { + _handler: I2C0_MS_TX, + }, + Vector { + _handler: I2C0_SL_RX, + }, + Vector { + _handler: I2C0_SL_TX, + }, + Vector { + _handler: I2C1_MS_RX, + }, + Vector { + _handler: I2C1_MS_TX, + }, + Vector { + _handler: I2C1_SL_RX, + }, + Vector { + _handler: I2C1_SL_TX, + }, + Vector { + _handler: I2C2_MS_RX, + }, + Vector { + _handler: I2C2_MS_TX, + }, + Vector { + _handler: I2C2_SL_RX, + }, + Vector { + _handler: I2C2_SL_TX, + }, + Vector { _handler: FPU }, + Vector { _handler: TXEV }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - U0"] + U0 = 0, + #[doc = "1 - U1"] + U1 = 1, + #[doc = "2 - U2"] + U2 = 2, + #[doc = "3 - U3"] + U3 = 3, + #[doc = "4 - U4"] + U4 = 4, + #[doc = "5 - U5"] + U5 = 5, + #[doc = "6 - U6"] + U6 = 6, + #[doc = "7 - U7"] + U7 = 7, + #[doc = "8 - U8"] + U8 = 8, + #[doc = "9 - U9"] + U9 = 9, + #[doc = "10 - U10"] + U10 = 10, + #[doc = "11 - U11"] + U11 = 11, + #[doc = "12 - U12"] + U12 = 12, + #[doc = "13 - U13"] + U13 = 13, + #[doc = "14 - U14"] + U14 = 14, + #[doc = "15 - U15"] + U15 = 15, + #[doc = "16 - SPI0_TX"] + SPI0_TX = 16, + #[doc = "17 - SPI0_RX"] + SPI0_RX = 17, + #[doc = "18 - SPI1_TX"] + SPI1_TX = 18, + #[doc = "19 - SPI1_RX"] + SPI1_RX = 19, + #[doc = "20 - SPI2_TX"] + SPI2_TX = 20, + #[doc = "21 - SPI2_RX"] + SPI2_RX = 21, + #[doc = "22 - SPI3_TX"] + SPI3_TX = 22, + #[doc = "23 - SPI3_RX"] + SPI3_RX = 23, + #[doc = "24 - UART0_TX"] + UART0_TX = 24, + #[doc = "25 - UART0_RX"] + UART0_RX = 25, + #[doc = "26 - UART1_TX"] + UART1_TX = 26, + #[doc = "27 - UART1_RX"] + UART1_RX = 27, + #[doc = "28 - UART2_TX"] + UART2_TX = 28, + #[doc = "29 - UART2_RX"] + UART2_RX = 29, + #[doc = "30 - I2C0_MS"] + I2C0_MS = 30, + #[doc = "31 - I2C0_SL"] + I2C0_SL = 31, + #[doc = "32 - I2C1_MS"] + I2C1_MS = 32, + #[doc = "33 - I2C1_SL"] + I2C1_SL = 33, + #[doc = "34 - I2C2_MS"] + I2C2_MS = 34, + #[doc = "35 - I2C2_SL"] + I2C2_SL = 35, + #[doc = "36 - Ethernet"] + Ethernet = 36, + #[doc = "37 - U37"] + U37 = 37, + #[doc = "38 - SpW"] + SpW = 38, + #[doc = "39 - U39"] + U39 = 39, + #[doc = "40 - DAC0"] + DAC0 = 40, + #[doc = "41 - DAC1"] + DAC1 = 41, + #[doc = "42 - TRNG"] + TRNG = 42, + #[doc = "43 - DMA_ERROR"] + DMA_ERROR = 43, + #[doc = "44 - ADC"] + ADC = 44, + #[doc = "45 - LoCLK"] + LoCLK = 45, + #[doc = "46 - LVD"] + LVD = 46, + #[doc = "47 - WATCHDOG"] + WATCHDOG = 47, + #[doc = "48 - TIM0"] + TIM0 = 48, + #[doc = "49 - TIM1"] + TIM1 = 49, + #[doc = "50 - TIM2"] + TIM2 = 50, + #[doc = "51 - TIM3"] + TIM3 = 51, + #[doc = "52 - TIM4"] + TIM4 = 52, + #[doc = "53 - TIM5"] + TIM5 = 53, + #[doc = "54 - TIM6"] + TIM6 = 54, + #[doc = "55 - TIM7"] + TIM7 = 55, + #[doc = "56 - TIM8"] + TIM8 = 56, + #[doc = "57 - TIM9"] + TIM9 = 57, + #[doc = "58 - TIM10"] + TIM10 = 58, + #[doc = "59 - TIM11"] + TIM11 = 59, + #[doc = "60 - TIM12"] + TIM12 = 60, + #[doc = "61 - TIM13"] + TIM13 = 61, + #[doc = "62 - TIM14"] + TIM14 = 62, + #[doc = "63 - TIM15"] + TIM15 = 63, + #[doc = "64 - TIM16"] + TIM16 = 64, + #[doc = "65 - TIM17"] + TIM17 = 65, + #[doc = "66 - TIM18"] + TIM18 = 66, + #[doc = "67 - TIM19"] + TIM19 = 67, + #[doc = "68 - TIM20"] + TIM20 = 68, + #[doc = "69 - TIM21"] + TIM21 = 69, + #[doc = "70 - TIM22"] + TIM22 = 70, + #[doc = "71 - TIM23"] + TIM23 = 71, + #[doc = "72 - CAN0"] + CAN0 = 72, + #[doc = "73 - U73"] + U73 = 73, + #[doc = "74 - CAN1"] + CAN1 = 74, + #[doc = "75 - U75"] + U75 = 75, + #[doc = "76 - EDAC_MBE"] + EDAC_MBE = 76, + #[doc = "77 - EDAC_SBE"] + EDAC_SBE = 77, + #[doc = "78 - PORTA0"] + PORTA0 = 78, + #[doc = "79 - PORTA1"] + PORTA1 = 79, + #[doc = "80 - PORTA2"] + PORTA2 = 80, + #[doc = "81 - PORTA3"] + PORTA3 = 81, + #[doc = "82 - PORTA4"] + PORTA4 = 82, + #[doc = "83 - PORTA5"] + PORTA5 = 83, + #[doc = "84 - PORTA6"] + PORTA6 = 84, + #[doc = "85 - PORTA7"] + PORTA7 = 85, + #[doc = "86 - PORTA8"] + PORTA8 = 86, + #[doc = "87 - PORTA9"] + PORTA9 = 87, + #[doc = "88 - PORTA10"] + PORTA10 = 88, + #[doc = "89 - PORTA11"] + PORTA11 = 89, + #[doc = "90 - PORTA12"] + PORTA12 = 90, + #[doc = "91 - PORTA13"] + PORTA13 = 91, + #[doc = "92 - PORTA14"] + PORTA14 = 92, + #[doc = "93 - PORTA15"] + PORTA15 = 93, + #[doc = "94 - PORTB0"] + PORTB0 = 94, + #[doc = "95 - PORTB1"] + PORTB1 = 95, + #[doc = "96 - PORTB2"] + PORTB2 = 96, + #[doc = "97 - PORTB3"] + PORTB3 = 97, + #[doc = "98 - PORTB4"] + PORTB4 = 98, + #[doc = "99 - PORTB5"] + PORTB5 = 99, + #[doc = "100 - PORTB6"] + PORTB6 = 100, + #[doc = "101 - PORTB7"] + PORTB7 = 101, + #[doc = "102 - PORTB8"] + PORTB8 = 102, + #[doc = "103 - PORTB9"] + PORTB9 = 103, + #[doc = "104 - PORTB10"] + PORTB10 = 104, + #[doc = "105 - PORTB11"] + PORTB11 = 105, + #[doc = "106 - PORTB12"] + PORTB12 = 106, + #[doc = "107 - PORTB13"] + PORTB13 = 107, + #[doc = "108 - PORTB14"] + PORTB14 = 108, + #[doc = "109 - PORTB15"] + PORTB15 = 109, + #[doc = "110 - PORTC0"] + PORTC0 = 110, + #[doc = "111 - PORTC1"] + PORTC1 = 111, + #[doc = "112 - PORTC2"] + PORTC2 = 112, + #[doc = "113 - PORTC3"] + PORTC3 = 113, + #[doc = "114 - PORTC4"] + PORTC4 = 114, + #[doc = "115 - PORTC5"] + PORTC5 = 115, + #[doc = "116 - PORTC6"] + PORTC6 = 116, + #[doc = "117 - PORTC7"] + PORTC7 = 117, + #[doc = "118 - PORTC8"] + PORTC8 = 118, + #[doc = "119 - PORTC9"] + PORTC9 = 119, + #[doc = "120 - PORTC10"] + PORTC10 = 120, + #[doc = "121 - PORTC11"] + PORTC11 = 121, + #[doc = "122 - PORTC12"] + PORTC12 = 122, + #[doc = "123 - PORTC13"] + PORTC13 = 123, + #[doc = "124 - PORTC14"] + PORTC14 = 124, + #[doc = "125 - PORTC15"] + PORTC15 = 125, + #[doc = "126 - PORTD0"] + PORTD0 = 126, + #[doc = "127 - PORTD1"] + PORTD1 = 127, + #[doc = "128 - PORTD2"] + PORTD2 = 128, + #[doc = "129 - PORTD3"] + PORTD3 = 129, + #[doc = "130 - PORTD4"] + PORTD4 = 130, + #[doc = "131 - PORTD5"] + PORTD5 = 131, + #[doc = "132 - PORTD6"] + PORTD6 = 132, + #[doc = "133 - PORTD7"] + PORTD7 = 133, + #[doc = "134 - PORTD8"] + PORTD8 = 134, + #[doc = "135 - PORTD9"] + PORTD9 = 135, + #[doc = "136 - PORTD10"] + PORTD10 = 136, + #[doc = "137 - PORTD11"] + PORTD11 = 137, + #[doc = "138 - PORTD12"] + PORTD12 = 138, + #[doc = "139 - PORTD13"] + PORTD13 = 139, + #[doc = "140 - PORTD14"] + PORTD14 = 140, + #[doc = "141 - PORTD15"] + PORTD15 = 141, + #[doc = "142 - PORTE0"] + PORTE0 = 142, + #[doc = "143 - PORTE1"] + PORTE1 = 143, + #[doc = "144 - PORTE2"] + PORTE2 = 144, + #[doc = "145 - PORTE3"] + PORTE3 = 145, + #[doc = "146 - PORTE4"] + PORTE4 = 146, + #[doc = "147 - PORTE5"] + PORTE5 = 147, + #[doc = "148 - PORTE6"] + PORTE6 = 148, + #[doc = "149 - PORTE7"] + PORTE7 = 149, + #[doc = "150 - PORTE8"] + PORTE8 = 150, + #[doc = "151 - PORTE9"] + PORTE9 = 151, + #[doc = "152 - PORTE10"] + PORTE10 = 152, + #[doc = "153 - PORTE11"] + PORTE11 = 153, + #[doc = "154 - PORTE12"] + PORTE12 = 154, + #[doc = "155 - PORTE13"] + PORTE13 = 155, + #[doc = "156 - PORTE14"] + PORTE14 = 156, + #[doc = "157 - PORTE15"] + PORTE15 = 157, + #[doc = "158 - PORTF0"] + PORTF0 = 158, + #[doc = "159 - PORTF1"] + PORTF1 = 159, + #[doc = "160 - PORTF2"] + PORTF2 = 160, + #[doc = "161 - PORTF3"] + PORTF3 = 161, + #[doc = "162 - PORTF4"] + PORTF4 = 162, + #[doc = "163 - PORTF5"] + PORTF5 = 163, + #[doc = "164 - PORTF6"] + PORTF6 = 164, + #[doc = "165 - PORTF7"] + PORTF7 = 165, + #[doc = "166 - PORTF8"] + PORTF8 = 166, + #[doc = "167 - PORTF9"] + PORTF9 = 167, + #[doc = "168 - PORTF10"] + PORTF10 = 168, + #[doc = "169 - PORTF11"] + PORTF11 = 169, + #[doc = "170 - PORTF12"] + PORTF12 = 170, + #[doc = "171 - PORTF13"] + PORTF13 = 171, + #[doc = "172 - PORTF14"] + PORTF14 = 172, + #[doc = "173 - PORTF15"] + PORTF15 = 173, + #[doc = "174 - DMA_ACTIVE0"] + DMA_ACTIVE0 = 174, + #[doc = "175 - DMA_ACTIVE1"] + DMA_ACTIVE1 = 175, + #[doc = "176 - DMA_ACTIVE2"] + DMA_ACTIVE2 = 176, + #[doc = "177 - DMA_ACTIVE3"] + DMA_ACTIVE3 = 177, + #[doc = "178 - DMA_DONE0"] + DMA_DONE0 = 178, + #[doc = "179 - DMA_DONE1"] + DMA_DONE1 = 179, + #[doc = "180 - DMA_DONE2"] + DMA_DONE2 = 180, + #[doc = "181 - DMA_DONE3"] + DMA_DONE3 = 181, + #[doc = "182 - I2C0_MS_RX"] + I2C0_MS_RX = 182, + #[doc = "183 - I2C0_MS_TX"] + I2C0_MS_TX = 183, + #[doc = "184 - I2C0_SL_RX"] + I2C0_SL_RX = 184, + #[doc = "185 - I2C0_SL_TX"] + I2C0_SL_TX = 185, + #[doc = "186 - I2C1_MS_RX"] + I2C1_MS_RX = 186, + #[doc = "187 - I2C1_MS_TX"] + I2C1_MS_TX = 187, + #[doc = "188 - I2C1_SL_RX"] + I2C1_SL_RX = 188, + #[doc = "189 - I2C1_SL_TX"] + I2C1_SL_TX = 189, + #[doc = "190 - I2C2_MS_RX"] + I2C2_MS_RX = 190, + #[doc = "191 - I2C2_MS_TX"] + I2C2_MS_TX = 191, + #[doc = "192 - I2C2_SL_RX"] + I2C2_SL_RX = 192, + #[doc = "193 - I2C2_SL_TX"] + I2C2_SL_TX = 193, + #[doc = "194 - FPU"] + FPU = 194, + #[doc = "195 - TXEV"] + TXEV = 195, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Clock Generation Peripheral"] +pub struct Clkgen { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Clkgen {} +impl Clkgen { + #[doc = r"Pointer to the register block"] + pub const PTR: *const clkgen::RegisterBlock = 0x4000_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const clkgen::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Clkgen { + type Target = clkgen::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Clkgen { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Clkgen").finish() + } +} +#[doc = "Clock Generation Peripheral"] +pub mod clkgen; +#[doc = "System Configuration Peripheral"] +pub struct Sysconfig { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Sysconfig {} +impl Sysconfig { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sysconfig::RegisterBlock = 0x4001_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sysconfig::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Sysconfig { + type Target = sysconfig::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Sysconfig { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Sysconfig").finish() + } +} +#[doc = "System Configuration Peripheral"] +pub mod sysconfig; +#[doc = "DMA Controller Block"] +pub struct Dma { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Dma {} +impl Dma { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dma::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dma::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Dma { + type Target = dma::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Dma { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Dma").finish() + } +} +#[doc = "DMA Controller Block"] +pub mod dma; +#[doc = "IO Pin Configuration Peripheral"] +pub struct Ioconfig { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Ioconfig {} +impl Ioconfig { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ioconfig::RegisterBlock = 0x4001_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ioconfig::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Ioconfig { + type Target = ioconfig::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Ioconfig { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Ioconfig").finish() + } +} +#[doc = "IO Pin Configuration Peripheral"] +pub mod ioconfig; +#[doc = "Utility Peripheral"] +pub struct Utility { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Utility {} +impl Utility { + #[doc = r"Pointer to the register block"] + pub const PTR: *const utility::RegisterBlock = 0x4002_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const utility::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Utility { + type Target = utility::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Utility { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Utility").finish() + } +} +#[doc = "Utility Peripheral"] +pub mod utility; +#[doc = "GPIO Peripheral"] +pub struct Porta { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Porta {} +impl Porta { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Porta { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Porta { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Porta").finish() + } +} +#[doc = "GPIO Peripheral"] +pub mod porta; +#[doc = "GPIO Peripheral"] +pub struct Portb { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Portb {} +impl Portb { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Portb { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Portb { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portb").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portb; +#[doc = "GPIO Peripheral"] +pub struct Portc { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Portc {} +impl Portc { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Portc { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Portc { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portc").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portc; +#[doc = "GPIO Peripheral"] +pub struct Portd { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Portd {} +impl Portd { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Portd { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Portd { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portd").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portd; +#[doc = "GPIO Peripheral"] +pub struct Porte { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Porte {} +impl Porte { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Porte { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Porte { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Porte").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as porte; +#[doc = "GPIO Peripheral"] +pub struct Portf { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Portf {} +impl Portf { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Portf { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Portf { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portf").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portf; +#[doc = "GPIO Peripheral"] +pub struct Portg { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Portg {} +impl Portg { + #[doc = r"Pointer to the register block"] + pub const PTR: *const porta::RegisterBlock = 0x4001_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const porta::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Portg { + type Target = porta::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Portg { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Portg").finish() + } +} +#[doc = "GPIO Peripheral"] +pub use self::porta as portg; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim0 {} +impl Tim0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim0 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim0").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub mod tim0; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim1 {} +impl Tim1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_8400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim1 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim1").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim1; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim2 {} +impl Tim2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_8800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim2 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim2").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim2; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim3 {} +impl Tim3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_8c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim3 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim3").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim3; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim4 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim4 {} +impl Tim4 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim4 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim4 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim4").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim4; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim5 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim5 {} +impl Tim5 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_9400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim5 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim5 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim5").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim5; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim6 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim6 {} +impl Tim6 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_9800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim6 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim6 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim6").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim6; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim7 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim7 {} +impl Tim7 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_9c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim7 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim7 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim7").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim7; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim8 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim8 {} +impl Tim8 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim8 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim8 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim8").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim8; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim9 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim9 {} +impl Tim9 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_a400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim9 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim9 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim9").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim9; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim10 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim10 {} +impl Tim10 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_a800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim10 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim10 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim10").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim10; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim11 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim11 {} +impl Tim11 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_ac00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim11 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim11 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim11").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim11; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim12 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim12 {} +impl Tim12 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_b000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim12 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim12 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim12").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim12; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim13 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim13 {} +impl Tim13 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_b400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim13 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim13 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim13").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim13; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim14 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim14 {} +impl Tim14 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_b800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim14 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim14 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim14").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim14; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim15 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim15 {} +impl Tim15 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4001_bc00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim15 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim15 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim15").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim15; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim16 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim16 {} +impl Tim16 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim16 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim16 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim16").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim16; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim17 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim17 {} +impl Tim17 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_8400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim17 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim17 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim17").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim17; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim18 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim18 {} +impl Tim18 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_8800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim18 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim18 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim18").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim18; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim19 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim19 {} +impl Tim19 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_8c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim19 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim19 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim19").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim19; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim20 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim20 {} +impl Tim20 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_9000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim20 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim20 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim20").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim20; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim21 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim21 {} +impl Tim21 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_9400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim21 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim21 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim21").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim21; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim22 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim22 {} +impl Tim22 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_9800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim22 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim22 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim22").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim22; +#[doc = "Timer/Counter Peripheral"] +pub struct Tim23 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Tim23 {} +impl Tim23 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tim0::RegisterBlock = 0x4002_9c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tim0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Tim23 { + type Target = tim0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Tim23 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Tim23").finish() + } +} +#[doc = "Timer/Counter Peripheral"] +pub use self::tim0 as tim23; +#[doc = "UART Peripheral"] +pub struct Uart0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Uart0 {} +impl Uart0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4002_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Uart0 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Uart0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Uart0").finish() + } +} +#[doc = "UART Peripheral"] +pub mod uart0; +#[doc = "UART Peripheral"] +pub struct Uart1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Uart1 {} +impl Uart1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4002_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Uart1 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Uart1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Uart1").finish() + } +} +#[doc = "UART Peripheral"] +pub use self::uart0 as uart1; +#[doc = "UART Peripheral"] +pub struct Uart2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Uart2 {} +impl Uart2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const uart0::RegisterBlock = 0x4001_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const uart0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Uart2 { + type Target = uart0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Uart2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Uart2").finish() + } +} +#[doc = "UART Peripheral"] +pub use self::uart0 as uart2; +#[doc = "SPI Peripheral"] +pub struct Spi0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Spi0 {} +impl Spi0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4001_5000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Spi0 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Spi0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spi0").finish() + } +} +#[doc = "SPI Peripheral"] +pub mod spi0; +#[doc = "SPI Peripheral"] +pub struct Spi1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Spi1 {} +impl Spi1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4001_5400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Spi1 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Spi1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spi1").finish() + } +} +#[doc = "SPI Peripheral"] +pub use self::spi0 as spi1; +#[doc = "SPI Peripheral"] +pub struct Spi2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Spi2 {} +impl Spi2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4001_5800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Spi2 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Spi2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spi2").finish() + } +} +#[doc = "SPI Peripheral"] +pub use self::spi0 as spi2; +#[doc = "SPI Peripheral"] +pub struct Spi3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Spi3 {} +impl Spi3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spi0::RegisterBlock = 0x4001_5c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spi0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Spi3 { + type Target = spi0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Spi3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spi3").finish() + } +} +#[doc = "SPI Peripheral"] +pub use self::spi0 as spi3; +#[doc = "I2C Peripheral"] +pub struct I2c0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2c0 {} +impl I2c0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4001_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2c0 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2c0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2c0").finish() + } +} +#[doc = "I2C Peripheral"] +pub mod i2c0; +#[doc = "I2C Peripheral"] +pub struct I2c1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2c1 {} +impl I2c1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4001_6400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2c1 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2c1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2c1").finish() + } +} +#[doc = "I2C Peripheral"] +pub use self::i2c0 as i2c1; +#[doc = "I2C Peripheral"] +pub struct I2c2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for I2c2 {} +impl I2c2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const i2c0::RegisterBlock = 0x4001_6800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const i2c0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for I2c2 { + type Target = i2c0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for I2c2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("I2c2").finish() + } +} +#[doc = "I2C Peripheral"] +pub use self::i2c0 as i2c2; +#[doc = "CAN Peripheral"] +pub struct Can0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Can0 {} +impl Can0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4001_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Can0 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Can0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Can0").finish() + } +} +#[doc = "CAN Peripheral"] +pub mod can0; +#[doc = "CAN Peripheral"] +pub struct Can1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Can1 {} +impl Can1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const can0::RegisterBlock = 0x4001_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const can0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Can1 { + type Target = can0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Can1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Can1").finish() + } +} +#[doc = "CAN Peripheral"] +pub use self::can0 as can1; +#[doc = "Analog to Digital Converter Peripheral"] +pub struct Adc { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Adc {} +impl Adc { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x4002_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Adc { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Adc { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Adc").finish() + } +} +#[doc = "Analog to Digital Converter Peripheral"] +pub mod adc; +#[doc = "Digital to Analog Converter Peripheral"] +pub struct Dac0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Dac0 {} +impl Dac0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac0::RegisterBlock = 0x4002_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Dac0 { + type Target = dac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Dac0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Dac0").finish() + } +} +#[doc = "Digital to Analog Converter Peripheral"] +pub mod dac0; +#[doc = "Digital to Analog Converter Peripheral"] +pub struct Dac1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Dac1 {} +impl Dac1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dac0::RegisterBlock = 0x4002_3800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dac0::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Dac1 { + type Target = dac0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Dac1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Dac1").finish() + } +} +#[doc = "Digital to Analog Converter Peripheral"] +pub use self::dac0 as dac1; +#[doc = "SpaceWire Peripheral"] +pub struct Spw { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Spw {} +impl Spw { + #[doc = r"Pointer to the register block"] + pub const PTR: *const spw::RegisterBlock = 0x4000_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const spw::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Spw { + type Target = spw::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Spw { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Spw").finish() + } +} +#[doc = "SpaceWire Peripheral"] +pub mod spw; +#[doc = "Interrupt Router Peripheral"] +pub struct IrqRouter { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for IrqRouter {} +impl IrqRouter { + #[doc = r"Pointer to the register block"] + pub const PTR: *const irq_router::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const irq_router::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for IrqRouter { + type Target = irq_router::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for IrqRouter { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("IrqRouter").finish() + } +} +#[doc = "Interrupt Router Peripheral"] +pub mod irq_router; +#[doc = "Watchdog Block Peripheral"] +pub struct WatchDog { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WatchDog {} +impl WatchDog { + #[doc = r"Pointer to the register block"] + pub const PTR: *const watch_dog::RegisterBlock = 0x4002_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const watch_dog::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for WatchDog { + type Target = watch_dog::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WatchDog { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WatchDog").finish() + } +} +#[doc = "Watchdog Block Peripheral"] +pub mod watch_dog; +#[doc = "True Random Number Generator"] +pub struct Trng { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Trng {} +impl Trng { + #[doc = r"Pointer to the register block"] + pub const PTR: *const trng::RegisterBlock = 0x4002_7000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const trng::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Trng { + type Target = trng::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Trng { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Trng").finish() + } +} +#[doc = "True Random Number Generator"] +pub mod trng; +#[doc = "Ethernet Block"] +pub struct Eth { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for Eth {} +impl Eth { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eth::RegisterBlock = 0x4000_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eth::RegisterBlock { + Self::PTR + } + #[doc = r" Steal an instance of this peripheral"] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"] + #[doc = r" that may race with any existing instances, for example by only"] + #[doc = r" accessing read-only or write-only registers, or by consuming the"] + #[doc = r" original peripheral and using critical sections to coordinate"] + #[doc = r" access between multiple new instances."] + #[doc = r""] + #[doc = r" Additionally, other software such as HALs may rely on only one"] + #[doc = r" peripheral instance existing to ensure memory safety; ensure"] + #[doc = r" no stolen instances are passed to such software."] + pub unsafe fn steal() -> Self { + Self { + _marker: PhantomData, + } + } +} +impl Deref for Eth { + type Target = eth::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for Eth { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("Eth").finish() + } +} +#[doc = "Ethernet Block"] +pub mod eth; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "CLKGEN"] + pub clkgen: Clkgen, + #[doc = "SYSCONFIG"] + pub sysconfig: Sysconfig, + #[doc = "DMA"] + pub dma: Dma, + #[doc = "IOCONFIG"] + pub ioconfig: Ioconfig, + #[doc = "UTILITY"] + pub utility: Utility, + #[doc = "PORTA"] + pub porta: Porta, + #[doc = "PORTB"] + pub portb: Portb, + #[doc = "PORTC"] + pub portc: Portc, + #[doc = "PORTD"] + pub portd: Portd, + #[doc = "PORTE"] + pub porte: Porte, + #[doc = "PORTF"] + pub portf: Portf, + #[doc = "PORTG"] + pub portg: Portg, + #[doc = "TIM0"] + pub tim0: Tim0, + #[doc = "TIM1"] + pub tim1: Tim1, + #[doc = "TIM2"] + pub tim2: Tim2, + #[doc = "TIM3"] + pub tim3: Tim3, + #[doc = "TIM4"] + pub tim4: Tim4, + #[doc = "TIM5"] + pub tim5: Tim5, + #[doc = "TIM6"] + pub tim6: Tim6, + #[doc = "TIM7"] + pub tim7: Tim7, + #[doc = "TIM8"] + pub tim8: Tim8, + #[doc = "TIM9"] + pub tim9: Tim9, + #[doc = "TIM10"] + pub tim10: Tim10, + #[doc = "TIM11"] + pub tim11: Tim11, + #[doc = "TIM12"] + pub tim12: Tim12, + #[doc = "TIM13"] + pub tim13: Tim13, + #[doc = "TIM14"] + pub tim14: Tim14, + #[doc = "TIM15"] + pub tim15: Tim15, + #[doc = "TIM16"] + pub tim16: Tim16, + #[doc = "TIM17"] + pub tim17: Tim17, + #[doc = "TIM18"] + pub tim18: Tim18, + #[doc = "TIM19"] + pub tim19: Tim19, + #[doc = "TIM20"] + pub tim20: Tim20, + #[doc = "TIM21"] + pub tim21: Tim21, + #[doc = "TIM22"] + pub tim22: Tim22, + #[doc = "TIM23"] + pub tim23: Tim23, + #[doc = "UART0"] + pub uart0: Uart0, + #[doc = "UART1"] + pub uart1: Uart1, + #[doc = "UART2"] + pub uart2: Uart2, + #[doc = "SPI0"] + pub spi0: Spi0, + #[doc = "SPI1"] + pub spi1: Spi1, + #[doc = "SPI2"] + pub spi2: Spi2, + #[doc = "SPI3"] + pub spi3: Spi3, + #[doc = "I2C0"] + pub i2c0: I2c0, + #[doc = "I2C1"] + pub i2c1: I2c1, + #[doc = "I2C2"] + pub i2c2: I2c2, + #[doc = "CAN0"] + pub can0: Can0, + #[doc = "CAN1"] + pub can1: Can1, + #[doc = "ADC"] + pub adc: Adc, + #[doc = "DAC0"] + pub dac0: Dac0, + #[doc = "DAC1"] + pub dac1: Dac1, + #[doc = "SPW"] + pub spw: Spw, + #[doc = "IRQ_ROUTER"] + pub irq_router: IrqRouter, + #[doc = "WATCH_DOG"] + pub watch_dog: WatchDog, + #[doc = "TRNG"] + pub trng: Trng, + #[doc = "ETH"] + pub eth: Eth, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + clkgen: Clkgen { + _marker: PhantomData, + }, + sysconfig: Sysconfig { + _marker: PhantomData, + }, + dma: Dma { + _marker: PhantomData, + }, + ioconfig: Ioconfig { + _marker: PhantomData, + }, + utility: Utility { + _marker: PhantomData, + }, + porta: Porta { + _marker: PhantomData, + }, + portb: Portb { + _marker: PhantomData, + }, + portc: Portc { + _marker: PhantomData, + }, + portd: Portd { + _marker: PhantomData, + }, + porte: Porte { + _marker: PhantomData, + }, + portf: Portf { + _marker: PhantomData, + }, + portg: Portg { + _marker: PhantomData, + }, + tim0: Tim0 { + _marker: PhantomData, + }, + tim1: Tim1 { + _marker: PhantomData, + }, + tim2: Tim2 { + _marker: PhantomData, + }, + tim3: Tim3 { + _marker: PhantomData, + }, + tim4: Tim4 { + _marker: PhantomData, + }, + tim5: Tim5 { + _marker: PhantomData, + }, + tim6: Tim6 { + _marker: PhantomData, + }, + tim7: Tim7 { + _marker: PhantomData, + }, + tim8: Tim8 { + _marker: PhantomData, + }, + tim9: Tim9 { + _marker: PhantomData, + }, + tim10: Tim10 { + _marker: PhantomData, + }, + tim11: Tim11 { + _marker: PhantomData, + }, + tim12: Tim12 { + _marker: PhantomData, + }, + tim13: Tim13 { + _marker: PhantomData, + }, + tim14: Tim14 { + _marker: PhantomData, + }, + tim15: Tim15 { + _marker: PhantomData, + }, + tim16: Tim16 { + _marker: PhantomData, + }, + tim17: Tim17 { + _marker: PhantomData, + }, + tim18: Tim18 { + _marker: PhantomData, + }, + tim19: Tim19 { + _marker: PhantomData, + }, + tim20: Tim20 { + _marker: PhantomData, + }, + tim21: Tim21 { + _marker: PhantomData, + }, + tim22: Tim22 { + _marker: PhantomData, + }, + tim23: Tim23 { + _marker: PhantomData, + }, + uart0: Uart0 { + _marker: PhantomData, + }, + uart1: Uart1 { + _marker: PhantomData, + }, + uart2: Uart2 { + _marker: PhantomData, + }, + spi0: Spi0 { + _marker: PhantomData, + }, + spi1: Spi1 { + _marker: PhantomData, + }, + spi2: Spi2 { + _marker: PhantomData, + }, + spi3: Spi3 { + _marker: PhantomData, + }, + i2c0: I2c0 { + _marker: PhantomData, + }, + i2c1: I2c1 { + _marker: PhantomData, + }, + i2c2: I2c2 { + _marker: PhantomData, + }, + can0: Can0 { + _marker: PhantomData, + }, + can1: Can1 { + _marker: PhantomData, + }, + adc: Adc { + _marker: PhantomData, + }, + dac0: Dac0 { + _marker: PhantomData, + }, + dac1: Dac1 { + _marker: PhantomData, + }, + spw: Spw { + _marker: PhantomData, + }, + irq_router: IrqRouter { + _marker: PhantomData, + }, + watch_dog: WatchDog { + _marker: PhantomData, + }, + trng: Trng { + _marker: PhantomData, + }, + eth: Eth { + _marker: PhantomData, + }, + } + } +} diff --git a/va416xx/src/porta.rs b/va416xx/src/porta.rs new file mode 100644 index 0000000..2a15691 --- /dev/null +++ b/va416xx/src/porta.rs @@ -0,0 +1,442 @@ +// Added manually. +#![allow(clippy::identity_op)] + +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved_0_datain: [u8; 0x04], + _reserved_1_datainraw: [u8; 0x04], + _reserved_2_dataout: [u8; 0x04], + _reserved_3_dataoutraw: [u8; 0x04], + _reserved_4_setout: [u8; 0x04], + _reserved_5_clrout: [u8; 0x04], + _reserved_6_togout: [u8; 0x04], + _reserved_7_datamask: [u8; 0x04], + _reserved_8_dir: [u8; 0x04], + _reserved_9_pulse: [u8; 0x04], + _reserved_10_pulsebase: [u8; 0x04], + _reserved_11_delay: [u8; 0x04], + _reserved_12_delay: [u8; 0x04], + irq_sen: IrqSen, + irq_edge: IrqEdge, + irq_evt: IrqEvt, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + edge_status: EdgeStatus, + _reserved20: [u8; 0x03ac], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Data In Register by Byte"] + #[inline(always)] + pub const fn datainbyte(&self, n: usize) -> &Datainbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(0).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x00 - Data In Register by Byte"] + #[inline(always)] + pub fn datainbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(0).add(1 * n).cast() }) + } + #[doc = "0x00 - Data In Register"] + #[inline(always)] + pub const fn datain(&self) -> &Datain { + unsafe { &*(self as *const Self).cast::().add(0).cast() } + } + #[doc = "0x04 - Data In Raw Register by Byte"] + #[inline(always)] + pub const fn datainrawbyte0(&self, n: usize) -> &Datainrawbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(4).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x04 - Data In Raw Register by Byte"] + #[inline(always)] + pub fn datainrawbyte0_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(4).add(1 * n).cast() }) + } + #[doc = "0x04 - Data In Raw Register"] + #[inline(always)] + pub const fn datainraw(&self) -> &Datainraw { + unsafe { &*(self as *const Self).cast::().add(4).cast() } + } + #[doc = "0x08 - Data Out Register by Byte"] + #[inline(always)] + pub const fn dataoutbyte(&self, n: usize) -> &Dataoutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(8).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x08 - Data Out Register by Byte"] + #[inline(always)] + pub fn dataoutbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(8).add(1 * n).cast() }) + } + #[doc = "0x08 - Data Out Register"] + #[inline(always)] + pub const fn dataout(&self) -> &Dataout { + unsafe { &*(self as *const Self).cast::().add(8).cast() } + } + #[doc = "0x0c - Data Out Register by Byte"] + #[inline(always)] + pub const fn dataoutrawbyte0(&self, n: usize) -> &Dataoutrawbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(12).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x0c - Data Out Register by Byte"] + #[inline(always)] + pub fn dataoutrawbyte0_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(12).add(1 * n).cast() }) + } + #[doc = "0x0c - Data Out Register"] + #[inline(always)] + pub const fn dataoutraw(&self) -> &Dataoutraw { + unsafe { &*(self as *const Self).cast::().add(12).cast() } + } + #[doc = "0x10 - Set Out Register by Byte"] + #[inline(always)] + pub const fn setoutbyte0(&self, n: usize) -> &Setoutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(16).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x10 - Set Out Register by Byte"] + #[inline(always)] + pub fn setoutbyte0_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(16).add(1 * n).cast() }) + } + #[doc = "0x10 - Set Out Register"] + #[inline(always)] + pub const fn setout(&self) -> &Setout { + unsafe { &*(self as *const Self).cast::().add(16).cast() } + } + #[doc = "0x14 - Clear Out Register by Byte"] + #[inline(always)] + pub const fn clroutbyte0(&self, n: usize) -> &Clroutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(20).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x14 - Clear Out Register by Byte"] + #[inline(always)] + pub fn clroutbyte0_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(20).add(1 * n).cast() }) + } + #[doc = "0x14 - Clear Out Register"] + #[inline(always)] + pub const fn clrout(&self) -> &Clrout { + unsafe { &*(self as *const Self).cast::().add(20).cast() } + } + #[doc = "0x18 - Toggle Out Register by Byte"] + #[inline(always)] + pub const fn togoutbyte0(&self, n: usize) -> &Togoutbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(24).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x18 - Toggle Out Register by Byte"] + #[inline(always)] + pub fn togoutbyte0_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(24).add(1 * n).cast() }) + } + #[doc = "0x18 - Toggle Out Register"] + #[inline(always)] + pub const fn togout(&self) -> &Togout { + unsafe { &*(self as *const Self).cast::().add(24).cast() } + } + #[doc = "0x1c - Data Out Register by Byte"] + #[inline(always)] + pub const fn datamaskbyte(&self, n: usize) -> &Datamaskbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(28).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x1c - Data Out Register by Byte"] + #[inline(always)] + pub fn datamaskbyte_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(28).add(1 * n).cast() }) + } + #[doc = "0x1c - Data mask Register"] + #[inline(always)] + pub const fn datamask(&self) -> &Datamask { + unsafe { &*(self as *const Self).cast::().add(28).cast() } + } + #[doc = "0x20 - Direction Register by Byte"] + #[inline(always)] + pub const fn dirbyte0(&self, n: usize) -> &Dirbyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(32).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x20 - Direction Register by Byte"] + #[inline(always)] + pub fn dirbyte0_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(32).add(1 * n).cast() }) + } + #[doc = "0x20 - Direction Register (1:Output, 0:Input)"] + #[inline(always)] + pub const fn dir(&self) -> &Dir { + unsafe { &*(self as *const Self).cast::().add(32).cast() } + } + #[doc = "0x24 - Pulse Mode Register by Byte"] + #[inline(always)] + pub const fn pulsebyte0(&self, n: usize) -> &Pulsebyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(36).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x24 - Pulse Mode Register by Byte"] + #[inline(always)] + pub fn pulsebyte0_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(36).add(1 * n).cast() }) + } + #[doc = "0x24 - Pulse Mode Register"] + #[inline(always)] + pub const fn pulse(&self) -> &Pulse { + unsafe { &*(self as *const Self).cast::().add(36).cast() } + } + #[doc = "0x28 - Pulse Base Mode Register by Byte"] + #[inline(always)] + pub const fn pulsebasebyte0(&self, n: usize) -> &Pulsebasebyte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(40).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x28 - Pulse Base Mode Register by Byte"] + #[inline(always)] + pub fn pulsebasebyte0_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(40).add(1 * n).cast() }) + } + #[doc = "0x28 - Pulse Base Value Register"] + #[inline(always)] + pub const fn pulsebase(&self) -> &Pulsebase { + unsafe { &*(self as *const Self).cast::().add(40).cast() } + } + #[doc = "0x2c - Delay1 Register by Byte"] + #[inline(always)] + pub const fn delay1byte0(&self, n: usize) -> &Delay1byte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(44).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x2c - Delay1 Register by Byte"] + #[inline(always)] + pub fn delay1byte0_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(44).add(1 * n).cast() }) + } + #[doc = "0x2c - Delay1 Register"] + #[inline(always)] + pub const fn delay1(&self) -> &Delay1 { + unsafe { &*(self as *const Self).cast::().add(44).cast() } + } + #[doc = "0x30 - Delay2 Register by Byte"] + #[inline(always)] + pub const fn delay2byte0(&self, n: usize) -> &Delay2byte { + #[allow(clippy::no_effect)] + [(); 4][n]; + unsafe { &*(self as *const Self).cast::().add(48).add(1 * n).cast() } + } + #[doc = "Iterator for array of:"] + #[doc = "0x30 - Delay2 Register by Byte"] + #[inline(always)] + pub fn delay2byte0_iter(&self) -> impl Iterator { + (0..4) + .map(move |n| unsafe { &*(self as *const Self).cast::().add(48).add(1 * n).cast() }) + } + #[doc = "0x30 - Delay2 Register"] + #[inline(always)] + pub const fn delay2(&self) -> &Delay2 { + unsafe { &*(self as *const Self).cast::().add(48).cast() } + } + #[doc = "0x34 - Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] + #[inline(always)] + pub const fn irq_sen(&self) -> &IrqSen { + &self.irq_sen + } + #[doc = "0x38 - Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"] + #[inline(always)] + pub const fn irq_edge(&self) -> &IrqEdge { + &self.irq_edge + } + #[doc = "0x3c - Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"] + #[inline(always)] + pub const fn irq_evt(&self) -> &IrqEvt { + &self.irq_evt + } + #[doc = "0x40 - Interrupt Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x44 - Raw Interrupt Status"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x48 - Masked Interrupt Status"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x4c - Edge Status Register"] + #[inline(always)] + pub const fn edge_status(&self) -> &EdgeStatus { + &self.edge_status + } + #[doc = "0x3fc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`] +module"] +#[doc(alias = "DATAIN")] +pub type Datain = crate::Reg; +#[doc = "Data In Register"] +pub mod datain; +#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`] +module"] +#[doc(alias = "DATAINBYTE")] +pub type Datainbyte = crate::Reg; +#[doc = "Data In Register by Byte"] +pub mod datainbyte; +pub use datain as datainraw; +pub use datainbyte as datainrawbyte; +pub use Datain as Datainraw; +pub use Datainbyte as Datainrawbyte; +#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`] +module"] +#[doc(alias = "DATAOUT")] +pub type Dataout = crate::Reg; +#[doc = "Data Out Register"] +pub mod dataout; +#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`] +module"] +#[doc(alias = "DATAOUTBYTE")] +pub type Dataoutbyte = crate::Reg; +#[doc = "Data Out Register by Byte"] +pub mod dataoutbyte; +pub use dataout as dataoutraw; +pub use dataout as setout; +pub use dataout as clrout; +pub use dataout as togout; +pub use dataoutbyte as dataoutrawbyte; +pub use dataoutbyte as setoutbyte; +pub use dataoutbyte as clroutbyte; +pub use dataoutbyte as togoutbyte; +pub use Dataout as Dataoutraw; +pub use Dataout as Setout; +pub use Dataout as Clrout; +pub use Dataout as Togout; +pub use Dataoutbyte as Dataoutrawbyte; +pub use Dataoutbyte as Setoutbyte; +pub use Dataoutbyte as Clroutbyte; +pub use Dataoutbyte as Togoutbyte; +#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`] +module"] +#[doc(alias = "DATAMASK")] +pub type Datamask = crate::Reg; +#[doc = "Data mask Register"] +pub mod datamask; +#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`] +module"] +#[doc(alias = "DATAMASKBYTE")] +pub type Datamaskbyte = crate::Reg; +#[doc = "Data Out Register by Byte"] +pub mod datamaskbyte; +pub use datamask as dir; +pub use datamask as pulse; +pub use datamask as pulsebase; +pub use datamask as delay1; +pub use datamask as delay2; +pub use datamaskbyte as dirbyte; +pub use datamaskbyte as pulsebyte; +pub use datamaskbyte as pulsebasebyte; +pub use datamaskbyte as delay1byte; +pub use datamaskbyte as delay2byte; +pub use Datamask as Dir; +pub use Datamask as Pulse; +pub use Datamask as Pulsebase; +pub use Datamask as Delay1; +pub use Datamask as Delay2; +pub use Datamaskbyte as Dirbyte; +pub use Datamaskbyte as Pulsebyte; +pub use Datamaskbyte as Pulsebasebyte; +pub use Datamaskbyte as Delay1byte; +pub use Datamaskbyte as Delay2byte; +#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`] +module"] +#[doc(alias = "IRQ_SEN")] +pub type IrqSen = crate::Reg; +#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"] +pub mod irq_sen; +#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`] +module"] +#[doc(alias = "IRQ_EDGE")] +pub type IrqEdge = crate::Reg; +#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"] +pub mod irq_edge; +#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`] +module"] +#[doc(alias = "IRQ_EVT")] +pub type IrqEvt = crate::Reg; +#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"] +pub mod irq_evt; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] +module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] +module"] +#[doc(alias = "IRQ_RAW")] +pub type IrqRaw = crate::Reg; +#[doc = "Raw Interrupt Status"] +pub mod irq_raw; +#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] +module"] +#[doc(alias = "IRQ_END")] +pub type IrqEnd = crate::Reg; +#[doc = "Masked Interrupt Status"] +pub mod irq_end; +#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`] +module"] +#[doc(alias = "EDGE_STATUS")] +pub type EdgeStatus = crate::Reg; +#[doc = "Edge Status Register"] +pub mod edge_status; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/porta/datain.rs b/va416xx/src/porta/datain.rs new file mode 100644 index 0000000..5f6a720 --- /dev/null +++ b/va416xx/src/porta/datain.rs @@ -0,0 +1,18 @@ +#[doc = "Register `DATAIN` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Data In Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datain::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatainSpec; +impl crate::RegisterSpec for DatainSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`datain::R`](R) reader structure"] +impl crate::Readable for DatainSpec {} +#[doc = "`reset()` method sets DATAIN to value 0"] +impl crate::Resettable for DatainSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/porta/datainbyte.rs b/va416xx/src/porta/datainbyte.rs new file mode 100644 index 0000000..06d7f67 --- /dev/null +++ b/va416xx/src/porta/datainbyte.rs @@ -0,0 +1,19 @@ +#[doc = "Register `DATAINBYTE[%s]` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Data In Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datainbyte::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatainbyteSpec; +impl crate::RegisterSpec for DatainbyteSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`datainbyte::R`](R) reader structure"] +impl crate::Readable for DatainbyteSpec {} +#[doc = "`reset()` method sets DATAINBYTE[%s] +to value 0"] +impl crate::Resettable for DatainbyteSpec { + const RESET_VALUE: u8 = 0; +} diff --git a/va416xx/src/porta/datamask.rs b/va416xx/src/porta/datamask.rs new file mode 100644 index 0000000..6df9aac --- /dev/null +++ b/va416xx/src/porta/datamask.rs @@ -0,0 +1,27 @@ +#[doc = "Register `DATAMASK` reader"] +pub type R = crate::R; +#[doc = "Register `DATAMASK` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatamaskSpec; +impl crate::RegisterSpec for DatamaskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`datamask::R`](R) reader structure"] +impl crate::Readable for DatamaskSpec {} +#[doc = "`write(|w| ..)` method takes [`datamask::W`](W) writer structure"] +impl crate::Writable for DatamaskSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATAMASK to value 0"] +impl crate::Resettable for DatamaskSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/porta/datamaskbyte.rs b/va416xx/src/porta/datamaskbyte.rs new file mode 100644 index 0000000..29ecd88 --- /dev/null +++ b/va416xx/src/porta/datamaskbyte.rs @@ -0,0 +1,28 @@ +#[doc = "Register `DATAMASKBYTE[%s]` reader"] +pub type R = crate::R; +#[doc = "Register `DATAMASKBYTE[%s]` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Out Register by Byte\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`datamaskbyte::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`datamaskbyte::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DatamaskbyteSpec; +impl crate::RegisterSpec for DatamaskbyteSpec { + type Ux = u8; +} +#[doc = "`read()` method returns [`datamaskbyte::R`](R) reader structure"] +impl crate::Readable for DatamaskbyteSpec {} +#[doc = "`write(|w| ..)` method takes [`datamaskbyte::W`](W) writer structure"] +impl crate::Writable for DatamaskbyteSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0; +} +#[doc = "`reset()` method sets DATAMASKBYTE[%s] +to value 0"] +impl crate::Resettable for DatamaskbyteSpec { + const RESET_VALUE: u8 = 0; +} diff --git a/va416xx/src/porta/dataout.rs b/va416xx/src/porta/dataout.rs new file mode 100644 index 0000000..6250016 --- /dev/null +++ b/va416xx/src/porta/dataout.rs @@ -0,0 +1,23 @@ +#[doc = "Register `DATAOUT` writer"] +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W {} +#[doc = "Data Out Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataout::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataoutSpec; +impl crate::RegisterSpec for DataoutSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`dataout::W`](W) writer structure"] +impl crate::Writable for DataoutSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATAOUT to value 0"] +impl crate::Resettable for DataoutSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/porta/dataoutbyte.rs b/va416xx/src/porta/dataoutbyte.rs new file mode 100644 index 0000000..a712f13 --- /dev/null +++ b/va416xx/src/porta/dataoutbyte.rs @@ -0,0 +1,24 @@ +#[doc = "Register `DATAOUTBYTE[%s]` writer"] +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W {} +#[doc = "Data Out Register by Byte\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dataoutbyte::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataoutbyteSpec; +impl crate::RegisterSpec for DataoutbyteSpec { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [`dataoutbyte::W`](W) writer structure"] +impl crate::Writable for DataoutbyteSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0; +} +#[doc = "`reset()` method sets DATAOUTBYTE[%s] +to value 0"] +impl crate::Resettable for DataoutbyteSpec { + const RESET_VALUE: u8 = 0; +} diff --git a/va416xx/src/porta/edge_status.rs b/va416xx/src/porta/edge_status.rs new file mode 100644 index 0000000..0a90d70 --- /dev/null +++ b/va416xx/src/porta/edge_status.rs @@ -0,0 +1,27 @@ +#[doc = "Register `EDGE_STATUS` reader"] +pub type R = crate::R; +#[doc = "Register `EDGE_STATUS` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Edge Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`edge_status::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`edge_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EdgeStatusSpec; +impl crate::RegisterSpec for EdgeStatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`edge_status::R`](R) reader structure"] +impl crate::Readable for EdgeStatusSpec {} +#[doc = "`write(|w| ..)` method takes [`edge_status::W`](W) writer structure"] +impl crate::Writable for EdgeStatusSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EDGE_STATUS to value 0"] +impl crate::Resettable for EdgeStatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/porta/irq_edge.rs b/va416xx/src/porta/irq_edge.rs new file mode 100644 index 0000000..fddfc1c --- /dev/null +++ b/va416xx/src/porta/irq_edge.rs @@ -0,0 +1,27 @@ +#[doc = "Register `IRQ_EDGE` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_EDGE` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_edge::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_edge::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEdgeSpec; +impl crate::RegisterSpec for IrqEdgeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_edge::R`](R) reader structure"] +impl crate::Readable for IrqEdgeSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_edge::W`](W) writer structure"] +impl crate::Writable for IrqEdgeSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_EDGE to value 0"] +impl crate::Resettable for IrqEdgeSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/porta/irq_enb.rs b/va416xx/src/porta/irq_enb.rs new file mode 100644 index 0000000..2696b81 --- /dev/null +++ b/va416xx/src/porta/irq_enb.rs @@ -0,0 +1,27 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/porta/irq_end.rs b/va416xx/src/porta/irq_end.rs new file mode 100644 index 0000000..cf88a8a --- /dev/null +++ b/va416xx/src/porta/irq_end.rs @@ -0,0 +1,18 @@ +#[doc = "Register `IRQ_END` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Masked Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEndSpec; +impl crate::RegisterSpec for IrqEndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"] +impl crate::Readable for IrqEndSpec {} +#[doc = "`reset()` method sets IRQ_END to value 0"] +impl crate::Resettable for IrqEndSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/porta/irq_evt.rs b/va416xx/src/porta/irq_evt.rs new file mode 100644 index 0000000..1e98fa4 --- /dev/null +++ b/va416xx/src/porta/irq_evt.rs @@ -0,0 +1,27 @@ +#[doc = "Register `IRQ_EVT` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_EVT` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_evt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_evt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEvtSpec; +impl crate::RegisterSpec for IrqEvtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_evt::R`](R) reader structure"] +impl crate::Readable for IrqEvtSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_evt::W`](W) writer structure"] +impl crate::Writable for IrqEvtSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_EVT to value 0"] +impl crate::Resettable for IrqEvtSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/porta/irq_raw.rs b/va416xx/src/porta/irq_raw.rs new file mode 100644 index 0000000..0e153ef --- /dev/null +++ b/va416xx/src/porta/irq_raw.rs @@ -0,0 +1,18 @@ +#[doc = "Register `IRQ_RAW` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqRawSpec; +impl crate::RegisterSpec for IrqRawSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"] +impl crate::Readable for IrqRawSpec {} +#[doc = "`reset()` method sets IRQ_RAW to value 0"] +impl crate::Resettable for IrqRawSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/porta/irq_sen.rs b/va416xx/src/porta/irq_sen.rs new file mode 100644 index 0000000..5b4c44a --- /dev/null +++ b/va416xx/src/porta/irq_sen.rs @@ -0,0 +1,27 @@ +#[doc = "Register `IRQ_SEN` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_SEN` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_sen::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_sen::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqSenSpec; +impl crate::RegisterSpec for IrqSenSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_sen::R`](R) reader structure"] +impl crate::Readable for IrqSenSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_sen::W`](W) writer structure"] +impl crate::Writable for IrqSenSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_SEN to value 0"] +impl crate::Resettable for IrqSenSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/porta/perid.rs b/va416xx/src/porta/perid.rs new file mode 100644 index 0000000..a5e57df --- /dev/null +++ b/va416xx/src/porta/perid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0210_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0210_07e9; +} diff --git a/va416xx/src/spi0.rs b/va416xx/src/spi0.rs new file mode 100644 index 0000000..e8f0c47 --- /dev/null +++ b/va416xx/src/spi0.rs @@ -0,0 +1,163 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl0: Ctrl0, + ctrl1: Ctrl1, + data: Data, + status: Status, + clkprescale: Clkprescale, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + txfifoirqtrg: Txfifoirqtrg, + fifo_clr: FifoClr, + state: State, + _reserved13: [u8; 0x03c8], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register 0"] + #[inline(always)] + pub const fn ctrl0(&self) -> &Ctrl0 { + &self.ctrl0 + } + #[doc = "0x04 - Control Register 1"] + #[inline(always)] + pub const fn ctrl1(&self) -> &Ctrl1 { + &self.ctrl1 + } + #[doc = "0x08 - Data Input/Output"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x0c - Status Register"] + #[inline(always)] + pub const fn status(&self) -> &Status { + &self.status + } + #[doc = "0x10 - Clock Pre Scale divide value"] + #[inline(always)] + pub const fn clkprescale(&self) -> &Clkprescale { + &self.clkprescale + } + #[doc = "0x14 - Interrupt Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x18 - Raw Interrupt Status Register"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x1c - Enabled Interrupt Status Register"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x20 - Clear Interrupt Status Register"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x24 - Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x28 - Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x2c - Clear FIFO Register"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x30 - Internal STATE of SPI Controller"] + #[inline(always)] + pub const fn state(&self) -> &State { + &self.state + } + #[doc = "0x3fc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] +module"] +#[doc(alias = "CTRL0")] +pub type Ctrl0 = crate::Reg; +#[doc = "Control Register 0"] +pub mod ctrl0; +#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] +module"] +#[doc(alias = "CTRL1")] +pub type Ctrl1 = crate::Reg; +#[doc = "Control Register 1"] +pub mod ctrl1; +#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] +module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data Input/Output"] +pub mod data; +#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] +module"] +#[doc(alias = "STATUS")] +pub type Status = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`] +module"] +#[doc(alias = "CLKPRESCALE")] +pub type Clkprescale = crate::Reg; +#[doc = "Clock Pre Scale divide value"] +pub mod clkprescale; +#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] +module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Interrupt Enable Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] +module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] +module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] +module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] +module"] +#[doc(alias = "STATE")] +pub type State = crate::Reg; +#[doc = "Internal STATE of SPI Controller"] +pub mod state; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/spi0/clkprescale.rs b/va416xx/src/spi0/clkprescale.rs new file mode 100644 index 0000000..ea5249f --- /dev/null +++ b/va416xx/src/spi0/clkprescale.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CLKPRESCALE` reader"] +pub type R = crate::R; +#[doc = "Register `CLKPRESCALE` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Clock Pre Scale divide value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkprescale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkprescale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkprescaleSpec; +impl crate::RegisterSpec for ClkprescaleSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkprescale::R`](R) reader structure"] +impl crate::Readable for ClkprescaleSpec {} +#[doc = "`write(|w| ..)` method takes [`clkprescale::W`](W) writer structure"] +impl crate::Writable for ClkprescaleSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKPRESCALE to value 0"] +impl crate::Resettable for ClkprescaleSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spi0/ctrl0.rs b/va416xx/src/spi0/ctrl0.rs new file mode 100644 index 0000000..4e41012 --- /dev/null +++ b/va416xx/src/spi0/ctrl0.rs @@ -0,0 +1,85 @@ +#[doc = "Register `CTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `SIZE` reader - Data Size(0x3=>4, 0xf=>16)"] +pub type SizeR = crate::FieldReader; +#[doc = "Field `SIZE` writer - Data Size(0x3=>4, 0xf=>16)"] +pub type SizeW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `SPO` reader - SPI Clock Polarity"] +pub type SpoR = crate::BitReader; +#[doc = "Field `SPO` writer - SPI Clock Polarity"] +pub type SpoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPH` reader - SPI Clock Phase"] +pub type SphR = crate::BitReader; +#[doc = "Field `SPH` writer - SPI Clock Phase"] +pub type SphW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SCRDV` reader - Serial Clock Rate divide+1 value"] +pub type ScrdvR = crate::FieldReader; +#[doc = "Field `SCRDV` writer - Serial Clock Rate divide+1 value"] +pub type ScrdvW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"] + #[inline(always)] + pub fn size(&self) -> SizeR { + SizeR::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 6 - SPI Clock Polarity"] + #[inline(always)] + pub fn spo(&self) -> SpoR { + SpoR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - SPI Clock Phase"] + #[inline(always)] + pub fn sph(&self) -> SphR { + SphR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"] + #[inline(always)] + pub fn scrdv(&self) -> ScrdvR { + ScrdvR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SizeW { + SizeW::new(self, 0) + } + #[doc = "Bit 6 - SPI Clock Polarity"] + #[inline(always)] + #[must_use] + pub fn spo(&mut self) -> SpoW { + SpoW::new(self, 6) + } + #[doc = "Bit 7 - SPI Clock Phase"] + #[inline(always)] + #[must_use] + pub fn sph(&mut self) -> SphW { + SphW::new(self, 7) + } + #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"] + #[inline(always)] + #[must_use] + pub fn scrdv(&mut self) -> ScrdvW { + ScrdvW::new(self, 8) + } +} +#[doc = "Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl0Spec; +impl crate::RegisterSpec for Ctrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl0::R`](R) reader structure"] +impl crate::Readable for Ctrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"] +impl crate::Writable for Ctrl0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL0 to value 0"] +impl crate::Resettable for Ctrl0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spi0/ctrl1.rs b/va416xx/src/spi0/ctrl1.rs new file mode 100644 index 0000000..45d9ec8 --- /dev/null +++ b/va416xx/src/spi0/ctrl1.rs @@ -0,0 +1,175 @@ +#[doc = "Register `CTRL1` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL1` writer"] +pub type W = crate::W; +#[doc = "Field `LBM` reader - Loop Back"] +pub type LbmR = crate::BitReader; +#[doc = "Field `LBM` writer - Loop Back"] +pub type LbmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MS` reader - Master/Slave (0:Master, 1:Slave)"] +pub type MsR = crate::BitReader; +#[doc = "Field `MS` writer - Master/Slave (0:Master, 1:Slave)"] +pub type MsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SOD` reader - Slave output Disable"] +pub type SodR = crate::BitReader; +#[doc = "Field `SOD` writer - Slave output Disable"] +pub type SodW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SS` reader - Slave Select"] +pub type SsR = crate::FieldReader; +#[doc = "Field `SS` writer - Slave Select"] +pub type SsW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `BLOCKMODE` reader - Block Mode Enable"] +pub type BlockmodeR = crate::BitReader; +#[doc = "Field `BLOCKMODE` writer - Block Mode Enable"] +pub type BlockmodeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BMSTART` reader - Block Mode Start Status Enable"] +pub type BmstartR = crate::BitReader; +#[doc = "Field `BMSTART` writer - Block Mode Start Status Enable"] +pub type BmstartW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BMSTALL` reader - Block Mode Stall Enable"] +pub type BmstallR = crate::BitReader; +#[doc = "Field `BMSTALL` writer - Block Mode Stall Enable"] +pub type BmstallW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MDLYCAP` reader - Master Delayed Capture Enable"] +pub type MdlycapR = crate::BitReader; +#[doc = "Field `MDLYCAP` writer - Master Delayed Capture Enable"] +pub type MdlycapW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MTXPAUSE` reader - Master Tx Pause Enable"] +pub type MtxpauseR = crate::BitReader; +#[doc = "Field `MTXPAUSE` writer - Master Tx Pause Enable"] +pub type MtxpauseW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Loop Back"] + #[inline(always)] + pub fn lbm(&self) -> LbmR { + LbmR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"] + #[inline(always)] + pub fn ms(&self) -> MsR { + MsR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave output Disable"] + #[inline(always)] + pub fn sod(&self) -> SodR { + SodR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Slave Select"] + #[inline(always)] + pub fn ss(&self) -> SsR { + SsR::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Block Mode Enable"] + #[inline(always)] + pub fn blockmode(&self) -> BlockmodeR { + BlockmodeR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Block Mode Start Status Enable"] + #[inline(always)] + pub fn bmstart(&self) -> BmstartR { + BmstartR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Block Mode Stall Enable"] + #[inline(always)] + pub fn bmstall(&self) -> BmstallR { + BmstallR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Master Delayed Capture Enable"] + #[inline(always)] + pub fn mdlycap(&self) -> MdlycapR { + MdlycapR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Master Tx Pause Enable"] + #[inline(always)] + pub fn mtxpause(&self) -> MtxpauseR { + MtxpauseR::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Loop Back"] + #[inline(always)] + #[must_use] + pub fn lbm(&mut self) -> LbmW { + LbmW::new(self, 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 1) + } + #[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"] + #[inline(always)] + #[must_use] + pub fn ms(&mut self) -> MsW { + MsW::new(self, 2) + } + #[doc = "Bit 3 - Slave output Disable"] + #[inline(always)] + #[must_use] + pub fn sod(&mut self) -> SodW { + SodW::new(self, 3) + } + #[doc = "Bits 4:6 - Slave Select"] + #[inline(always)] + #[must_use] + pub fn ss(&mut self) -> SsW { + SsW::new(self, 4) + } + #[doc = "Bit 7 - Block Mode Enable"] + #[inline(always)] + #[must_use] + pub fn blockmode(&mut self) -> BlockmodeW { + BlockmodeW::new(self, 7) + } + #[doc = "Bit 8 - Block Mode Start Status Enable"] + #[inline(always)] + #[must_use] + pub fn bmstart(&mut self) -> BmstartW { + BmstartW::new(self, 8) + } + #[doc = "Bit 9 - Block Mode Stall Enable"] + #[inline(always)] + #[must_use] + pub fn bmstall(&mut self) -> BmstallW { + BmstallW::new(self, 9) + } + #[doc = "Bit 10 - Master Delayed Capture Enable"] + #[inline(always)] + #[must_use] + pub fn mdlycap(&mut self) -> MdlycapW { + MdlycapW::new(self, 10) + } + #[doc = "Bit 11 - Master Tx Pause Enable"] + #[inline(always)] + #[must_use] + pub fn mtxpause(&mut self) -> MtxpauseW { + MtxpauseW::new(self, 11) + } +} +#[doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ctrl1Spec; +impl crate::RegisterSpec for Ctrl1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl1::R`](R) reader structure"] +impl crate::Readable for Ctrl1Spec {} +#[doc = "`write(|w| ..)` method takes [`ctrl1::W`](W) writer structure"] +impl crate::Writable for Ctrl1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL1 to value 0"] +impl crate::Resettable for Ctrl1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spi0/data.rs b/va416xx/src/spi0/data.rs new file mode 100644 index 0000000..30b85c9 --- /dev/null +++ b/va416xx/src/spi0/data.rs @@ -0,0 +1,27 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Input/Output\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spi0/fifo_clr.rs b/va416xx/src/spi0/fifo_clr.rs new file mode 100644 index 0000000..156da87 --- /dev/null +++ b/va416xx/src/spi0/fifo_clr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + #[must_use] + pub fn rxfifo(&mut self) -> RxfifoW { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + #[must_use] + pub fn txfifo(&mut self) -> TxfifoW { + TxfifoW::new(self, 1) + } +} +#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spi0/irq_enb.rs b/va416xx/src/spi0/irq_enb.rs new file mode 100644 index 0000000..68d93bc --- /dev/null +++ b/va416xx/src/spi0/irq_enb.rs @@ -0,0 +1,85 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `RORIM` reader - RX Overrun"] +pub type RorimR = crate::BitReader; +#[doc = "Field `RORIM` writer - RX Overrun"] +pub type RorimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RTIM` reader - RX Timeout"] +pub type RtimR = crate::BitReader; +#[doc = "Field `RTIM` writer - RX Timeout"] +pub type RtimW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RXIM` reader - RX Fifo is at least half full"] +pub type RximR = crate::BitReader; +#[doc = "Field `RXIM` writer - RX Fifo is at least half full"] +pub type RximW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXIM` reader - TX Fifo is at least half empty"] +pub type TximR = crate::BitReader; +#[doc = "Field `TXIM` writer - TX Fifo is at least half empty"] +pub type TximW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + pub fn rorim(&self) -> RorimR { + RorimR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + pub fn rtim(&self) -> RtimR { + RtimR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + pub fn rxim(&self) -> RximR { + RximR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + pub fn txim(&self) -> TximR { + TximR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RX Overrun"] + #[inline(always)] + #[must_use] + pub fn rorim(&mut self) -> RorimW { + RorimW::new(self, 0) + } + #[doc = "Bit 1 - RX Timeout"] + #[inline(always)] + #[must_use] + pub fn rtim(&mut self) -> RtimW { + RtimW::new(self, 1) + } + #[doc = "Bit 2 - RX Fifo is at least half full"] + #[inline(always)] + #[must_use] + pub fn rxim(&mut self) -> RximW { + RximW::new(self, 2) + } + #[doc = "Bit 3 - TX Fifo is at least half empty"] + #[inline(always)] + #[must_use] + pub fn txim(&mut self) -> TximW { + TximW::new(self, 3) + } +} +#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spi0/perid.rs b/va416xx/src/spi0/perid.rs new file mode 100644 index 0000000..9d82261 --- /dev/null +++ b/va416xx/src/spi0/perid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0213_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0213_07e9; +} diff --git a/va416xx/src/spi0/rxfifoirqtrg.rs b/va416xx/src/spi0/rxfifoirqtrg.rs new file mode 100644 index 0000000..46124d5 --- /dev/null +++ b/va416xx/src/spi0/rxfifoirqtrg.rs @@ -0,0 +1,27 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spi0/state.rs b/va416xx/src/spi0/state.rs new file mode 100644 index 0000000..aaa69d0 --- /dev/null +++ b/va416xx/src/spi0/state.rs @@ -0,0 +1,18 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of SPI Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StateSpec; +impl crate::RegisterSpec for StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for StateSpec {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for StateSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spi0/status.rs b/va416xx/src/spi0/status.rs new file mode 100644 index 0000000..d076d06 --- /dev/null +++ b/va416xx/src/spi0/status.rs @@ -0,0 +1,71 @@ +#[doc = "Register `STATUS` reader"] +pub type R = crate::R; +#[doc = "Field `TFE` reader - Transmit FIFO empty"] +pub type TfeR = crate::BitReader; +#[doc = "Field `TNF` reader - Transmit FIFO not full"] +pub type TnfR = crate::BitReader; +#[doc = "Field `RNE` reader - Receive FIFO not empty"] +pub type RneR = crate::BitReader; +#[doc = "Field `RFF` reader - Receive FIFO Full"] +pub type RffR = crate::BitReader; +#[doc = "Field `BUSY` reader - Busy"] +pub type BusyR = crate::BitReader; +#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte in BLOCKMODE"] +pub type RxdatafirstR = crate::BitReader; +#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"] +pub type RxtriggerR = crate::BitReader; +#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"] +pub type TxtriggerR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Transmit FIFO empty"] + #[inline(always)] + pub fn tfe(&self) -> TfeR { + TfeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit FIFO not full"] + #[inline(always)] + pub fn tnf(&self) -> TnfR { + TnfR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive FIFO not empty"] + #[inline(always)] + pub fn rne(&self) -> RneR { + RneR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive FIFO Full"] + #[inline(always)] + pub fn rff(&self) -> RffR { + RffR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BusyR { + BusyR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pending Data is first Byte in BLOCKMODE"] + #[inline(always)] + pub fn rxdatafirst(&self) -> RxdatafirstR { + RxdatafirstR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RX FIFO Above Trigger Level"] + #[inline(always)] + pub fn rxtrigger(&self) -> RxtriggerR { + RxtriggerR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - TX FIFO Below Trigger Level"] + #[inline(always)] + pub fn txtrigger(&self) -> TxtriggerR { + TxtriggerR::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StatusSpec; +impl crate::RegisterSpec for StatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`status::R`](R) reader structure"] +impl crate::Readable for StatusSpec {} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for StatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spi0/txfifoirqtrg.rs b/va416xx/src/spi0/txfifoirqtrg.rs new file mode 100644 index 0000000..0d13e54 --- /dev/null +++ b/va416xx/src/spi0/txfifoirqtrg.rs @@ -0,0 +1,27 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spw.rs b/va416xx/src/spw.rs new file mode 100644 index 0000000..5e89f66 --- /dev/null +++ b/va416xx/src/spw.rs @@ -0,0 +1,151 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + sts: Sts, + defaddr: Defaddr, + clkdiv: Clkdiv, + dkey: Dkey, + tc: Tc, + tdr: Tdr, + _reserved7: [u8; 0x04], + dmactrl0: Dmactrl0, + dmamaxlen0: Dmamaxlen0, + dmatxdesc0: Dmatxdesc0, + dmarxdesc0: Dmarxdesc0, + dmaaddr0: Dmaaddr0, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - Status/Interrupt Source Register"] + #[inline(always)] + pub const fn sts(&self) -> &Sts { + &self.sts + } + #[doc = "0x08 - Node Address Register"] + #[inline(always)] + pub const fn defaddr(&self) -> &Defaddr { + &self.defaddr + } + #[doc = "0x0c - Clock Divisor Register"] + #[inline(always)] + pub const fn clkdiv(&self) -> &Clkdiv { + &self.clkdiv + } + #[doc = "0x10 - Destination Key"] + #[inline(always)] + pub const fn dkey(&self) -> &Dkey { + &self.dkey + } + #[doc = "0x14 - Time Code Register"] + #[inline(always)] + pub const fn tc(&self) -> &Tc { + &self.tc + } + #[doc = "0x18 - Timer and Disconnect Register"] + #[inline(always)] + pub const fn tdr(&self) -> &Tdr { + &self.tdr + } + #[doc = "0x20 - DMA Control Register"] + #[inline(always)] + pub const fn dmactrl0(&self) -> &Dmactrl0 { + &self.dmactrl0 + } + #[doc = "0x24 - DMA RX Maximum Length Register"] + #[inline(always)] + pub const fn dmamaxlen0(&self) -> &Dmamaxlen0 { + &self.dmamaxlen0 + } + #[doc = "0x28 - DMA Transmitter Descriptor Table Address Register"] + #[inline(always)] + pub const fn dmatxdesc0(&self) -> &Dmatxdesc0 { + &self.dmatxdesc0 + } + #[doc = "0x2c - DMA Receiver Table Destination Register"] + #[inline(always)] + pub const fn dmarxdesc0(&self) -> &Dmarxdesc0 { + &self.dmarxdesc0 + } + #[doc = "0x30 - DMA Receiver Table Address Register"] + #[inline(always)] + pub const fn dmaaddr0(&self) -> &Dmaaddr0 { + &self.dmaaddr0 + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] +module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "STS (rw) register accessor: Status/Interrupt Source Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sts::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sts`] +module"] +#[doc(alias = "STS")] +pub type Sts = crate::Reg; +#[doc = "Status/Interrupt Source Register"] +pub mod sts; +#[doc = "DEFADDR (rw) register accessor: Node Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`defaddr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`defaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@defaddr`] +module"] +#[doc(alias = "DEFADDR")] +pub type Defaddr = crate::Reg; +#[doc = "Node Address Register"] +pub mod defaddr; +#[doc = "CLKDIV (rw) register accessor: Clock Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`] +module"] +#[doc(alias = "CLKDIV")] +pub type Clkdiv = crate::Reg; +#[doc = "Clock Divisor Register"] +pub mod clkdiv; +#[doc = "DKEY (rw) register accessor: Destination Key\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dkey::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dkey::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dkey`] +module"] +#[doc(alias = "DKEY")] +pub type Dkey = crate::Reg; +#[doc = "Destination Key"] +pub mod dkey; +#[doc = "TC (rw) register accessor: Time Code Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`] +module"] +#[doc(alias = "TC")] +pub type Tc = crate::Reg; +#[doc = "Time Code Register"] +pub mod tc; +#[doc = "TDR (r) register accessor: Timer and Disconnect Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tdr`] +module"] +#[doc(alias = "TDR")] +pub type Tdr = crate::Reg; +#[doc = "Timer and Disconnect Register"] +pub mod tdr; +#[doc = "DMACTRL0 (rw) register accessor: DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmactrl0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmactrl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactrl0`] +module"] +#[doc(alias = "DMACTRL0")] +pub type Dmactrl0 = crate::Reg; +#[doc = "DMA Control Register"] +pub mod dmactrl0; +#[doc = "DMAMAXLEN0 (rw) register accessor: DMA RX Maximum Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmamaxlen0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmamaxlen0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmamaxlen0`] +module"] +#[doc(alias = "DMAMAXLEN0")] +pub type Dmamaxlen0 = crate::Reg; +#[doc = "DMA RX Maximum Length Register"] +pub mod dmamaxlen0; +#[doc = "DMATXDESC0 (rw) register accessor: DMA Transmitter Descriptor Table Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmatxdesc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatxdesc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmatxdesc0`] +module"] +#[doc(alias = "DMATXDESC0")] +pub type Dmatxdesc0 = crate::Reg; +#[doc = "DMA Transmitter Descriptor Table Address Register"] +pub mod dmatxdesc0; +#[doc = "DMARXDESC0 (rw) register accessor: DMA Receiver Table Destination Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmarxdesc0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmarxdesc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmarxdesc0`] +module"] +#[doc(alias = "DMARXDESC0")] +pub type Dmarxdesc0 = crate::Reg; +#[doc = "DMA Receiver Table Destination Register"] +pub mod dmarxdesc0; +#[doc = "DMAADDR0 (rw) register accessor: DMA Receiver Table Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaaddr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaaddr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaaddr0`] +module"] +#[doc(alias = "DMAADDR0")] +pub type Dmaaddr0 = crate::Reg; +#[doc = "DMA Receiver Table Address Register"] +pub mod dmaaddr0; diff --git a/va416xx/src/spw/clkdiv.rs b/va416xx/src/spw/clkdiv.rs new file mode 100644 index 0000000..ab8ee77 --- /dev/null +++ b/va416xx/src/spw/clkdiv.rs @@ -0,0 +1,55 @@ +#[doc = "Register `CLKDIV` reader"] +pub type R = crate::R; +#[doc = "Register `CLKDIV` writer"] +pub type W = crate::W; +#[doc = "Field `CLKDIVRUN` reader - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] +pub type ClkdivrunR = crate::FieldReader; +#[doc = "Field `CLKDIVRUN` writer - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] +pub type ClkdivrunW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CLKDIVSTART` reader - 8-bit Clock divisor value used for the clock-divider during startup"] +pub type ClkdivstartR = crate::FieldReader; +#[doc = "Field `CLKDIVSTART` writer - 8-bit Clock divisor value used for the clock-divider during startup"] +pub type ClkdivstartW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] + #[inline(always)] + pub fn clkdivrun(&self) -> ClkdivrunR { + ClkdivrunR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - 8-bit Clock divisor value used for the clock-divider during startup"] + #[inline(always)] + pub fn clkdivstart(&self) -> ClkdivstartR { + ClkdivstartR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state"] + #[inline(always)] + #[must_use] + pub fn clkdivrun(&mut self) -> ClkdivrunW { + ClkdivrunW::new(self, 0) + } + #[doc = "Bits 8:15 - 8-bit Clock divisor value used for the clock-divider during startup"] + #[inline(always)] + #[must_use] + pub fn clkdivstart(&mut self) -> ClkdivstartW { + ClkdivstartW::new(self, 8) + } +} +#[doc = "Clock Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkdivSpec; +impl crate::RegisterSpec for ClkdivSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkdiv::R`](R) reader structure"] +impl crate::Readable for ClkdivSpec {} +#[doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"] +impl crate::Writable for ClkdivSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKDIV to value 0x0909"] +impl crate::Resettable for ClkdivSpec { + const RESET_VALUE: u32 = 0x0909; +} diff --git a/va416xx/src/spw/ctrl.rs b/va416xx/src/spw/ctrl.rs new file mode 100644 index 0000000..097fdd5 --- /dev/null +++ b/va416xx/src/spw/ctrl.rs @@ -0,0 +1,366 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LD` reader - Disable the SpaceWire CODEC"] +pub type LdR = crate::BitReader; +#[doc = "Field `LD` writer - Disable the SpaceWire CODEC"] +pub type LdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LS` reader - Start the link"] +pub type LsR = crate::BitReader; +#[doc = "Field `LS` writer - Start the link"] +pub type LsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AS` reader - Automatically start the link when a NULL has been received"] +pub type AsR = crate::BitReader; +#[doc = "Field `AS` writer - Automatically start the link when a NULL has been received"] +pub type AsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IE` reader - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] +pub type IeR = crate::BitReader; +#[doc = "Field `IE` writer - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] +pub type IeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TI` reader - The host can generate a tick by writing a one to this field"] +pub type TiR = crate::BitReader; +#[doc = "Field `TI` writer - The host can generate a tick by writing a one to this field"] +pub type TiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PM` reader - Enable Promiscuous mode"] +pub type PmR = crate::BitReader; +#[doc = "Field `PM` writer - Enable Promiscuous mode"] +pub type PmW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RS` reader - Make complete reset of the SpaceWire node. Self-clearing"] +pub type RsR = crate::BitReader; +#[doc = "Field `RS` writer - Make complete reset of the SpaceWire node. Self-clearing"] +pub type RsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TQ` reader - Generate interrupt when a valid time-code is received"] +pub type TqR = crate::BitReader; +#[doc = "Field `TQ` writer - Generate interrupt when a valid time-code is received"] +pub type TqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LI` reader - Generate interrupt when link error occurs"] +pub type LiR = crate::BitReader; +#[doc = "Field `LI` writer - Generate interrupt when link error occurs"] +pub type LiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TT` reader - Enable time-code transmissions"] +pub type TtR = crate::BitReader; +#[doc = "Field `TT` writer - Enable time-code transmissions"] +pub type TtW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TR` reader - Enable time-code receptions"] +pub type TrR = crate::BitReader; +#[doc = "Field `TR` writer - Enable time-code receptions"] +pub type TrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TF` reader - Time-code Flag Filter"] +pub type TfR = crate::BitReader; +#[doc = "Field `TF` writer - Time-code Flag Filter"] +pub type TfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TL` reader - Transmitter Enable Lock Control"] +pub type TlR = crate::BitReader; +#[doc = "Field `TL` writer - Transmitter Enable Lock Control"] +pub type TlW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PE` reader - SpW Plug-and-Play Enable"] +pub type PeR = crate::BitReader; +#[doc = "Field `PE` writer - SpW Plug-and-Play Enable"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RE` reader - Enable RMAP command handler"] +pub type ReR = crate::BitReader; +#[doc = "Field `RE` writer - Enable RMAP command handler"] +pub type ReW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RD` reader - If set only one RMAP buffer is used"] +pub type RdR = crate::BitReader; +#[doc = "Field `RD` writer - If set only one RMAP buffer is used"] +pub type RdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PNPA` reader - SpW Plug-and-Play Available"] +pub type PnpaR = crate::FieldReader; +#[doc = "Field `NP` reader - Disable port force"] +pub type NpR = crate::BitReader; +#[doc = "Field `NP` writer - Disable port force"] +pub type NpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PS` reader - Selects the active port when the no port force bit is zero"] +pub type PsR = crate::BitReader; +#[doc = "Field `PS` writer - Selects the active port when the no port force bit is zero"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LE` reader - Loop-back Enable"] +pub type LeR = crate::BitReader; +#[doc = "Field `LE` writer - Loop-back Enable"] +pub type LeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ID` reader - Interrupt distribution available"] +pub type IdR = crate::BitReader; +#[doc = "Field `CC` reader - CCSDS/CCITT CRC-16"] +pub type CcR = crate::BitReader; +#[doc = "Field `PO` reader - The number of available SpaceWire ports minus one"] +pub type PoR = crate::BitReader; +#[doc = "Field `NCH` reader - Number of DMA Channels minus one"] +pub type NchR = crate::FieldReader; +#[doc = "Field `RC` reader - Reads as 1 if RMAP CRC is enabled in the core"] +pub type RcR = crate::BitReader; +#[doc = "Field `RX` reader - Reads as 1 if unaligned writes are available for the receiver"] +pub type RxR = crate::BitReader; +#[doc = "Field `RA` reader - Reads as 1 if the RMAP command handler is available"] +pub type RaR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Disable the SpaceWire CODEC"] + #[inline(always)] + pub fn ld(&self) -> LdR { + LdR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Start the link"] + #[inline(always)] + pub fn ls(&self) -> LsR { + LsR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Automatically start the link when a NULL has been received"] + #[inline(always)] + pub fn as_(&self) -> AsR { + AsR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] + #[inline(always)] + pub fn ie(&self) -> IeR { + IeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - The host can generate a tick by writing a one to this field"] + #[inline(always)] + pub fn ti(&self) -> TiR { + TiR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Enable Promiscuous mode"] + #[inline(always)] + pub fn pm(&self) -> PmR { + PmR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Make complete reset of the SpaceWire node. Self-clearing"] + #[inline(always)] + pub fn rs(&self) -> RsR { + RsR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Generate interrupt when a valid time-code is received"] + #[inline(always)] + pub fn tq(&self) -> TqR { + TqR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Generate interrupt when link error occurs"] + #[inline(always)] + pub fn li(&self) -> LiR { + LiR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable time-code transmissions"] + #[inline(always)] + pub fn tt(&self) -> TtR { + TtR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable time-code receptions"] + #[inline(always)] + pub fn tr(&self) -> TrR { + TrR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Time-code Flag Filter"] + #[inline(always)] + pub fn tf(&self) -> TfR { + TfR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Transmitter Enable Lock Control"] + #[inline(always)] + pub fn tl(&self) -> TlR { + TlR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 15 - SpW Plug-and-Play Enable"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Enable RMAP command handler"] + #[inline(always)] + pub fn re(&self) -> ReR { + ReR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - If set only one RMAP buffer is used"] + #[inline(always)] + pub fn rd(&self) -> RdR { + RdR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 18:19 - SpW Plug-and-Play Available"] + #[inline(always)] + pub fn pnpa(&self) -> PnpaR { + PnpaR::new(((self.bits >> 18) & 3) as u8) + } + #[doc = "Bit 20 - Disable port force"] + #[inline(always)] + pub fn np(&self) -> NpR { + NpR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Selects the active port when the no port force bit is zero"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Loop-back Enable"] + #[inline(always)] + pub fn le(&self) -> LeR { + LeR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 24 - Interrupt distribution available"] + #[inline(always)] + pub fn id(&self) -> IdR { + IdR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - CCSDS/CCITT CRC-16"] + #[inline(always)] + pub fn cc(&self) -> CcR { + CcR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - The number of available SpaceWire ports minus one"] + #[inline(always)] + pub fn po(&self) -> PoR { + PoR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bits 27:28 - Number of DMA Channels minus one"] + #[inline(always)] + pub fn nch(&self) -> NchR { + NchR::new(((self.bits >> 27) & 3) as u8) + } + #[doc = "Bit 29 - Reads as 1 if RMAP CRC is enabled in the core"] + #[inline(always)] + pub fn rc(&self) -> RcR { + RcR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Reads as 1 if unaligned writes are available for the receiver"] + #[inline(always)] + pub fn rx(&self) -> RxR { + RxR::new(((self.bits >> 30) & 1) != 0) + } + #[doc = "Bit 31 - Reads as 1 if the RMAP command handler is available"] + #[inline(always)] + pub fn ra(&self) -> RaR { + RaR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Disable the SpaceWire CODEC"] + #[inline(always)] + #[must_use] + pub fn ld(&mut self) -> LdW { + LdW::new(self, 0) + } + #[doc = "Bit 1 - Start the link"] + #[inline(always)] + #[must_use] + pub fn ls(&mut self) -> LsW { + LsW::new(self, 1) + } + #[doc = "Bit 2 - Automatically start the link when a NULL has been received"] + #[inline(always)] + #[must_use] + pub fn as_(&mut self) -> AsW { + AsW::new(self, 2) + } + #[doc = "Bit 3 - If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IeW { + IeW::new(self, 3) + } + #[doc = "Bit 4 - The host can generate a tick by writing a one to this field"] + #[inline(always)] + #[must_use] + pub fn ti(&mut self) -> TiW { + TiW::new(self, 4) + } + #[doc = "Bit 5 - Enable Promiscuous mode"] + #[inline(always)] + #[must_use] + pub fn pm(&mut self) -> PmW { + PmW::new(self, 5) + } + #[doc = "Bit 6 - Make complete reset of the SpaceWire node. Self-clearing"] + #[inline(always)] + #[must_use] + pub fn rs(&mut self) -> RsW { + RsW::new(self, 6) + } + #[doc = "Bit 8 - Generate interrupt when a valid time-code is received"] + #[inline(always)] + #[must_use] + pub fn tq(&mut self) -> TqW { + TqW::new(self, 8) + } + #[doc = "Bit 9 - Generate interrupt when link error occurs"] + #[inline(always)] + #[must_use] + pub fn li(&mut self) -> LiW { + LiW::new(self, 9) + } + #[doc = "Bit 10 - Enable time-code transmissions"] + #[inline(always)] + #[must_use] + pub fn tt(&mut self) -> TtW { + TtW::new(self, 10) + } + #[doc = "Bit 11 - Enable time-code receptions"] + #[inline(always)] + #[must_use] + pub fn tr(&mut self) -> TrW { + TrW::new(self, 11) + } + #[doc = "Bit 12 - Time-code Flag Filter"] + #[inline(always)] + #[must_use] + pub fn tf(&mut self) -> TfW { + TfW::new(self, 12) + } + #[doc = "Bit 13 - Transmitter Enable Lock Control"] + #[inline(always)] + #[must_use] + pub fn tl(&mut self) -> TlW { + TlW::new(self, 13) + } + #[doc = "Bit 15 - SpW Plug-and-Play Enable"] + #[inline(always)] + #[must_use] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 15) + } + #[doc = "Bit 16 - Enable RMAP command handler"] + #[inline(always)] + #[must_use] + pub fn re(&mut self) -> ReW { + ReW::new(self, 16) + } + #[doc = "Bit 17 - If set only one RMAP buffer is used"] + #[inline(always)] + #[must_use] + pub fn rd(&mut self) -> RdW { + RdW::new(self, 17) + } + #[doc = "Bit 20 - Disable port force"] + #[inline(always)] + #[must_use] + pub fn np(&mut self) -> NpW { + NpW::new(self, 20) + } + #[doc = "Bit 21 - Selects the active port when the no port force bit is zero"] + #[inline(always)] + #[must_use] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 21) + } + #[doc = "Bit 22 - Loop-back Enable"] + #[inline(always)] + #[must_use] + pub fn le(&mut self) -> LeW { + LeW::new(self, 22) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0xa201_0004"] +impl crate::Resettable for CtrlSpec { + const RESET_VALUE: u32 = 0xa201_0004; +} diff --git a/va416xx/src/spw/defaddr.rs b/va416xx/src/spw/defaddr.rs new file mode 100644 index 0000000..3231286 --- /dev/null +++ b/va416xx/src/spw/defaddr.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DEFADDR` reader"] +pub type R = crate::R; +#[doc = "Register `DEFADDR` writer"] +pub type W = crate::W; +#[doc = "Field `DEFADDR` reader - 8-bit node address used for node identification on the SpaceWire network"] +pub type DefaddrR = crate::FieldReader; +#[doc = "Field `DEFADDR` writer - 8-bit node address used for node identification on the SpaceWire network"] +pub type DefaddrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `DEFMASK` reader - 8-bit default mask used for node identification on the SpaceWire network"] +pub type DefmaskR = crate::FieldReader; +#[doc = "Field `DEFMASK` writer - 8-bit default mask used for node identification on the SpaceWire network"] +pub type DefmaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - 8-bit node address used for node identification on the SpaceWire network"] + #[inline(always)] + pub fn defaddr(&self) -> DefaddrR { + DefaddrR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - 8-bit default mask used for node identification on the SpaceWire network"] + #[inline(always)] + pub fn defmask(&self) -> DefmaskR { + DefmaskR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - 8-bit node address used for node identification on the SpaceWire network"] + #[inline(always)] + #[must_use] + pub fn defaddr(&mut self) -> DefaddrW { + DefaddrW::new(self, 0) + } + #[doc = "Bits 8:15 - 8-bit default mask used for node identification on the SpaceWire network"] + #[inline(always)] + #[must_use] + pub fn defmask(&mut self) -> DefmaskW { + DefmaskW::new(self, 8) + } +} +#[doc = "Node Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`defaddr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`defaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DefaddrSpec; +impl crate::RegisterSpec for DefaddrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`defaddr::R`](R) reader structure"] +impl crate::Readable for DefaddrSpec {} +#[doc = "`write(|w| ..)` method takes [`defaddr::W`](W) writer structure"] +impl crate::Writable for DefaddrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEFADDR to value 0xfe"] +impl crate::Resettable for DefaddrSpec { + const RESET_VALUE: u32 = 0xfe; +} diff --git a/va416xx/src/spw/dkey.rs b/va416xx/src/spw/dkey.rs new file mode 100644 index 0000000..8b6dec4 --- /dev/null +++ b/va416xx/src/spw/dkey.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DKEY` reader"] +pub type R = crate::R; +#[doc = "Register `DKEY` writer"] +pub type W = crate::W; +#[doc = "Field `DESTKEY` reader - RMAP destination key"] +pub type DestkeyR = crate::FieldReader; +#[doc = "Field `DESTKEY` writer - RMAP destination key"] +pub type DestkeyW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - RMAP destination key"] + #[inline(always)] + pub fn destkey(&self) -> DestkeyR { + DestkeyR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - RMAP destination key"] + #[inline(always)] + #[must_use] + pub fn destkey(&mut self) -> DestkeyW { + DestkeyW::new(self, 0) + } +} +#[doc = "Destination Key\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dkey::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dkey::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DkeySpec; +impl crate::RegisterSpec for DkeySpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dkey::R`](R) reader structure"] +impl crate::Readable for DkeySpec {} +#[doc = "`write(|w| ..)` method takes [`dkey::W`](W) writer structure"] +impl crate::Writable for DkeySpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DKEY to value 0"] +impl crate::Resettable for DkeySpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spw/dmaaddr0.rs b/va416xx/src/spw/dmaaddr0.rs new file mode 100644 index 0000000..321fb26 --- /dev/null +++ b/va416xx/src/spw/dmaaddr0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DMAADDR0` reader"] +pub type R = crate::R; +#[doc = "Register `DMAADDR0` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - Address"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `MASK` reader - Mask"] +pub type MaskR = crate::FieldReader; +#[doc = "Field `MASK` writer - Mask"] +pub type MaskW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Address"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Mask"] + #[inline(always)] + pub fn mask(&self) -> MaskR { + MaskR::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> AddrW { + AddrW::new(self, 0) + } + #[doc = "Bits 8:15 - Mask"] + #[inline(always)] + #[must_use] + pub fn mask(&mut self) -> MaskW { + MaskW::new(self, 8) + } +} +#[doc = "DMA Receiver Table Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaaddr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaaddr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmaaddr0Spec; +impl crate::RegisterSpec for Dmaaddr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmaaddr0::R`](R) reader structure"] +impl crate::Readable for Dmaaddr0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmaaddr0::W`](W) writer structure"] +impl crate::Writable for Dmaaddr0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMAADDR0 to value 0"] +impl crate::Resettable for Dmaaddr0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spw/dmactrl0.rs b/va416xx/src/spw/dmactrl0.rs new file mode 100644 index 0000000..583e94f --- /dev/null +++ b/va416xx/src/spw/dmactrl0.rs @@ -0,0 +1,384 @@ +#[doc = "Register `DMACTRL0` reader"] +pub type R = crate::R; +#[doc = "Register `DMACTRL0` writer"] +pub type W = crate::W; +#[doc = "Field `TE` reader - Write a one to this bit each time new descriptors are activated in the table"] +pub type TeR = crate::BitReader; +#[doc = "Field `TE` writer - Write a one to this bit each time new descriptors are activated in the table"] +pub type TeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RE` reader - Packets are allowed to be received to this channel"] +pub type ReR = crate::BitReader; +#[doc = "Field `RE` writer - Packets are allowed to be received to this channel"] +pub type ReW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TI` reader - An interrupt will be generated each time a packet is transmitted"] +pub type TiR = crate::BitReader; +#[doc = "Field `TI` writer - An interrupt will be generated each time a packet is transmitted"] +pub type TiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RI` reader - An interrupt will be generated each time a packet has been received"] +pub type RiR = crate::BitReader; +#[doc = "Field `RI` writer - An interrupt will be generated each time a packet has been received"] +pub type RiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AI` reader - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] +pub type AiR = crate::BitReader; +#[doc = "Field `AI` writer - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] +pub type AiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PS` reader - Set each time a packet has been sent"] +pub type PsR = crate::BitReader; +#[doc = "Field `PS` writer - Set each time a packet has been sent"] +pub type PsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PR` reader - Set each time a packet has been received"] +pub type PrR = crate::BitReader; +#[doc = "Field `PR` writer - Set each time a packet has been received"] +pub type PrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TA` reader - An error response was detected on the AHB bus - DMA transmit"] +pub type TaR = crate::BitReader; +#[doc = "Field `TA` writer - An error response was detected on the AHB bus - DMA transmit"] +pub type TaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RA` reader - An error response was detected on the AHB bus - DMA receive"] +pub type RaR = crate::BitReader; +#[doc = "Field `RA` writer - An error response was detected on the AHB bus - DMA receive"] +pub type RaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AT` reader - Abort the currently transmitting packet and disable transmissions"] +pub type AtR = crate::BitReader; +#[doc = "Field `RX` reader - Reception to the DMA channel is currently active"] +pub type RxR = crate::BitReader; +#[doc = "Field `RD` reader - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] +pub type RdR = crate::BitReader; +#[doc = "Field `RD` writer - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] +pub type RdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `NS` reader - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] +pub type NsR = crate::BitReader; +#[doc = "Field `NS` writer - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] +pub type NsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EN` reader - Enable Address"] +pub type EnR = crate::BitReader; +#[doc = "Field `EN` writer - Enable Address"] +pub type EnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SA` reader - Strip Address"] +pub type SaR = crate::BitReader; +#[doc = "Field `SA` writer - Strip Address"] +pub type SaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SP` reader - Strip PID"] +pub type SpR = crate::BitReader; +#[doc = "Field `SP` writer - Strip PID"] +pub type SpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LE` reader - Disable transmitter when a link error occurs"] +pub type LeR = crate::BitReader; +#[doc = "Field `LE` writer - Disable transmitter when a link error occurs"] +pub type LeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TL` reader - Transmit Enable Lock"] +pub type TlR = crate::BitReader; +#[doc = "Field `TL` writer - Transmit Enable Lock"] +pub type TlW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TP` reader - Transmit Packet IRQ"] +pub type TpR = crate::BitReader; +#[doc = "Field `TP` writer - Transmit Packet IRQ"] +pub type TpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RP` reader - Receive Packet IRQ"] +pub type RpR = crate::BitReader; +#[doc = "Field `RP` writer - Receive Packet IRQ"] +pub type RpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IT` reader - Interrupt code transmit enable on truncation"] +pub type ItR = crate::BitReader; +#[doc = "Field `IT` writer - Interrupt code transmit enable on truncation"] +pub type ItW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IE` reader - Interrupt code transmit enable on EEP"] +pub type IeR = crate::BitReader; +#[doc = "Field `IE` writer - Interrupt code transmit enable on EEP"] +pub type IeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TR` reader - Truncated"] +pub type TrR = crate::BitReader; +#[doc = "Field `TR` writer - Truncated"] +pub type TrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EP` reader - EEP Termination"] +pub type EpR = crate::BitReader; +#[doc = "Field `EP` writer - EEP Termination"] +pub type EpW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTNUM` reader - Interrupt number used for this channel"] +pub type IntnumR = crate::FieldReader; +#[doc = "Field `INTNUM` writer - Interrupt number used for this channel"] +pub type IntnumW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bit 0 - Write a one to this bit each time new descriptors are activated in the table"] + #[inline(always)] + pub fn te(&self) -> TeR { + TeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Packets are allowed to be received to this channel"] + #[inline(always)] + pub fn re(&self) -> ReR { + ReR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - An interrupt will be generated each time a packet is transmitted"] + #[inline(always)] + pub fn ti(&self) -> TiR { + TiR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - An interrupt will be generated each time a packet has been received"] + #[inline(always)] + pub fn ri(&self) -> RiR { + RiR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] + #[inline(always)] + pub fn ai(&self) -> AiR { + AiR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Set each time a packet has been sent"] + #[inline(always)] + pub fn ps(&self) -> PsR { + PsR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Set each time a packet has been received"] + #[inline(always)] + pub fn pr(&self) -> PrR { + PrR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - An error response was detected on the AHB bus - DMA transmit"] + #[inline(always)] + pub fn ta(&self) -> TaR { + TaR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - An error response was detected on the AHB bus - DMA receive"] + #[inline(always)] + pub fn ra(&self) -> RaR { + RaR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Abort the currently transmitting packet and disable transmissions"] + #[inline(always)] + pub fn at(&self) -> AtR { + AtR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Reception to the DMA channel is currently active"] + #[inline(always)] + pub fn rx(&self) -> RxR { + RxR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] + #[inline(always)] + pub fn rd(&self) -> RdR { + RdR::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] + #[inline(always)] + pub fn ns(&self) -> NsR { + NsR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Enable Address"] + #[inline(always)] + pub fn en(&self) -> EnR { + EnR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Strip Address"] + #[inline(always)] + pub fn sa(&self) -> SaR { + SaR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Strip PID"] + #[inline(always)] + pub fn sp(&self) -> SpR { + SpR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Disable transmitter when a link error occurs"] + #[inline(always)] + pub fn le(&self) -> LeR { + LeR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Transmit Enable Lock"] + #[inline(always)] + pub fn tl(&self) -> TlR { + TlR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Transmit Packet IRQ"] + #[inline(always)] + pub fn tp(&self) -> TpR { + TpR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Receive Packet IRQ"] + #[inline(always)] + pub fn rp(&self) -> RpR { + RpR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Interrupt code transmit enable on truncation"] + #[inline(always)] + pub fn it(&self) -> ItR { + ItR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Interrupt code transmit enable on EEP"] + #[inline(always)] + pub fn ie(&self) -> IeR { + IeR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Truncated"] + #[inline(always)] + pub fn tr(&self) -> TrR { + TrR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - EEP Termination"] + #[inline(always)] + pub fn ep(&self) -> EpR { + EpR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 26:31 - Interrupt number used for this channel"] + #[inline(always)] + pub fn intnum(&self) -> IntnumR { + IntnumR::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Write a one to this bit each time new descriptors are activated in the table"] + #[inline(always)] + #[must_use] + pub fn te(&mut self) -> TeW { + TeW::new(self, 0) + } + #[doc = "Bit 1 - Packets are allowed to be received to this channel"] + #[inline(always)] + #[must_use] + pub fn re(&mut self) -> ReW { + ReW::new(self, 1) + } + #[doc = "Bit 2 - An interrupt will be generated each time a packet is transmitted"] + #[inline(always)] + #[must_use] + pub fn ti(&mut self) -> TiW { + TiW::new(self, 2) + } + #[doc = "Bit 3 - An interrupt will be generated each time a packet has been received"] + #[inline(always)] + #[must_use] + pub fn ri(&mut self) -> RiW { + RiW::new(self, 3) + } + #[doc = "Bit 4 - An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus"] + #[inline(always)] + #[must_use] + pub fn ai(&mut self) -> AiW { + AiW::new(self, 4) + } + #[doc = "Bit 5 - Set each time a packet has been sent"] + #[inline(always)] + #[must_use] + pub fn ps(&mut self) -> PsW { + PsW::new(self, 5) + } + #[doc = "Bit 6 - Set each time a packet has been received"] + #[inline(always)] + #[must_use] + pub fn pr(&mut self) -> PrW { + PrW::new(self, 6) + } + #[doc = "Bit 7 - An error response was detected on the AHB bus - DMA transmit"] + #[inline(always)] + #[must_use] + pub fn ta(&mut self) -> TaW { + TaW::new(self, 7) + } + #[doc = "Bit 8 - An error response was detected on the AHB bus - DMA receive"] + #[inline(always)] + #[must_use] + pub fn ra(&mut self) -> RaW { + RaW::new(self, 8) + } + #[doc = "Bit 11 - Indicates to the GRSPW that there are enabled descriptors in the descriptor table"] + #[inline(always)] + #[must_use] + pub fn rd(&mut self) -> RdW { + RdW::new(self, 11) + } + #[doc = "Bit 12 - If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated"] + #[inline(always)] + #[must_use] + pub fn ns(&mut self) -> NsW { + NsW::new(self, 12) + } + #[doc = "Bit 13 - Enable Address"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EnW { + EnW::new(self, 13) + } + #[doc = "Bit 14 - Strip Address"] + #[inline(always)] + #[must_use] + pub fn sa(&mut self) -> SaW { + SaW::new(self, 14) + } + #[doc = "Bit 15 - Strip PID"] + #[inline(always)] + #[must_use] + pub fn sp(&mut self) -> SpW { + SpW::new(self, 15) + } + #[doc = "Bit 16 - Disable transmitter when a link error occurs"] + #[inline(always)] + #[must_use] + pub fn le(&mut self) -> LeW { + LeW::new(self, 16) + } + #[doc = "Bit 17 - Transmit Enable Lock"] + #[inline(always)] + #[must_use] + pub fn tl(&mut self) -> TlW { + TlW::new(self, 17) + } + #[doc = "Bit 18 - Transmit Packet IRQ"] + #[inline(always)] + #[must_use] + pub fn tp(&mut self) -> TpW { + TpW::new(self, 18) + } + #[doc = "Bit 19 - Receive Packet IRQ"] + #[inline(always)] + #[must_use] + pub fn rp(&mut self) -> RpW { + RpW::new(self, 19) + } + #[doc = "Bit 20 - Interrupt code transmit enable on truncation"] + #[inline(always)] + #[must_use] + pub fn it(&mut self) -> ItW { + ItW::new(self, 20) + } + #[doc = "Bit 21 - Interrupt code transmit enable on EEP"] + #[inline(always)] + #[must_use] + pub fn ie(&mut self) -> IeW { + IeW::new(self, 21) + } + #[doc = "Bit 22 - Truncated"] + #[inline(always)] + #[must_use] + pub fn tr(&mut self) -> TrW { + TrW::new(self, 22) + } + #[doc = "Bit 23 - EEP Termination"] + #[inline(always)] + #[must_use] + pub fn ep(&mut self) -> EpW { + EpW::new(self, 23) + } + #[doc = "Bits 26:31 - Interrupt number used for this channel"] + #[inline(always)] + #[must_use] + pub fn intnum(&mut self) -> IntnumW { + IntnumW::new(self, 26) + } +} +#[doc = "DMA Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmactrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmactrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmactrl0Spec; +impl crate::RegisterSpec for Dmactrl0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmactrl0::R`](R) reader structure"] +impl crate::Readable for Dmactrl0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmactrl0::W`](W) writer structure"] +impl crate::Writable for Dmactrl0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMACTRL0 to value 0"] +impl crate::Resettable for Dmactrl0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spw/dmamaxlen0.rs b/va416xx/src/spw/dmamaxlen0.rs new file mode 100644 index 0000000..d809bbf --- /dev/null +++ b/va416xx/src/spw/dmamaxlen0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `DMAMAXLEN0` reader"] +pub type R = crate::R; +#[doc = "Register `DMAMAXLEN0` writer"] +pub type W = crate::W; +#[doc = "Field `RXMAXLEN` reader - Receiver packet maximum length in bytes"] +pub type RxmaxlenR = crate::FieldReader; +#[doc = "Field `RXMAXLEN` writer - Receiver packet maximum length in bytes"] +pub type RxmaxlenW<'a, REG> = crate::FieldWriter<'a, REG, 23, u32>; +impl R { + #[doc = "Bits 2:24 - Receiver packet maximum length in bytes"] + #[inline(always)] + pub fn rxmaxlen(&self) -> RxmaxlenR { + RxmaxlenR::new((self.bits >> 2) & 0x007f_ffff) + } +} +impl W { + #[doc = "Bits 2:24 - Receiver packet maximum length in bytes"] + #[inline(always)] + #[must_use] + pub fn rxmaxlen(&mut self) -> RxmaxlenW { + RxmaxlenW::new(self, 2) + } +} +#[doc = "DMA RX Maximum Length Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmamaxlen0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmamaxlen0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmamaxlen0Spec; +impl crate::RegisterSpec for Dmamaxlen0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmamaxlen0::R`](R) reader structure"] +impl crate::Readable for Dmamaxlen0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmamaxlen0::W`](W) writer structure"] +impl crate::Writable for Dmamaxlen0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMAMAXLEN0 to value 0"] +impl crate::Resettable for Dmamaxlen0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spw/dmarxdesc0.rs b/va416xx/src/spw/dmarxdesc0.rs new file mode 100644 index 0000000..50b31d3 --- /dev/null +++ b/va416xx/src/spw/dmarxdesc0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DMARXDESC0` reader"] +pub type R = crate::R; +#[doc = "Register `DMARXDESC0` writer"] +pub type W = crate::W; +#[doc = "Field `DESCSEL` reader - Offset into the descriptor table"] +pub type DescselR = crate::FieldReader; +#[doc = "Field `DESCSEL` writer - Offset into the descriptor table"] +pub type DescselW<'a, REG> = crate::FieldWriter<'a, REG, 7>; +#[doc = "Field `DESCBASEADDR` reader - Sets the base address of the descriptor table"] +pub type DescbaseaddrR = crate::FieldReader; +#[doc = "Field `DESCBASEADDR` writer - Sets the base address of the descriptor table"] +pub type DescbaseaddrW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 3:9 - Offset into the descriptor table"] + #[inline(always)] + pub fn descsel(&self) -> DescselR { + DescselR::new(((self.bits >> 3) & 0x7f) as u8) + } + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + pub fn descbaseaddr(&self) -> DescbaseaddrR { + DescbaseaddrR::new((self.bits >> 10) & 0x003f_ffff) + } +} +impl W { + #[doc = "Bits 3:9 - Offset into the descriptor table"] + #[inline(always)] + #[must_use] + pub fn descsel(&mut self) -> DescselW { + DescselW::new(self, 3) + } + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + #[must_use] + pub fn descbaseaddr(&mut self) -> DescbaseaddrW { + DescbaseaddrW::new(self, 10) + } +} +#[doc = "DMA Receiver Table Destination Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmarxdesc0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmarxdesc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmarxdesc0Spec; +impl crate::RegisterSpec for Dmarxdesc0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmarxdesc0::R`](R) reader structure"] +impl crate::Readable for Dmarxdesc0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmarxdesc0::W`](W) writer structure"] +impl crate::Writable for Dmarxdesc0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMARXDESC0 to value 0"] +impl crate::Resettable for Dmarxdesc0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spw/dmatxdesc0.rs b/va416xx/src/spw/dmatxdesc0.rs new file mode 100644 index 0000000..baf9a6d --- /dev/null +++ b/va416xx/src/spw/dmatxdesc0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `DMATXDESC0` reader"] +pub type R = crate::R; +#[doc = "Register `DMATXDESC0` writer"] +pub type W = crate::W; +#[doc = "Field `DESCSEL` reader - Offset into the descriptor table"] +pub type DescselR = crate::FieldReader; +#[doc = "Field `DESCSEL` writer - Offset into the descriptor table"] +pub type DescselW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `DESCBASEADDR` reader - Sets the base address of the descriptor table"] +pub type DescbaseaddrR = crate::FieldReader; +#[doc = "Field `DESCBASEADDR` writer - Sets the base address of the descriptor table"] +pub type DescbaseaddrW<'a, REG> = crate::FieldWriter<'a, REG, 22, u32>; +impl R { + #[doc = "Bits 4:9 - Offset into the descriptor table"] + #[inline(always)] + pub fn descsel(&self) -> DescselR { + DescselR::new(((self.bits >> 4) & 0x3f) as u8) + } + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + pub fn descbaseaddr(&self) -> DescbaseaddrR { + DescbaseaddrR::new((self.bits >> 10) & 0x003f_ffff) + } +} +impl W { + #[doc = "Bits 4:9 - Offset into the descriptor table"] + #[inline(always)] + #[must_use] + pub fn descsel(&mut self) -> DescselW { + DescselW::new(self, 4) + } + #[doc = "Bits 10:31 - Sets the base address of the descriptor table"] + #[inline(always)] + #[must_use] + pub fn descbaseaddr(&mut self) -> DescbaseaddrW { + DescbaseaddrW::new(self, 10) + } +} +#[doc = "DMA Transmitter Descriptor Table Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmatxdesc0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatxdesc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dmatxdesc0Spec; +impl crate::RegisterSpec for Dmatxdesc0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dmatxdesc0::R`](R) reader structure"] +impl crate::Readable for Dmatxdesc0Spec {} +#[doc = "`write(|w| ..)` method takes [`dmatxdesc0::W`](W) writer structure"] +impl crate::Writable for Dmatxdesc0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DMATXDESC0 to value 0"] +impl crate::Resettable for Dmatxdesc0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spw/sts.rs b/va416xx/src/spw/sts.rs new file mode 100644 index 0000000..1dc5074 --- /dev/null +++ b/va416xx/src/spw/sts.rs @@ -0,0 +1,205 @@ +#[doc = "Register `STS` reader"] +pub type R = crate::R; +#[doc = "Register `STS` writer"] +pub type W = crate::W; +#[doc = "Field `TO` reader - A new time count value was received"] +pub type ToR = crate::BitReader; +#[doc = "Field `TO` writer - A new time count value was received"] +pub type ToW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CE` reader - Credit has occurred"] +pub type CeR = crate::BitReader; +#[doc = "Field `CE` writer - Credit has occurred"] +pub type CeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ER` reader - Escape error has occurred"] +pub type ErR = crate::BitReader; +#[doc = "Field `ER` writer - Escape error has occurred"] +pub type ErW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DE` reader - Disconnection error has occurred"] +pub type DeR = crate::BitReader; +#[doc = "Field `DE` writer - Disconnection error has occurred"] +pub type DeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PE` reader - Parity error has occurred"] +pub type PeR = crate::BitReader; +#[doc = "Field `PE` writer - Parity error has occurred"] +pub type PeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WE` reader - A synchronization problem has occurred when receiving NChars"] +pub type WeR = crate::BitReader; +#[doc = "Field `WE` writer - A synchronization problem has occurred when receiving NChars"] +pub type WeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IA` reader - Packet is received with an invalid destination address field"] +pub type IaR = crate::BitReader; +#[doc = "Field `IA` writer - Packet is received with an invalid destination address field"] +pub type IaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EE` reader - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] +pub type EeR = crate::BitReader; +#[doc = "Field `EE` writer - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] +pub type EeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AP` reader - Active port"] +pub type ApR = crate::BitReader; +#[doc = "Field `AP` writer - Active port"] +pub type ApW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LS` reader - Link State"] +pub type LsR = crate::FieldReader; +#[doc = "Field `LS` writer - Link State"] +pub type LsW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `NTXD` reader - Number of Transmit Descriptors"] +pub type NtxdR = crate::FieldReader; +#[doc = "Field `NTXD` writer - Number of Transmit Descriptors"] +pub type NtxdW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `NRXD` reader - Number of Receive Descriptors"] +pub type NrxdR = crate::FieldReader; +#[doc = "Field `NRXD` writer - Number of Receive Descriptors"] +pub type NrxdW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bit 0 - A new time count value was received"] + #[inline(always)] + pub fn to(&self) -> ToR { + ToR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Credit has occurred"] + #[inline(always)] + pub fn ce(&self) -> CeR { + CeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Escape error has occurred"] + #[inline(always)] + pub fn er(&self) -> ErR { + ErR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Disconnection error has occurred"] + #[inline(always)] + pub fn de(&self) -> DeR { + DeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Parity error has occurred"] + #[inline(always)] + pub fn pe(&self) -> PeR { + PeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - A synchronization problem has occurred when receiving NChars"] + #[inline(always)] + pub fn we(&self) -> WeR { + WeR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Packet is received with an invalid destination address field"] + #[inline(always)] + pub fn ia(&self) -> IaR { + IaR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] + #[inline(always)] + pub fn ee(&self) -> EeR { + EeR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Active port"] + #[inline(always)] + pub fn ap(&self) -> ApR { + ApR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 21:23 - Link State"] + #[inline(always)] + pub fn ls(&self) -> LsR { + LsR::new(((self.bits >> 21) & 7) as u8) + } + #[doc = "Bits 24:25 - Number of Transmit Descriptors"] + #[inline(always)] + pub fn ntxd(&self) -> NtxdR { + NtxdR::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bits 26:27 - Number of Receive Descriptors"] + #[inline(always)] + pub fn nrxd(&self) -> NrxdR { + NrxdR::new(((self.bits >> 26) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - A new time count value was received"] + #[inline(always)] + #[must_use] + pub fn to(&mut self) -> ToW { + ToW::new(self, 0) + } + #[doc = "Bit 1 - Credit has occurred"] + #[inline(always)] + #[must_use] + pub fn ce(&mut self) -> CeW { + CeW::new(self, 1) + } + #[doc = "Bit 2 - Escape error has occurred"] + #[inline(always)] + #[must_use] + pub fn er(&mut self) -> ErW { + ErW::new(self, 2) + } + #[doc = "Bit 3 - Disconnection error has occurred"] + #[inline(always)] + #[must_use] + pub fn de(&mut self) -> DeW { + DeW::new(self, 3) + } + #[doc = "Bit 4 - Parity error has occurred"] + #[inline(always)] + #[must_use] + pub fn pe(&mut self) -> PeW { + PeW::new(self, 4) + } + #[doc = "Bit 6 - A synchronization problem has occurred when receiving NChars"] + #[inline(always)] + #[must_use] + pub fn we(&mut self) -> WeW { + WeW::new(self, 6) + } + #[doc = "Bit 7 - Packet is received with an invalid destination address field"] + #[inline(always)] + #[must_use] + pub fn ia(&mut self) -> IaW { + IaW::new(self, 7) + } + #[doc = "Bit 8 - Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet"] + #[inline(always)] + #[must_use] + pub fn ee(&mut self) -> EeW { + EeW::new(self, 8) + } + #[doc = "Bit 9 - Active port"] + #[inline(always)] + #[must_use] + pub fn ap(&mut self) -> ApW { + ApW::new(self, 9) + } + #[doc = "Bits 21:23 - Link State"] + #[inline(always)] + #[must_use] + pub fn ls(&mut self) -> LsW { + LsW::new(self, 21) + } + #[doc = "Bits 24:25 - Number of Transmit Descriptors"] + #[inline(always)] + #[must_use] + pub fn ntxd(&mut self) -> NtxdW { + NtxdW::new(self, 24) + } + #[doc = "Bits 26:27 - Number of Receive Descriptors"] + #[inline(always)] + #[must_use] + pub fn nrxd(&mut self) -> NrxdW { + NrxdW::new(self, 26) + } +} +#[doc = "Status/Interrupt Source Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sts::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StsSpec; +impl crate::RegisterSpec for StsSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sts::R`](R) reader structure"] +impl crate::Readable for StsSpec {} +#[doc = "`write(|w| ..)` method takes [`sts::W`](W) writer structure"] +impl crate::Writable for StsSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets STS to value 0x0640_0000"] +impl crate::Resettable for StsSpec { + const RESET_VALUE: u32 = 0x0640_0000; +} diff --git a/va416xx/src/spw/tc.rs b/va416xx/src/spw/tc.rs new file mode 100644 index 0000000..5f44ccb --- /dev/null +++ b/va416xx/src/spw/tc.rs @@ -0,0 +1,55 @@ +#[doc = "Register `TC` reader"] +pub type R = crate::R; +#[doc = "Register `TC` writer"] +pub type W = crate::W; +#[doc = "Field `TIMECNT` reader - The current value of the system time counter"] +pub type TimecntR = crate::FieldReader; +#[doc = "Field `TIMECNT` writer - The current value of the system time counter"] +pub type TimecntW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `TIRQ_END` reader - The current value of the time control flags"] +pub type TirqEndR = crate::FieldReader; +#[doc = "Field `TIRQ_END` writer - The current value of the time control flags"] +pub type TirqEndW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:5 - The current value of the system time counter"] + #[inline(always)] + pub fn timecnt(&self) -> TimecntR { + TimecntR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:7 - The current value of the time control flags"] + #[inline(always)] + pub fn tirq_end(&self) -> TirqEndR { + TirqEndR::new(((self.bits >> 6) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - The current value of the system time counter"] + #[inline(always)] + #[must_use] + pub fn timecnt(&mut self) -> TimecntW { + TimecntW::new(self, 0) + } + #[doc = "Bits 6:7 - The current value of the time control flags"] + #[inline(always)] + #[must_use] + pub fn tirq_end(&mut self) -> TirqEndW { + TirqEndW::new(self, 6) + } +} +#[doc = "Time Code Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TcSpec; +impl crate::RegisterSpec for TcSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tc::R`](R) reader structure"] +impl crate::Readable for TcSpec {} +#[doc = "`write(|w| ..)` method takes [`tc::W`](W) writer structure"] +impl crate::Writable for TcSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TC to value 0"] +impl crate::Resettable for TcSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/spw/tdr.rs b/va416xx/src/spw/tdr.rs new file mode 100644 index 0000000..9945a45 --- /dev/null +++ b/va416xx/src/spw/tdr.rs @@ -0,0 +1,29 @@ +#[doc = "Register `TDR` reader"] +pub type R = crate::R; +#[doc = "Field `TIMER64` reader - Used to generate the 6.4 and 12.8 us time periods"] +pub type Timer64R = crate::FieldReader; +#[doc = "Field `DISCONNECT` reader - Used to generate the 850 ns disconnect time period"] +pub type DisconnectR = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Used to generate the 6.4 and 12.8 us time periods"] + #[inline(always)] + pub fn timer64(&self) -> Timer64R { + Timer64R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:21 - Used to generate the 850 ns disconnect time period"] + #[inline(always)] + pub fn disconnect(&self) -> DisconnectR { + DisconnectR::new(((self.bits >> 12) & 0x03ff) as u16) + } +} +#[doc = "Timer and Disconnect Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tdr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TdrSpec; +impl crate::RegisterSpec for TdrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tdr::R`](R) reader structure"] +impl crate::Readable for TdrSpec {} +#[doc = "`reset()` method sets TDR to value 0"] +impl crate::Resettable for TdrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig.rs b/va416xx/src/sysconfig.rs new file mode 100644 index 0000000..52d41fa --- /dev/null +++ b/va416xx/src/sysconfig.rs @@ -0,0 +1,495 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + rst_stat: RstStat, + rst_cntl_rom: RstCntlRom, + rst_cntl_ram0: RstCntlRam0, + rst_cntl_ram1: RstCntlRam1, + rom_prot: RomProt, + rom_scrub: RomScrub, + ram0_scrub: Ram0Scrub, + ram1_scrub: Ram1Scrub, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + ram0_sbe: Ram0Sbe, + ram1_sbe: Ram1Sbe, + ram0_mbe: Ram0Mbe, + ram1_mbe: Ram1Mbe, + rom_sbe: RomSbe, + rom_mbe: RomMbe, + rom_retries: RomRetries, + refresh_config_h: RefreshConfigH, + tim_reset: TimReset, + tim_clk_enable: TimClkEnable, + peripheral_reset: PeripheralReset, + peripheral_clk_enable: PeripheralClkEnable, + spw_m4_ctrl: SpwM4Ctrl, + pmu_ctrl: PmuCtrl, + wakeup_cnt: WakeupCnt, + ebi_cfg0: EbiCfg0, + ebi_cfg1: EbiCfg1, + ebi_cfg2: EbiCfg2, + ebi_cfg3: EbiCfg3, + analog_cntl: AnalogCntl, + sw_clkdiv10: SwClkdiv10, + refresh_config_l: RefreshConfigL, + _reserved34: [u8; 0x0f48], + dac0_cal: Dac0Cal, + dac1_cal: Dac1Cal, + adc_cal: AdcCal, + bg_cal: BgCal, + dreg_cal: DregCal, + areg_cal: AregCal, + hbo_cal: HboCal, + ef_config: EfConfig, + ef_id0: EfId0, + ef_id1: EfId1, + procid: Procid, + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - System Reset Status"] + #[inline(always)] + pub const fn rst_stat(&self) -> &RstStat { + &self.rst_stat + } + #[doc = "0x04 - ROM Reset Control"] + #[inline(always)] + pub const fn rst_cntl_rom(&self) -> &RstCntlRom { + &self.rst_cntl_rom + } + #[doc = "0x08 - RAM Reset Control"] + #[inline(always)] + pub const fn rst_cntl_ram0(&self) -> &RstCntlRam0 { + &self.rst_cntl_ram0 + } + #[doc = "0x0c - RAM Reset Control"] + #[inline(always)] + pub const fn rst_cntl_ram1(&self) -> &RstCntlRam1 { + &self.rst_cntl_ram1 + } + #[doc = "0x10 - ROM Protection Configuration"] + #[inline(always)] + pub const fn rom_prot(&self) -> &RomProt { + &self.rom_prot + } + #[doc = "0x14 - ROM Scrub Period Configuration"] + #[inline(always)] + pub const fn rom_scrub(&self) -> &RomScrub { + &self.rom_scrub + } + #[doc = "0x18 - RAM0 Scrub Period Configuration"] + #[inline(always)] + pub const fn ram0_scrub(&self) -> &Ram0Scrub { + &self.ram0_scrub + } + #[doc = "0x1c - RAM1 Scrub Period Configuration"] + #[inline(always)] + pub const fn ram1_scrub(&self) -> &Ram1Scrub { + &self.ram1_scrub + } + #[doc = "0x20 - Enable EDAC Error Interrupt Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x24 - Raw EDAC Error Interrupt Status"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x28 - Enabled EDAC Error Interrupt Status"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x2c - Clear EDAC Error Interrupt Status"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x30 - Count of RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub const fn ram0_sbe(&self) -> &Ram0Sbe { + &self.ram0_sbe + } + #[doc = "0x34 - Count of RAM1 EDAC Single Bit Errors"] + #[inline(always)] + pub const fn ram1_sbe(&self) -> &Ram1Sbe { + &self.ram1_sbe + } + #[doc = "0x38 - Count of RAM0 EDAC Multi Bit Errors"] + #[inline(always)] + pub const fn ram0_mbe(&self) -> &Ram0Mbe { + &self.ram0_mbe + } + #[doc = "0x3c - Count of RAM1 EDAC Multi Bit Errors"] + #[inline(always)] + pub const fn ram1_mbe(&self) -> &Ram1Mbe { + &self.ram1_mbe + } + #[doc = "0x40 - Count of ROM EDAC Single Bit Errors"] + #[inline(always)] + pub const fn rom_sbe(&self) -> &RomSbe { + &self.rom_sbe + } + #[doc = "0x44 - Count of ROM EDAC Multi Bit Errors"] + #[inline(always)] + pub const fn rom_mbe(&self) -> &RomMbe { + &self.rom_mbe + } + #[doc = "0x48 - ROM BOOT Retry count"] + #[inline(always)] + pub const fn rom_retries(&self) -> &RomRetries { + &self.rom_retries + } + #[doc = "0x4c - Register Refresh Rate for TMR registers"] + #[inline(always)] + pub const fn refresh_config_h(&self) -> &RefreshConfigH { + &self.refresh_config_h + } + #[doc = "0x50 - TIM Reset Control"] + #[inline(always)] + pub const fn tim_reset(&self) -> &TimReset { + &self.tim_reset + } + #[doc = "0x54 - TIM Enable Control"] + #[inline(always)] + pub const fn tim_clk_enable(&self) -> &TimClkEnable { + &self.tim_clk_enable + } + #[doc = "0x58 - Peripheral Reset Control"] + #[inline(always)] + pub const fn peripheral_reset(&self) -> &PeripheralReset { + &self.peripheral_reset + } + #[doc = "0x5c - Peripheral Enable Control"] + #[inline(always)] + pub const fn peripheral_clk_enable(&self) -> &PeripheralClkEnable { + &self.peripheral_clk_enable + } + #[doc = "0x60 - SPW M4 control register"] + #[inline(always)] + pub const fn spw_m4_ctrl(&self) -> &SpwM4Ctrl { + &self.spw_m4_ctrl + } + #[doc = "0x64 - PMU Control Register"] + #[inline(always)] + pub const fn pmu_ctrl(&self) -> &PmuCtrl { + &self.pmu_ctrl + } + #[doc = "0x68 - Wakeup Control"] + #[inline(always)] + pub const fn wakeup_cnt(&self) -> &WakeupCnt { + &self.wakeup_cnt + } + #[doc = "0x6c - EBI Config Register 0"] + #[inline(always)] + pub const fn ebi_cfg0(&self) -> &EbiCfg0 { + &self.ebi_cfg0 + } + #[doc = "0x70 - EBI Config Register 1"] + #[inline(always)] + pub const fn ebi_cfg1(&self) -> &EbiCfg1 { + &self.ebi_cfg1 + } + #[doc = "0x74 - EBI Config Register 2"] + #[inline(always)] + pub const fn ebi_cfg2(&self) -> &EbiCfg2 { + &self.ebi_cfg2 + } + #[doc = "0x78 - EBI Config Register 3"] + #[inline(always)] + pub const fn ebi_cfg3(&self) -> &EbiCfg3 { + &self.ebi_cfg3 + } + #[doc = "0x7c - Analog Control Register"] + #[inline(always)] + pub const fn analog_cntl(&self) -> &AnalogCntl { + &self.analog_cntl + } + #[doc = "0x80 - Initial SpW Clock Divider Value"] + #[inline(always)] + pub const fn sw_clkdiv10(&self) -> &SwClkdiv10 { + &self.sw_clkdiv10 + } + #[doc = "0x84 - Register Refresh Rate for TMR registers"] + #[inline(always)] + pub const fn refresh_config_l(&self) -> &RefreshConfigL { + &self.refresh_config_l + } + #[doc = "0xfd0 - DAC0 Calibration Register"] + #[inline(always)] + pub const fn dac0_cal(&self) -> &Dac0Cal { + &self.dac0_cal + } + #[doc = "0xfd4 - DAC1 Calibration Register"] + #[inline(always)] + pub const fn dac1_cal(&self) -> &Dac1Cal { + &self.dac1_cal + } + #[doc = "0xfd8 - ADC Calibration Register"] + #[inline(always)] + pub const fn adc_cal(&self) -> &AdcCal { + &self.adc_cal + } + #[doc = "0xfdc - Bandgap Calibration Register"] + #[inline(always)] + pub const fn bg_cal(&self) -> &BgCal { + &self.bg_cal + } + #[doc = "0xfe0 - Digital LDO Regulator Calibration Register"] + #[inline(always)] + pub const fn dreg_cal(&self) -> &DregCal { + &self.dreg_cal + } + #[doc = "0xfe4 - Analog LDO Regulator Calibration Register"] + #[inline(always)] + pub const fn areg_cal(&self) -> &AregCal { + &self.areg_cal + } + #[doc = "0xfe8 - Heart Beat OSC Calibration Register"] + #[inline(always)] + pub const fn hbo_cal(&self) -> &HboCal { + &self.hbo_cal + } + #[doc = "0xfec - EFuse Config Register"] + #[inline(always)] + pub const fn ef_config(&self) -> &EfConfig { + &self.ef_config + } + #[doc = "0xff0 - EFuse ID0 Register"] + #[inline(always)] + pub const fn ef_id0(&self) -> &EfId0 { + &self.ef_id0 + } + #[doc = "0xff4 - EFuse ID1 Register"] + #[inline(always)] + pub const fn ef_id1(&self) -> &EfId1 { + &self.ef_id1 + } + #[doc = "0xff8 - Processor ID Register"] + #[inline(always)] + pub const fn procid(&self) -> &Procid { + &self.procid + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "RST_STAT (rw) register accessor: System Reset Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_stat::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_stat::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_stat`] +module"] +#[doc(alias = "RST_STAT")] +pub type RstStat = crate::Reg; +#[doc = "System Reset Status"] +pub mod rst_stat; +pub use rst_stat as rst_cntl_rom; +pub use rst_stat as rst_cntl_ram0; +pub use rst_stat as rst_cntl_ram1; +pub use RstStat as RstCntlRom; +pub use RstStat as RstCntlRam0; +pub use RstStat as RstCntlRam1; +#[doc = "ROM_PROT (rw) register accessor: ROM Protection Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_prot::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_prot::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_prot`] +module"] +#[doc(alias = "ROM_PROT")] +pub type RomProt = crate::Reg; +#[doc = "ROM Protection Configuration"] +pub mod rom_prot; +#[doc = "ROM_SCRUB (rw) register accessor: ROM Scrub Period Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_scrub::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_scrub::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_scrub`] +module"] +#[doc(alias = "ROM_SCRUB")] +pub type RomScrub = crate::Reg; +#[doc = "ROM Scrub Period Configuration"] +pub mod rom_scrub; +pub use rom_scrub as ram0_scrub; +pub use rom_scrub as ram1_scrub; +pub use RomScrub as Ram0Scrub; +pub use RomScrub as Ram1Scrub; +#[doc = "IRQ_ENB (rw) register accessor: Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] +module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "Enable EDAC Error Interrupt Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RAM0_SBE (rw) register accessor: Count of RAM0 EDAC Single Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram0_sbe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram0_sbe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram0_sbe`] +module"] +#[doc(alias = "RAM0_SBE")] +pub type Ram0Sbe = crate::Reg; +#[doc = "Count of RAM0 EDAC Single Bit Errors"] +pub mod ram0_sbe; +pub use ram0_sbe as ram1_sbe; +pub use Ram0Sbe as Ram1Sbe; +#[doc = "RAM0_MBE (rw) register accessor: Count of RAM0 EDAC Multi Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram0_mbe::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram0_mbe::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram0_mbe`] +module"] +#[doc(alias = "RAM0_MBE")] +pub type Ram0Mbe = crate::Reg; +#[doc = "Count of RAM0 EDAC Multi Bit Errors"] +pub mod ram0_mbe; +pub use ram0_mbe as ram1_mbe; +pub use ram0_mbe as rom_mbe; +pub use ram0_sbe as rom_sbe; +pub use Ram0Mbe as Ram1Mbe; +pub use Ram0Mbe as RomMbe; +pub use Ram0Sbe as RomSbe; +#[doc = "ROM_RETRIES (r) register accessor: ROM BOOT Retry count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_retries::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_retries`] +module"] +#[doc(alias = "ROM_RETRIES")] +pub type RomRetries = crate::Reg; +#[doc = "ROM BOOT Retry count"] +pub mod rom_retries; +#[doc = "REFRESH_CONFIG_H (rw) register accessor: Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config_h::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config_h::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config_h`] +module"] +#[doc(alias = "REFRESH_CONFIG_H")] +pub type RefreshConfigH = crate::Reg; +#[doc = "Register Refresh Rate for TMR registers"] +pub mod refresh_config_h; +#[doc = "TIM_RESET (rw) register accessor: TIM Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_reset`] +module"] +#[doc(alias = "TIM_RESET")] +pub type TimReset = crate::Reg; +#[doc = "TIM Reset Control"] +pub mod tim_reset; +#[doc = "TIM_CLK_ENABLE (rw) register accessor: TIM Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_clk_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_clk_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tim_clk_enable`] +module"] +#[doc(alias = "TIM_CLK_ENABLE")] +pub type TimClkEnable = crate::Reg; +#[doc = "TIM Enable Control"] +pub mod tim_clk_enable; +#[doc = "PERIPHERAL_RESET (rw) register accessor: Peripheral Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@peripheral_reset`] +module"] +#[doc(alias = "PERIPHERAL_RESET")] +pub type PeripheralReset = crate::Reg; +#[doc = "Peripheral Reset Control"] +pub mod peripheral_reset; +pub use peripheral_reset as peripheral_clk_enable; +pub use PeripheralReset as PeripheralClkEnable; +#[doc = "SPW_M4_CTRL (rw) register accessor: SPW M4 control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spw_m4_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spw_m4_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spw_m4_ctrl`] +module"] +#[doc(alias = "SPW_M4_CTRL")] +pub type SpwM4Ctrl = crate::Reg; +#[doc = "SPW M4 control register"] +pub mod spw_m4_ctrl; +#[doc = "PMU_CTRL (rw) register accessor: PMU Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmu_ctrl`] +module"] +#[doc(alias = "PMU_CTRL")] +pub type PmuCtrl = crate::Reg; +#[doc = "PMU Control Register"] +pub mod pmu_ctrl; +#[doc = "WAKEUP_CNT (rw) register accessor: Wakeup Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_cnt::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_cnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wakeup_cnt`] +module"] +#[doc(alias = "WAKEUP_CNT")] +pub type WakeupCnt = crate::Reg; +#[doc = "Wakeup Control"] +pub mod wakeup_cnt; +#[doc = "EBI_CFG0 (rw) register accessor: EBI Config Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ebi_cfg0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ebi_cfg0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ebi_cfg0`] +module"] +#[doc(alias = "EBI_CFG0")] +pub type EbiCfg0 = crate::Reg; +#[doc = "EBI Config Register 0"] +pub mod ebi_cfg0; +pub use ebi_cfg0 as ebi_cfg1; +pub use ebi_cfg0 as ebi_cfg2; +pub use ebi_cfg0 as ebi_cfg3; +pub use EbiCfg0 as EbiCfg1; +pub use EbiCfg0 as EbiCfg2; +pub use EbiCfg0 as EbiCfg3; +#[doc = "ANALOG_CNTL (rw) register accessor: Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`analog_cntl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`analog_cntl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@analog_cntl`] +module"] +#[doc(alias = "ANALOG_CNTL")] +pub type AnalogCntl = crate::Reg; +#[doc = "Analog Control Register"] +pub mod analog_cntl; +#[doc = "SW_CLKDIV10 (rw) register accessor: Initial SpW Clock Divider Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_clkdiv10::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_clkdiv10::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_clkdiv10`] +module"] +#[doc(alias = "SW_CLKDIV10")] +pub type SwClkdiv10 = crate::Reg; +#[doc = "Initial SpW Clock Divider Value"] +pub mod sw_clkdiv10; +#[doc = "REFRESH_CONFIG_L (rw) register accessor: Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config_l::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config_l::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refresh_config_l`] +module"] +#[doc(alias = "REFRESH_CONFIG_L")] +pub type RefreshConfigL = crate::Reg; +#[doc = "Register Refresh Rate for TMR registers"] +pub mod refresh_config_l; +#[doc = "DAC0_CAL (r) register accessor: DAC0 Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac0_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac0_cal`] +module"] +#[doc(alias = "DAC0_CAL")] +pub type Dac0Cal = crate::Reg; +#[doc = "DAC0 Calibration Register"] +pub mod dac0_cal; +#[doc = "DAC1_CAL (r) register accessor: DAC1 Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac1_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac1_cal`] +module"] +#[doc(alias = "DAC1_CAL")] +pub type Dac1Cal = crate::Reg; +#[doc = "DAC1 Calibration Register"] +pub mod dac1_cal; +#[doc = "ADC_CAL (r) register accessor: ADC Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc_cal`] +module"] +#[doc(alias = "ADC_CAL")] +pub type AdcCal = crate::Reg; +#[doc = "ADC Calibration Register"] +pub mod adc_cal; +#[doc = "BG_CAL (r) register accessor: Bandgap Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bg_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bg_cal`] +module"] +#[doc(alias = "BG_CAL")] +pub type BgCal = crate::Reg; +#[doc = "Bandgap Calibration Register"] +pub mod bg_cal; +#[doc = "DREG_CAL (r) register accessor: Digital LDO Regulator Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dreg_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dreg_cal`] +module"] +#[doc(alias = "DREG_CAL")] +pub type DregCal = crate::Reg; +#[doc = "Digital LDO Regulator Calibration Register"] +pub mod dreg_cal; +#[doc = "AREG_CAL (r) register accessor: Analog LDO Regulator Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`areg_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@areg_cal`] +module"] +#[doc(alias = "AREG_CAL")] +pub type AregCal = crate::Reg; +#[doc = "Analog LDO Regulator Calibration Register"] +pub mod areg_cal; +#[doc = "HBO_CAL (r) register accessor: Heart Beat OSC Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hbo_cal::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hbo_cal`] +module"] +#[doc(alias = "HBO_CAL")] +pub type HboCal = crate::Reg; +#[doc = "Heart Beat OSC Calibration Register"] +pub mod hbo_cal; +#[doc = "EF_CONFIG (r) register accessor: EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_config`] +module"] +#[doc(alias = "EF_CONFIG")] +pub type EfConfig = crate::Reg; +#[doc = "EFuse Config Register"] +pub mod ef_config; +#[doc = "EF_ID0 (r) register accessor: EFuse ID0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id0`] +module"] +#[doc(alias = "EF_ID0")] +pub type EfId0 = crate::Reg; +#[doc = "EFuse ID0 Register"] +pub mod ef_id0; +#[doc = "EF_ID1 (r) register accessor: EFuse ID1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ef_id1`] +module"] +#[doc(alias = "EF_ID1")] +pub type EfId1 = crate::Reg; +#[doc = "EFuse ID1 Register"] +pub mod ef_id1; +#[doc = "PROCID (r) register accessor: Processor ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`procid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@procid`] +module"] +#[doc(alias = "PROCID")] +pub type Procid = crate::Reg; +#[doc = "Processor ID Register"] +pub mod procid; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/sysconfig/adc_cal.rs b/va416xx/src/sysconfig/adc_cal.rs new file mode 100644 index 0000000..c06c3e1 --- /dev/null +++ b/va416xx/src/sysconfig/adc_cal.rs @@ -0,0 +1,22 @@ +#[doc = "Register `ADC_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `ADC_CAL` reader - ADC Calibration bits"] +pub type AdcCalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - ADC Calibration bits"] + #[inline(always)] + pub fn adc_cal(&self) -> AdcCalR { + AdcCalR::new((self.bits & 0x1f) as u8) + } +} +#[doc = "ADC Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AdcCalSpec; +impl crate::RegisterSpec for AdcCalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`adc_cal::R`](R) reader structure"] +impl crate::Readable for AdcCalSpec {} +#[doc = "`reset()` method sets ADC_CAL to value 0"] +impl crate::Resettable for AdcCalSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/analog_cntl.rs b/va416xx/src/sysconfig/analog_cntl.rs new file mode 100644 index 0000000..6001d88 --- /dev/null +++ b/va416xx/src/sysconfig/analog_cntl.rs @@ -0,0 +1,235 @@ +#[doc = "Register `ANALOG_CNTL` reader"] +pub type R = crate::R; +#[doc = "Register `ANALOG_CNTL` writer"] +pub type W = crate::W; +#[doc = "Field `TMOSC` reader - Test Mode"] +pub type TmoscR = crate::BitReader; +#[doc = "Field `TMOSC` writer - Test Mode"] +pub type TmoscW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMPOKDIS` reader - Test Mode"] +pub type TmpokdisR = crate::BitReader; +#[doc = "Field `TMPOKDIS` writer - Test Mode"] +pub type TmpokdisW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TM_ADCMUX_N` reader - Test Mode"] +pub type TmAdcmuxNR = crate::BitReader; +#[doc = "Field `TM_ADCMUX_N` writer - Test Mode"] +pub type TmAdcmuxNW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TM_ADCMUX_P` reader - Test Mode"] +pub type TmAdcmuxPR = crate::BitReader; +#[doc = "Field `TM_ADCMUX_P` writer - Test Mode"] +pub type TmAdcmuxPW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMRATIO` reader - Test Mode"] +pub type TmratioR = crate::BitReader; +#[doc = "Field `TMRATIO` writer - Test Mode"] +pub type TmratioW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TMATOMUX` reader - Test Mode"] +pub type TmatomuxR = crate::FieldReader; +#[doc = "Field `TMATOMUX` writer - Test Mode"] +pub type TmatomuxW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `ADC_STEST` reader - Number of clocks for sample time"] +pub type AdcStestR = crate::FieldReader; +#[doc = "Field `ADC_STEST` writer - Number of clocks for sample time"] +pub type AdcStestW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `RCLK_POS_EN` reader - Enable normal test clock"] +pub type RclkPosEnR = crate::BitReader; +#[doc = "Field `RCLK_POS_EN` writer - Enable normal test clock"] +pub type RclkPosEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RCLK_NEG_EN` reader - Enable inverted test clock"] +pub type RclkNegEnR = crate::BitReader; +#[doc = "Field `RCLK_NEG_EN` writer - Enable inverted test clock"] +pub type RclkNegEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB2CLK_POS_EN` reader - Enable normal APB2CLK for test output"] +pub type Apb2clkPosEnR = crate::BitReader; +#[doc = "Field `APB2CLK_POS_EN` writer - Enable normal APB2CLK for test output"] +pub type Apb2clkPosEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `APB2CLK_NEG_EN` reader - Enable inverted APB2CLK for test output"] +pub type Apb2clkNegEnR = crate::BitReader; +#[doc = "Field `APB2CLK_NEG_EN` writer - Enable inverted APB2CLK for test output"] +pub type Apb2clkNegEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TM_ANALOG_PD_EN` reader - Enables pull down on analog pads"] +pub type TmAnalogPdEnR = crate::BitReader; +#[doc = "Field `TM_ANALOG_PD_EN` writer - Enables pull down on analog pads"] +pub type TmAnalogPdEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `JMP2BOOT` reader - Enables a skip of all delay counters and eFuse read"] +pub type Jmp2bootR = crate::BitReader; +#[doc = "Field `JMP2BOOT` writer - Enables a skip of all delay counters and eFuse read"] +pub type Jmp2bootW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SKIPBOOT` reader - Enables a skip of all delay counters, eFuse read, and boot"] +pub type SkipbootR = crate::BitReader; +#[doc = "Field `SKIPBOOT` writer - Enables a skip of all delay counters, eFuse read, and boot"] +pub type SkipbootW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Test Mode"] + #[inline(always)] + pub fn tmosc(&self) -> TmoscR { + TmoscR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Test Mode"] + #[inline(always)] + pub fn tmpokdis(&self) -> TmpokdisR { + TmpokdisR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Test Mode"] + #[inline(always)] + pub fn tm_adcmux_n(&self) -> TmAdcmuxNR { + TmAdcmuxNR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Test Mode"] + #[inline(always)] + pub fn tm_adcmux_p(&self) -> TmAdcmuxPR { + TmAdcmuxPR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Test Mode"] + #[inline(always)] + pub fn tmratio(&self) -> TmratioR { + TmratioR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Test Mode"] + #[inline(always)] + pub fn tmatomux(&self) -> TmatomuxR { + TmatomuxR::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bits 9:12 - Number of clocks for sample time"] + #[inline(always)] + pub fn adc_stest(&self) -> AdcStestR { + AdcStestR::new(((self.bits >> 9) & 0x0f) as u8) + } + #[doc = "Bit 14 - Enable normal test clock"] + #[inline(always)] + pub fn rclk_pos_en(&self) -> RclkPosEnR { + RclkPosEnR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Enable inverted test clock"] + #[inline(always)] + pub fn rclk_neg_en(&self) -> RclkNegEnR { + RclkNegEnR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Enable normal APB2CLK for test output"] + #[inline(always)] + pub fn apb2clk_pos_en(&self) -> Apb2clkPosEnR { + Apb2clkPosEnR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Enable inverted APB2CLK for test output"] + #[inline(always)] + pub fn apb2clk_neg_en(&self) -> Apb2clkNegEnR { + Apb2clkNegEnR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Enables pull down on analog pads"] + #[inline(always)] + pub fn tm_analog_pd_en(&self) -> TmAnalogPdEnR { + TmAnalogPdEnR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"] + #[inline(always)] + pub fn jmp2boot(&self) -> Jmp2bootR { + Jmp2bootR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"] + #[inline(always)] + pub fn skipboot(&self) -> SkipbootR { + SkipbootR::new(((self.bits >> 20) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Test Mode"] + #[inline(always)] + #[must_use] + pub fn tmosc(&mut self) -> TmoscW { + TmoscW::new(self, 0) + } + #[doc = "Bit 1 - Test Mode"] + #[inline(always)] + #[must_use] + pub fn tmpokdis(&mut self) -> TmpokdisW { + TmpokdisW::new(self, 1) + } + #[doc = "Bit 2 - Test Mode"] + #[inline(always)] + #[must_use] + pub fn tm_adcmux_n(&mut self) -> TmAdcmuxNW { + TmAdcmuxNW::new(self, 2) + } + #[doc = "Bit 3 - Test Mode"] + #[inline(always)] + #[must_use] + pub fn tm_adcmux_p(&mut self) -> TmAdcmuxPW { + TmAdcmuxPW::new(self, 3) + } + #[doc = "Bit 4 - Test Mode"] + #[inline(always)] + #[must_use] + pub fn tmratio(&mut self) -> TmratioW { + TmratioW::new(self, 4) + } + #[doc = "Bits 5:6 - Test Mode"] + #[inline(always)] + #[must_use] + pub fn tmatomux(&mut self) -> TmatomuxW { + TmatomuxW::new(self, 5) + } + #[doc = "Bits 9:12 - Number of clocks for sample time"] + #[inline(always)] + #[must_use] + pub fn adc_stest(&mut self) -> AdcStestW { + AdcStestW::new(self, 9) + } + #[doc = "Bit 14 - Enable normal test clock"] + #[inline(always)] + #[must_use] + pub fn rclk_pos_en(&mut self) -> RclkPosEnW { + RclkPosEnW::new(self, 14) + } + #[doc = "Bit 15 - Enable inverted test clock"] + #[inline(always)] + #[must_use] + pub fn rclk_neg_en(&mut self) -> RclkNegEnW { + RclkNegEnW::new(self, 15) + } + #[doc = "Bit 16 - Enable normal APB2CLK for test output"] + #[inline(always)] + #[must_use] + pub fn apb2clk_pos_en(&mut self) -> Apb2clkPosEnW { + Apb2clkPosEnW::new(self, 16) + } + #[doc = "Bit 17 - Enable inverted APB2CLK for test output"] + #[inline(always)] + #[must_use] + pub fn apb2clk_neg_en(&mut self) -> Apb2clkNegEnW { + Apb2clkNegEnW::new(self, 17) + } + #[doc = "Bit 18 - Enables pull down on analog pads"] + #[inline(always)] + #[must_use] + pub fn tm_analog_pd_en(&mut self) -> TmAnalogPdEnW { + TmAnalogPdEnW::new(self, 18) + } + #[doc = "Bit 19 - Enables a skip of all delay counters and eFuse read"] + #[inline(always)] + #[must_use] + pub fn jmp2boot(&mut self) -> Jmp2bootW { + Jmp2bootW::new(self, 19) + } + #[doc = "Bit 20 - Enables a skip of all delay counters, eFuse read, and boot"] + #[inline(always)] + #[must_use] + pub fn skipboot(&mut self) -> SkipbootW { + SkipbootW::new(self, 20) + } +} +#[doc = "Analog Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`analog_cntl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`analog_cntl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AnalogCntlSpec; +impl crate::RegisterSpec for AnalogCntlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`analog_cntl::R`](R) reader structure"] +impl crate::Readable for AnalogCntlSpec {} +#[doc = "`write(|w| ..)` method takes [`analog_cntl::W`](W) writer structure"] +impl crate::Writable for AnalogCntlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ANALOG_CNTL to value 0"] +impl crate::Resettable for AnalogCntlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/areg_cal.rs b/va416xx/src/sysconfig/areg_cal.rs new file mode 100644 index 0000000..afc4b2f --- /dev/null +++ b/va416xx/src/sysconfig/areg_cal.rs @@ -0,0 +1,22 @@ +#[doc = "Register `AREG_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `AREG_CAL` reader - Analog LDO Regulator Calibration bits"] +pub type AregCalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:8 - Analog LDO Regulator Calibration bits"] + #[inline(always)] + pub fn areg_cal(&self) -> AregCalR { + AregCalR::new((self.bits & 0x01ff) as u16) + } +} +#[doc = "Analog LDO Regulator Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`areg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AregCalSpec; +impl crate::RegisterSpec for AregCalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`areg_cal::R`](R) reader structure"] +impl crate::Readable for AregCalSpec {} +#[doc = "`reset()` method sets AREG_CAL to value 0"] +impl crate::Resettable for AregCalSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/bg_cal.rs b/va416xx/src/sysconfig/bg_cal.rs new file mode 100644 index 0000000..8e21f23 --- /dev/null +++ b/va416xx/src/sysconfig/bg_cal.rs @@ -0,0 +1,22 @@ +#[doc = "Register `BG_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `BG_CAL` reader - Bandgap Calibration bits"] +pub type BgCalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - Bandgap Calibration bits"] + #[inline(always)] + pub fn bg_cal(&self) -> BgCalR { + BgCalR::new((self.bits & 7) as u8) + } +} +#[doc = "Bandgap Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BgCalSpec; +impl crate::RegisterSpec for BgCalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`bg_cal::R`](R) reader structure"] +impl crate::Readable for BgCalSpec {} +#[doc = "`reset()` method sets BG_CAL to value 0"] +impl crate::Resettable for BgCalSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/dac0_cal.rs b/va416xx/src/sysconfig/dac0_cal.rs new file mode 100644 index 0000000..ba817c9 --- /dev/null +++ b/va416xx/src/sysconfig/dac0_cal.rs @@ -0,0 +1,22 @@ +#[doc = "Register `DAC0_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `DAC0_CAL` reader - DAC0 Calibration bits"] +pub type Dac0CalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - DAC0 Calibration bits"] + #[inline(always)] + pub fn dac0_cal(&self) -> Dac0CalR { + Dac0CalR::new((self.bits & 0x1f) as u8) + } +} +#[doc = "DAC0 Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac0_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dac0CalSpec; +impl crate::RegisterSpec for Dac0CalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dac0_cal::R`](R) reader structure"] +impl crate::Readable for Dac0CalSpec {} +#[doc = "`reset()` method sets DAC0_CAL to value 0"] +impl crate::Resettable for Dac0CalSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/dac1_cal.rs b/va416xx/src/sysconfig/dac1_cal.rs new file mode 100644 index 0000000..28d6dcc --- /dev/null +++ b/va416xx/src/sysconfig/dac1_cal.rs @@ -0,0 +1,22 @@ +#[doc = "Register `DAC1_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `DAC1_CAL` reader - DAC1 Calibration bits"] +pub type Dac1CalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:4 - DAC1 Calibration bits"] + #[inline(always)] + pub fn dac1_cal(&self) -> Dac1CalR { + Dac1CalR::new((self.bits & 0x1f) as u8) + } +} +#[doc = "DAC1 Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dac1_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Dac1CalSpec; +impl crate::RegisterSpec for Dac1CalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dac1_cal::R`](R) reader structure"] +impl crate::Readable for Dac1CalSpec {} +#[doc = "`reset()` method sets DAC1_CAL to value 0"] +impl crate::Resettable for Dac1CalSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/dreg_cal.rs b/va416xx/src/sysconfig/dreg_cal.rs new file mode 100644 index 0000000..c6778db --- /dev/null +++ b/va416xx/src/sysconfig/dreg_cal.rs @@ -0,0 +1,22 @@ +#[doc = "Register `DREG_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `DREG_CAL` reader - Digital LDO Regulator Calibration bits"] +pub type DregCalR = crate::FieldReader; +impl R { + #[doc = "Bits 0:8 - Digital LDO Regulator Calibration bits"] + #[inline(always)] + pub fn dreg_cal(&self) -> DregCalR { + DregCalR::new((self.bits & 0x01ff) as u16) + } +} +#[doc = "Digital LDO Regulator Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dreg_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DregCalSpec; +impl crate::RegisterSpec for DregCalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`dreg_cal::R`](R) reader structure"] +impl crate::Readable for DregCalSpec {} +#[doc = "`reset()` method sets DREG_CAL to value 0"] +impl crate::Resettable for DregCalSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/ebi_cfg0.rs b/va416xx/src/sysconfig/ebi_cfg0.rs new file mode 100644 index 0000000..08bb521 --- /dev/null +++ b/va416xx/src/sysconfig/ebi_cfg0.rs @@ -0,0 +1,115 @@ +#[doc = "Register `EBI_CFG0` reader"] +pub type R = crate::R; +#[doc = "Register `EBI_CFG0` writer"] +pub type W = crate::W; +#[doc = "Field `ADDRLOW0` reader - Lower bound address for CEN0"] +pub type Addrlow0R = crate::FieldReader; +#[doc = "Field `ADDRLOW0` writer - Lower bound address for CEN0"] +pub type Addrlow0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `ADDRHIGH0` reader - Upper bound address for CEN0"] +pub type Addrhigh0R = crate::FieldReader; +#[doc = "Field `ADDRHIGH0` writer - Upper bound address for CEN0"] +pub type Addrhigh0W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `CFGREADCYCLE` reader - Number of cycles for a read - N plus 1"] +pub type CfgreadcycleR = crate::FieldReader; +#[doc = "Field `CFGREADCYCLE` writer - Number of cycles for a read - N plus 1"] +pub type CfgreadcycleW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CFGWRITECYCLE` reader - Number of cycles for a write - N plus 1"] +pub type CfgwritecycleR = crate::FieldReader; +#[doc = "Field `CFGWRITECYCLE` writer - Number of cycles for a write - N plus 1"] +pub type CfgwritecycleW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CFGTURNAROUNDCYCLE` reader - Number of cycles for turnaround - N plus 1"] +pub type CfgturnaroundcycleR = crate::FieldReader; +#[doc = "Field `CFGTURNAROUNDCYCLE` writer - Number of cycles for turnaround - N plus 1"] +pub type CfgturnaroundcycleW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CFGSIZE` reader - 8 bit (0) or 16 bit (1) port size"] +pub type CfgsizeR = crate::BitReader; +#[doc = "Field `CFGSIZE` writer - 8 bit (0) or 16 bit (1) port size"] +pub type CfgsizeW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + pub fn addrlow0(&self) -> Addrlow0R { + Addrlow0R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + pub fn addrhigh0(&self) -> Addrhigh0R { + Addrhigh0R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + pub fn cfgreadcycle(&self) -> CfgreadcycleR { + CfgreadcycleR::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + pub fn cfgwritecycle(&self) -> CfgwritecycleR { + CfgwritecycleR::new(((self.bits >> 19) & 7) as u8) + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + pub fn cfgturnaroundcycle(&self) -> CfgturnaroundcycleR { + CfgturnaroundcycleR::new(((self.bits >> 22) & 7) as u8) + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + pub fn cfgsize(&self) -> CfgsizeR { + CfgsizeR::new(((self.bits >> 25) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:7 - Lower bound address for CEN0"] + #[inline(always)] + #[must_use] + pub fn addrlow0(&mut self) -> Addrlow0W { + Addrlow0W::new(self, 0) + } + #[doc = "Bits 8:15 - Upper bound address for CEN0"] + #[inline(always)] + #[must_use] + pub fn addrhigh0(&mut self) -> Addrhigh0W { + Addrhigh0W::new(self, 8) + } + #[doc = "Bits 16:18 - Number of cycles for a read - N plus 1"] + #[inline(always)] + #[must_use] + pub fn cfgreadcycle(&mut self) -> CfgreadcycleW { + CfgreadcycleW::new(self, 16) + } + #[doc = "Bits 19:21 - Number of cycles for a write - N plus 1"] + #[inline(always)] + #[must_use] + pub fn cfgwritecycle(&mut self) -> CfgwritecycleW { + CfgwritecycleW::new(self, 19) + } + #[doc = "Bits 22:24 - Number of cycles for turnaround - N plus 1"] + #[inline(always)] + #[must_use] + pub fn cfgturnaroundcycle(&mut self) -> CfgturnaroundcycleW { + CfgturnaroundcycleW::new(self, 22) + } + #[doc = "Bit 25 - 8 bit (0) or 16 bit (1) port size"] + #[inline(always)] + #[must_use] + pub fn cfgsize(&mut self) -> CfgsizeW { + CfgsizeW::new(self, 25) + } +} +#[doc = "EBI Config Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ebi_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ebi_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EbiCfg0Spec; +impl crate::RegisterSpec for EbiCfg0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ebi_cfg0::R`](R) reader structure"] +impl crate::Readable for EbiCfg0Spec {} +#[doc = "`write(|w| ..)` method takes [`ebi_cfg0::W`](W) writer structure"] +impl crate::Writable for EbiCfg0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets EBI_CFG0 to value 0"] +impl crate::Resettable for EbiCfg0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/ef_config.rs b/va416xx/src/sysconfig/ef_config.rs new file mode 100644 index 0000000..462b89e --- /dev/null +++ b/va416xx/src/sysconfig/ef_config.rs @@ -0,0 +1,92 @@ +#[doc = "Register `EF_CONFIG` reader"] +pub type R = crate::R; +#[doc = "Field `ROM_SPEED` reader - Specifies the speed of ROM_SCK"] +pub type RomSpeedR = crate::FieldReader; +#[doc = "Field `ROM_SIZE` reader - Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset"] +pub type RomSizeR = crate::FieldReader; +#[doc = "Field `ROM_NOCHECK` reader - When set to 1, the ROM check is skipped"] +pub type RomNocheckR = crate::BitReader; +#[doc = "Field `BOOT_DELAY` reader - Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset"] +pub type BootDelayR = crate::FieldReader; +#[doc = "Field `ROM_READ` reader - SPI ROM read instruction code"] +pub type RomReadR = crate::FieldReader; +#[doc = "Field `ROM_LATENCY` reader - Number of bits of latency from Address until data from the SPI ROM"] +pub type RomLatencyR = crate::FieldReader; +#[doc = "Field `ROM_ADDRESS` reader - ROM Address Mode"] +pub type RomAddressR = crate::FieldReader; +#[doc = "Field `ROM_DLYCAP` reader - ROM SPI Delayed capture"] +pub type RomDlycapR = crate::BitReader; +#[doc = "Field `ROM_STATUS` reader - The first data byte from the SPI ROM following an address is taken as a status byte"] +pub type RomStatusR = crate::BitReader; +#[doc = "Field `RM` reader - This bit controls the internal RAM read timing and must be maintained at this value"] +pub type RmR = crate::BitReader; +#[doc = "Field `WM` reader - This bit controls the internal RAM write timing and must be maintained at this value"] +pub type WmR = crate::BitReader; +impl R { + #[doc = "Bits 0:1 - Specifies the speed of ROM_SCK"] + #[inline(always)] + pub fn rom_speed(&self) -> RomSpeedR { + RomSpeedR::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:5 - Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset"] + #[inline(always)] + pub fn rom_size(&self) -> RomSizeR { + RomSizeR::new(((self.bits >> 2) & 0x0f) as u8) + } + #[doc = "Bit 6 - When set to 1, the ROM check is skipped"] + #[inline(always)] + pub fn rom_nocheck(&self) -> RomNocheckR { + RomNocheckR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 7:9 - Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset"] + #[inline(always)] + pub fn boot_delay(&self) -> BootDelayR { + BootDelayR::new(((self.bits >> 7) & 7) as u8) + } + #[doc = "Bits 10:17 - SPI ROM read instruction code"] + #[inline(always)] + pub fn rom_read(&self) -> RomReadR { + RomReadR::new(((self.bits >> 10) & 0xff) as u8) + } + #[doc = "Bits 18:22 - Number of bits of latency from Address until data from the SPI ROM"] + #[inline(always)] + pub fn rom_latency(&self) -> RomLatencyR { + RomLatencyR::new(((self.bits >> 18) & 0x1f) as u8) + } + #[doc = "Bits 23:24 - ROM Address Mode"] + #[inline(always)] + pub fn rom_address(&self) -> RomAddressR { + RomAddressR::new(((self.bits >> 23) & 3) as u8) + } + #[doc = "Bit 25 - ROM SPI Delayed capture"] + #[inline(always)] + pub fn rom_dlycap(&self) -> RomDlycapR { + RomDlycapR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - The first data byte from the SPI ROM following an address is taken as a status byte"] + #[inline(always)] + pub fn rom_status(&self) -> RomStatusR { + RomStatusR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - This bit controls the internal RAM read timing and must be maintained at this value"] + #[inline(always)] + pub fn rm(&self) -> RmR { + RmR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - This bit controls the internal RAM write timing and must be maintained at this value"] + #[inline(always)] + pub fn wm(&self) -> WmR { + WmR::new(((self.bits >> 28) & 1) != 0) + } +} +#[doc = "EFuse Config Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_config::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EfConfigSpec; +impl crate::RegisterSpec for EfConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ef_config::R`](R) reader structure"] +impl crate::Readable for EfConfigSpec {} +#[doc = "`reset()` method sets EF_CONFIG to value 0x0a80_0c40"] +impl crate::Resettable for EfConfigSpec { + const RESET_VALUE: u32 = 0x0a80_0c40; +} diff --git a/va416xx/src/sysconfig/ef_id0.rs b/va416xx/src/sysconfig/ef_id0.rs new file mode 100644 index 0000000..1cc8166 --- /dev/null +++ b/va416xx/src/sysconfig/ef_id0.rs @@ -0,0 +1,18 @@ +#[doc = "Register `EF_ID0` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "EFuse ID0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EfId0Spec; +impl crate::RegisterSpec for EfId0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ef_id0::R`](R) reader structure"] +impl crate::Readable for EfId0Spec {} +#[doc = "`reset()` method sets EF_ID0 to value 0"] +impl crate::Resettable for EfId0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/ef_id1.rs b/va416xx/src/sysconfig/ef_id1.rs new file mode 100644 index 0000000..4470af5 --- /dev/null +++ b/va416xx/src/sysconfig/ef_id1.rs @@ -0,0 +1,18 @@ +#[doc = "Register `EF_ID1` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "EFuse ID1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ef_id1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EfId1Spec; +impl crate::RegisterSpec for EfId1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ef_id1::R`](R) reader structure"] +impl crate::Readable for EfId1Spec {} +#[doc = "`reset()` method sets EF_ID1 to value 0"] +impl crate::Resettable for EfId1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/hbo_cal.rs b/va416xx/src/sysconfig/hbo_cal.rs new file mode 100644 index 0000000..6817d67 --- /dev/null +++ b/va416xx/src/sysconfig/hbo_cal.rs @@ -0,0 +1,29 @@ +#[doc = "Register `HBO_CAL` reader"] +pub type R = crate::R; +#[doc = "Field `HBO_CAL` reader - Heart Beat OSC Calibration bits"] +pub type HboCalR = crate::FieldReader; +#[doc = "Field `OSC_CAL` reader - 1MHz OSC Calibration bit"] +pub type OscCalR = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - Heart Beat OSC Calibration bits"] + #[inline(always)] + pub fn hbo_cal(&self) -> HboCalR { + HboCalR::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - 1MHz OSC Calibration bit"] + #[inline(always)] + pub fn osc_cal(&self) -> OscCalR { + OscCalR::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Heart Beat OSC Calibration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hbo_cal::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct HboCalSpec; +impl crate::RegisterSpec for HboCalSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`hbo_cal::R`](R) reader structure"] +impl crate::Readable for HboCalSpec {} +#[doc = "`reset()` method sets HBO_CAL to value 0"] +impl crate::Resettable for HboCalSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/irq_enb.rs b/va416xx/src/sysconfig/irq_enb.rs new file mode 100644 index 0000000..2f4635f --- /dev/null +++ b/va416xx/src/sysconfig/irq_enb.rs @@ -0,0 +1,115 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `ROMMBE` reader - ROM Multi Bit Interrupt"] +pub type RommbeR = crate::BitReader; +#[doc = "Field `ROMMBE` writer - ROM Multi Bit Interrupt"] +pub type RommbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ROMSBE` reader - ROM Single Bit Interrupt"] +pub type RomsbeR = crate::BitReader; +#[doc = "Field `ROMSBE` writer - ROM Single Bit Interrupt"] +pub type RomsbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAM0MBE` reader - RAM0 Multi Bit Interrupt"] +pub type Ram0mbeR = crate::BitReader; +#[doc = "Field `RAM0MBE` writer - RAM0 Multi Bit Interrupt"] +pub type Ram0mbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAM0SBE` reader - RAM0 Single Bit Interrupt"] +pub type Ram0sbeR = crate::BitReader; +#[doc = "Field `RAM0SBE` writer - RAM0 Single Bit Interrupt"] +pub type Ram0sbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAM1MBE` reader - RAM1 Multi Bit Interrupt"] +pub type Ram1mbeR = crate::BitReader; +#[doc = "Field `RAM1MBE` writer - RAM1 Multi Bit Interrupt"] +pub type Ram1mbeW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RAM1SBE` reader - RAM1 Single Bit Interrupt"] +pub type Ram1sbeR = crate::BitReader; +#[doc = "Field `RAM1SBE` writer - RAM1 Single Bit Interrupt"] +pub type Ram1sbeW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - ROM Multi Bit Interrupt"] + #[inline(always)] + pub fn rommbe(&self) -> RommbeR { + RommbeR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ROM Single Bit Interrupt"] + #[inline(always)] + pub fn romsbe(&self) -> RomsbeR { + RomsbeR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram0mbe(&self) -> Ram0mbeR { + Ram0mbeR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RAM0 Single Bit Interrupt"] + #[inline(always)] + pub fn ram0sbe(&self) -> Ram0sbeR { + Ram0sbeR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"] + #[inline(always)] + pub fn ram1mbe(&self) -> Ram1mbeR { + Ram1mbeR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - RAM1 Single Bit Interrupt"] + #[inline(always)] + pub fn ram1sbe(&self) -> Ram1sbeR { + Ram1sbeR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ROM Multi Bit Interrupt"] + #[inline(always)] + #[must_use] + pub fn rommbe(&mut self) -> RommbeW { + RommbeW::new(self, 0) + } + #[doc = "Bit 1 - ROM Single Bit Interrupt"] + #[inline(always)] + #[must_use] + pub fn romsbe(&mut self) -> RomsbeW { + RomsbeW::new(self, 1) + } + #[doc = "Bit 2 - RAM0 Multi Bit Interrupt"] + #[inline(always)] + #[must_use] + pub fn ram0mbe(&mut self) -> Ram0mbeW { + Ram0mbeW::new(self, 2) + } + #[doc = "Bit 3 - RAM0 Single Bit Interrupt"] + #[inline(always)] + #[must_use] + pub fn ram0sbe(&mut self) -> Ram0sbeW { + Ram0sbeW::new(self, 3) + } + #[doc = "Bit 4 - RAM1 Multi Bit Interrupt"] + #[inline(always)] + #[must_use] + pub fn ram1mbe(&mut self) -> Ram1mbeW { + Ram1mbeW::new(self, 4) + } + #[doc = "Bit 5 - RAM1 Single Bit Interrupt"] + #[inline(always)] + #[must_use] + pub fn ram1sbe(&mut self) -> Ram1sbeW { + Ram1sbeW::new(self, 5) + } +} +#[doc = "Enable EDAC Error Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/perid.rs b/va416xx/src/sysconfig/perid.rs new file mode 100644 index 0000000..5ba23b5 --- /dev/null +++ b/va416xx/src/sysconfig/perid.rs @@ -0,0 +1,36 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +#[doc = "Field `MANUFACTURER_ID` reader - MANUFACTURER_ID"] +pub type ManufacturerIdR = crate::FieldReader; +#[doc = "Field `PERIPHERAL_ID` reader - PERIPHERAL_ID"] +pub type PeripheralIdR = crate::FieldReader; +#[doc = "Field `PERIPHERAL_VER` reader - PERIPHERAL_VER"] +pub type PeripheralVerR = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - MANUFACTURER_ID"] + #[inline(always)] + pub fn manufacturer_id(&self) -> ManufacturerIdR { + ManufacturerIdR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:23 - PERIPHERAL_ID"] + #[inline(always)] + pub fn peripheral_id(&self) -> PeripheralIdR { + PeripheralIdR::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - PERIPHERAL_VER"] + #[inline(always)] + pub fn peripheral_ver(&self) -> PeripheralVerR { + PeripheralVerR::new(((self.bits >> 24) & 0xff) as u8) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0280_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0280_07e9; +} diff --git a/va416xx/src/sysconfig/peripheral_reset.rs b/va416xx/src/sysconfig/peripheral_reset.rs new file mode 100644 index 0000000..ae813cc --- /dev/null +++ b/va416xx/src/sysconfig/peripheral_reset.rs @@ -0,0 +1,490 @@ +#[doc = "Register `PERIPHERAL_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `PERIPHERAL_RESET` writer"] +pub type W = crate::W; +#[doc = "Field `SPI0` reader - Resetn of SPI0"] +pub type Spi0R = crate::BitReader; +#[doc = "Field `SPI0` writer - Resetn of SPI0"] +pub type Spi0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI1` reader - Resetn of SPI1"] +pub type Spi1R = crate::BitReader; +#[doc = "Field `SPI1` writer - Resetn of SPI1"] +pub type Spi1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI2` reader - Resetn of SPI2"] +pub type Spi2R = crate::BitReader; +#[doc = "Field `SPI2` writer - Resetn of SPI2"] +pub type Spi2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPI3` reader - Resetn of SPI3"] +pub type Spi3R = crate::BitReader; +#[doc = "Field `SPI3` writer - Resetn of SPI3"] +pub type Spi3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART0` reader - Resetn of UART0"] +pub type Uart0R = crate::BitReader; +#[doc = "Field `UART0` writer - Resetn of UART0"] +pub type Uart0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART1` reader - Resetn of UART1"] +pub type Uart1R = crate::BitReader; +#[doc = "Field `UART1` writer - Resetn of UART1"] +pub type Uart1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UART2` reader - Resetn of UART2"] +pub type Uart2R = crate::BitReader; +#[doc = "Field `UART2` writer - Resetn of UART2"] +pub type Uart2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C0` reader - Resetn of I2C0"] +pub type I2c0R = crate::BitReader; +#[doc = "Field `I2C0` writer - Resetn of I2C0"] +pub type I2c0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C1` reader - Resetn of I2C1"] +pub type I2c1R = crate::BitReader; +#[doc = "Field `I2C1` writer - Resetn of I2C1"] +pub type I2c1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `I2C2` reader - Resetn of I2C2"] +pub type I2c2R = crate::BitReader; +#[doc = "Field `I2C2` writer - Resetn of I2C2"] +pub type I2c2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAN0` reader - Resetn of CAN0"] +pub type Can0R = crate::BitReader; +#[doc = "Field `CAN0` writer - Resetn of CAN0"] +pub type Can0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CAN1` reader - Resetn of CAN1"] +pub type Can1R = crate::BitReader; +#[doc = "Field `CAN1` writer - Resetn of CAN1"] +pub type Can1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TRNG` reader - Resetn of TRNG"] +pub type TrngR = crate::BitReader; +#[doc = "Field `TRNG` writer - Resetn of TRNG"] +pub type TrngW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ADC` reader - Resetn of ADC"] +pub type AdcR = crate::BitReader; +#[doc = "Field `ADC` writer - Resetn of ADC"] +pub type AdcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DAC` reader - Resetn of DAC"] +pub type DacR = crate::BitReader; +#[doc = "Field `DAC` writer - Resetn of DAC"] +pub type DacW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DMA` reader - Resetn of DMA"] +pub type DmaR = crate::BitReader; +#[doc = "Field `DMA` writer - Resetn of DMA"] +pub type DmaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EBI` reader - Resetn of EBI"] +pub type EbiR = crate::BitReader; +#[doc = "Field `EBI` writer - Resetn of EBI"] +pub type EbiW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ETH` reader - Resetn of Ethernet"] +pub type EthR = crate::BitReader; +#[doc = "Field `ETH` writer - Resetn of Ethernet"] +pub type EthW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SPW` reader - Resetn of SpaceWire"] +pub type SpwR = crate::BitReader; +#[doc = "Field `SPW` writer - Resetn of SpaceWire"] +pub type SpwW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CLKGEN` reader - RESETn of PLL in Clock Generation Module"] +pub type ClkgenR = crate::BitReader; +#[doc = "Field `CLKGEN` writer - RESETn of PLL in Clock Generation Module"] +pub type ClkgenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ` reader - Resetn of IRQ Router"] +pub type IrqR = crate::BitReader; +#[doc = "Field `IRQ` writer - Resetn of IRQ Router"] +pub type IrqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IOCONFIG` reader - Resetn of IO CONFIG"] +pub type IoconfigR = crate::BitReader; +#[doc = "Field `IOCONFIG` writer - Resetn of IO CONFIG"] +pub type IoconfigW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `UTILITY` reader - Resetn of UTILITY peripheral"] +pub type UtilityR = crate::BitReader; +#[doc = "Field `UTILITY` writer - Resetn of UTILITY peripheral"] +pub type UtilityW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDOG` reader - Resetn of WDOG"] +pub type WdogR = crate::BitReader; +#[doc = "Field `WDOG` writer - Resetn of WDOG"] +pub type WdogW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTA` reader - Resetn of PORTA"] +pub type PortaR = crate::BitReader; +#[doc = "Field `PORTA` writer - Resetn of PORTA"] +pub type PortaW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTB` reader - Resetn of PORTB"] +pub type PortbR = crate::BitReader; +#[doc = "Field `PORTB` writer - Resetn of PORTB"] +pub type PortbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTC` reader - Resetn of PORTC"] +pub type PortcR = crate::BitReader; +#[doc = "Field `PORTC` writer - Resetn of PORTC"] +pub type PortcW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTD` reader - Resetn of PORTD"] +pub type PortdR = crate::BitReader; +#[doc = "Field `PORTD` writer - Resetn of PORTD"] +pub type PortdW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTE` reader - Resetn of PORTE"] +pub type PorteR = crate::BitReader; +#[doc = "Field `PORTE` writer - Resetn of PORTE"] +pub type PorteW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTF` reader - Resetn of PORTF"] +pub type PortfR = crate::BitReader; +#[doc = "Field `PORTF` writer - Resetn of PORTF"] +pub type PortfW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORTG` reader - Resetn of PORTG"] +pub type PortgR = crate::BitReader; +#[doc = "Field `PORTG` writer - Resetn of PORTG"] +pub type PortgW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Resetn of SPI0"] + #[inline(always)] + pub fn spi0(&self) -> Spi0R { + Spi0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Resetn of SPI1"] + #[inline(always)] + pub fn spi1(&self) -> Spi1R { + Spi1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Resetn of SPI2"] + #[inline(always)] + pub fn spi2(&self) -> Spi2R { + Spi2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Resetn of SPI3"] + #[inline(always)] + pub fn spi3(&self) -> Spi3R { + Spi3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Resetn of UART0"] + #[inline(always)] + pub fn uart0(&self) -> Uart0R { + Uart0R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Resetn of UART1"] + #[inline(always)] + pub fn uart1(&self) -> Uart1R { + Uart1R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Resetn of UART2"] + #[inline(always)] + pub fn uart2(&self) -> Uart2R { + Uart2R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Resetn of I2C0"] + #[inline(always)] + pub fn i2c0(&self) -> I2c0R { + I2c0R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Resetn of I2C1"] + #[inline(always)] + pub fn i2c1(&self) -> I2c1R { + I2c1R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Resetn of I2C2"] + #[inline(always)] + pub fn i2c2(&self) -> I2c2R { + I2c2R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Resetn of CAN0"] + #[inline(always)] + pub fn can0(&self) -> Can0R { + Can0R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Resetn of CAN1"] + #[inline(always)] + pub fn can1(&self) -> Can1R { + Can1R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Resetn of TRNG"] + #[inline(always)] + pub fn trng(&self) -> TrngR { + TrngR::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Resetn of ADC"] + #[inline(always)] + pub fn adc(&self) -> AdcR { + AdcR::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Resetn of DAC"] + #[inline(always)] + pub fn dac(&self) -> DacR { + DacR::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Resetn of DMA"] + #[inline(always)] + pub fn dma(&self) -> DmaR { + DmaR::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Resetn of EBI"] + #[inline(always)] + pub fn ebi(&self) -> EbiR { + EbiR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Resetn of Ethernet"] + #[inline(always)] + pub fn eth(&self) -> EthR { + EthR::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Resetn of SpaceWire"] + #[inline(always)] + pub fn spw(&self) -> SpwR { + SpwR::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"] + #[inline(always)] + pub fn clkgen(&self) -> ClkgenR { + ClkgenR::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Resetn of IRQ Router"] + #[inline(always)] + pub fn irq(&self) -> IrqR { + IrqR::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Resetn of IO CONFIG"] + #[inline(always)] + pub fn ioconfig(&self) -> IoconfigR { + IoconfigR::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Resetn of UTILITY peripheral"] + #[inline(always)] + pub fn utility(&self) -> UtilityR { + UtilityR::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Resetn of WDOG"] + #[inline(always)] + pub fn wdog(&self) -> WdogR { + WdogR::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Resetn of PORTA"] + #[inline(always)] + pub fn porta(&self) -> PortaR { + PortaR::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Resetn of PORTB"] + #[inline(always)] + pub fn portb(&self) -> PortbR { + PortbR::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Resetn of PORTC"] + #[inline(always)] + pub fn portc(&self) -> PortcR { + PortcR::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Resetn of PORTD"] + #[inline(always)] + pub fn portd(&self) -> PortdR { + PortdR::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Resetn of PORTE"] + #[inline(always)] + pub fn porte(&self) -> PorteR { + PorteR::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Resetn of PORTF"] + #[inline(always)] + pub fn portf(&self) -> PortfR { + PortfR::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Resetn of PORTG"] + #[inline(always)] + pub fn portg(&self) -> PortgR { + PortgR::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Resetn of SPI0"] + #[inline(always)] + #[must_use] + pub fn spi0(&mut self) -> Spi0W { + Spi0W::new(self, 0) + } + #[doc = "Bit 1 - Resetn of SPI1"] + #[inline(always)] + #[must_use] + pub fn spi1(&mut self) -> Spi1W { + Spi1W::new(self, 1) + } + #[doc = "Bit 2 - Resetn of SPI2"] + #[inline(always)] + #[must_use] + pub fn spi2(&mut self) -> Spi2W { + Spi2W::new(self, 2) + } + #[doc = "Bit 3 - Resetn of SPI3"] + #[inline(always)] + #[must_use] + pub fn spi3(&mut self) -> Spi3W { + Spi3W::new(self, 3) + } + #[doc = "Bit 4 - Resetn of UART0"] + #[inline(always)] + #[must_use] + pub fn uart0(&mut self) -> Uart0W { + Uart0W::new(self, 4) + } + #[doc = "Bit 5 - Resetn of UART1"] + #[inline(always)] + #[must_use] + pub fn uart1(&mut self) -> Uart1W { + Uart1W::new(self, 5) + } + #[doc = "Bit 6 - Resetn of UART2"] + #[inline(always)] + #[must_use] + pub fn uart2(&mut self) -> Uart2W { + Uart2W::new(self, 6) + } + #[doc = "Bit 7 - Resetn of I2C0"] + #[inline(always)] + #[must_use] + pub fn i2c0(&mut self) -> I2c0W { + I2c0W::new(self, 7) + } + #[doc = "Bit 8 - Resetn of I2C1"] + #[inline(always)] + #[must_use] + pub fn i2c1(&mut self) -> I2c1W { + I2c1W::new(self, 8) + } + #[doc = "Bit 9 - Resetn of I2C2"] + #[inline(always)] + #[must_use] + pub fn i2c2(&mut self) -> I2c2W { + I2c2W::new(self, 9) + } + #[doc = "Bit 10 - Resetn of CAN0"] + #[inline(always)] + #[must_use] + pub fn can0(&mut self) -> Can0W { + Can0W::new(self, 10) + } + #[doc = "Bit 11 - Resetn of CAN1"] + #[inline(always)] + #[must_use] + pub fn can1(&mut self) -> Can1W { + Can1W::new(self, 11) + } + #[doc = "Bit 12 - Resetn of TRNG"] + #[inline(always)] + #[must_use] + pub fn trng(&mut self) -> TrngW { + TrngW::new(self, 12) + } + #[doc = "Bit 13 - Resetn of ADC"] + #[inline(always)] + #[must_use] + pub fn adc(&mut self) -> AdcW { + AdcW::new(self, 13) + } + #[doc = "Bit 14 - Resetn of DAC"] + #[inline(always)] + #[must_use] + pub fn dac(&mut self) -> DacW { + DacW::new(self, 14) + } + #[doc = "Bit 15 - Resetn of DMA"] + #[inline(always)] + #[must_use] + pub fn dma(&mut self) -> DmaW { + DmaW::new(self, 15) + } + #[doc = "Bit 16 - Resetn of EBI"] + #[inline(always)] + #[must_use] + pub fn ebi(&mut self) -> EbiW { + EbiW::new(self, 16) + } + #[doc = "Bit 17 - Resetn of Ethernet"] + #[inline(always)] + #[must_use] + pub fn eth(&mut self) -> EthW { + EthW::new(self, 17) + } + #[doc = "Bit 18 - Resetn of SpaceWire"] + #[inline(always)] + #[must_use] + pub fn spw(&mut self) -> SpwW { + SpwW::new(self, 18) + } + #[doc = "Bit 19 - RESETn of PLL in Clock Generation Module"] + #[inline(always)] + #[must_use] + pub fn clkgen(&mut self) -> ClkgenW { + ClkgenW::new(self, 19) + } + #[doc = "Bit 20 - Resetn of IRQ Router"] + #[inline(always)] + #[must_use] + pub fn irq(&mut self) -> IrqW { + IrqW::new(self, 20) + } + #[doc = "Bit 21 - Resetn of IO CONFIG"] + #[inline(always)] + #[must_use] + pub fn ioconfig(&mut self) -> IoconfigW { + IoconfigW::new(self, 21) + } + #[doc = "Bit 22 - Resetn of UTILITY peripheral"] + #[inline(always)] + #[must_use] + pub fn utility(&mut self) -> UtilityW { + UtilityW::new(self, 22) + } + #[doc = "Bit 23 - Resetn of WDOG"] + #[inline(always)] + #[must_use] + pub fn wdog(&mut self) -> WdogW { + WdogW::new(self, 23) + } + #[doc = "Bit 24 - Resetn of PORTA"] + #[inline(always)] + #[must_use] + pub fn porta(&mut self) -> PortaW { + PortaW::new(self, 24) + } + #[doc = "Bit 25 - Resetn of PORTB"] + #[inline(always)] + #[must_use] + pub fn portb(&mut self) -> PortbW { + PortbW::new(self, 25) + } + #[doc = "Bit 26 - Resetn of PORTC"] + #[inline(always)] + #[must_use] + pub fn portc(&mut self) -> PortcW { + PortcW::new(self, 26) + } + #[doc = "Bit 27 - Resetn of PORTD"] + #[inline(always)] + #[must_use] + pub fn portd(&mut self) -> PortdW { + PortdW::new(self, 27) + } + #[doc = "Bit 28 - Resetn of PORTE"] + #[inline(always)] + #[must_use] + pub fn porte(&mut self) -> PorteW { + PorteW::new(self, 28) + } + #[doc = "Bit 29 - Resetn of PORTF"] + #[inline(always)] + #[must_use] + pub fn portf(&mut self) -> PortfW { + PortfW::new(self, 29) + } + #[doc = "Bit 30 - Resetn of PORTG"] + #[inline(always)] + #[must_use] + pub fn portg(&mut self) -> PortgW { + PortgW::new(self, 30) + } +} +#[doc = "Peripheral Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peripheral_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peripheral_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeripheralResetSpec; +impl crate::RegisterSpec for PeripheralResetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`peripheral_reset::R`](R) reader structure"] +impl crate::Readable for PeripheralResetSpec {} +#[doc = "`write(|w| ..)` method takes [`peripheral_reset::W`](W) writer structure"] +impl crate::Writable for PeripheralResetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PERIPHERAL_RESET to value 0x7f7b_efff"] +impl crate::Resettable for PeripheralResetSpec { + const RESET_VALUE: u32 = 0x7f7b_efff; +} diff --git a/va416xx/src/sysconfig/pmu_ctrl.rs b/va416xx/src/sysconfig/pmu_ctrl.rs new file mode 100644 index 0000000..6fae35d --- /dev/null +++ b/va416xx/src/sysconfig/pmu_ctrl.rs @@ -0,0 +1,40 @@ +#[doc = "Register `PMU_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `PMU_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `LVL_SLCT` reader - Select the POK detect level"] +pub type LvlSlctR = crate::FieldReader; +#[doc = "Field `LVL_SLCT` writer - Select the POK detect level"] +pub type LvlSlctW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Select the POK detect level"] + #[inline(always)] + pub fn lvl_slct(&self) -> LvlSlctR { + LvlSlctR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Select the POK detect level"] + #[inline(always)] + #[must_use] + pub fn lvl_slct(&mut self) -> LvlSlctW { + LvlSlctW::new(self, 0) + } +} +#[doc = "PMU Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmu_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmu_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PmuCtrlSpec; +impl crate::RegisterSpec for PmuCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pmu_ctrl::R`](R) reader structure"] +impl crate::Readable for PmuCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`pmu_ctrl::W`](W) writer structure"] +impl crate::Writable for PmuCtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PMU_CTRL to value 0"] +impl crate::Resettable for PmuCtrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/procid.rs b/va416xx/src/sysconfig/procid.rs new file mode 100644 index 0000000..ae1cf1b --- /dev/null +++ b/va416xx/src/sysconfig/procid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PROCID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Processor ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`procid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ProcidSpec; +impl crate::RegisterSpec for ProcidSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`procid::R`](R) reader structure"] +impl crate::Readable for ProcidSpec {} +#[doc = "`reset()` method sets PROCID to value 0x0400_57e3"] +impl crate::Resettable for ProcidSpec { + const RESET_VALUE: u32 = 0x0400_57e3; +} diff --git a/va416xx/src/sysconfig/ram0_mbe.rs b/va416xx/src/sysconfig/ram0_mbe.rs new file mode 100644 index 0000000..d6d6207 --- /dev/null +++ b/va416xx/src/sysconfig/ram0_mbe.rs @@ -0,0 +1,40 @@ +#[doc = "Register `RAM0_MBE` reader"] +pub type R = crate::R; +#[doc = "Register `RAM0_MBE` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - RAM0 Multi Bit Errors"] +pub type CountR = crate::FieldReader; +#[doc = "Field `COUNT` writer - RAM0 Multi Bit Errors"] +pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RAM0 Multi Bit Errors"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> CountW { + CountW::new(self, 0) + } +} +#[doc = "Count of RAM0 EDAC Multi Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram0_mbe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram0_mbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ram0MbeSpec; +impl crate::RegisterSpec for Ram0MbeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram0_mbe::R`](R) reader structure"] +impl crate::Readable for Ram0MbeSpec {} +#[doc = "`write(|w| ..)` method takes [`ram0_mbe::W`](W) writer structure"] +impl crate::Writable for Ram0MbeSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RAM0_MBE to value 0"] +impl crate::Resettable for Ram0MbeSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/ram0_sbe.rs b/va416xx/src/sysconfig/ram0_sbe.rs new file mode 100644 index 0000000..c84d091 --- /dev/null +++ b/va416xx/src/sysconfig/ram0_sbe.rs @@ -0,0 +1,40 @@ +#[doc = "Register `RAM0_SBE` reader"] +pub type R = crate::R; +#[doc = "Register `RAM0_SBE` writer"] +pub type W = crate::W; +#[doc = "Field `COUNT` reader - RAM0 EDAC Single Bit Errors"] +pub type CountR = crate::FieldReader; +#[doc = "Field `COUNT` writer - RAM0 EDAC Single Bit Errors"] +pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +impl R { + #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - RAM0 EDAC Single Bit Errors"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> CountW { + CountW::new(self, 0) + } +} +#[doc = "Count of RAM0 EDAC Single Bit Errors\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram0_sbe::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram0_sbe::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Ram0SbeSpec; +impl crate::RegisterSpec for Ram0SbeSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram0_sbe::R`](R) reader structure"] +impl crate::Readable for Ram0SbeSpec {} +#[doc = "`write(|w| ..)` method takes [`ram0_sbe::W`](W) writer structure"] +impl crate::Writable for Ram0SbeSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RAM0_SBE to value 0"] +impl crate::Resettable for Ram0SbeSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/refresh_config_h.rs b/va416xx/src/sysconfig/refresh_config_h.rs new file mode 100644 index 0000000..6573d77 --- /dev/null +++ b/va416xx/src/sysconfig/refresh_config_h.rs @@ -0,0 +1,55 @@ +#[doc = "Register `REFRESH_CONFIG_H` reader"] +pub type R = crate::R; +#[doc = "Register `REFRESH_CONFIG_H` writer"] +pub type W = crate::W; +#[doc = "Field `DIVCOUNT` reader - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub type DivcountR = crate::FieldReader; +#[doc = "Field `DIVCOUNT` writer - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub type DivcountW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +#[doc = "Field `TESTMODE` reader - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] +pub type TestmodeR = crate::FieldReader; +#[doc = "Field `TESTMODE` writer - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] +pub type TestmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + pub fn divcount(&self) -> DivcountR { + DivcountR::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] + #[inline(always)] + pub fn testmode(&self) -> TestmodeR { + TestmodeR::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + #[must_use] + pub fn divcount(&mut self) -> DivcountW { + DivcountW::new(self, 0) + } + #[doc = "Bits 30:31 - Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly."] + #[inline(always)] + #[must_use] + pub fn testmode(&mut self) -> TestmodeW { + TestmodeW::new(self, 30) + } +} +#[doc = "Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config_h::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config_h::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RefreshConfigHSpec; +impl crate::RegisterSpec for RefreshConfigHSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`refresh_config_h::R`](R) reader structure"] +impl crate::Readable for RefreshConfigHSpec {} +#[doc = "`write(|w| ..)` method takes [`refresh_config_h::W`](W) writer structure"] +impl crate::Writable for RefreshConfigHSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets REFRESH_CONFIG_H to value 0"] +impl crate::Resettable for RefreshConfigHSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/refresh_config_l.rs b/va416xx/src/sysconfig/refresh_config_l.rs new file mode 100644 index 0000000..c8d1367 --- /dev/null +++ b/va416xx/src/sysconfig/refresh_config_l.rs @@ -0,0 +1,40 @@ +#[doc = "Register `REFRESH_CONFIG_L` reader"] +pub type R = crate::R; +#[doc = "Register `REFRESH_CONFIG_L` writer"] +pub type W = crate::W; +#[doc = "Field `DIVCOUNT` reader - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub type DivcountR = crate::FieldReader; +#[doc = "Field `DIVCOUNT` writer - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] +pub type DivcountW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + pub fn divcount(&self) -> DivcountR { + DivcountR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles"] + #[inline(always)] + #[must_use] + pub fn divcount(&mut self) -> DivcountW { + DivcountW::new(self, 0) + } +} +#[doc = "Register Refresh Rate for TMR registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refresh_config_l::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refresh_config_l::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RefreshConfigLSpec; +impl crate::RegisterSpec for RefreshConfigLSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`refresh_config_l::R`](R) reader structure"] +impl crate::Readable for RefreshConfigLSpec {} +#[doc = "`write(|w| ..)` method takes [`refresh_config_l::W`](W) writer structure"] +impl crate::Writable for RefreshConfigLSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets REFRESH_CONFIG_L to value 0x0f"] +impl crate::Resettable for RefreshConfigLSpec { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/va416xx/src/sysconfig/rom_prot.rs b/va416xx/src/sysconfig/rom_prot.rs new file mode 100644 index 0000000..657c3ab --- /dev/null +++ b/va416xx/src/sysconfig/rom_prot.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ROM_PROT` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_PROT` writer"] +pub type W = crate::W; +#[doc = "Field `WREN` reader - ROM Write Enable Bit"] +pub type WrenR = crate::BitReader; +#[doc = "Field `WREN` writer - ROM Write Enable Bit"] +pub type WrenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - ROM Write Enable Bit"] + #[inline(always)] + pub fn wren(&self) -> WrenR { + WrenR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ROM Write Enable Bit"] + #[inline(always)] + #[must_use] + pub fn wren(&mut self) -> WrenW { + WrenW::new(self, 0) + } +} +#[doc = "ROM Protection Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_prot::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_prot::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomProtSpec; +impl crate::RegisterSpec for RomProtSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_prot::R`](R) reader structure"] +impl crate::Readable for RomProtSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_prot::W`](W) writer structure"] +impl crate::Writable for RomProtSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ROM_PROT to value 0"] +impl crate::Resettable for RomProtSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/rom_retries.rs b/va416xx/src/sysconfig/rom_retries.rs new file mode 100644 index 0000000..8f60e8a --- /dev/null +++ b/va416xx/src/sysconfig/rom_retries.rs @@ -0,0 +1,22 @@ +#[doc = "Register `ROM_RETRIES` reader"] +pub type R = crate::R; +#[doc = "Field `COUNT` reader - Count of ROM block Retries"] +pub type CountR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Count of ROM block Retries"] + #[inline(always)] + pub fn count(&self) -> CountR { + CountR::new((self.bits & 0xff) as u8) + } +} +#[doc = "ROM BOOT Retry count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_retries::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomRetriesSpec; +impl crate::RegisterSpec for RomRetriesSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_retries::R`](R) reader structure"] +impl crate::Readable for RomRetriesSpec {} +#[doc = "`reset()` method sets ROM_RETRIES to value 0"] +impl crate::Resettable for RomRetriesSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/rom_scrub.rs b/va416xx/src/sysconfig/rom_scrub.rs new file mode 100644 index 0000000..20d5262 --- /dev/null +++ b/va416xx/src/sysconfig/rom_scrub.rs @@ -0,0 +1,48 @@ +#[doc = "Register `ROM_SCRUB` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_SCRUB` writer"] +pub type W = crate::W; +#[doc = "Field `VALUE` reader - Counter divide value"] +pub type ValueR = crate::FieldReader; +#[doc = "Field `VALUE` writer - Counter divide value"] +pub type ValueW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +#[doc = "Field `RESET` writer - Reset Counter"] +pub type ResetW<'a, REG> = crate::BitWriter1C<'a, REG>; +impl R { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + pub fn value(&self) -> ValueR { + ValueR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Counter divide value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> ValueW { + ValueW::new(self, 0) + } + #[doc = "Bit 31 - Reset Counter"] + #[inline(always)] + #[must_use] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 31) + } +} +#[doc = "ROM Scrub Period Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_scrub::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_scrub::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomScrubSpec; +impl crate::RegisterSpec for RomScrubSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_scrub::R`](R) reader structure"] +impl crate::Readable for RomScrubSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_scrub::W`](W) writer structure"] +impl crate::Writable for RomScrubSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8000_0000; +} +#[doc = "`reset()` method sets ROM_SCRUB to value 0"] +impl crate::Resettable for RomScrubSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/rst_stat.rs b/va416xx/src/sysconfig/rst_stat.rs new file mode 100644 index 0000000..2424cab --- /dev/null +++ b/va416xx/src/sysconfig/rst_stat.rs @@ -0,0 +1,107 @@ +#[doc = "Register `RST_STAT` reader"] +pub type R = crate::R; +#[doc = "Register `RST_STAT` writer"] +pub type W = crate::W; +#[doc = "Field `POR` reader - Power On Reset Status"] +pub type PorR = crate::BitReader; +#[doc = "Field `POR` writer - Power On Reset Status"] +pub type PorW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `EXTRST` reader - External Reset Status"] +pub type ExtrstR = crate::BitReader; +#[doc = "Field `EXTRST` writer - External Reset Status"] +pub type ExtrstW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `SYSRSTREQ` reader - SYSRESETREQ Reset Status"] +pub type SysrstreqR = crate::BitReader; +#[doc = "Field `SYSRSTREQ` writer - SYSRESETREQ Reset Status"] +pub type SysrstreqW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOKUP` reader - LOOKUP Reset Status"] +pub type LookupR = crate::BitReader; +#[doc = "Field `LOOKUP` writer - LOOKUP Reset Status"] +pub type LookupW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WATCHDOG` reader - WATCHDOG Reset Status"] +pub type WatchdogR = crate::BitReader; +#[doc = "Field `WATCHDOG` writer - WATCHDOG Reset Status"] +pub type WatchdogW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `MEMERR` reader - Memory Error Reset Status"] +pub type MemerrR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + pub fn por(&self) -> PorR { + PorR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + pub fn extrst(&self) -> ExtrstR { + ExtrstR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + pub fn sysrstreq(&self) -> SysrstreqR { + SysrstreqR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + pub fn lookup(&self) -> LookupR { + LookupR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + pub fn watchdog(&self) -> WatchdogR { + WatchdogR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Memory Error Reset Status"] + #[inline(always)] + pub fn memerr(&self) -> MemerrR { + MemerrR::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Power On Reset Status"] + #[inline(always)] + #[must_use] + pub fn por(&mut self) -> PorW { + PorW::new(self, 0) + } + #[doc = "Bit 1 - External Reset Status"] + #[inline(always)] + #[must_use] + pub fn extrst(&mut self) -> ExtrstW { + ExtrstW::new(self, 1) + } + #[doc = "Bit 2 - SYSRESETREQ Reset Status"] + #[inline(always)] + #[must_use] + pub fn sysrstreq(&mut self) -> SysrstreqW { + SysrstreqW::new(self, 2) + } + #[doc = "Bit 3 - LOOKUP Reset Status"] + #[inline(always)] + #[must_use] + pub fn lookup(&mut self) -> LookupW { + LookupW::new(self, 3) + } + #[doc = "Bit 4 - WATCHDOG Reset Status"] + #[inline(always)] + #[must_use] + pub fn watchdog(&mut self) -> WatchdogW { + WatchdogW::new(self, 4) + } +} +#[doc = "System Reset Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_stat::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RstStatSpec; +impl crate::RegisterSpec for RstStatSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_stat::R`](R) reader structure"] +impl crate::Readable for RstStatSpec {} +#[doc = "`write(|w| ..)` method takes [`rst_stat::W`](W) writer structure"] +impl crate::Writable for RstStatSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RST_STAT to value 0"] +impl crate::Resettable for RstStatSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/spw_m4_ctrl.rs b/va416xx/src/sysconfig/spw_m4_ctrl.rs new file mode 100644 index 0000000..98b6e0e --- /dev/null +++ b/va416xx/src/sysconfig/spw_m4_ctrl.rs @@ -0,0 +1,70 @@ +#[doc = "Register `SPW_M4_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `SPW_M4_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `REG_WR_KEY` reader - Fuse-analog register writes enabled when key = 0xfeed"] +pub type RegWrKeyR = crate::FieldReader; +#[doc = "Field `REG_WR_KEY` writer - Fuse-analog register writes enabled when key = 0xfeed"] +pub type RegWrKeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>; +#[doc = "Field `SPW_PAD_EN` reader - SPW pad enable"] +pub type SpwPadEnR = crate::BitReader; +#[doc = "Field `SPW_PAD_EN` writer - SPW pad enable"] +pub type SpwPadEnW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LREN` reader - Lockup reset enable"] +pub type LrenR = crate::BitReader; +#[doc = "Field `LREN` writer - Lockup reset enable"] +pub type LrenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"] + #[inline(always)] + pub fn reg_wr_key(&self) -> RegWrKeyR { + RegWrKeyR::new((self.bits & 0xffff) as u16) + } + #[doc = "Bit 16 - SPW pad enable"] + #[inline(always)] + pub fn spw_pad_en(&self) -> SpwPadEnR { + SpwPadEnR::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Lockup reset enable"] + #[inline(always)] + pub fn lren(&self) -> LrenR { + LrenR::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:15 - Fuse-analog register writes enabled when key = 0xfeed"] + #[inline(always)] + #[must_use] + pub fn reg_wr_key(&mut self) -> RegWrKeyW { + RegWrKeyW::new(self, 0) + } + #[doc = "Bit 16 - SPW pad enable"] + #[inline(always)] + #[must_use] + pub fn spw_pad_en(&mut self) -> SpwPadEnW { + SpwPadEnW::new(self, 16) + } + #[doc = "Bit 17 - Lockup reset enable"] + #[inline(always)] + #[must_use] + pub fn lren(&mut self) -> LrenW { + LrenW::new(self, 17) + } +} +#[doc = "SPW M4 control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spw_m4_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spw_m4_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SpwM4CtrlSpec; +impl crate::RegisterSpec for SpwM4CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`spw_m4_ctrl::R`](R) reader structure"] +impl crate::Readable for SpwM4CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`spw_m4_ctrl::W`](W) writer structure"] +impl crate::Writable for SpwM4CtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SPW_M4_CTRL to value 0x0003_0000"] +impl crate::Resettable for SpwM4CtrlSpec { + const RESET_VALUE: u32 = 0x0003_0000; +} diff --git a/va416xx/src/sysconfig/sw_clkdiv10.rs b/va416xx/src/sysconfig/sw_clkdiv10.rs new file mode 100644 index 0000000..966c53e --- /dev/null +++ b/va416xx/src/sysconfig/sw_clkdiv10.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SW_CLKDIV10` reader"] +pub type R = crate::R; +#[doc = "Register `SW_CLKDIV10` writer"] +pub type W = crate::W; +#[doc = "Field `SW_CLKDIV10` reader - Defines the initial value for the SpW clock, defaults to divide by ten"] +pub type SwClkdiv10R = crate::FieldReader; +#[doc = "Field `SW_CLKDIV10` writer - Defines the initial value for the SpW clock, defaults to divide by ten"] +pub type SwClkdiv10W<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"] + #[inline(always)] + pub fn sw_clkdiv10(&self) -> SwClkdiv10R { + SwClkdiv10R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Defines the initial value for the SpW clock, defaults to divide by ten"] + #[inline(always)] + #[must_use] + pub fn sw_clkdiv10(&mut self) -> SwClkdiv10W { + SwClkdiv10W::new(self, 0) + } +} +#[doc = "Initial SpW Clock Divider Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_clkdiv10::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_clkdiv10::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwClkdiv10Spec; +impl crate::RegisterSpec for SwClkdiv10Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_clkdiv10::R`](R) reader structure"] +impl crate::Readable for SwClkdiv10Spec {} +#[doc = "`write(|w| ..)` method takes [`sw_clkdiv10::W`](W) writer structure"] +impl crate::Writable for SwClkdiv10Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_CLKDIV10 to value 0x09"] +impl crate::Resettable for SwClkdiv10Spec { + const RESET_VALUE: u32 = 0x09; +} diff --git a/va416xx/src/sysconfig/tim_clk_enable.rs b/va416xx/src/sysconfig/tim_clk_enable.rs new file mode 100644 index 0000000..20fbf6d --- /dev/null +++ b/va416xx/src/sysconfig/tim_clk_enable.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TIM_CLK_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `TIM_CLK_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `TIMERS` reader - Clock enable of a given TIMER"] +pub type TimersR = crate::FieldReader; +#[doc = "Field `TIMERS` writer - Clock enable of a given TIMER"] +pub type TimersW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Clock enable of a given TIMER"] + #[inline(always)] + pub fn timers(&self) -> TimersR { + TimersR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Clock enable of a given TIMER"] + #[inline(always)] + #[must_use] + pub fn timers(&mut self) -> TimersW { + TimersW::new(self, 0) + } +} +#[doc = "TIM Enable Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_clk_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_clk_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimClkEnableSpec; +impl crate::RegisterSpec for TimClkEnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tim_clk_enable::R`](R) reader structure"] +impl crate::Readable for TimClkEnableSpec {} +#[doc = "`write(|w| ..)` method takes [`tim_clk_enable::W`](W) writer structure"] +impl crate::Writable for TimClkEnableSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIM_CLK_ENABLE to value 0"] +impl crate::Resettable for TimClkEnableSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/sysconfig/tim_reset.rs b/va416xx/src/sysconfig/tim_reset.rs new file mode 100644 index 0000000..dee7acf --- /dev/null +++ b/va416xx/src/sysconfig/tim_reset.rs @@ -0,0 +1,40 @@ +#[doc = "Register `TIM_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `TIM_RESET` writer"] +pub type W = crate::W; +#[doc = "Field `TIM_RESET` reader - Reset of a given TIMER"] +pub type TimResetR = crate::FieldReader; +#[doc = "Field `TIM_RESET` writer - Reset of a given TIMER"] +pub type TimResetW<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>; +impl R { + #[doc = "Bits 0:23 - Reset of a given TIMER"] + #[inline(always)] + pub fn tim_reset(&self) -> TimResetR { + TimResetR::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Reset of a given TIMER"] + #[inline(always)] + #[must_use] + pub fn tim_reset(&mut self) -> TimResetW { + TimResetW::new(self, 0) + } +} +#[doc = "TIM Reset Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tim_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tim_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TimResetSpec; +impl crate::RegisterSpec for TimResetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`tim_reset::R`](R) reader structure"] +impl crate::Readable for TimResetSpec {} +#[doc = "`write(|w| ..)` method takes [`tim_reset::W`](W) writer structure"] +impl crate::Writable for TimResetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TIM_RESET to value 0xffff_ffff"] +impl crate::Resettable for TimResetSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va416xx/src/sysconfig/wakeup_cnt.rs b/va416xx/src/sysconfig/wakeup_cnt.rs new file mode 100644 index 0000000..d83ae80 --- /dev/null +++ b/va416xx/src/sysconfig/wakeup_cnt.rs @@ -0,0 +1,55 @@ +#[doc = "Register `WAKEUP_CNT` reader"] +pub type R = crate::R; +#[doc = "Register `WAKEUP_CNT` writer"] +pub type W = crate::W; +#[doc = "Field `WKUP_CNT` reader - Used to set a time to wake up the processor after the device has been put in a low power state"] +pub type WkupCntR = crate::FieldReader; +#[doc = "Field `WKUP_CNT` writer - Used to set a time to wake up the processor after the device has been put in a low power state"] +pub type WkupCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `CNTSTRT` reader - Launch SLP mode in analog block"] +pub type CntstrtR = crate::BitReader; +#[doc = "Field `CNTSTRT` writer - Launch SLP mode in analog block"] +pub type CntstrtW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"] + #[inline(always)] + pub fn wkup_cnt(&self) -> WkupCntR { + WkupCntR::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Launch SLP mode in analog block"] + #[inline(always)] + pub fn cntstrt(&self) -> CntstrtR { + CntstrtR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Used to set a time to wake up the processor after the device has been put in a low power state"] + #[inline(always)] + #[must_use] + pub fn wkup_cnt(&mut self) -> WkupCntW { + WkupCntW::new(self, 0) + } + #[doc = "Bit 3 - Launch SLP mode in analog block"] + #[inline(always)] + #[must_use] + pub fn cntstrt(&mut self) -> CntstrtW { + CntstrtW::new(self, 3) + } +} +#[doc = "Wakeup Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wakeup_cnt::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wakeup_cnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WakeupCntSpec; +impl crate::RegisterSpec for WakeupCntSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wakeup_cnt::R`](R) reader structure"] +impl crate::Readable for WakeupCntSpec {} +#[doc = "`write(|w| ..)` method takes [`wakeup_cnt::W`](W) writer structure"] +impl crate::Writable for WakeupCntSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WAKEUP_CNT to value 0x07"] +impl crate::Resettable for WakeupCntSpec { + const RESET_VALUE: u32 = 0x07; +} diff --git a/va416xx/src/tim0.rs b/va416xx/src/tim0.rs new file mode 100644 index 0000000..2423944 --- /dev/null +++ b/va416xx/src/tim0.rs @@ -0,0 +1,142 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + ctrl: Ctrl, + rst_value: RstValue, + cnt_value: CntValue, + enable: Enable, + csd_ctrl: CsdCtrl, + cascade0: Cascade0, + cascade1: Cascade1, + cascade2: Cascade2, + _reserved_8_pwm_value: [u8; 0x04], + pwmb_value: PwmbValue, + _reserved10: [u8; 0x03d4], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x04 - The value that counter start from after reaching 0."] + #[inline(always)] + pub const fn rst_value(&self) -> &RstValue { + &self.rst_value + } + #[doc = "0x08 - The current value of the counter"] + #[inline(always)] + pub const fn cnt_value(&self) -> &CntValue { + &self.cnt_value + } + #[doc = "0x0c - Alternate access to the Counter ENABLE bit in the CTRL Register"] + #[inline(always)] + pub const fn enable(&self) -> &Enable { + &self.enable + } + #[doc = "0x10 - The Cascade Control Register. Controls the counter external enable signals"] + #[inline(always)] + pub const fn csd_ctrl(&self) -> &CsdCtrl { + &self.csd_ctrl + } + #[doc = "0x14 - Cascade Enable Selection"] + #[inline(always)] + pub const fn cascade0(&self) -> &Cascade0 { + &self.cascade0 + } + #[doc = "0x18 - Cascade Enable Selection"] + #[inline(always)] + pub const fn cascade1(&self) -> &Cascade1 { + &self.cascade1 + } + #[doc = "0x1c - Cascade Enable Selection"] + #[inline(always)] + pub const fn cascade2(&self) -> &Cascade2 { + &self.cascade2 + } + #[doc = "0x20 - The Pulse Width Modulation ValueA"] + #[inline(always)] + pub const fn pwma_value(&self) -> &PwmaValue { + unsafe { &*(self as *const Self).cast::().add(32).cast() } + } + #[doc = "0x20 - The Pulse Width Modulation Value"] + #[inline(always)] + pub const fn pwm_value(&self) -> &PwmValue { + unsafe { &*(self as *const Self).cast::().add(32).cast() } + } + #[doc = "0x24 - The Pulse Width Modulation ValueB"] + #[inline(always)] + pub const fn pwmb_value(&self) -> &PwmbValue { + &self.pwmb_value + } + #[doc = "0x3fc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] +module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "RST_VALUE (rw) register accessor: The value that counter start from after reaching 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_value`] +module"] +#[doc(alias = "RST_VALUE")] +pub type RstValue = crate::Reg; +#[doc = "The value that counter start from after reaching 0."] +pub mod rst_value; +#[doc = "CNT_VALUE (rw) register accessor: The current value of the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cnt_value`] +module"] +#[doc(alias = "CNT_VALUE")] +pub type CntValue = crate::Reg; +#[doc = "The current value of the counter"] +pub mod cnt_value; +#[doc = "ENABLE (rw) register accessor: Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] +module"] +#[doc(alias = "ENABLE")] +pub type Enable = crate::Reg; +#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register"] +pub mod enable; +#[doc = "CSD_CTRL (rw) register accessor: The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csd_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csd_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csd_ctrl`] +module"] +#[doc(alias = "CSD_CTRL")] +pub type CsdCtrl = crate::Reg; +#[doc = "The Cascade Control Register. Controls the counter external enable signals"] +pub mod csd_ctrl; +#[doc = "CASCADE0 (rw) register accessor: Cascade Enable Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cascade0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cascade0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cascade0`] +module"] +#[doc(alias = "CASCADE0")] +pub type Cascade0 = crate::Reg; +#[doc = "Cascade Enable Selection"] +pub mod cascade0; +pub use cascade0 as cascade1; +pub use cascade0 as cascade2; +pub use Cascade0 as Cascade1; +pub use Cascade0 as Cascade2; +#[doc = "PWM_VALUE (rw) register accessor: The Pulse Width Modulation Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_value`] +module"] +#[doc(alias = "PWM_VALUE")] +pub type PwmValue = crate::Reg; +#[doc = "The Pulse Width Modulation Value"] +pub mod pwm_value; +#[doc = "PWMA_VALUE (rw) register accessor: The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwma_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwma_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwma_value`] +module"] +#[doc(alias = "PWMA_VALUE")] +pub type PwmaValue = crate::Reg; +#[doc = "The Pulse Width Modulation ValueA"] +pub mod pwma_value; +#[doc = "PWMB_VALUE (rw) register accessor: The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmb_value::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmb_value::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmb_value`] +module"] +#[doc(alias = "PWMB_VALUE")] +pub type PwmbValue = crate::Reg; +#[doc = "The Pulse Width Modulation ValueB"] +pub mod pwmb_value; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/tim0/cascade0.rs b/va416xx/src/tim0/cascade0.rs new file mode 100644 index 0000000..984dd73 --- /dev/null +++ b/va416xx/src/tim0/cascade0.rs @@ -0,0 +1,40 @@ +#[doc = "Register `CASCADE0` reader"] +pub type R = crate::R; +#[doc = "Register `CASCADE0` writer"] +pub type W = crate::W; +#[doc = "Field `CASSEL` reader - Cascade Selection"] +pub type CasselR = crate::FieldReader; +#[doc = "Field `CASSEL` writer - Cascade Selection"] +pub type CasselW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + pub fn cassel(&self) -> CasselR { + CasselR::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Cascade Selection"] + #[inline(always)] + #[must_use] + pub fn cassel(&mut self) -> CasselW { + CasselW::new(self, 0) + } +} +#[doc = "Cascade Enable Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cascade0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cascade0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Cascade0Spec; +impl crate::RegisterSpec for Cascade0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cascade0::R`](R) reader structure"] +impl crate::Readable for Cascade0Spec {} +#[doc = "`write(|w| ..)` method takes [`cascade0::W`](W) writer structure"] +impl crate::Writable for Cascade0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CASCADE0 to value 0"] +impl crate::Resettable for Cascade0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/tim0/cnt_value.rs b/va416xx/src/tim0/cnt_value.rs new file mode 100644 index 0000000..f5ee38a --- /dev/null +++ b/va416xx/src/tim0/cnt_value.rs @@ -0,0 +1,27 @@ +#[doc = "Register `CNT_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `CNT_VALUE` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The current value of the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CntValueSpec; +impl crate::RegisterSpec for CntValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`cnt_value::R`](R) reader structure"] +impl crate::Readable for CntValueSpec {} +#[doc = "`write(|w| ..)` method takes [`cnt_value::W`](W) writer structure"] +impl crate::Writable for CntValueSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CNT_VALUE to value 0"] +impl crate::Resettable for CntValueSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/tim0/csd_ctrl.rs b/va416xx/src/tim0/csd_ctrl.rs new file mode 100644 index 0000000..d7827ed --- /dev/null +++ b/va416xx/src/tim0/csd_ctrl.rs @@ -0,0 +1,175 @@ +#[doc = "Register `CSD_CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CSD_CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `CSDEN0` reader - Cascade 0 Enable"] +pub type Csden0R = crate::BitReader; +#[doc = "Field `CSDEN0` writer - Cascade 0 Enable"] +pub type Csden0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDINV0` reader - Cascade 0 Invert"] +pub type Csdinv0R = crate::BitReader; +#[doc = "Field `CSDINV0` writer - Cascade 0 Invert"] +pub type Csdinv0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDEN1` reader - Cascade 1 Enable"] +pub type Csden1R = crate::BitReader; +#[doc = "Field `CSDEN1` writer - Cascade 1 Enable"] +pub type Csden1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDINV1` reader - Cascade 1 Invert"] +pub type Csdinv1R = crate::BitReader; +#[doc = "Field `CSDINV1` writer - Cascade 1 Invert"] +pub type Csdinv1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DCASOP` reader - Dual Cascade Operation (0:AND, 1:OR)"] +pub type DcasopR = crate::BitReader; +#[doc = "Field `DCASOP` writer - Dual Cascade Operation (0:AND, 1:OR)"] +pub type DcasopW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDTRG0` reader - Cascade 0 Enabled as Trigger"] +pub type Csdtrg0R = crate::BitReader; +#[doc = "Field `CSDTRG0` writer - Cascade 0 Enabled as Trigger"] +pub type Csdtrg0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDTRG1` reader - Cascade 1 Enabled as Trigger"] +pub type Csdtrg1R = crate::BitReader; +#[doc = "Field `CSDTRG1` writer - Cascade 1 Enabled as Trigger"] +pub type Csdtrg1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDEN2` reader - Cascade 2 Enable"] +pub type Csden2R = crate::BitReader; +#[doc = "Field `CSDEN2` writer - Cascade 2 Enable"] +pub type Csden2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDINV2` reader - Cascade 2 Invert"] +pub type Csdinv2R = crate::BitReader; +#[doc = "Field `CSDINV2` writer - Cascade 2 Invert"] +pub type Csdinv2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CSDTRG2` reader - Cascade 2 Trigger mode"] +pub type Csdtrg2R = crate::BitReader; +#[doc = "Field `CSDTRG2` writer - Cascade 2 Trigger mode"] +pub type Csdtrg2W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Cascade 0 Enable"] + #[inline(always)] + pub fn csden0(&self) -> Csden0R { + Csden0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Cascade 0 Invert"] + #[inline(always)] + pub fn csdinv0(&self) -> Csdinv0R { + Csdinv0R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Cascade 1 Enable"] + #[inline(always)] + pub fn csden1(&self) -> Csden1R { + Csden1R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Cascade 1 Invert"] + #[inline(always)] + pub fn csdinv1(&self) -> Csdinv1R { + Csdinv1R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"] + #[inline(always)] + pub fn dcasop(&self) -> DcasopR { + DcasopR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg0(&self) -> Csdtrg0R { + Csdtrg0R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"] + #[inline(always)] + pub fn csdtrg1(&self) -> Csdtrg1R { + Csdtrg1R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Cascade 2 Enable"] + #[inline(always)] + pub fn csden2(&self) -> Csden2R { + Csden2R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Cascade 2 Invert"] + #[inline(always)] + pub fn csdinv2(&self) -> Csdinv2R { + Csdinv2R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Cascade 2 Trigger mode"] + #[inline(always)] + pub fn csdtrg2(&self) -> Csdtrg2R { + Csdtrg2R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Cascade 0 Enable"] + #[inline(always)] + #[must_use] + pub fn csden0(&mut self) -> Csden0W { + Csden0W::new(self, 0) + } + #[doc = "Bit 1 - Cascade 0 Invert"] + #[inline(always)] + #[must_use] + pub fn csdinv0(&mut self) -> Csdinv0W { + Csdinv0W::new(self, 1) + } + #[doc = "Bit 2 - Cascade 1 Enable"] + #[inline(always)] + #[must_use] + pub fn csden1(&mut self) -> Csden1W { + Csden1W::new(self, 2) + } + #[doc = "Bit 3 - Cascade 1 Invert"] + #[inline(always)] + #[must_use] + pub fn csdinv1(&mut self) -> Csdinv1W { + Csdinv1W::new(self, 3) + } + #[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"] + #[inline(always)] + #[must_use] + pub fn dcasop(&mut self) -> DcasopW { + DcasopW::new(self, 4) + } + #[doc = "Bit 6 - Cascade 0 Enabled as Trigger"] + #[inline(always)] + #[must_use] + pub fn csdtrg0(&mut self) -> Csdtrg0W { + Csdtrg0W::new(self, 6) + } + #[doc = "Bit 7 - Cascade 1 Enabled as Trigger"] + #[inline(always)] + #[must_use] + pub fn csdtrg1(&mut self) -> Csdtrg1W { + Csdtrg1W::new(self, 7) + } + #[doc = "Bit 8 - Cascade 2 Enable"] + #[inline(always)] + #[must_use] + pub fn csden2(&mut self) -> Csden2W { + Csden2W::new(self, 8) + } + #[doc = "Bit 9 - Cascade 2 Invert"] + #[inline(always)] + #[must_use] + pub fn csdinv2(&mut self) -> Csdinv2W { + Csdinv2W::new(self, 9) + } + #[doc = "Bit 10 - Cascade 2 Trigger mode"] + #[inline(always)] + #[must_use] + pub fn csdtrg2(&mut self) -> Csdtrg2W { + Csdtrg2W::new(self, 10) + } +} +#[doc = "The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csd_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csd_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CsdCtrlSpec; +impl crate::RegisterSpec for CsdCtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`csd_ctrl::R`](R) reader structure"] +impl crate::Readable for CsdCtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`csd_ctrl::W`](W) writer structure"] +impl crate::Writable for CsdCtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CSD_CTRL to value 0"] +impl crate::Resettable for CsdCtrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/tim0/ctrl.rs b/va416xx/src/tim0/ctrl.rs new file mode 100644 index 0000000..32b2b66 --- /dev/null +++ b/va416xx/src/tim0/ctrl.rs @@ -0,0 +1,258 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - Counter Enable"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Counter Enable"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `ACTIVE` reader - Counter Active"] +pub type ActiveR = crate::BitReader; +#[doc = "Field `AUTO_DISABLE` reader - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] +pub type AutoDisableR = crate::BitReader; +#[doc = "Field `AUTO_DISABLE` writer - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] +pub type AutoDisableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTO_DEACTIVATE` reader - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] +pub type AutoDeactivateR = crate::BitReader; +#[doc = "Field `AUTO_DEACTIVATE` writer - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] +pub type AutoDeactivateW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_ENB` reader - Interrupt Enable"] +pub type IrqEnbR = crate::BitReader; +#[doc = "Field `IRQ_ENB` writer - Interrupt Enable"] +pub type IrqEnbW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Counter Status Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum StatusSel { + #[doc = "0: Single cycle pulse when the counter reaches 0"] + Done = 0, + #[doc = "1: Returns the counter ACTIVE bit"] + Active = 1, + #[doc = "2: Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + Toggle = 2, + #[doc = "3: Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + Pwma = 3, + #[doc = "4: Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + Pwmb = 4, + #[doc = "5: Returns the counter ENABLED bit"] + Enabled = 5, + #[doc = "6: Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + PwmaActive = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: StatusSel) -> Self { + variant as _ + } +} +impl crate::FieldSpec for StatusSel { + type Ux = u8; +} +impl crate::IsEnum for StatusSel {} +#[doc = "Field `STATUS_SEL` reader - Counter Status Selection"] +pub type StatusSelR = crate::FieldReader; +impl StatusSelR { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub const fn variant(&self) -> Option { + match self.bits { + 0 => Some(StatusSel::Done), + 1 => Some(StatusSel::Active), + 2 => Some(StatusSel::Toggle), + 3 => Some(StatusSel::Pwma), + 4 => Some(StatusSel::Pwmb), + 5 => Some(StatusSel::Enabled), + 6 => Some(StatusSel::PwmaActive), + _ => None, + } + } + #[doc = "Single cycle pulse when the counter reaches 0"] + #[inline(always)] + pub fn is_done(&self) -> bool { + *self == StatusSel::Done + } + #[doc = "Returns the counter ACTIVE bit"] + #[inline(always)] + pub fn is_active(&self) -> bool { + *self == StatusSel::Active + } + #[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + *self == StatusSel::Toggle + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + #[inline(always)] + pub fn is_pwma(&self) -> bool { + *self == StatusSel::Pwma + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + #[inline(always)] + pub fn is_pwmb(&self) -> bool { + *self == StatusSel::Pwmb + } + #[doc = "Returns the counter ENABLED bit"] + #[inline(always)] + pub fn is_enabled(&self) -> bool { + *self == StatusSel::Enabled + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + #[inline(always)] + pub fn is_pwma_active(&self) -> bool { + *self == StatusSel::PwmaActive + } +} +#[doc = "Field `STATUS_SEL` writer - Counter Status Selection"] +pub type StatusSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, StatusSel>; +impl<'a, REG> StatusSelW<'a, REG> +where + REG: crate::Writable + crate::RegisterSpec, + REG::Ux: From, +{ + #[doc = "Single cycle pulse when the counter reaches 0"] + #[inline(always)] + pub fn done(self) -> &'a mut crate::W { + self.variant(StatusSel::Done) + } + #[doc = "Returns the counter ACTIVE bit"] + #[inline(always)] + pub fn active(self) -> &'a mut crate::W { + self.variant(StatusSel::Active) + } + #[doc = "Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output."] + #[inline(always)] + pub fn toggle(self) -> &'a mut crate::W { + self.variant(StatusSel::Toggle) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"] + #[inline(always)] + pub fn pwma(self) -> &'a mut crate::W { + self.variant(StatusSel::Pwma) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"] + #[inline(always)] + pub fn pwmb(self) -> &'a mut crate::W { + self.variant(StatusSel::Pwmb) + } + #[doc = "Returns the counter ENABLED bit"] + #[inline(always)] + pub fn enabled(self) -> &'a mut crate::W { + self.variant(StatusSel::Enabled) + } + #[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"] + #[inline(always)] + pub fn pwma_active(self) -> &'a mut crate::W { + self.variant(StatusSel::PwmaActive) + } +} +#[doc = "Field `STATUS_INV` reader - Invert the Output Status"] +pub type StatusInvR = crate::BitReader; +#[doc = "Field `STATUS_INV` writer - Invert the Output Status"] +pub type StatusInvW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `REQ_STOP` reader - Stop Request"] +pub type ReqStopR = crate::BitReader; +#[doc = "Field `REQ_STOP` writer - Stop Request"] +pub type ReqStopW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Counter Active"] + #[inline(always)] + pub fn active(&self) -> ActiveR { + ActiveR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_disable(&self) -> AutoDisableR { + AutoDisableR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] + #[inline(always)] + pub fn auto_deactivate(&self) -> AutoDeactivateR { + AutoDeactivateR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Interrupt Enable"] + #[inline(always)] + pub fn irq_enb(&self) -> IrqEnbR { + IrqEnbR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:7 - Counter Status Selection"] + #[inline(always)] + pub fn status_sel(&self) -> StatusSelR { + StatusSelR::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bit 8 - Invert the Output Status"] + #[inline(always)] + pub fn status_inv(&self) -> StatusInvR { + StatusInvR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Stop Request"] + #[inline(always)] + pub fn req_stop(&self) -> ReqStopR { + ReqStopR::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 0) + } + #[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"] + #[inline(always)] + #[must_use] + pub fn auto_disable(&mut self) -> AutoDisableW { + AutoDisableW::new(self, 2) + } + #[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"] + #[inline(always)] + #[must_use] + pub fn auto_deactivate(&mut self) -> AutoDeactivateW { + AutoDeactivateW::new(self, 3) + } + #[doc = "Bit 4 - Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn irq_enb(&mut self) -> IrqEnbW { + IrqEnbW::new(self, 4) + } + #[doc = "Bits 5:7 - Counter Status Selection"] + #[inline(always)] + #[must_use] + pub fn status_sel(&mut self) -> StatusSelW { + StatusSelW::new(self, 5) + } + #[doc = "Bit 8 - Invert the Output Status"] + #[inline(always)] + #[must_use] + pub fn status_inv(&mut self) -> StatusInvW { + StatusInvW::new(self, 8) + } + #[doc = "Bit 9 - Stop Request"] + #[inline(always)] + #[must_use] + pub fn req_stop(&mut self) -> ReqStopW { + ReqStopW::new(self, 9) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/tim0/enable.rs b/va416xx/src/tim0/enable.rs new file mode 100644 index 0000000..2064cab --- /dev/null +++ b/va416xx/src/tim0/enable.rs @@ -0,0 +1,40 @@ +#[doc = "Register `ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `ENABLE` reader - Counter Enable"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Counter Enable"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Counter Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 0) + } +} +#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EnableSpec; +impl crate::RegisterSpec for EnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`enable::R`](R) reader structure"] +impl crate::Readable for EnableSpec {} +#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"] +impl crate::Writable for EnableSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for EnableSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/tim0/perid.rs b/va416xx/src/tim0/perid.rs new file mode 100644 index 0000000..9266a0a --- /dev/null +++ b/va416xx/src/tim0/perid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0211_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0211_07e9; +} diff --git a/va416xx/src/tim0/pwm_value.rs b/va416xx/src/tim0/pwm_value.rs new file mode 100644 index 0000000..b3b1480 --- /dev/null +++ b/va416xx/src/tim0/pwm_value.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PWM_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `PWM_VALUE` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The Pulse Width Modulation Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmValueSpec; +impl crate::RegisterSpec for PwmValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwm_value::R`](R) reader structure"] +impl crate::Readable for PwmValueSpec {} +#[doc = "`write(|w| ..)` method takes [`pwm_value::W`](W) writer structure"] +impl crate::Writable for PwmValueSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PWM_VALUE to value 0"] +impl crate::Resettable for PwmValueSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/tim0/pwma_value.rs b/va416xx/src/tim0/pwma_value.rs new file mode 100644 index 0000000..ec26532 --- /dev/null +++ b/va416xx/src/tim0/pwma_value.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PWMA_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `PWMA_VALUE` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwma_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwma_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmaValueSpec; +impl crate::RegisterSpec for PwmaValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwma_value::R`](R) reader structure"] +impl crate::Readable for PwmaValueSpec {} +#[doc = "`write(|w| ..)` method takes [`pwma_value::W`](W) writer structure"] +impl crate::Writable for PwmaValueSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PWMA_VALUE to value 0"] +impl crate::Resettable for PwmaValueSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/tim0/pwmb_value.rs b/va416xx/src/tim0/pwmb_value.rs new file mode 100644 index 0000000..587cb50 --- /dev/null +++ b/va416xx/src/tim0/pwmb_value.rs @@ -0,0 +1,27 @@ +#[doc = "Register `PWMB_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `PWMB_VALUE` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmb_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmb_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PwmbValueSpec; +impl crate::RegisterSpec for PwmbValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`pwmb_value::R`](R) reader structure"] +impl crate::Readable for PwmbValueSpec {} +#[doc = "`write(|w| ..)` method takes [`pwmb_value::W`](W) writer structure"] +impl crate::Writable for PwmbValueSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets PWMB_VALUE to value 0"] +impl crate::Resettable for PwmbValueSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/tim0/rst_value.rs b/va416xx/src/tim0/rst_value.rs new file mode 100644 index 0000000..2dfa5b4 --- /dev/null +++ b/va416xx/src/tim0/rst_value.rs @@ -0,0 +1,27 @@ +#[doc = "Register `RST_VALUE` reader"] +pub type R = crate::R; +#[doc = "Register `RST_VALUE` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "The value that counter start from after reaching 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RstValueSpec; +impl crate::RegisterSpec for RstValueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_value::R`](R) reader structure"] +impl crate::Readable for RstValueSpec {} +#[doc = "`write(|w| ..)` method takes [`rst_value::W`](W) writer structure"] +impl crate::Writable for RstValueSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RST_VALUE to value 0"] +impl crate::Resettable for RstValueSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng.rs b/va416xx/src/trng.rs new file mode 100644 index 0000000..c748ffd --- /dev/null +++ b/va416xx/src/trng.rs @@ -0,0 +1,234 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + _reserved0: [u8; 0x0100], + imr: Imr, + isr: Isr, + icr: Icr, + config: Config, + valid: Valid, + ehr_data0: EhrData0, + ehr_data1: EhrData1, + ehr_data2: EhrData2, + ehr_data3: EhrData3, + ehr_data4: EhrData4, + ehr_data5: EhrData5, + rnd_source_enable: RndSourceEnable, + sample_cnt1: SampleCnt1, + autocorr_statistic: AutocorrStatistic, + debug_control: DebugControl, + _reserved15: [u8; 0x04], + sw_reset: SwReset, + _reserved16: [u8; 0x74], + busy: Busy, + rst_bits_counter: RstBitsCounter, + _reserved18: [u8; 0x20], + bist_cntr0: BistCntr0, + bist_cntr1: BistCntr1, + bist_cntr2: BistCntr2, +} +impl RegisterBlock { + #[doc = "0x100 - Interrupt Mask Register"] + #[inline(always)] + pub const fn imr(&self) -> &Imr { + &self.imr + } + #[doc = "0x104 - Interrupt Status Register"] + #[inline(always)] + pub const fn isr(&self) -> &Isr { + &self.isr + } + #[doc = "0x108 - Interrupt Clear Register"] + #[inline(always)] + pub const fn icr(&self) -> &Icr { + &self.icr + } + #[doc = "0x10c - Configuration Register"] + #[inline(always)] + pub const fn config(&self) -> &Config { + &self.config + } + #[doc = "0x110 - Valid Register"] + #[inline(always)] + pub const fn valid(&self) -> &Valid { + &self.valid + } + #[doc = "0x114 - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data0(&self) -> &EhrData0 { + &self.ehr_data0 + } + #[doc = "0x118 - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data1(&self) -> &EhrData1 { + &self.ehr_data1 + } + #[doc = "0x11c - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data2(&self) -> &EhrData2 { + &self.ehr_data2 + } + #[doc = "0x120 - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data3(&self) -> &EhrData3 { + &self.ehr_data3 + } + #[doc = "0x124 - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data4(&self) -> &EhrData4 { + &self.ehr_data4 + } + #[doc = "0x128 - Entropy Holding Register Data Register"] + #[inline(always)] + pub const fn ehr_data5(&self) -> &EhrData5 { + &self.ehr_data5 + } + #[doc = "0x12c - Random Source Enable Register"] + #[inline(always)] + pub const fn rnd_source_enable(&self) -> &RndSourceEnable { + &self.rnd_source_enable + } + #[doc = "0x130 - Section TBD"] + #[inline(always)] + pub const fn sample_cnt1(&self) -> &SampleCnt1 { + &self.sample_cnt1 + } + #[doc = "0x134 - Auto-correlator Statistic Register"] + #[inline(always)] + pub const fn autocorr_statistic(&self) -> &AutocorrStatistic { + &self.autocorr_statistic + } + #[doc = "0x138 - Section TBD"] + #[inline(always)] + pub const fn debug_control(&self) -> &DebugControl { + &self.debug_control + } + #[doc = "0x140 - Reset Register"] + #[inline(always)] + pub const fn sw_reset(&self) -> &SwReset { + &self.sw_reset + } + #[doc = "0x1b8 - Busy Register"] + #[inline(always)] + pub const fn busy(&self) -> &Busy { + &self.busy + } + #[doc = "0x1bc - Reset Bits Counter Register"] + #[inline(always)] + pub const fn rst_bits_counter(&self) -> &RstBitsCounter { + &self.rst_bits_counter + } + #[doc = "0x1e0 - BIST Counter Register"] + #[inline(always)] + pub const fn bist_cntr0(&self) -> &BistCntr0 { + &self.bist_cntr0 + } + #[doc = "0x1e4 - BIST Counter Register"] + #[inline(always)] + pub const fn bist_cntr1(&self) -> &BistCntr1 { + &self.bist_cntr1 + } + #[doc = "0x1e8 - BIST Counter Register"] + #[inline(always)] + pub const fn bist_cntr2(&self) -> &BistCntr2 { + &self.bist_cntr2 + } +} +#[doc = "IMR (rw) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imr`] +module"] +#[doc(alias = "IMR")] +pub type Imr = crate::Reg; +#[doc = "Interrupt Mask Register"] +pub mod imr; +#[doc = "ISR (r) register accessor: Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@isr`] +module"] +#[doc(alias = "ISR")] +pub type Isr = crate::Reg; +#[doc = "Interrupt Status Register"] +pub mod isr; +#[doc = "ICR (rw) register accessor: Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@icr`] +module"] +#[doc(alias = "ICR")] +pub type Icr = crate::Reg; +#[doc = "Interrupt Clear Register"] +pub mod icr; +#[doc = "CONFIG (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@config`] +module"] +#[doc(alias = "CONFIG")] +pub type Config = crate::Reg; +#[doc = "Configuration Register"] +pub mod config; +#[doc = "VALID (r) register accessor: Valid Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`valid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@valid`] +module"] +#[doc(alias = "VALID")] +pub type Valid = crate::Reg; +#[doc = "Valid Register"] +pub mod valid; +#[doc = "EHR_DATA0 (r) register accessor: Entropy Holding Register Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ehr_data0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ehr_data0`] +module"] +#[doc(alias = "EHR_DATA0")] +pub type EhrData0 = crate::Reg; +#[doc = "Entropy Holding Register Data Register"] +pub mod ehr_data0; +pub use ehr_data0 as ehr_data1; +pub use ehr_data0 as ehr_data2; +pub use ehr_data0 as ehr_data3; +pub use ehr_data0 as ehr_data4; +pub use ehr_data0 as ehr_data5; +pub use EhrData0 as EhrData1; +pub use EhrData0 as EhrData2; +pub use EhrData0 as EhrData3; +pub use EhrData0 as EhrData4; +pub use EhrData0 as EhrData5; +#[doc = "RND_SOURCE_ENABLE (rw) register accessor: Random Source Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_source_enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_source_enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rnd_source_enable`] +module"] +#[doc(alias = "RND_SOURCE_ENABLE")] +pub type RndSourceEnable = crate::Reg; +#[doc = "Random Source Enable Register"] +pub mod rnd_source_enable; +#[doc = "SAMPLE_CNT1 (rw) register accessor: Section TBD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_cnt1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_cnt1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sample_cnt1`] +module"] +#[doc(alias = "SAMPLE_CNT1")] +pub type SampleCnt1 = crate::Reg; +#[doc = "Section TBD"] +pub mod sample_cnt1; +#[doc = "AUTOCORR_STATISTIC (rw) register accessor: Auto-correlator Statistic Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`autocorr_statistic::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`autocorr_statistic::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@autocorr_statistic`] +module"] +#[doc(alias = "AUTOCORR_STATISTIC")] +pub type AutocorrStatistic = crate::Reg; +#[doc = "Auto-correlator Statistic Register"] +pub mod autocorr_statistic; +#[doc = "DEBUG_CONTROL (rw) register accessor: Section TBD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@debug_control`] +module"] +#[doc(alias = "DEBUG_CONTROL")] +pub type DebugControl = crate::Reg; +#[doc = "Section TBD"] +pub mod debug_control; +#[doc = "SW_RESET (rw) register accessor: Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_reset::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_reset::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sw_reset`] +module"] +#[doc(alias = "SW_RESET")] +pub type SwReset = crate::Reg; +#[doc = "Reset Register"] +pub mod sw_reset; +#[doc = "BUSY (r) register accessor: Busy Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@busy`] +module"] +#[doc(alias = "BUSY")] +pub type Busy = crate::Reg; +#[doc = "Busy Register"] +pub mod busy; +#[doc = "RST_BITS_COUNTER (rw) register accessor: Reset Bits Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_bits_counter::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_bits_counter::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rst_bits_counter`] +module"] +#[doc(alias = "RST_BITS_COUNTER")] +pub type RstBitsCounter = crate::Reg; +#[doc = "Reset Bits Counter Register"] +pub mod rst_bits_counter; +#[doc = "BIST_CNTR0 (r) register accessor: BIST Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bist_cntr0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bist_cntr0`] +module"] +#[doc(alias = "BIST_CNTR0")] +pub type BistCntr0 = crate::Reg; +#[doc = "BIST Counter Register"] +pub mod bist_cntr0; +pub use bist_cntr0 as bist_cntr1; +pub use bist_cntr0 as bist_cntr2; +pub use BistCntr0 as BistCntr1; +pub use BistCntr0 as BistCntr2; diff --git a/va416xx/src/trng/autocorr_statistic.rs b/va416xx/src/trng/autocorr_statistic.rs new file mode 100644 index 0000000..e919aee --- /dev/null +++ b/va416xx/src/trng/autocorr_statistic.rs @@ -0,0 +1,55 @@ +#[doc = "Register `AUTOCORR_STATISTIC` reader"] +pub type R = crate::R; +#[doc = "Register `AUTOCORR_STATISTIC` writer"] +pub type W = crate::W; +#[doc = "Field `AUTOCORR_TRYS` reader - Count each time an autocorrelation test starts"] +pub type AutocorrTrysR = crate::FieldReader; +#[doc = "Field `AUTOCORR_TRYS` writer - Count each time an autocorrelation test starts"] +pub type AutocorrTrysW<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>; +#[doc = "Field `AUTOCORR_FAILS` reader - Count each time an autocorrelation test fails"] +pub type AutocorrFailsR = crate::FieldReader; +#[doc = "Field `AUTOCORR_FAILS` writer - Count each time an autocorrelation test fails"] +pub type AutocorrFailsW<'a, REG> = crate::FieldWriter<'a, REG, 8>; +impl R { + #[doc = "Bits 0:13 - Count each time an autocorrelation test starts"] + #[inline(always)] + pub fn autocorr_trys(&self) -> AutocorrTrysR { + AutocorrTrysR::new((self.bits & 0x3fff) as u16) + } + #[doc = "Bits 14:21 - Count each time an autocorrelation test fails"] + #[inline(always)] + pub fn autocorr_fails(&self) -> AutocorrFailsR { + AutocorrFailsR::new(((self.bits >> 14) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:13 - Count each time an autocorrelation test starts"] + #[inline(always)] + #[must_use] + pub fn autocorr_trys(&mut self) -> AutocorrTrysW { + AutocorrTrysW::new(self, 0) + } + #[doc = "Bits 14:21 - Count each time an autocorrelation test fails"] + #[inline(always)] + #[must_use] + pub fn autocorr_fails(&mut self) -> AutocorrFailsW { + AutocorrFailsW::new(self, 14) + } +} +#[doc = "Auto-correlator Statistic Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`autocorr_statistic::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`autocorr_statistic::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct AutocorrStatisticSpec; +impl crate::RegisterSpec for AutocorrStatisticSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`autocorr_statistic::R`](R) reader structure"] +impl crate::Readable for AutocorrStatisticSpec {} +#[doc = "`write(|w| ..)` method takes [`autocorr_statistic::W`](W) writer structure"] +impl crate::Writable for AutocorrStatisticSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets AUTOCORR_STATISTIC to value 0"] +impl crate::Resettable for AutocorrStatisticSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/bist_cntr0.rs b/va416xx/src/trng/bist_cntr0.rs new file mode 100644 index 0000000..36bca68 --- /dev/null +++ b/va416xx/src/trng/bist_cntr0.rs @@ -0,0 +1,22 @@ +#[doc = "Register `BIST_CNTR0` reader"] +pub type R = crate::R; +#[doc = "Field `ROSC_CNTR_VAL` reader - Returns the results of the TRNG BIST counter"] +pub type RoscCntrValR = crate::FieldReader; +impl R { + #[doc = "Bits 0:21 - Returns the results of the TRNG BIST counter"] + #[inline(always)] + pub fn rosc_cntr_val(&self) -> RoscCntrValR { + RoscCntrValR::new(self.bits & 0x003f_ffff) + } +} +#[doc = "BIST Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bist_cntr0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BistCntr0Spec; +impl crate::RegisterSpec for BistCntr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`bist_cntr0::R`](R) reader structure"] +impl crate::Readable for BistCntr0Spec {} +#[doc = "`reset()` method sets BIST_CNTR0 to value 0"] +impl crate::Resettable for BistCntr0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/busy.rs b/va416xx/src/trng/busy.rs new file mode 100644 index 0000000..a34661c --- /dev/null +++ b/va416xx/src/trng/busy.rs @@ -0,0 +1,22 @@ +#[doc = "Register `BUSY` reader"] +pub type R = crate::R; +#[doc = "Field `BUSY` reader - Reflects the status of the rng_busy signal"] +pub type BusyR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Reflects the status of the rng_busy signal"] + #[inline(always)] + pub fn busy(&self) -> BusyR { + BusyR::new((self.bits & 1) != 0) + } +} +#[doc = "Busy Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`busy::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct BusySpec; +impl crate::RegisterSpec for BusySpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`busy::R`](R) reader structure"] +impl crate::Readable for BusySpec {} +#[doc = "`reset()` method sets BUSY to value 0"] +impl crate::Resettable for BusySpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/config.rs b/va416xx/src/trng/config.rs new file mode 100644 index 0000000..83a2884 --- /dev/null +++ b/va416xx/src/trng/config.rs @@ -0,0 +1,40 @@ +#[doc = "Register `CONFIG` reader"] +pub type R = crate::R; +#[doc = "Register `CONFIG` writer"] +pub type W = crate::W; +#[doc = "Field `RND_SRC_SEL` reader - Selects the number of inverters (out of four possible selections) in the ring oscillator"] +pub type RndSrcSelR = crate::FieldReader; +#[doc = "Field `RND_SRC_SEL` writer - Selects the number of inverters (out of four possible selections) in the ring oscillator"] +pub type RndSrcSelW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +impl R { + #[doc = "Bits 0:1 - Selects the number of inverters (out of four possible selections) in the ring oscillator"] + #[inline(always)] + pub fn rnd_src_sel(&self) -> RndSrcSelR { + RndSrcSelR::new((self.bits & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Selects the number of inverters (out of four possible selections) in the ring oscillator"] + #[inline(always)] + #[must_use] + pub fn rnd_src_sel(&mut self) -> RndSrcSelW { + RndSrcSelW::new(self, 0) + } +} +#[doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ConfigSpec; +impl crate::RegisterSpec for ConfigSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`config::R`](R) reader structure"] +impl crate::Readable for ConfigSpec {} +#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"] +impl crate::Writable for ConfigSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CONFIG to value 0"] +impl crate::Resettable for ConfigSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/debug_control.rs b/va416xx/src/trng/debug_control.rs new file mode 100644 index 0000000..aed3a3f --- /dev/null +++ b/va416xx/src/trng/debug_control.rs @@ -0,0 +1,70 @@ +#[doc = "Register `DEBUG_CONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `DEBUG_CONTROL` writer"] +pub type W = crate::W; +#[doc = "Field `VNC_PYPASS` reader - The Von Neumann balancer is bypassed"] +pub type VncPypassR = crate::BitReader; +#[doc = "Field `VNC_PYPASS` writer - The Von Neumann balancer is bypassed"] +pub type VncPypassW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRNGT_BYPASS` reader - The CRNGT test in the TRNG is bypassed"] +pub type CrngtBypassR = crate::BitReader; +#[doc = "Field `CRNGT_BYPASS` writer - The CRNGT test in the TRNG is bypassed"] +pub type CrngtBypassW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTO_CORRELATE_BYPASS` reader - The autocorrelation test in the TRNG module is bypassed"] +pub type AutoCorrelateBypassR = crate::BitReader; +#[doc = "Field `AUTO_CORRELATE_BYPASS` writer - The autocorrelation test in the TRNG module is bypassed"] +pub type AutoCorrelateBypassW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 1 - The Von Neumann balancer is bypassed"] + #[inline(always)] + pub fn vnc_pypass(&self) -> VncPypassR { + VncPypassR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - The CRNGT test in the TRNG is bypassed"] + #[inline(always)] + pub fn crngt_bypass(&self) -> CrngtBypassR { + CrngtBypassR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - The autocorrelation test in the TRNG module is bypassed"] + #[inline(always)] + pub fn auto_correlate_bypass(&self) -> AutoCorrelateBypassR { + AutoCorrelateBypassR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - The Von Neumann balancer is bypassed"] + #[inline(always)] + #[must_use] + pub fn vnc_pypass(&mut self) -> VncPypassW { + VncPypassW::new(self, 1) + } + #[doc = "Bit 2 - The CRNGT test in the TRNG is bypassed"] + #[inline(always)] + #[must_use] + pub fn crngt_bypass(&mut self) -> CrngtBypassW { + CrngtBypassW::new(self, 2) + } + #[doc = "Bit 3 - The autocorrelation test in the TRNG module is bypassed"] + #[inline(always)] + #[must_use] + pub fn auto_correlate_bypass(&mut self) -> AutoCorrelateBypassW { + AutoCorrelateBypassW::new(self, 3) + } +} +#[doc = "Section TBD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`debug_control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`debug_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DebugControlSpec; +impl crate::RegisterSpec for DebugControlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`debug_control::R`](R) reader structure"] +impl crate::Readable for DebugControlSpec {} +#[doc = "`write(|w| ..)` method takes [`debug_control::W`](W) writer structure"] +impl crate::Writable for DebugControlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DEBUG_CONTROL to value 0"] +impl crate::Resettable for DebugControlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/ehr_data0.rs b/va416xx/src/trng/ehr_data0.rs new file mode 100644 index 0000000..1c6e91f --- /dev/null +++ b/va416xx/src/trng/ehr_data0.rs @@ -0,0 +1,22 @@ +#[doc = "Register `EHR_DATA0` reader"] +pub type R = crate::R; +#[doc = "Field `EHR_DATA` reader - 32 Bits of Entropy Holding Register"] +pub type EhrDataR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - 32 Bits of Entropy Holding Register"] + #[inline(always)] + pub fn ehr_data(&self) -> EhrDataR { + EhrDataR::new(self.bits) + } +} +#[doc = "Entropy Holding Register Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ehr_data0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EhrData0Spec; +impl crate::RegisterSpec for EhrData0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ehr_data0::R`](R) reader structure"] +impl crate::Readable for EhrData0Spec {} +#[doc = "`reset()` method sets EHR_DATA0 to value 0"] +impl crate::Resettable for EhrData0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/icr.rs b/va416xx/src/trng/icr.rs new file mode 100644 index 0000000..89ec323 --- /dev/null +++ b/va416xx/src/trng/icr.rs @@ -0,0 +1,89 @@ +#[doc = "Register `ICR` reader"] +pub type R = crate::R; +#[doc = "Register `ICR` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_VALID` reader - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] +registers have been read"] +pub type EhrValidR = crate::BitReader; +#[doc = "Field `EHR_VALID` writer - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] +registers have been read"] +pub type EhrValidW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOCORR_ERR` reader - Software cannot clear this bit. Only a TRNG reset can clear this bit"] +pub type AutocorrErrR = crate::BitReader; +#[doc = "Field `AUTOCORR_ERR` writer - Software cannot clear this bit. Only a TRNG reset can clear this bit"] +pub type AutocorrErrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRNGT_ERR` reader - Clear a Continuous Random Number Generation Testing (CRNGT) error"] +pub type CrngtErrR = crate::BitReader; +#[doc = "Field `CRNGT_ERR` writer - Clear a Continuous Random Number Generation Testing (CRNGT) error"] +pub type CrngtErrW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VN_ERR` reader - Clears a Von Neumann error"] +pub type VnErrR = crate::BitReader; +#[doc = "Field `VN_ERR` writer - Clears a Von Neumann error"] +pub type VnErrW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] +registers have been read"] + #[inline(always)] + pub fn ehr_valid(&self) -> EhrValidR { + EhrValidR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Software cannot clear this bit. Only a TRNG reset can clear this bit"] + #[inline(always)] + pub fn autocorr_err(&self) -> AutocorrErrR { + AutocorrErrR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Clear a Continuous Random Number Generation Testing (CRNGT) error"] + #[inline(always)] + pub fn crngt_err(&self) -> CrngtErrR { + CrngtErrR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Clears a Von Neumann error"] + #[inline(always)] + pub fn vn_err(&self) -> VnErrR { + VnErrR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Set to 1 after the EHR_DATA\\[0,1,2,3,4,5\\] +registers have been read"] + #[inline(always)] + #[must_use] + pub fn ehr_valid(&mut self) -> EhrValidW { + EhrValidW::new(self, 0) + } + #[doc = "Bit 1 - Software cannot clear this bit. Only a TRNG reset can clear this bit"] + #[inline(always)] + #[must_use] + pub fn autocorr_err(&mut self) -> AutocorrErrW { + AutocorrErrW::new(self, 1) + } + #[doc = "Bit 2 - Clear a Continuous Random Number Generation Testing (CRNGT) error"] + #[inline(always)] + #[must_use] + pub fn crngt_err(&mut self) -> CrngtErrW { + CrngtErrW::new(self, 2) + } + #[doc = "Bit 3 - Clears a Von Neumann error"] + #[inline(always)] + #[must_use] + pub fn vn_err(&mut self) -> VnErrW { + VnErrW::new(self, 3) + } +} +#[doc = "Interrupt Clear Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IcrSpec; +impl crate::RegisterSpec for IcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`icr::R`](R) reader structure"] +impl crate::Readable for IcrSpec {} +#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"] +impl crate::Writable for IcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ICR to value 0"] +impl crate::Resettable for IcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/imr.rs b/va416xx/src/trng/imr.rs new file mode 100644 index 0000000..b3137fa --- /dev/null +++ b/va416xx/src/trng/imr.rs @@ -0,0 +1,85 @@ +#[doc = "Register `IMR` reader"] +pub type R = crate::R; +#[doc = "Register `IMR` writer"] +pub type W = crate::W; +#[doc = "Field `EHR_VALID_INT_MASK` reader - Mask when the TRNG has collected 192 bits"] +pub type EhrValidIntMaskR = crate::BitReader; +#[doc = "Field `EHR_VALID_INT_MASK` writer - Mask when the TRNG has collected 192 bits"] +pub type EhrValidIntMaskW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOCORR_ERR_INT_MASK` reader - Mask the Autocorrelation error"] +pub type AutocorrErrIntMaskR = crate::BitReader; +#[doc = "Field `AUTOCORR_ERR_INT_MASK` writer - Mask the Autocorrelation error"] +pub type AutocorrErrIntMaskW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `CRNGT_ERR_INT_MASK` reader - Mask the CRNGT error"] +pub type CrngtErrIntMaskR = crate::BitReader; +#[doc = "Field `CRNGT_ERR_INT_MASK` writer - Mask the CRNGT error"] +pub type CrngtErrIntMaskW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `VN_ERR_INT_MASK` reader - Mask the Von Neumann error"] +pub type VnErrIntMaskR = crate::BitReader; +#[doc = "Field `VN_ERR_INT_MASK` writer - Mask the Von Neumann error"] +pub type VnErrIntMaskW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Mask when the TRNG has collected 192 bits"] + #[inline(always)] + pub fn ehr_valid_int_mask(&self) -> EhrValidIntMaskR { + EhrValidIntMaskR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Mask the Autocorrelation error"] + #[inline(always)] + pub fn autocorr_err_int_mask(&self) -> AutocorrErrIntMaskR { + AutocorrErrIntMaskR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Mask the CRNGT error"] + #[inline(always)] + pub fn crngt_err_int_mask(&self) -> CrngtErrIntMaskR { + CrngtErrIntMaskR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Mask the Von Neumann error"] + #[inline(always)] + pub fn vn_err_int_mask(&self) -> VnErrIntMaskR { + VnErrIntMaskR::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Mask when the TRNG has collected 192 bits"] + #[inline(always)] + #[must_use] + pub fn ehr_valid_int_mask(&mut self) -> EhrValidIntMaskW { + EhrValidIntMaskW::new(self, 0) + } + #[doc = "Bit 1 - Mask the Autocorrelation error"] + #[inline(always)] + #[must_use] + pub fn autocorr_err_int_mask(&mut self) -> AutocorrErrIntMaskW { + AutocorrErrIntMaskW::new(self, 1) + } + #[doc = "Bit 2 - Mask the CRNGT error"] + #[inline(always)] + #[must_use] + pub fn crngt_err_int_mask(&mut self) -> CrngtErrIntMaskW { + CrngtErrIntMaskW::new(self, 2) + } + #[doc = "Bit 3 - Mask the Von Neumann error"] + #[inline(always)] + #[must_use] + pub fn vn_err_int_mask(&mut self) -> VnErrIntMaskW { + VnErrIntMaskW::new(self, 3) + } +} +#[doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ImrSpec; +impl crate::RegisterSpec for ImrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`imr::R`](R) reader structure"] +impl crate::Readable for ImrSpec {} +#[doc = "`write(|w| ..)` method takes [`imr::W`](W) writer structure"] +impl crate::Writable for ImrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IMR to value 0x0f"] +impl crate::Resettable for ImrSpec { + const RESET_VALUE: u32 = 0x0f; +} diff --git a/va416xx/src/trng/isr.rs b/va416xx/src/trng/isr.rs new file mode 100644 index 0000000..57bdab4 --- /dev/null +++ b/va416xx/src/trng/isr.rs @@ -0,0 +1,43 @@ +#[doc = "Register `ISR` reader"] +pub type R = crate::R; +#[doc = "Field `EHR_VALID` reader - 192 bits have been collected in the TRNG"] +pub type EhrValidR = crate::BitReader; +#[doc = "Field `AUTOCORR_ERR` reader - Indicates that the Autocorrelation test failed four times in a row"] +pub type AutocorrErrR = crate::BitReader; +#[doc = "Field `CRNGT_ERR` reader - Indicates a Continuous Random Number Generation Testing (CRNGT) error"] +pub type CrngtErrR = crate::BitReader; +#[doc = "Field `VN_ERR` reader - Indicates a Von Neumann error"] +pub type VnErrR = crate::BitReader; +impl R { + #[doc = "Bit 0 - 192 bits have been collected in the TRNG"] + #[inline(always)] + pub fn ehr_valid(&self) -> EhrValidR { + EhrValidR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Indicates that the Autocorrelation test failed four times in a row"] + #[inline(always)] + pub fn autocorr_err(&self) -> AutocorrErrR { + AutocorrErrR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Indicates a Continuous Random Number Generation Testing (CRNGT) error"] + #[inline(always)] + pub fn crngt_err(&self) -> CrngtErrR { + CrngtErrR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Indicates a Von Neumann error"] + #[inline(always)] + pub fn vn_err(&self) -> VnErrR { + VnErrR::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`isr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IsrSpec; +impl crate::RegisterSpec for IsrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`isr::R`](R) reader structure"] +impl crate::Readable for IsrSpec {} +#[doc = "`reset()` method sets ISR to value 0"] +impl crate::Resettable for IsrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/rnd_source_enable.rs b/va416xx/src/trng/rnd_source_enable.rs new file mode 100644 index 0000000..194e5e0 --- /dev/null +++ b/va416xx/src/trng/rnd_source_enable.rs @@ -0,0 +1,40 @@ +#[doc = "Register `RND_SOURCE_ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `RND_SOURCE_ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `RND_SRC_EN` reader - The entropy source, ring oscillator, is enabled"] +pub type RndSrcEnR = crate::BitReader; +#[doc = "Field `RND_SRC_EN` writer - The entropy source, ring oscillator, is enabled"] +pub type RndSrcEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - The entropy source, ring oscillator, is enabled"] + #[inline(always)] + pub fn rnd_src_en(&self) -> RndSrcEnR { + RndSrcEnR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - The entropy source, ring oscillator, is enabled"] + #[inline(always)] + #[must_use] + pub fn rnd_src_en(&mut self) -> RndSrcEnW { + RndSrcEnW::new(self, 0) + } +} +#[doc = "Random Source Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rnd_source_enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rnd_source_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RndSourceEnableSpec; +impl crate::RegisterSpec for RndSourceEnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rnd_source_enable::R`](R) reader structure"] +impl crate::Readable for RndSourceEnableSpec {} +#[doc = "`write(|w| ..)` method takes [`rnd_source_enable::W`](W) writer structure"] +impl crate::Writable for RndSourceEnableSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RND_SOURCE_ENABLE to value 0"] +impl crate::Resettable for RndSourceEnableSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/rst_bits_counter.rs b/va416xx/src/trng/rst_bits_counter.rs new file mode 100644 index 0000000..1ec18a0 --- /dev/null +++ b/va416xx/src/trng/rst_bits_counter.rs @@ -0,0 +1,40 @@ +#[doc = "Register `RST_BITS_COUNTER` reader"] +pub type R = crate::R; +#[doc = "Register `RST_BITS_COUNTER` writer"] +pub type W = crate::W; +#[doc = "Field `RST_BITS_COUNTER` reader - Writing any value to this bit resets the bits counter and TRNG valid registers"] +pub type RstBitsCounterR = crate::BitReader; +#[doc = "Field `RST_BITS_COUNTER` writer - Writing any value to this bit resets the bits counter and TRNG valid registers"] +pub type RstBitsCounterW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Writing any value to this bit resets the bits counter and TRNG valid registers"] + #[inline(always)] + pub fn rst_bits_counter(&self) -> RstBitsCounterR { + RstBitsCounterR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Writing any value to this bit resets the bits counter and TRNG valid registers"] + #[inline(always)] + #[must_use] + pub fn rst_bits_counter(&mut self) -> RstBitsCounterW { + RstBitsCounterW::new(self, 0) + } +} +#[doc = "Reset Bits Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_bits_counter::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_bits_counter::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RstBitsCounterSpec; +impl crate::RegisterSpec for RstBitsCounterSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rst_bits_counter::R`](R) reader structure"] +impl crate::Readable for RstBitsCounterSpec {} +#[doc = "`write(|w| ..)` method takes [`rst_bits_counter::W`](W) writer structure"] +impl crate::Writable for RstBitsCounterSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RST_BITS_COUNTER to value 0"] +impl crate::Resettable for RstBitsCounterSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/sample_cnt1.rs b/va416xx/src/trng/sample_cnt1.rs new file mode 100644 index 0000000..21e445e --- /dev/null +++ b/va416xx/src/trng/sample_cnt1.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SAMPLE_CNT1` reader"] +pub type R = crate::R; +#[doc = "Register `SAMPLE_CNT1` writer"] +pub type W = crate::W; +#[doc = "Field `SAMPLE_CNTR1` reader - Sets the number of clk cycles between two consecutive ring oscillator samples"] +pub type SampleCntr1R = crate::FieldReader; +#[doc = "Field `SAMPLE_CNTR1` writer - Sets the number of clk cycles between two consecutive ring oscillator samples"] +pub type SampleCntr1W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Sets the number of clk cycles between two consecutive ring oscillator samples"] + #[inline(always)] + pub fn sample_cntr1(&self) -> SampleCntr1R { + SampleCntr1R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Sets the number of clk cycles between two consecutive ring oscillator samples"] + #[inline(always)] + #[must_use] + pub fn sample_cntr1(&mut self) -> SampleCntr1W { + SampleCntr1W::new(self, 0) + } +} +#[doc = "Section TBD\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sample_cnt1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sample_cnt1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SampleCnt1Spec; +impl crate::RegisterSpec for SampleCnt1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sample_cnt1::R`](R) reader structure"] +impl crate::Readable for SampleCnt1Spec {} +#[doc = "`write(|w| ..)` method takes [`sample_cnt1::W`](W) writer structure"] +impl crate::Writable for SampleCnt1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SAMPLE_CNT1 to value 0xffff"] +impl crate::Resettable for SampleCnt1Spec { + const RESET_VALUE: u32 = 0xffff; +} diff --git a/va416xx/src/trng/sw_reset.rs b/va416xx/src/trng/sw_reset.rs new file mode 100644 index 0000000..585f61e --- /dev/null +++ b/va416xx/src/trng/sw_reset.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SW_RESET` reader"] +pub type R = crate::R; +#[doc = "Register `SW_RESET` writer"] +pub type W = crate::W; +#[doc = "Field `SW_RESET` reader - Writing 1 to this register causes an internal TRNG reset"] +pub type SwResetR = crate::BitReader; +#[doc = "Field `SW_RESET` writer - Writing 1 to this register causes an internal TRNG reset"] +pub type SwResetW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Writing 1 to this register causes an internal TRNG reset"] + #[inline(always)] + pub fn sw_reset(&self) -> SwResetR { + SwResetR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Writing 1 to this register causes an internal TRNG reset"] + #[inline(always)] + #[must_use] + pub fn sw_reset(&mut self) -> SwResetW { + SwResetW::new(self, 0) + } +} +#[doc = "Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sw_reset::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sw_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SwResetSpec; +impl crate::RegisterSpec for SwResetSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`sw_reset::R`](R) reader structure"] +impl crate::Readable for SwResetSpec {} +#[doc = "`write(|w| ..)` method takes [`sw_reset::W`](W) writer structure"] +impl crate::Writable for SwResetSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SW_RESET to value 0"] +impl crate::Resettable for SwResetSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/trng/valid.rs b/va416xx/src/trng/valid.rs new file mode 100644 index 0000000..770e5ed --- /dev/null +++ b/va416xx/src/trng/valid.rs @@ -0,0 +1,22 @@ +#[doc = "Register `VALID` reader"] +pub type R = crate::R; +#[doc = "Field `EHR_VALID` reader - Indicates that the collection of bits in the TRNG is complete"] +pub type EhrValidR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Indicates that the collection of bits in the TRNG is complete"] + #[inline(always)] + pub fn ehr_valid(&self) -> EhrValidR { + EhrValidR::new((self.bits & 1) != 0) + } +} +#[doc = "Valid Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`valid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ValidSpec; +impl crate::RegisterSpec for ValidSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`valid::R`](R) reader structure"] +impl crate::Readable for ValidSpec {} +#[doc = "`reset()` method sets VALID to value 0"] +impl crate::Resettable for ValidSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0.rs b/va416xx/src/uart0.rs new file mode 100644 index 0000000..71aa47b --- /dev/null +++ b/va416xx/src/uart0.rs @@ -0,0 +1,223 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + data: Data, + enable: Enable, + ctrl: Ctrl, + clkscale: Clkscale, + rxstatus: Rxstatus, + txstatus: Txstatus, + fifo_clr: FifoClr, + txbreak: Txbreak, + addr9: Addr9, + addr9mask: Addr9mask, + irq_enb: IrqEnb, + irq_raw: IrqRaw, + irq_end: IrqEnd, + irq_clr: IrqClr, + rxfifoirqtrg: Rxfifoirqtrg, + txfifoirqtrg: Txfifoirqtrg, + rxfifortstrg: Rxfifortstrg, + state: State, + _reserved18: [u8; 0x0fb4], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Data In/Out Register"] + #[inline(always)] + pub const fn data(&self) -> &Data { + &self.data + } + #[doc = "0x04 - Enable Register"] + #[inline(always)] + pub const fn enable(&self) -> &Enable { + &self.enable + } + #[doc = "0x08 - Control Register"] + #[inline(always)] + pub const fn ctrl(&self) -> &Ctrl { + &self.ctrl + } + #[doc = "0x0c - Clock Scale Register"] + #[inline(always)] + pub const fn clkscale(&self) -> &Clkscale { + &self.clkscale + } + #[doc = "0x10 - Status Register"] + #[inline(always)] + pub const fn rxstatus(&self) -> &Rxstatus { + &self.rxstatus + } + #[doc = "0x14 - Status Register"] + #[inline(always)] + pub const fn txstatus(&self) -> &Txstatus { + &self.txstatus + } + #[doc = "0x18 - Clear FIFO Register"] + #[inline(always)] + pub const fn fifo_clr(&self) -> &FifoClr { + &self.fifo_clr + } + #[doc = "0x1c - Break Transmit Register"] + #[inline(always)] + pub const fn txbreak(&self) -> &Txbreak { + &self.txbreak + } + #[doc = "0x20 - Address9 Register"] + #[inline(always)] + pub const fn addr9(&self) -> &Addr9 { + &self.addr9 + } + #[doc = "0x24 - Address9 Mask Register"] + #[inline(always)] + pub const fn addr9mask(&self) -> &Addr9mask { + &self.addr9mask + } + #[doc = "0x28 - IRQ Enable Register"] + #[inline(always)] + pub const fn irq_enb(&self) -> &IrqEnb { + &self.irq_enb + } + #[doc = "0x2c - IRQ Raw Status Register"] + #[inline(always)] + pub const fn irq_raw(&self) -> &IrqRaw { + &self.irq_raw + } + #[doc = "0x30 - IRQ Enabled Status Register"] + #[inline(always)] + pub const fn irq_end(&self) -> &IrqEnd { + &self.irq_end + } + #[doc = "0x34 - IRQ Clear Status Register"] + #[inline(always)] + pub const fn irq_clr(&self) -> &IrqClr { + &self.irq_clr + } + #[doc = "0x38 - Rx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn rxfifoirqtrg(&self) -> &Rxfifoirqtrg { + &self.rxfifoirqtrg + } + #[doc = "0x3c - Tx FIFO IRQ Trigger Level"] + #[inline(always)] + pub const fn txfifoirqtrg(&self) -> &Txfifoirqtrg { + &self.txfifoirqtrg + } + #[doc = "0x40 - Rx FIFO RTS Trigger Level"] + #[inline(always)] + pub const fn rxfifortstrg(&self) -> &Rxfifortstrg { + &self.rxfifortstrg + } + #[doc = "0x44 - Internal STATE of UART Controller"] + #[inline(always)] + pub const fn state(&self) -> &State { + &self.state + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "DATA (rw) register accessor: Data In/Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] +module"] +#[doc(alias = "DATA")] +pub type Data = crate::Reg; +#[doc = "Data In/Out Register"] +pub mod data; +#[doc = "ENABLE (rw) register accessor: Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@enable`] +module"] +#[doc(alias = "ENABLE")] +pub type Enable = crate::Reg; +#[doc = "Enable Register"] +pub mod enable; +#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] +module"] +#[doc(alias = "CTRL")] +pub type Ctrl = crate::Reg; +#[doc = "Control Register"] +pub mod ctrl; +#[doc = "CLKSCALE (rw) register accessor: Clock Scale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] +module"] +#[doc(alias = "CLKSCALE")] +pub type Clkscale = crate::Reg; +#[doc = "Clock Scale Register"] +pub mod clkscale; +#[doc = "RXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxstatus`] +module"] +#[doc(alias = "RXSTATUS")] +pub type Rxstatus = crate::Reg; +#[doc = "Status Register"] +pub mod rxstatus; +#[doc = "TXSTATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txstatus::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txstatus`] +module"] +#[doc(alias = "TXSTATUS")] +pub type Txstatus = crate::Reg; +#[doc = "Status Register"] +pub mod txstatus; +#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] +module"] +#[doc(alias = "FIFO_CLR")] +pub type FifoClr = crate::Reg; +#[doc = "Clear FIFO Register"] +pub mod fifo_clr; +#[doc = "TXBREAK (w) register accessor: Break Transmit Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbreak::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbreak`] +module"] +#[doc(alias = "TXBREAK")] +pub type Txbreak = crate::Reg; +#[doc = "Break Transmit Register"] +pub mod txbreak; +#[doc = "ADDR9 (rw) register accessor: Address9 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9`] +module"] +#[doc(alias = "ADDR9")] +pub type Addr9 = crate::Reg; +#[doc = "Address9 Register"] +pub mod addr9; +#[doc = "ADDR9MASK (rw) register accessor: Address9 Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr9mask`] +module"] +#[doc(alias = "ADDR9MASK")] +pub type Addr9mask = crate::Reg; +#[doc = "Address9 Mask Register"] +pub mod addr9mask; +#[doc = "IRQ_ENB (rw) register accessor: IRQ Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] +module"] +#[doc(alias = "IRQ_ENB")] +pub type IrqEnb = crate::Reg; +#[doc = "IRQ Enable Register"] +pub mod irq_enb; +pub use irq_enb as irq_raw; +pub use irq_enb as irq_end; +pub use irq_enb as irq_clr; +pub use IrqEnb as IrqRaw; +pub use IrqEnb as IrqEnd; +pub use IrqEnb as IrqClr; +#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] +module"] +#[doc(alias = "RXFIFOIRQTRG")] +pub type Rxfifoirqtrg = crate::Reg; +#[doc = "Rx FIFO IRQ Trigger Level"] +pub mod rxfifoirqtrg; +#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] +module"] +#[doc(alias = "TXFIFOIRQTRG")] +pub type Txfifoirqtrg = crate::Reg; +#[doc = "Tx FIFO IRQ Trigger Level"] +pub mod txfifoirqtrg; +#[doc = "RXFIFORTSTRG (rw) register accessor: Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifortstrg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifortstrg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifortstrg`] +module"] +#[doc(alias = "RXFIFORTSTRG")] +pub type Rxfifortstrg = crate::Reg; +#[doc = "Rx FIFO RTS Trigger Level"] +pub mod rxfifortstrg; +#[doc = "STATE (r) register accessor: Internal STATE of UART Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] +module"] +#[doc(alias = "STATE")] +pub type State = crate::Reg; +#[doc = "Internal STATE of UART Controller"] +pub mod state; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/uart0/addr9.rs b/va416xx/src/uart0/addr9.rs new file mode 100644 index 0000000..bca4484 --- /dev/null +++ b/va416xx/src/uart0/addr9.rs @@ -0,0 +1,27 @@ +#[doc = "Register `ADDR9` reader"] +pub type R = crate::R; +#[doc = "Register `ADDR9` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Address9 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Addr9Spec; +impl crate::RegisterSpec for Addr9Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`addr9::R`](R) reader structure"] +impl crate::Readable for Addr9Spec {} +#[doc = "`write(|w| ..)` method takes [`addr9::W`](W) writer structure"] +impl crate::Writable for Addr9Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ADDR9 to value 0"] +impl crate::Resettable for Addr9Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/addr9mask.rs b/va416xx/src/uart0/addr9mask.rs new file mode 100644 index 0000000..f96e772 --- /dev/null +++ b/va416xx/src/uart0/addr9mask.rs @@ -0,0 +1,27 @@ +#[doc = "Register `ADDR9MASK` reader"] +pub type R = crate::R; +#[doc = "Register `ADDR9MASK` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Address9 Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9mask::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Addr9maskSpec; +impl crate::RegisterSpec for Addr9maskSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`addr9mask::R`](R) reader structure"] +impl crate::Readable for Addr9maskSpec {} +#[doc = "`write(|w| ..)` method takes [`addr9mask::W`](W) writer structure"] +impl crate::Writable for Addr9maskSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ADDR9MASK to value 0"] +impl crate::Resettable for Addr9maskSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/clkscale.rs b/va416xx/src/uart0/clkscale.rs new file mode 100644 index 0000000..14a5e79 --- /dev/null +++ b/va416xx/src/uart0/clkscale.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLKSCALE` reader"] +pub type R = crate::R; +#[doc = "Register `CLKSCALE` writer"] +pub type W = crate::W; +#[doc = "Field `FRAC` reader - Fractional Divide (64ths)"] +pub type FracR = crate::FieldReader; +#[doc = "Field `FRAC` writer - Fractional Divide (64ths)"] +pub type FracW<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `INT` reader - Integer Divide"] +pub type IntR = crate::FieldReader; +#[doc = "Field `INT` writer - Integer Divide"] +pub type IntW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>; +#[doc = "Field `RESET` writer - Reset Baud Counter"] +pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 0:5 - Fractional Divide (64ths)"] + #[inline(always)] + pub fn frac(&self) -> FracR { + FracR::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Integer Divide"] + #[inline(always)] + pub fn int(&self) -> IntR { + IntR::new((self.bits >> 6) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bits 0:5 - Fractional Divide (64ths)"] + #[inline(always)] + #[must_use] + pub fn frac(&mut self) -> FracW { + FracW::new(self, 0) + } + #[doc = "Bits 6:23 - Integer Divide"] + #[inline(always)] + #[must_use] + pub fn int(&mut self) -> IntW { + IntW::new(self, 6) + } + #[doc = "Bit 31 - Reset Baud Counter"] + #[inline(always)] + #[must_use] + pub fn reset(&mut self) -> ResetW { + ResetW::new(self, 31) + } +} +#[doc = "Clock Scale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct ClkscaleSpec; +impl crate::RegisterSpec for ClkscaleSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`clkscale::R`](R) reader structure"] +impl crate::Readable for ClkscaleSpec {} +#[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"] +impl crate::Writable for ClkscaleSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CLKSCALE to value 0"] +impl crate::Resettable for ClkscaleSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/ctrl.rs b/va416xx/src/uart0/ctrl.rs new file mode 100644 index 0000000..965c45a --- /dev/null +++ b/va416xx/src/uart0/ctrl.rs @@ -0,0 +1,190 @@ +#[doc = "Register `CTRL` reader"] +pub type R = crate::R; +#[doc = "Register `CTRL` writer"] +pub type W = crate::W; +#[doc = "Field `PAREN` reader - Parity Enable"] +pub type ParenR = crate::BitReader; +#[doc = "Field `PAREN` writer - Parity Enable"] +pub type ParenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PAREVEN` reader - Parity Even/Odd(1/0)"] +pub type ParevenR = crate::BitReader; +#[doc = "Field `PAREVEN` writer - Parity Even/Odd(1/0)"] +pub type ParevenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PARSTK` reader - Parity Sticky"] +pub type ParstkR = crate::BitReader; +#[doc = "Field `PARSTK` writer - Parity Sticky"] +pub type ParstkW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `STOPBITS` reader - Stop Bits 1/2(0/1)"] +pub type StopbitsR = crate::BitReader; +#[doc = "Field `STOPBITS` writer - Stop Bits 1/2(0/1)"] +pub type StopbitsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WORDSIZE` reader - Word Size in Bits 5/6/7/8(00/01/10/11)"] +pub type WordsizeR = crate::FieldReader; +#[doc = "Field `WORDSIZE` writer - Word Size in Bits 5/6/7/8(00/01/10/11)"] +pub type WordsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>; +#[doc = "Field `LOOPBACK` reader - Loopback Enable"] +pub type LoopbackR = crate::BitReader; +#[doc = "Field `LOOPBACK` writer - Loopback Enable"] +pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `LOOPBACKBLK` reader - Loopback Block"] +pub type LoopbackblkR = crate::BitReader; +#[doc = "Field `LOOPBACKBLK` writer - Loopback Block"] +pub type LoopbackblkW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTOCTS` reader - Enable Auto CTS mode"] +pub type AutoctsR = crate::BitReader; +#[doc = "Field `AUTOCTS` writer - Enable Auto CTS mode"] +pub type AutoctsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `DEFRTS` reader - Default RTSn value"] +pub type DefrtsR = crate::BitReader; +#[doc = "Field `DEFRTS` writer - Default RTSn value"] +pub type DefrtsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `AUTORTS` reader - Enable Auto RTS mode"] +pub type AutortsR = crate::BitReader; +#[doc = "Field `AUTORTS` writer - Enable Auto RTS mode"] +pub type AutortsW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `BAUD8` reader - Enable BAUD8 mode"] +pub type Baud8R = crate::BitReader; +#[doc = "Field `BAUD8` writer - Enable BAUD8 mode"] +pub type Baud8W<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Parity Enable"] + #[inline(always)] + pub fn paren(&self) -> ParenR { + ParenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Parity Even/Odd(1/0)"] + #[inline(always)] + pub fn pareven(&self) -> ParevenR { + ParevenR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Parity Sticky"] + #[inline(always)] + pub fn parstk(&self) -> ParstkR { + ParstkR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Stop Bits 1/2(0/1)"] + #[inline(always)] + pub fn stopbits(&self) -> StopbitsR { + StopbitsR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"] + #[inline(always)] + pub fn wordsize(&self) -> WordsizeR { + WordsizeR::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Loopback Enable"] + #[inline(always)] + pub fn loopback(&self) -> LoopbackR { + LoopbackR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Loopback Block"] + #[inline(always)] + pub fn loopbackblk(&self) -> LoopbackblkR { + LoopbackblkR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Enable Auto CTS mode"] + #[inline(always)] + pub fn autocts(&self) -> AutoctsR { + AutoctsR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Default RTSn value"] + #[inline(always)] + pub fn defrts(&self) -> DefrtsR { + DefrtsR::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Enable Auto RTS mode"] + #[inline(always)] + pub fn autorts(&self) -> AutortsR { + AutortsR::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Enable BAUD8 mode"] + #[inline(always)] + pub fn baud8(&self) -> Baud8R { + Baud8R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Enable"] + #[inline(always)] + #[must_use] + pub fn paren(&mut self) -> ParenW { + ParenW::new(self, 0) + } + #[doc = "Bit 1 - Parity Even/Odd(1/0)"] + #[inline(always)] + #[must_use] + pub fn pareven(&mut self) -> ParevenW { + ParevenW::new(self, 1) + } + #[doc = "Bit 2 - Parity Sticky"] + #[inline(always)] + #[must_use] + pub fn parstk(&mut self) -> ParstkW { + ParstkW::new(self, 2) + } + #[doc = "Bit 3 - Stop Bits 1/2(0/1)"] + #[inline(always)] + #[must_use] + pub fn stopbits(&mut self) -> StopbitsW { + StopbitsW::new(self, 3) + } + #[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"] + #[inline(always)] + #[must_use] + pub fn wordsize(&mut self) -> WordsizeW { + WordsizeW::new(self, 4) + } + #[doc = "Bit 6 - Loopback Enable"] + #[inline(always)] + #[must_use] + pub fn loopback(&mut self) -> LoopbackW { + LoopbackW::new(self, 6) + } + #[doc = "Bit 7 - Loopback Block"] + #[inline(always)] + #[must_use] + pub fn loopbackblk(&mut self) -> LoopbackblkW { + LoopbackblkW::new(self, 7) + } + #[doc = "Bit 8 - Enable Auto CTS mode"] + #[inline(always)] + #[must_use] + pub fn autocts(&mut self) -> AutoctsW { + AutoctsW::new(self, 8) + } + #[doc = "Bit 9 - Default RTSn value"] + #[inline(always)] + #[must_use] + pub fn defrts(&mut self) -> DefrtsW { + DefrtsW::new(self, 9) + } + #[doc = "Bit 10 - Enable Auto RTS mode"] + #[inline(always)] + #[must_use] + pub fn autorts(&mut self) -> AutortsW { + AutortsW::new(self, 10) + } + #[doc = "Bit 11 - Enable BAUD8 mode"] + #[inline(always)] + #[must_use] + pub fn baud8(&mut self) -> Baud8W { + Baud8W::new(self, 11) + } +} +#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct CtrlSpec; +impl crate::RegisterSpec for CtrlSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"] +impl crate::Readable for CtrlSpec {} +#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"] +impl crate::Writable for CtrlSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CtrlSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/data.rs b/va416xx/src/uart0/data.rs new file mode 100644 index 0000000..bc64a6c --- /dev/null +++ b/va416xx/src/uart0/data.rs @@ -0,0 +1,27 @@ +#[doc = "Register `DATA` reader"] +pub type R = crate::R; +#[doc = "Register `DATA` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data In/Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct DataSpec; +impl crate::RegisterSpec for DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`data::R`](R) reader structure"] +impl crate::Readable for DataSpec {} +#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"] +impl crate::Writable for DataSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/enable.rs b/va416xx/src/uart0/enable.rs new file mode 100644 index 0000000..ad6f797 --- /dev/null +++ b/va416xx/src/uart0/enable.rs @@ -0,0 +1,55 @@ +#[doc = "Register `ENABLE` reader"] +pub type R = crate::R; +#[doc = "Register `ENABLE` writer"] +pub type W = crate::W; +#[doc = "Field `RXENABLE` reader - Rx Enable"] +pub type RxenableR = crate::BitReader; +#[doc = "Field `RXENABLE` writer - Rx Enable"] +pub type RxenableW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXENABLE` reader - Tx Enable"] +pub type TxenableR = crate::BitReader; +#[doc = "Field `TXENABLE` writer - Tx Enable"] +pub type TxenableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Rx Enable"] + #[inline(always)] + pub fn rxenable(&self) -> RxenableR { + RxenableR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tx Enable"] + #[inline(always)] + pub fn txenable(&self) -> TxenableR { + TxenableR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Rx Enable"] + #[inline(always)] + #[must_use] + pub fn rxenable(&mut self) -> RxenableW { + RxenableW::new(self, 0) + } + #[doc = "Bit 1 - Tx Enable"] + #[inline(always)] + #[must_use] + pub fn txenable(&mut self) -> TxenableW { + TxenableW::new(self, 1) + } +} +#[doc = "Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct EnableSpec; +impl crate::RegisterSpec for EnableSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`enable::R`](R) reader structure"] +impl crate::Readable for EnableSpec {} +#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"] +impl crate::Writable for EnableSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ENABLE to value 0"] +impl crate::Resettable for EnableSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/fifo_clr.rs b/va416xx/src/uart0/fifo_clr.rs new file mode 100644 index 0000000..156da87 --- /dev/null +++ b/va416xx/src/uart0/fifo_clr.rs @@ -0,0 +1,35 @@ +#[doc = "Register `FIFO_CLR` writer"] +pub type W = crate::W; +#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"] +pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"] +pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>; +impl W { + #[doc = "Bit 0 - Clear Rx FIFO"] + #[inline(always)] + #[must_use] + pub fn rxfifo(&mut self) -> RxfifoW { + RxfifoW::new(self, 0) + } + #[doc = "Bit 1 - Clear Tx FIFO"] + #[inline(always)] + #[must_use] + pub fn txfifo(&mut self) -> TxfifoW { + TxfifoW::new(self, 1) + } +} +#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct FifoClrSpec; +impl crate::RegisterSpec for FifoClrSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"] +impl crate::Writable for FifoClrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets FIFO_CLR to value 0"] +impl crate::Resettable for FifoClrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/irq_enb.rs b/va416xx/src/uart0/irq_enb.rs new file mode 100644 index 0000000..6702628 --- /dev/null +++ b/va416xx/src/uart0/irq_enb.rs @@ -0,0 +1,130 @@ +#[doc = "Register `IRQ_ENB` reader"] +pub type R = crate::R; +#[doc = "Register `IRQ_ENB` writer"] +pub type W = crate::W; +#[doc = "Field `IRQ_RX` reader - RX Interrupt"] +pub type IrqRxR = crate::BitReader; +#[doc = "Field `IRQ_RX` writer - RX Interrupt"] +pub type IrqRxW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_RX_STATUS` reader - RX Status Interrupt"] +pub type IrqRxStatusR = crate::BitReader; +#[doc = "Field `IRQ_RX_STATUS` writer - RX Status Interrupt"] +pub type IrqRxStatusW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_RX_TO` reader - RX Timeout Interrupt"] +pub type IrqRxToR = crate::BitReader; +#[doc = "Field `IRQ_RX_TO` writer - RX Timeout Interrupt"] +pub type IrqRxToW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX` reader - TX Interrupt"] +pub type IrqTxR = crate::BitReader; +#[doc = "Field `IRQ_TX` writer - TX Interrupt"] +pub type IrqTxW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX_STATUS` reader - TX Status Interrupt"] +pub type IrqTxStatusR = crate::BitReader; +#[doc = "Field `IRQ_TX_STATUS` writer - TX Status Interrupt"] +pub type IrqTxStatusW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX_EMPTY` reader - TX Empty Interrupt"] +pub type IrqTxEmptyR = crate::BitReader; +#[doc = "Field `IRQ_TX_EMPTY` writer - TX Empty Interrupt"] +pub type IrqTxEmptyW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `IRQ_TX_CTS` reader - TX CTS Change Interrupt"] +pub type IrqTxCtsR = crate::BitReader; +#[doc = "Field `IRQ_TX_CTS` writer - TX CTS Change Interrupt"] +pub type IrqTxCtsW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + pub fn irq_rx(&self) -> IrqRxR { + IrqRxR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + pub fn irq_rx_status(&self) -> IrqRxStatusR { + IrqRxStatusR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + pub fn irq_rx_to(&self) -> IrqRxToR { + IrqRxToR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + pub fn irq_tx(&self) -> IrqTxR { + IrqTxR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + pub fn irq_tx_status(&self) -> IrqTxStatusR { + IrqTxStatusR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + pub fn irq_tx_empty(&self) -> IrqTxEmptyR { + IrqTxEmptyR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + pub fn irq_tx_cts(&self) -> IrqTxCtsR { + IrqTxCtsR::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - RX Interrupt"] + #[inline(always)] + #[must_use] + pub fn irq_rx(&mut self) -> IrqRxW { + IrqRxW::new(self, 0) + } + #[doc = "Bit 1 - RX Status Interrupt"] + #[inline(always)] + #[must_use] + pub fn irq_rx_status(&mut self) -> IrqRxStatusW { + IrqRxStatusW::new(self, 1) + } + #[doc = "Bit 2 - RX Timeout Interrupt"] + #[inline(always)] + #[must_use] + pub fn irq_rx_to(&mut self) -> IrqRxToW { + IrqRxToW::new(self, 2) + } + #[doc = "Bit 4 - TX Interrupt"] + #[inline(always)] + #[must_use] + pub fn irq_tx(&mut self) -> IrqTxW { + IrqTxW::new(self, 4) + } + #[doc = "Bit 5 - TX Status Interrupt"] + #[inline(always)] + #[must_use] + pub fn irq_tx_status(&mut self) -> IrqTxStatusW { + IrqTxStatusW::new(self, 5) + } + #[doc = "Bit 6 - TX Empty Interrupt"] + #[inline(always)] + #[must_use] + pub fn irq_tx_empty(&mut self) -> IrqTxEmptyW { + IrqTxEmptyW::new(self, 6) + } + #[doc = "Bit 7 - TX CTS Change Interrupt"] + #[inline(always)] + #[must_use] + pub fn irq_tx_cts(&mut self) -> IrqTxCtsW { + IrqTxCtsW::new(self, 7) + } +} +#[doc = "IRQ Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct IrqEnbSpec; +impl crate::RegisterSpec for IrqEnbSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"] +impl crate::Readable for IrqEnbSpec {} +#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"] +impl crate::Writable for IrqEnbSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets IRQ_ENB to value 0"] +impl crate::Resettable for IrqEnbSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/perid.rs b/va416xx/src/uart0/perid.rs new file mode 100644 index 0000000..c2b57d9 --- /dev/null +++ b/va416xx/src/uart0/perid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0212_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0212_07e9; +} diff --git a/va416xx/src/uart0/rxfifoirqtrg.rs b/va416xx/src/uart0/rxfifoirqtrg.rs new file mode 100644 index 0000000..46124d5 --- /dev/null +++ b/va416xx/src/uart0/rxfifoirqtrg.rs @@ -0,0 +1,27 @@ +#[doc = "Register `RXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFOIRQTRG` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifoirqtrgSpec; +impl crate::RegisterSpec for RxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for RxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for RxfifoirqtrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"] +impl crate::Resettable for RxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/rxfifortstrg.rs b/va416xx/src/uart0/rxfifortstrg.rs new file mode 100644 index 0000000..dd8afea --- /dev/null +++ b/va416xx/src/uart0/rxfifortstrg.rs @@ -0,0 +1,27 @@ +#[doc = "Register `RXFIFORTSTRG` reader"] +pub type R = crate::R; +#[doc = "Register `RXFIFORTSTRG` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifortstrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifortstrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxfifortstrgSpec; +impl crate::RegisterSpec for RxfifortstrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxfifortstrg::R`](R) reader structure"] +impl crate::Readable for RxfifortstrgSpec {} +#[doc = "`write(|w| ..)` method takes [`rxfifortstrg::W`](W) writer structure"] +impl crate::Writable for RxfifortstrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RXFIFORTSTRG to value 0"] +impl crate::Resettable for RxfifortstrgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/rxstatus.rs b/va416xx/src/uart0/rxstatus.rs new file mode 100644 index 0000000..c519eb8 --- /dev/null +++ b/va416xx/src/uart0/rxstatus.rs @@ -0,0 +1,92 @@ +#[doc = "Register `RXSTATUS` reader"] +pub type R = crate::R; +#[doc = "Field `RDAVL` reader - Read Data Available"] +pub type RdavlR = crate::BitReader; +#[doc = "Field `RDNFULL` reader - Read Fifo NOT Full"] +pub type RdnfullR = crate::BitReader; +#[doc = "Field `RXBUSY` reader - RX Busy Receiving"] +pub type RxbusyR = crate::BitReader; +#[doc = "Field `RXTO` reader - RX Receive Timeout"] +pub type RxtoR = crate::BitReader; +#[doc = "Field `RXOVR` reader - Read Fifo Overflow"] +pub type RxovrR = crate::BitReader; +#[doc = "Field `RXFRM` reader - RX Framing Error"] +pub type RxfrmR = crate::BitReader; +#[doc = "Field `RXPAR` reader - RX Parity Error"] +pub type RxparR = crate::BitReader; +#[doc = "Field `RXBRK` reader - RX Break Error"] +pub type RxbrkR = crate::BitReader; +#[doc = "Field `RXBUSYBRK` reader - RX Busy Receiving Break"] +pub type RxbusybrkR = crate::BitReader; +#[doc = "Field `RXADDR9` reader - Address Match for 9 bit mode"] +pub type Rxaddr9R = crate::BitReader; +#[doc = "Field `RXRTSN` reader - RX RTSn Output Value"] +pub type RxrtsnR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Read Data Available"] + #[inline(always)] + pub fn rdavl(&self) -> RdavlR { + RdavlR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Read Fifo NOT Full"] + #[inline(always)] + pub fn rdnfull(&self) -> RdnfullR { + RdnfullR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - RX Busy Receiving"] + #[inline(always)] + pub fn rxbusy(&self) -> RxbusyR { + RxbusyR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RX Receive Timeout"] + #[inline(always)] + pub fn rxto(&self) -> RxtoR { + RxtoR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Read Fifo Overflow"] + #[inline(always)] + pub fn rxovr(&self) -> RxovrR { + RxovrR::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - RX Framing Error"] + #[inline(always)] + pub fn rxfrm(&self) -> RxfrmR { + RxfrmR::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RX Parity Error"] + #[inline(always)] + pub fn rxpar(&self) -> RxparR { + RxparR::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - RX Break Error"] + #[inline(always)] + pub fn rxbrk(&self) -> RxbrkR { + RxbrkR::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - RX Busy Receiving Break"] + #[inline(always)] + pub fn rxbusybrk(&self) -> RxbusybrkR { + RxbusybrkR::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Address Match for 9 bit mode"] + #[inline(always)] + pub fn rxaddr9(&self) -> Rxaddr9R { + Rxaddr9R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 15 - RX RTSn Output Value"] + #[inline(always)] + pub fn rxrtsn(&self) -> RxrtsnR { + RxrtsnR::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RxstatusSpec; +impl crate::RegisterSpec for RxstatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rxstatus::R`](R) reader structure"] +impl crate::Readable for RxstatusSpec {} +#[doc = "`reset()` method sets RXSTATUS to value 0"] +impl crate::Resettable for RxstatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/state.rs b/va416xx/src/uart0/state.rs new file mode 100644 index 0000000..17ec5bc --- /dev/null +++ b/va416xx/src/uart0/state.rs @@ -0,0 +1,18 @@ +#[doc = "Register `STATE` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Internal STATE of UART Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct StateSpec; +impl crate::RegisterSpec for StateSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`state::R`](R) reader structure"] +impl crate::Readable for StateSpec {} +#[doc = "`reset()` method sets STATE to value 0"] +impl crate::Resettable for StateSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/txbreak.rs b/va416xx/src/uart0/txbreak.rs new file mode 100644 index 0000000..69a167f --- /dev/null +++ b/va416xx/src/uart0/txbreak.rs @@ -0,0 +1,23 @@ +#[doc = "Register `TXBREAK` writer"] +pub type W = crate::W; +impl core::fmt::Debug for crate::generic::Reg { + fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { + write!(f, "(not readable)") + } +} +impl W {} +#[doc = "Break Transmit Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbreak::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxbreakSpec; +impl crate::RegisterSpec for TxbreakSpec { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [`txbreak::W`](W) writer structure"] +impl crate::Writable for TxbreakSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TXBREAK to value 0"] +impl crate::Resettable for TxbreakSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/txfifoirqtrg.rs b/va416xx/src/uart0/txfifoirqtrg.rs new file mode 100644 index 0000000..0d13e54 --- /dev/null +++ b/va416xx/src/uart0/txfifoirqtrg.rs @@ -0,0 +1,27 @@ +#[doc = "Register `TXFIFOIRQTRG` reader"] +pub type R = crate::R; +#[doc = "Register `TXFIFOIRQTRG` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxfifoirqtrgSpec; +impl crate::RegisterSpec for TxfifoirqtrgSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"] +impl crate::Readable for TxfifoirqtrgSpec {} +#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"] +impl crate::Writable for TxfifoirqtrgSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"] +impl crate::Resettable for TxfifoirqtrgSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/uart0/txstatus.rs b/va416xx/src/uart0/txstatus.rs new file mode 100644 index 0000000..42852d9 --- /dev/null +++ b/va416xx/src/uart0/txstatus.rs @@ -0,0 +1,50 @@ +#[doc = "Register `TXSTATUS` reader"] +pub type R = crate::R; +#[doc = "Field `WRRDY` reader - Write Fifo NOT Full"] +pub type WrrdyR = crate::BitReader; +#[doc = "Field `WRBUSY` reader - Write Fifo Full"] +pub type WrbusyR = crate::BitReader; +#[doc = "Field `TXBUSY` reader - TX Busy Transmitting"] +pub type TxbusyR = crate::BitReader; +#[doc = "Field `WRLOST` reader - Write Data Lost (Fifo Overflow)"] +pub type WrlostR = crate::BitReader; +#[doc = "Field `TXCTSN` reader - TX CTSn Input Value"] +pub type TxctsnR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Write Fifo NOT Full"] + #[inline(always)] + pub fn wrrdy(&self) -> WrrdyR { + WrrdyR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Write Fifo Full"] + #[inline(always)] + pub fn wrbusy(&self) -> WrbusyR { + WrbusyR::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - TX Busy Transmitting"] + #[inline(always)] + pub fn txbusy(&self) -> TxbusyR { + TxbusyR::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Write Data Lost (Fifo Overflow)"] + #[inline(always)] + pub fn wrlost(&self) -> WrlostR { + WrlostR::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 15 - TX CTSn Input Value"] + #[inline(always)] + pub fn txctsn(&self) -> TxctsnR { + TxctsnR::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txstatus::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct TxstatusSpec; +impl crate::RegisterSpec for TxstatusSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`txstatus::R`](R) reader structure"] +impl crate::Readable for TxstatusSpec {} +#[doc = "`reset()` method sets TXSTATUS to value 0"] +impl crate::Resettable for TxstatusSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility.rs b/va416xx/src/utility.rs new file mode 100644 index 0000000..9866ff5 --- /dev/null +++ b/va416xx/src/utility.rs @@ -0,0 +1,188 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + synd_data: SyndData, + synd_synd: SyndSynd, + synd_enc_32_44: SyndEnc32_44, + synd_check_32_44_data: SyndCheck32_44Data, + synd_check_32_44_synd: SyndCheck32_44Synd, + rom_trap_address: RomTrapAddress, + rom_trap_synd: RomTrapSynd, + ram_trap_addr0: RamTrapAddr0, + ram_trap_synd0: RamTrapSynd0, + ram_trap_addr1: RamTrapAddr1, + ram_trap_synd1: RamTrapSynd1, + _reserved11: [u8; 0xf4], + synd_enc_32_52: SyndEnc32_52, + synd_check_32_52_data: SyndCheck32_52Data, + synd_check_32_52_synd: SyndCheck32_52Synd, + _reserved14: [u8; 0x0ed0], + perid: Perid, +} +impl RegisterBlock { + #[doc = "0x00 - Data Register"] + #[inline(always)] + pub const fn synd_data(&self) -> &SyndData { + &self.synd_data + } + #[doc = "0x04 - Syndrome Data Register"] + #[inline(always)] + pub const fn synd_synd(&self) -> &SyndSynd { + &self.synd_synd + } + #[doc = "0x08 - EDAC Encode"] + #[inline(always)] + pub const fn synd_enc_32_44(&self) -> &SyndEnc32_44 { + &self.synd_enc_32_44 + } + #[doc = "0x0c - EDAC Decode Data"] + #[inline(always)] + pub const fn synd_check_32_44_data(&self) -> &SyndCheck32_44Data { + &self.synd_check_32_44_data + } + #[doc = "0x10 - EDAC Decode Syndrome"] + #[inline(always)] + pub const fn synd_check_32_44_synd(&self) -> &SyndCheck32_44Synd { + &self.synd_check_32_44_synd + } + #[doc = "0x14 - ROM EDAC Trap Address"] + #[inline(always)] + pub const fn rom_trap_address(&self) -> &RomTrapAddress { + &self.rom_trap_address + } + #[doc = "0x18 - ROM EDAC Trap Syndrome"] + #[inline(always)] + pub const fn rom_trap_synd(&self) -> &RomTrapSynd { + &self.rom_trap_synd + } + #[doc = "0x1c - RAM0 EDAC Trap Address"] + #[inline(always)] + pub const fn ram_trap_addr0(&self) -> &RamTrapAddr0 { + &self.ram_trap_addr0 + } + #[doc = "0x20 - RAM0 EDAC Trap Syndrome"] + #[inline(always)] + pub const fn ram_trap_synd0(&self) -> &RamTrapSynd0 { + &self.ram_trap_synd0 + } + #[doc = "0x24 - RAM1 EDAC Trap Address"] + #[inline(always)] + pub const fn ram_trap_addr1(&self) -> &RamTrapAddr1 { + &self.ram_trap_addr1 + } + #[doc = "0x28 - RAM1 EDAC Trap Syndrome"] + #[inline(always)] + pub const fn ram_trap_synd1(&self) -> &RamTrapSynd1 { + &self.ram_trap_synd1 + } + #[doc = "0x120 - EDAC Encode"] + #[inline(always)] + pub const fn synd_enc_32_52(&self) -> &SyndEnc32_52 { + &self.synd_enc_32_52 + } + #[doc = "0x124 - EDAC Decode Data"] + #[inline(always)] + pub const fn synd_check_32_52_data(&self) -> &SyndCheck32_52Data { + &self.synd_check_32_52_data + } + #[doc = "0x128 - EDAC Decode Syndrome"] + #[inline(always)] + pub const fn synd_check_32_52_synd(&self) -> &SyndCheck32_52Synd { + &self.synd_check_32_52_synd + } + #[doc = "0xffc - Peripheral ID Register"] + #[inline(always)] + pub const fn perid(&self) -> &Perid { + &self.perid + } +} +#[doc = "SYND_DATA (rw) register accessor: Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_data::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_data::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_data`] +module"] +#[doc(alias = "SYND_DATA")] +pub type SyndData = crate::Reg; +#[doc = "Data Register"] +pub mod synd_data; +#[doc = "SYND_SYND (rw) register accessor: Syndrome Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_synd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_synd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_synd`] +module"] +#[doc(alias = "SYND_SYND")] +pub type SyndSynd = crate::Reg; +#[doc = "Syndrome Data Register"] +pub mod synd_synd; +#[doc = "SYND_ENC_32_44 (rw) register accessor: EDAC Encode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_enc_32_44::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_enc_32_44::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_32_44`] +module"] +#[doc(alias = "SYND_ENC_32_44")] +pub type SyndEnc32_44 = crate::Reg; +#[doc = "EDAC Encode"] +pub mod synd_enc_32_44; +#[doc = "SYND_CHECK_32_44_DATA (r) register accessor: EDAC Decode Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_44_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_44_data`] +module"] +#[doc(alias = "SYND_CHECK_32_44_DATA")] +pub type SyndCheck32_44Data = crate::Reg; +#[doc = "EDAC Decode Data"] +pub mod synd_check_32_44_data; +#[doc = "SYND_CHECK_32_44_SYND (r) register accessor: EDAC Decode Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_44_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_44_synd`] +module"] +#[doc(alias = "SYND_CHECK_32_44_SYND")] +pub type SyndCheck32_44Synd = crate::Reg; +#[doc = "EDAC Decode Syndrome"] +pub mod synd_check_32_44_synd; +#[doc = "ROM_TRAP_ADDRESS (rw) register accessor: ROM EDAC Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_address`] +module"] +#[doc(alias = "ROM_TRAP_ADDRESS")] +pub type RomTrapAddress = crate::Reg; +#[doc = "ROM EDAC Trap Address"] +pub mod rom_trap_address; +#[doc = "ROM_TRAP_SYND (rw) register accessor: ROM EDAC Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_synd::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_synd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_trap_synd`] +module"] +#[doc(alias = "ROM_TRAP_SYND")] +pub type RomTrapSynd = crate::Reg; +#[doc = "ROM EDAC Trap Syndrome"] +pub mod rom_trap_synd; +#[doc = "RAM_TRAP_ADDR0 (rw) register accessor: RAM0 EDAC Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_trap_addr0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_trap_addr0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_trap_addr0`] +module"] +#[doc(alias = "RAM_TRAP_ADDR0")] +pub type RamTrapAddr0 = crate::Reg; +#[doc = "RAM0 EDAC Trap Address"] +pub mod ram_trap_addr0; +#[doc = "RAM_TRAP_SYND0 (rw) register accessor: RAM0 EDAC Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_trap_synd0::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_trap_synd0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_trap_synd0`] +module"] +#[doc(alias = "RAM_TRAP_SYND0")] +pub type RamTrapSynd0 = crate::Reg; +#[doc = "RAM0 EDAC Trap Syndrome"] +pub mod ram_trap_synd0; +#[doc = "RAM_TRAP_ADDR1 (rw) register accessor: RAM1 EDAC Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_trap_addr1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_trap_addr1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_trap_addr1`] +module"] +#[doc(alias = "RAM_TRAP_ADDR1")] +pub type RamTrapAddr1 = crate::Reg; +#[doc = "RAM1 EDAC Trap Address"] +pub mod ram_trap_addr1; +#[doc = "RAM_TRAP_SYND1 (rw) register accessor: RAM1 EDAC Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_trap_synd1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_trap_synd1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram_trap_synd1`] +module"] +#[doc(alias = "RAM_TRAP_SYND1")] +pub type RamTrapSynd1 = crate::Reg; +#[doc = "RAM1 EDAC Trap Syndrome"] +pub mod ram_trap_synd1; +#[doc = "SYND_ENC_32_52 (r) register accessor: EDAC Encode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_enc_32_52::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_enc_32_52`] +module"] +#[doc(alias = "SYND_ENC_32_52")] +pub type SyndEnc32_52 = crate::Reg; +#[doc = "EDAC Encode"] +pub mod synd_enc_32_52; +#[doc = "SYND_CHECK_32_52_DATA (r) register accessor: EDAC Decode Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_52_data::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_52_data`] +module"] +#[doc(alias = "SYND_CHECK_32_52_DATA")] +pub type SyndCheck32_52Data = crate::Reg; +#[doc = "EDAC Decode Data"] +pub mod synd_check_32_52_data; +#[doc = "SYND_CHECK_32_52_SYND (r) register accessor: EDAC Decode Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_52_synd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@synd_check_32_52_synd`] +module"] +#[doc(alias = "SYND_CHECK_32_52_SYND")] +pub type SyndCheck32_52Synd = crate::Reg; +#[doc = "EDAC Decode Syndrome"] +pub mod synd_check_32_52_synd; +#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] +module"] +#[doc(alias = "PERID")] +pub type Perid = crate::Reg; +#[doc = "Peripheral ID Register"] +pub mod perid; diff --git a/va416xx/src/utility/perid.rs b/va416xx/src/utility/perid.rs new file mode 100644 index 0000000..8a3adc5 --- /dev/null +++ b/va416xx/src/utility/perid.rs @@ -0,0 +1,18 @@ +#[doc = "Register `PERID` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PeridSpec; +impl crate::RegisterSpec for PeridSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`perid::R`](R) reader structure"] +impl crate::Readable for PeridSpec {} +#[doc = "`reset()` method sets PERID to value 0x0284_07e9"] +impl crate::Resettable for PeridSpec { + const RESET_VALUE: u32 = 0x0284_07e9; +} diff --git a/va416xx/src/utility/ram_trap_addr0.rs b/va416xx/src/utility/ram_trap_addr0.rs new file mode 100644 index 0000000..d29dd1a --- /dev/null +++ b/va416xx/src/utility/ram_trap_addr0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `RAM_TRAP_ADDR0` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_TRAP_ADDR0` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - Address bits for trap match"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address bits for trap match"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; +#[doc = "Field `ENABLE` reader - Enable Trap mode"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable Trap mode"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new((self.bits >> 2) & 0x1fff_ffff) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> AddrW { + AddrW::new(self, 2) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 31) + } +} +#[doc = "RAM0 EDAC Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_trap_addr0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_trap_addr0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamTrapAddr0Spec; +impl crate::RegisterSpec for RamTrapAddr0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_trap_addr0::R`](R) reader structure"] +impl crate::Readable for RamTrapAddr0Spec {} +#[doc = "`write(|w| ..)` method takes [`ram_trap_addr0::W`](W) writer structure"] +impl crate::Writable for RamTrapAddr0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RAM_TRAP_ADDR0 to value 0"] +impl crate::Resettable for RamTrapAddr0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/ram_trap_addr1.rs b/va416xx/src/utility/ram_trap_addr1.rs new file mode 100644 index 0000000..ce2b329 --- /dev/null +++ b/va416xx/src/utility/ram_trap_addr1.rs @@ -0,0 +1,55 @@ +#[doc = "Register `RAM_TRAP_ADDR1` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_TRAP_ADDR1` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - Address bits for trap match"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address bits for trap match"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; +#[doc = "Field `ENABLE` reader - Enable Trap mode"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable Trap mode"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new((self.bits >> 2) & 0x1fff_ffff) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> AddrW { + AddrW::new(self, 2) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 31) + } +} +#[doc = "RAM1 EDAC Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_trap_addr1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_trap_addr1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamTrapAddr1Spec; +impl crate::RegisterSpec for RamTrapAddr1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_trap_addr1::R`](R) reader structure"] +impl crate::Readable for RamTrapAddr1Spec {} +#[doc = "`write(|w| ..)` method takes [`ram_trap_addr1::W`](W) writer structure"] +impl crate::Writable for RamTrapAddr1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RAM_TRAP_ADDR1 to value 0"] +impl crate::Resettable for RamTrapAddr1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/ram_trap_synd0.rs b/va416xx/src/utility/ram_trap_synd0.rs new file mode 100644 index 0000000..7eaf19f --- /dev/null +++ b/va416xx/src/utility/ram_trap_synd0.rs @@ -0,0 +1,55 @@ +#[doc = "Register `RAM_TRAP_SYND0` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_TRAP_SYND0` writer"] +pub type W = crate::W; +#[doc = "Field `RAM_SYND_7_0` reader - 6-bit syndrome value for bits 15-0"] +pub type RamSynd7_0R = crate::FieldReader; +#[doc = "Field `RAM_SYND_7_0` writer - 6-bit syndrome value for bits 15-0"] +pub type RamSynd7_0W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `RAM_SYND_31_16` reader - 6-bit syndrome value for bits 31-16"] +pub type RamSynd31_16R = crate::FieldReader; +#[doc = "Field `RAM_SYND_31_16` writer - 6-bit syndrome value for bits 31-16"] +pub type RamSynd31_16W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn ram_synd_7_0(&self) -> RamSynd7_0R { + RamSynd7_0R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn ram_synd_31_16(&self) -> RamSynd31_16R { + RamSynd31_16R::new(((self.bits >> 6) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + #[must_use] + pub fn ram_synd_7_0(&mut self) -> RamSynd7_0W { + RamSynd7_0W::new(self, 0) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + #[must_use] + pub fn ram_synd_31_16(&mut self) -> RamSynd31_16W { + RamSynd31_16W::new(self, 6) + } +} +#[doc = "RAM0 EDAC Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_trap_synd0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_trap_synd0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamTrapSynd0Spec; +impl crate::RegisterSpec for RamTrapSynd0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_trap_synd0::R`](R) reader structure"] +impl crate::Readable for RamTrapSynd0Spec {} +#[doc = "`write(|w| ..)` method takes [`ram_trap_synd0::W`](W) writer structure"] +impl crate::Writable for RamTrapSynd0Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RAM_TRAP_SYND0 to value 0"] +impl crate::Resettable for RamTrapSynd0Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/ram_trap_synd1.rs b/va416xx/src/utility/ram_trap_synd1.rs new file mode 100644 index 0000000..adf1ba5 --- /dev/null +++ b/va416xx/src/utility/ram_trap_synd1.rs @@ -0,0 +1,55 @@ +#[doc = "Register `RAM_TRAP_SYND1` reader"] +pub type R = crate::R; +#[doc = "Register `RAM_TRAP_SYND1` writer"] +pub type W = crate::W; +#[doc = "Field `RAM_SYND_7_0` reader - 6-bit syndrome value for bits 15-0"] +pub type RamSynd7_0R = crate::FieldReader; +#[doc = "Field `RAM_SYND_7_0` writer - 6-bit syndrome value for bits 15-0"] +pub type RamSynd7_0W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `RAM_SYND_31_16` reader - 6-bit syndrome value for bits 31-16"] +pub type RamSynd31_16R = crate::FieldReader; +#[doc = "Field `RAM_SYND_31_16` writer - 6-bit syndrome value for bits 31-16"] +pub type RamSynd31_16W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn ram_synd_7_0(&self) -> RamSynd7_0R { + RamSynd7_0R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn ram_synd_31_16(&self) -> RamSynd31_16R { + RamSynd31_16R::new(((self.bits >> 6) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + #[must_use] + pub fn ram_synd_7_0(&mut self) -> RamSynd7_0W { + RamSynd7_0W::new(self, 0) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + #[must_use] + pub fn ram_synd_31_16(&mut self) -> RamSynd31_16W { + RamSynd31_16W::new(self, 6) + } +} +#[doc = "RAM1 EDAC Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ram_trap_synd1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ram_trap_synd1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RamTrapSynd1Spec; +impl crate::RegisterSpec for RamTrapSynd1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`ram_trap_synd1::R`](R) reader structure"] +impl crate::Readable for RamTrapSynd1Spec {} +#[doc = "`write(|w| ..)` method takes [`ram_trap_synd1::W`](W) writer structure"] +impl crate::Writable for RamTrapSynd1Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets RAM_TRAP_SYND1 to value 0"] +impl crate::Resettable for RamTrapSynd1Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/rom_trap_address.rs b/va416xx/src/utility/rom_trap_address.rs new file mode 100644 index 0000000..722dc0c --- /dev/null +++ b/va416xx/src/utility/rom_trap_address.rs @@ -0,0 +1,55 @@ +#[doc = "Register `ROM_TRAP_ADDRESS` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_TRAP_ADDRESS` writer"] +pub type W = crate::W; +#[doc = "Field `ADDR` reader - Address bits for trap match"] +pub type AddrR = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address bits for trap match"] +pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 29, u32>; +#[doc = "Field `ENABLE` reader - Enable Trap mode"] +pub type EnableR = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable Trap mode"] +pub type EnableW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + pub fn addr(&self) -> AddrR { + AddrR::new((self.bits >> 2) & 0x1fff_ffff) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + pub fn enable(&self) -> EnableR { + EnableR::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 2:30 - Address bits for trap match"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> AddrW { + AddrW::new(self, 2) + } + #[doc = "Bit 31 - Enable Trap mode"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> EnableW { + EnableW::new(self, 31) + } +} +#[doc = "ROM EDAC Trap Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_address::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_address::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomTrapAddressSpec; +impl crate::RegisterSpec for RomTrapAddressSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_trap_address::R`](R) reader structure"] +impl crate::Readable for RomTrapAddressSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_trap_address::W`](W) writer structure"] +impl crate::Writable for RomTrapAddressSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ROM_TRAP_ADDRESS to value 0"] +impl crate::Resettable for RomTrapAddressSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/rom_trap_synd.rs b/va416xx/src/utility/rom_trap_synd.rs new file mode 100644 index 0000000..81faf4e --- /dev/null +++ b/va416xx/src/utility/rom_trap_synd.rs @@ -0,0 +1,55 @@ +#[doc = "Register `ROM_TRAP_SYND` reader"] +pub type R = crate::R; +#[doc = "Register `ROM_TRAP_SYND` writer"] +pub type W = crate::W; +#[doc = "Field `ROM_SYND_7_0` reader - 6-bit syndrome value for bits 15-0"] +pub type RomSynd7_0R = crate::FieldReader; +#[doc = "Field `ROM_SYND_7_0` writer - 6-bit syndrome value for bits 15-0"] +pub type RomSynd7_0W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `R0M_SYND_31_16` reader - 6-bit syndrome value for bits 31-16"] +pub type R0mSynd31_16R = crate::FieldReader; +#[doc = "Field `R0M_SYND_31_16` writer - 6-bit syndrome value for bits 31-16"] +pub type R0mSynd31_16W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + pub fn rom_synd_7_0(&self) -> RomSynd7_0R { + RomSynd7_0R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + pub fn r0m_synd_31_16(&self) -> R0mSynd31_16R { + R0mSynd31_16R::new(((self.bits >> 6) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - 6-bit syndrome value for bits 15-0"] + #[inline(always)] + #[must_use] + pub fn rom_synd_7_0(&mut self) -> RomSynd7_0W { + RomSynd7_0W::new(self, 0) + } + #[doc = "Bits 6:11 - 6-bit syndrome value for bits 31-16"] + #[inline(always)] + #[must_use] + pub fn r0m_synd_31_16(&mut self) -> R0mSynd31_16W { + R0mSynd31_16W::new(self, 6) + } +} +#[doc = "ROM EDAC Trap Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rom_trap_synd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rom_trap_synd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct RomTrapSyndSpec; +impl crate::RegisterSpec for RomTrapSyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`rom_trap_synd::R`](R) reader structure"] +impl crate::Readable for RomTrapSyndSpec {} +#[doc = "`write(|w| ..)` method takes [`rom_trap_synd::W`](W) writer structure"] +impl crate::Writable for RomTrapSyndSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets ROM_TRAP_SYND to value 0"] +impl crate::Resettable for RomTrapSyndSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/synd_check_32_44_data.rs b/va416xx/src/utility/synd_check_32_44_data.rs new file mode 100644 index 0000000..0adfd8b --- /dev/null +++ b/va416xx/src/utility/synd_check_32_44_data.rs @@ -0,0 +1,18 @@ +#[doc = "Register `SYND_CHECK_32_44_DATA` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "EDAC Decode Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_44_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32_44DataSpec; +impl crate::RegisterSpec for SyndCheck32_44DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_44_data::R`](R) reader structure"] +impl crate::Readable for SyndCheck32_44DataSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_44_DATA to value 0"] +impl crate::Resettable for SyndCheck32_44DataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/synd_check_32_44_synd.rs b/va416xx/src/utility/synd_check_32_44_synd.rs new file mode 100644 index 0000000..a0d7f6b --- /dev/null +++ b/va416xx/src/utility/synd_check_32_44_synd.rs @@ -0,0 +1,36 @@ +#[doc = "Register `SYND_CHECK_32_44_SYND` reader"] +pub type R = crate::R; +#[doc = "Field `SYND_CHECK_32_44_SYND` reader - Correct syndrome value"] +pub type SyndCheck32_44SyndR = crate::FieldReader; +#[doc = "Field `SBE` reader - Single bit error detect status"] +pub type SbeR = crate::FieldReader; +#[doc = "Field `MBE` reader - Multiple bit error detect status"] +pub type MbeR = crate::FieldReader; +impl R { + #[doc = "Bits 0:11 - Correct syndrome value"] + #[inline(always)] + pub fn synd_check_32_44_synd(&self) -> SyndCheck32_44SyndR { + SyndCheck32_44SyndR::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 12:13 - Single bit error detect status"] + #[inline(always)] + pub fn sbe(&self) -> SbeR { + SbeR::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bits 14:15 - Multiple bit error detect status"] + #[inline(always)] + pub fn mbe(&self) -> MbeR { + MbeR::new(((self.bits >> 14) & 3) as u8) + } +} +#[doc = "EDAC Decode Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_44_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32_44SyndSpec; +impl crate::RegisterSpec for SyndCheck32_44SyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_44_synd::R`](R) reader structure"] +impl crate::Readable for SyndCheck32_44SyndSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_44_SYND to value 0"] +impl crate::Resettable for SyndCheck32_44SyndSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/synd_check_32_52_data.rs b/va416xx/src/utility/synd_check_32_52_data.rs new file mode 100644 index 0000000..df77cde --- /dev/null +++ b/va416xx/src/utility/synd_check_32_52_data.rs @@ -0,0 +1,18 @@ +#[doc = "Register `SYND_CHECK_32_52_DATA` reader"] +pub type R = crate::R; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +#[doc = "EDAC Decode Data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_52_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32_52DataSpec; +impl crate::RegisterSpec for SyndCheck32_52DataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_52_data::R`](R) reader structure"] +impl crate::Readable for SyndCheck32_52DataSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_52_DATA to value 0"] +impl crate::Resettable for SyndCheck32_52DataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/synd_check_32_52_synd.rs b/va416xx/src/utility/synd_check_32_52_synd.rs new file mode 100644 index 0000000..55fea27 --- /dev/null +++ b/va416xx/src/utility/synd_check_32_52_synd.rs @@ -0,0 +1,36 @@ +#[doc = "Register `SYND_CHECK_32_52_SYND` reader"] +pub type R = crate::R; +#[doc = "Field `SYND_CHECK_32_52_SYND` reader - Corrected syndrome value"] +pub type SyndCheck32_52SyndR = crate::FieldReader; +#[doc = "Field `SBE` reader - Single bit error detect status"] +pub type SbeR = crate::FieldReader; +#[doc = "Field `MBE` reader - Multiple bit error detect status"] +pub type MbeR = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - Corrected syndrome value"] + #[inline(always)] + pub fn synd_check_32_52_synd(&self) -> SyndCheck32_52SyndR { + SyndCheck32_52SyndR::new(self.bits & 0x000f_ffff) + } + #[doc = "Bits 24:27 - Single bit error detect status"] + #[inline(always)] + pub fn sbe(&self) -> SbeR { + SbeR::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Multiple bit error detect status"] + #[inline(always)] + pub fn mbe(&self) -> MbeR { + MbeR::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "EDAC Decode Syndrome\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_check_32_52_synd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndCheck32_52SyndSpec; +impl crate::RegisterSpec for SyndCheck32_52SyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_check_32_52_synd::R`](R) reader structure"] +impl crate::Readable for SyndCheck32_52SyndSpec {} +#[doc = "`reset()` method sets SYND_CHECK_32_52_SYND to value 0"] +impl crate::Resettable for SyndCheck32_52SyndSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/synd_data.rs b/va416xx/src/utility/synd_data.rs new file mode 100644 index 0000000..044ed82 --- /dev/null +++ b/va416xx/src/utility/synd_data.rs @@ -0,0 +1,27 @@ +#[doc = "Register `SYND_DATA` reader"] +pub type R = crate::R; +#[doc = "Register `SYND_DATA` writer"] +pub type W = crate::W; +impl core::fmt::Debug for R { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + write!(f, "{}", self.bits()) + } +} +impl W {} +#[doc = "Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_data::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndDataSpec; +impl crate::RegisterSpec for SyndDataSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_data::R`](R) reader structure"] +impl crate::Readable for SyndDataSpec {} +#[doc = "`write(|w| ..)` method takes [`synd_data::W`](W) writer structure"] +impl crate::Writable for SyndDataSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYND_DATA to value 0"] +impl crate::Resettable for SyndDataSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/synd_enc_32_44.rs b/va416xx/src/utility/synd_enc_32_44.rs new file mode 100644 index 0000000..adc5116 --- /dev/null +++ b/va416xx/src/utility/synd_enc_32_44.rs @@ -0,0 +1,55 @@ +#[doc = "Register `SYND_ENC_32_44` reader"] +pub type R = crate::R; +#[doc = "Register `SYND_ENC_32_44` writer"] +pub type W = crate::W; +#[doc = "Field `SYND_ENC_7_0` reader - Computed syndrome value for bits 15-0"] +pub type SyndEnc7_0R = crate::FieldReader; +#[doc = "Field `SYND_ENC_7_0` writer - Computed syndrome value for bits 15-0"] +pub type SyndEnc7_0W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +#[doc = "Field `SYND_ENC_31_16` reader - Computed syndrome value for bits 31-16"] +pub type SyndEnc31_16R = crate::FieldReader; +#[doc = "Field `SYND_ENC_31_16` writer - Computed syndrome value for bits 31-16"] +pub type SyndEnc31_16W<'a, REG> = crate::FieldWriter<'a, REG, 6>; +impl R { + #[doc = "Bits 0:5 - Computed syndrome value for bits 15-0"] + #[inline(always)] + pub fn synd_enc_7_0(&self) -> SyndEnc7_0R { + SyndEnc7_0R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Computed syndrome value for bits 31-16"] + #[inline(always)] + pub fn synd_enc_31_16(&self) -> SyndEnc31_16R { + SyndEnc31_16R::new(((self.bits >> 6) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Computed syndrome value for bits 15-0"] + #[inline(always)] + #[must_use] + pub fn synd_enc_7_0(&mut self) -> SyndEnc7_0W { + SyndEnc7_0W::new(self, 0) + } + #[doc = "Bits 6:11 - Computed syndrome value for bits 31-16"] + #[inline(always)] + #[must_use] + pub fn synd_enc_31_16(&mut self) -> SyndEnc31_16W { + SyndEnc31_16W::new(self, 6) + } +} +#[doc = "EDAC Encode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_enc_32_44::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_enc_32_44::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndEnc32_44Spec; +impl crate::RegisterSpec for SyndEnc32_44Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_enc_32_44::R`](R) reader structure"] +impl crate::Readable for SyndEnc32_44Spec {} +#[doc = "`write(|w| ..)` method takes [`synd_enc_32_44::W`](W) writer structure"] +impl crate::Writable for SyndEnc32_44Spec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYND_ENC_32_44 to value 0"] +impl crate::Resettable for SyndEnc32_44Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/synd_enc_32_52.rs b/va416xx/src/utility/synd_enc_32_52.rs new file mode 100644 index 0000000..a8abc21 --- /dev/null +++ b/va416xx/src/utility/synd_enc_32_52.rs @@ -0,0 +1,22 @@ +#[doc = "Register `SYND_ENC_32_52` reader"] +pub type R = crate::R; +#[doc = "Field `SYND_ENC_32_52` reader - Computed syndrome value for bits 15-0"] +pub type SyndEnc32_52R = crate::FieldReader; +impl R { + #[doc = "Bits 0:19 - Computed syndrome value for bits 15-0"] + #[inline(always)] + pub fn synd_enc_32_52(&self) -> SyndEnc32_52R { + SyndEnc32_52R::new(self.bits & 0x000f_ffff) + } +} +#[doc = "EDAC Encode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_enc_32_52::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndEnc32_52Spec; +impl crate::RegisterSpec for SyndEnc32_52Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_enc_32_52::R`](R) reader structure"] +impl crate::Readable for SyndEnc32_52Spec {} +#[doc = "`reset()` method sets SYND_ENC_32_52 to value 0"] +impl crate::Resettable for SyndEnc32_52Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/utility/synd_synd.rs b/va416xx/src/utility/synd_synd.rs new file mode 100644 index 0000000..be106b1 --- /dev/null +++ b/va416xx/src/utility/synd_synd.rs @@ -0,0 +1,40 @@ +#[doc = "Register `SYND_SYND` reader"] +pub type R = crate::R; +#[doc = "Register `SYND_SYND` writer"] +pub type W = crate::W; +#[doc = "Field `SYND_SYND` reader - Provides bits 11:0 for syndrome, 2x6-bit"] +pub type SyndSyndR = crate::FieldReader; +#[doc = "Field `SYND_SYND` writer - Provides bits 11:0 for syndrome, 2x6-bit"] +pub type SyndSyndW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>; +impl R { + #[doc = "Bits 0:11 - Provides bits 11:0 for syndrome, 2x6-bit"] + #[inline(always)] + pub fn synd_synd(&self) -> SyndSyndR { + SyndSyndR::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Provides bits 11:0 for syndrome, 2x6-bit"] + #[inline(always)] + #[must_use] + pub fn synd_synd(&mut self) -> SyndSyndW { + SyndSyndW::new(self, 0) + } +} +#[doc = "Syndrome Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`synd_synd::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`synd_synd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct SyndSyndSpec; +impl crate::RegisterSpec for SyndSyndSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`synd_synd::R`](R) reader structure"] +impl crate::Readable for SyndSyndSpec {} +#[doc = "`write(|w| ..)` method takes [`synd_synd::W`](W) writer structure"] +impl crate::Writable for SyndSyndSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets SYND_SYND to value 0"] +impl crate::Resettable for SyndSyndSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/watch_dog.rs b/va416xx/src/watch_dog.rs new file mode 100644 index 0000000..2ec0e75 --- /dev/null +++ b/va416xx/src/watch_dog.rs @@ -0,0 +1,213 @@ +#[repr(C)] +#[doc = "Register block"] +pub struct RegisterBlock { + wdogload: Wdogload, + wdogvalue: Wdogvalue, + wdogcontrol: Wdogcontrol, + wdogintclr: Wdogintclr, + wdogris: Wdogris, + wdogmis: Wdogmis, + _reserved6: [u8; 0xa8], + wdoglock: Wdoglock, + _reserved7: [u8; 0x0e3c], + wdogitcr: Wdogitcr, + wdogitop: Wdogitop, + _reserved9: [u8; 0xd8], + wdogperiphid0: Wdogperiphid0, + wdogperiphid1: Wdogperiphid1, + wdogperiphid2: Wdogperiphid2, + wdogperiphid3: Wdogperiphid3, + wdogpcellid0: Wdogpcellid0, + wdogpcellid1: Wdogpcellid1, + wdogpcellid2: Wdogpcellid2, + wdogpcellid3: Wdogpcellid3, +} +impl RegisterBlock { + #[doc = "0x00 - Counter Start Value"] + #[inline(always)] + pub const fn wdogload(&self) -> &Wdogload { + &self.wdogload + } + #[doc = "0x04 - Down Counter Value"] + #[inline(always)] + pub const fn wdogvalue(&self) -> &Wdogvalue { + &self.wdogvalue + } + #[doc = "0x08 - Enable for block reset and interrupt"] + #[inline(always)] + pub const fn wdogcontrol(&self) -> &Wdogcontrol { + &self.wdogcontrol + } + #[doc = "0x0c - A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register"] + #[inline(always)] + pub const fn wdogintclr(&self) -> &Wdogintclr { + &self.wdogintclr + } + #[doc = "0x10 - Raw interrupt status"] + #[inline(always)] + pub const fn wdogris(&self) -> &Wdogris { + &self.wdogris + } + #[doc = "0x14 - Interrupt status"] + #[inline(always)] + pub const fn wdogmis(&self) -> &Wdogmis { + &self.wdogmis + } + #[doc = "0xc0 - Lock"] + #[inline(always)] + pub const fn wdoglock(&self) -> &Wdoglock { + &self.wdoglock + } + #[doc = "0xf00 - Integration test control"] + #[inline(always)] + pub const fn wdogitcr(&self) -> &Wdogitcr { + &self.wdogitcr + } + #[doc = "0xf04 - Integration test output set"] + #[inline(always)] + pub const fn wdogitop(&self) -> &Wdogitop { + &self.wdogitop + } + #[doc = "0xfe0 - Peripheral ID"] + #[inline(always)] + pub const fn wdogperiphid0(&self) -> &Wdogperiphid0 { + &self.wdogperiphid0 + } + #[doc = "0xfe4 - Peripheral ID"] + #[inline(always)] + pub const fn wdogperiphid1(&self) -> &Wdogperiphid1 { + &self.wdogperiphid1 + } + #[doc = "0xfe8 - Peripheral ID"] + #[inline(always)] + pub const fn wdogperiphid2(&self) -> &Wdogperiphid2 { + &self.wdogperiphid2 + } + #[doc = "0xfec - Peripheral ID"] + #[inline(always)] + pub const fn wdogperiphid3(&self) -> &Wdogperiphid3 { + &self.wdogperiphid3 + } + #[doc = "0xff0 - PrimeCell ID"] + #[inline(always)] + pub const fn wdogpcellid0(&self) -> &Wdogpcellid0 { + &self.wdogpcellid0 + } + #[doc = "0xff4 - PrimeCell ID"] + #[inline(always)] + pub const fn wdogpcellid1(&self) -> &Wdogpcellid1 { + &self.wdogpcellid1 + } + #[doc = "0xff8 - PrimeCell ID"] + #[inline(always)] + pub const fn wdogpcellid2(&self) -> &Wdogpcellid2 { + &self.wdogpcellid2 + } + #[doc = "0xffc - PrimeCell ID"] + #[inline(always)] + pub const fn wdogpcellid3(&self) -> &Wdogpcellid3 { + &self.wdogpcellid3 + } +} +#[doc = "WDOGLOAD (rw) register accessor: Counter Start Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogload::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdogload::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogload`] +module"] +#[doc(alias = "WDOGLOAD")] +pub type Wdogload = crate::Reg; +#[doc = "Counter Start Value"] +pub mod wdogload; +#[doc = "WDOGVALUE (r) register accessor: Down Counter Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogvalue::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogvalue`] +module"] +#[doc(alias = "WDOGVALUE")] +pub type Wdogvalue = crate::Reg; +#[doc = "Down Counter Value"] +pub mod wdogvalue; +#[doc = "WDOGCONTROL (rw) register accessor: Enable for block reset and interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogcontrol::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdogcontrol::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogcontrol`] +module"] +#[doc(alias = "WDOGCONTROL")] +pub type Wdogcontrol = crate::Reg; +#[doc = "Enable for block reset and interrupt"] +pub mod wdogcontrol; +#[doc = "WDOGINTCLR (rw) register accessor: A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogintclr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdogintclr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogintclr`] +module"] +#[doc(alias = "WDOGINTCLR")] +pub type Wdogintclr = crate::Reg; +#[doc = "A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register"] +pub mod wdogintclr; +#[doc = "WDOGRIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogris`] +module"] +#[doc(alias = "WDOGRIS")] +pub type Wdogris = crate::Reg; +#[doc = "Raw interrupt status"] +pub mod wdogris; +#[doc = "WDOGMIS (r) register accessor: Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogmis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogmis`] +module"] +#[doc(alias = "WDOGMIS")] +pub type Wdogmis = crate::Reg; +#[doc = "Interrupt status"] +pub mod wdogmis; +#[doc = "WDOGLOCK (rw) register accessor: Lock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdoglock::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdoglock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdoglock`] +module"] +#[doc(alias = "WDOGLOCK")] +pub type Wdoglock = crate::Reg; +#[doc = "Lock"] +pub mod wdoglock; +#[doc = "WDOGITCR (rw) register accessor: Integration test control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogitcr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdogitcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogitcr`] +module"] +#[doc(alias = "WDOGITCR")] +pub type Wdogitcr = crate::Reg; +#[doc = "Integration test control"] +pub mod wdogitcr; +#[doc = "WDOGITOP (rw) register accessor: Integration test output set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogitop::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdogitop::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogitop`] +module"] +#[doc(alias = "WDOGITOP")] +pub type Wdogitop = crate::Reg; +#[doc = "Integration test output set"] +pub mod wdogitop; +#[doc = "WDOGPERIPHID0 (r) register accessor: Peripheral ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogperiphid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogperiphid0`] +module"] +#[doc(alias = "WDOGPERIPHID0")] +pub type Wdogperiphid0 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid0; +#[doc = "WDOGPERIPHID1 (r) register accessor: Peripheral ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogperiphid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogperiphid1`] +module"] +#[doc(alias = "WDOGPERIPHID1")] +pub type Wdogperiphid1 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid1; +#[doc = "WDOGPERIPHID2 (r) register accessor: Peripheral ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogperiphid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogperiphid2`] +module"] +#[doc(alias = "WDOGPERIPHID2")] +pub type Wdogperiphid2 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid2; +#[doc = "WDOGPERIPHID3 (r) register accessor: Peripheral ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogperiphid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogperiphid3`] +module"] +#[doc(alias = "WDOGPERIPHID3")] +pub type Wdogperiphid3 = crate::Reg; +#[doc = "Peripheral ID"] +pub mod wdogperiphid3; +#[doc = "WDOGPCELLID0 (r) register accessor: PrimeCell ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogpcellid0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogpcellid0`] +module"] +#[doc(alias = "WDOGPCELLID0")] +pub type Wdogpcellid0 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid0; +#[doc = "WDOGPCELLID1 (r) register accessor: PrimeCell ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogpcellid1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogpcellid1`] +module"] +#[doc(alias = "WDOGPCELLID1")] +pub type Wdogpcellid1 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid1; +#[doc = "WDOGPCELLID2 (r) register accessor: PrimeCell ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogpcellid2::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogpcellid2`] +module"] +#[doc(alias = "WDOGPCELLID2")] +pub type Wdogpcellid2 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid2; +#[doc = "WDOGPCELLID3 (r) register accessor: PrimeCell ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogpcellid3::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wdogpcellid3`] +module"] +#[doc(alias = "WDOGPCELLID3")] +pub type Wdogpcellid3 = crate::Reg; +#[doc = "PrimeCell ID"] +pub mod wdogpcellid3; diff --git a/va416xx/src/watch_dog/wdogcontrol.rs b/va416xx/src/watch_dog/wdogcontrol.rs new file mode 100644 index 0000000..3749f4f --- /dev/null +++ b/va416xx/src/watch_dog/wdogcontrol.rs @@ -0,0 +1,55 @@ +#[doc = "Register `WDOGCONTROL` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGCONTROL` writer"] +pub type W = crate::W; +#[doc = "Field `INTEN` reader - Enable watchdog interrupt"] +pub type IntenR = crate::BitReader; +#[doc = "Field `INTEN` writer - Enable watchdog interrupt"] +pub type IntenW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `RESEN` reader - Enable watchdog reset output"] +pub type ResenR = crate::BitReader; +#[doc = "Field `RESEN` writer - Enable watchdog reset output"] +pub type ResenW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable watchdog interrupt"] + #[inline(always)] + pub fn inten(&self) -> IntenR { + IntenR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable watchdog reset output"] + #[inline(always)] + pub fn resen(&self) -> ResenR { + ResenR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable watchdog interrupt"] + #[inline(always)] + #[must_use] + pub fn inten(&mut self) -> IntenW { + IntenW::new(self, 0) + } + #[doc = "Bit 1 - Enable watchdog reset output"] + #[inline(always)] + #[must_use] + pub fn resen(&mut self) -> ResenW { + ResenW::new(self, 1) + } +} +#[doc = "Enable for block reset and interrupt\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogcontrol::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdogcontrol::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogcontrolSpec; +impl crate::RegisterSpec for WdogcontrolSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogcontrol::R`](R) reader structure"] +impl crate::Readable for WdogcontrolSpec {} +#[doc = "`write(|w| ..)` method takes [`wdogcontrol::W`](W) writer structure"] +impl crate::Writable for WdogcontrolSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDOGCONTROL to value 0"] +impl crate::Resettable for WdogcontrolSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/watch_dog/wdogintclr.rs b/va416xx/src/watch_dog/wdogintclr.rs new file mode 100644 index 0000000..e4e036c --- /dev/null +++ b/va416xx/src/watch_dog/wdogintclr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WDOGINTCLR` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGINTCLR` writer"] +pub type W = crate::W; +#[doc = "Field `CLEAR` reader - Write any value to clear interrupt"] +pub type ClearR = crate::FieldReader; +#[doc = "Field `CLEAR` writer - Write any value to clear interrupt"] +pub type ClearW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Write any value to clear interrupt"] + #[inline(always)] + pub fn clear(&self) -> ClearR { + ClearR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Write any value to clear interrupt"] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> ClearW { + ClearW::new(self, 0) + } +} +#[doc = "A write of any value clears the WDT module interrupt, and reloads the counter from the value in the WDOGLOAD Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogintclr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdogintclr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogintclrSpec; +impl crate::RegisterSpec for WdogintclrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogintclr::R`](R) reader structure"] +impl crate::Readable for WdogintclrSpec {} +#[doc = "`write(|w| ..)` method takes [`wdogintclr::W`](W) writer structure"] +impl crate::Writable for WdogintclrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDOGINTCLR to value 0"] +impl crate::Resettable for WdogintclrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/watch_dog/wdogitcr.rs b/va416xx/src/watch_dog/wdogitcr.rs new file mode 100644 index 0000000..682fa54 --- /dev/null +++ b/va416xx/src/watch_dog/wdogitcr.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WDOGITCR` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGITCR` writer"] +pub type W = crate::W; +#[doc = "Field `TEST_MODE_EN` reader - Enable test mode of WDOGINT and WDOGRES"] +pub type TestModeEnR = crate::BitReader; +#[doc = "Field `TEST_MODE_EN` writer - Enable test mode of WDOGINT and WDOGRES"] +pub type TestModeEnW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Enable test mode of WDOGINT and WDOGRES"] + #[inline(always)] + pub fn test_mode_en(&self) -> TestModeEnR { + TestModeEnR::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Enable test mode of WDOGINT and WDOGRES"] + #[inline(always)] + #[must_use] + pub fn test_mode_en(&mut self) -> TestModeEnW { + TestModeEnW::new(self, 0) + } +} +#[doc = "Integration test control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogitcr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdogitcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogitcrSpec; +impl crate::RegisterSpec for WdogitcrSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogitcr::R`](R) reader structure"] +impl crate::Readable for WdogitcrSpec {} +#[doc = "`write(|w| ..)` method takes [`wdogitcr::W`](W) writer structure"] +impl crate::Writable for WdogitcrSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDOGITCR to value 0"] +impl crate::Resettable for WdogitcrSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/watch_dog/wdogitop.rs b/va416xx/src/watch_dog/wdogitop.rs new file mode 100644 index 0000000..25eedbe --- /dev/null +++ b/va416xx/src/watch_dog/wdogitop.rs @@ -0,0 +1,55 @@ +#[doc = "Register `WDOGITOP` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGITOP` writer"] +pub type W = crate::W; +#[doc = "Field `WDOGRES` reader - Set output value"] +pub type WdogresR = crate::BitReader; +#[doc = "Field `WDOGRES` writer - Set output value"] +pub type WdogresW<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `WDOGINT` reader - Set output value"] +pub type WdogintR = crate::BitReader; +#[doc = "Field `WDOGINT` writer - Set output value"] +pub type WdogintW<'a, REG> = crate::BitWriter<'a, REG>; +impl R { + #[doc = "Bit 0 - Set output value"] + #[inline(always)] + pub fn wdogres(&self) -> WdogresR { + WdogresR::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Set output value"] + #[inline(always)] + pub fn wdogint(&self) -> WdogintR { + WdogintR::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Set output value"] + #[inline(always)] + #[must_use] + pub fn wdogres(&mut self) -> WdogresW { + WdogresW::new(self, 0) + } + #[doc = "Bit 1 - Set output value"] + #[inline(always)] + #[must_use] + pub fn wdogint(&mut self) -> WdogintW { + WdogintW::new(self, 1) + } +} +#[doc = "Integration test output set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogitop::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdogitop::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogitopSpec; +impl crate::RegisterSpec for WdogitopSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogitop::R`](R) reader structure"] +impl crate::Readable for WdogitopSpec {} +#[doc = "`write(|w| ..)` method takes [`wdogitop::W`](W) writer structure"] +impl crate::Writable for WdogitopSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDOGITOP to value 0"] +impl crate::Resettable for WdogitopSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/watch_dog/wdogload.rs b/va416xx/src/watch_dog/wdogload.rs new file mode 100644 index 0000000..4d21910 --- /dev/null +++ b/va416xx/src/watch_dog/wdogload.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WDOGLOAD` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGLOAD` writer"] +pub type W = crate::W; +#[doc = "Field `CNT` reader - Count to load"] +pub type CntR = crate::FieldReader; +#[doc = "Field `CNT` writer - Count to load"] +pub type CntW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Count to load"] + #[inline(always)] + pub fn cnt(&self) -> CntR { + CntR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Count to load"] + #[inline(always)] + #[must_use] + pub fn cnt(&mut self) -> CntW { + CntW::new(self, 0) + } +} +#[doc = "Counter Start Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogload::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdogload::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogloadSpec; +impl crate::RegisterSpec for WdogloadSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogload::R`](R) reader structure"] +impl crate::Readable for WdogloadSpec {} +#[doc = "`write(|w| ..)` method takes [`wdogload::W`](W) writer structure"] +impl crate::Writable for WdogloadSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDOGLOAD to value 0xffff_ffff"] +impl crate::Resettable for WdogloadSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va416xx/src/watch_dog/wdoglock.rs b/va416xx/src/watch_dog/wdoglock.rs new file mode 100644 index 0000000..c92b686 --- /dev/null +++ b/va416xx/src/watch_dog/wdoglock.rs @@ -0,0 +1,40 @@ +#[doc = "Register `WDOGLOCK` reader"] +pub type R = crate::R; +#[doc = "Register `WDOGLOCK` writer"] +pub type W = crate::W; +#[doc = "Field `REG_WR_EN` reader - Register write enable status"] +pub type RegWrEnR = crate::FieldReader; +#[doc = "Field `REG_WR_EN` writer - Register write enable status"] +pub type RegWrEnW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>; +impl R { + #[doc = "Bits 0:31 - Register write enable status"] + #[inline(always)] + pub fn reg_wr_en(&self) -> RegWrEnR { + RegWrEnR::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Register write enable status"] + #[inline(always)] + #[must_use] + pub fn reg_wr_en(&mut self) -> RegWrEnW { + RegWrEnW::new(self, 0) + } +} +#[doc = "Lock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdoglock::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wdoglock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdoglockSpec; +impl crate::RegisterSpec for WdoglockSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdoglock::R`](R) reader structure"] +impl crate::Readable for WdoglockSpec {} +#[doc = "`write(|w| ..)` method takes [`wdoglock::W`](W) writer structure"] +impl crate::Writable for WdoglockSpec { + type Safety = crate::Unsafe; + const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0; +} +#[doc = "`reset()` method sets WDOGLOCK to value 0"] +impl crate::Resettable for WdoglockSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/watch_dog/wdogmis.rs b/va416xx/src/watch_dog/wdogmis.rs new file mode 100644 index 0000000..94b8e40 --- /dev/null +++ b/va416xx/src/watch_dog/wdogmis.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGMIS` reader"] +pub type R = crate::R; +#[doc = "Field `INTERRUPT` reader - Masked Interrupt Status"] +pub type InterruptR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Masked Interrupt Status"] + #[inline(always)] + pub fn interrupt(&self) -> InterruptR { + InterruptR::new((self.bits & 1) != 0) + } +} +#[doc = "Interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogmis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogmisSpec; +impl crate::RegisterSpec for WdogmisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogmis::R`](R) reader structure"] +impl crate::Readable for WdogmisSpec {} +#[doc = "`reset()` method sets WDOGMIS to value 0"] +impl crate::Resettable for WdogmisSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/watch_dog/wdogpcellid0.rs b/va416xx/src/watch_dog/wdogpcellid0.rs new file mode 100644 index 0000000..3e9b39b --- /dev/null +++ b/va416xx/src/watch_dog/wdogpcellid0.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPCELLID0` reader"] +pub type R = crate::R; +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub type PcellidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PcellidR { + PcellidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogpcellid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogpcellid0Spec; +impl crate::RegisterSpec for Wdogpcellid0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogpcellid0::R`](R) reader structure"] +impl crate::Readable for Wdogpcellid0Spec {} +#[doc = "`reset()` method sets WDOGPCELLID0 to value 0x0d"] +impl crate::Resettable for Wdogpcellid0Spec { + const RESET_VALUE: u32 = 0x0d; +} diff --git a/va416xx/src/watch_dog/wdogpcellid1.rs b/va416xx/src/watch_dog/wdogpcellid1.rs new file mode 100644 index 0000000..33483b0 --- /dev/null +++ b/va416xx/src/watch_dog/wdogpcellid1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPCELLID1` reader"] +pub type R = crate::R; +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub type PcellidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PcellidR { + PcellidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogpcellid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogpcellid1Spec; +impl crate::RegisterSpec for Wdogpcellid1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogpcellid1::R`](R) reader structure"] +impl crate::Readable for Wdogpcellid1Spec {} +#[doc = "`reset()` method sets WDOGPCELLID1 to value 0xf0"] +impl crate::Resettable for Wdogpcellid1Spec { + const RESET_VALUE: u32 = 0xf0; +} diff --git a/va416xx/src/watch_dog/wdogpcellid2.rs b/va416xx/src/watch_dog/wdogpcellid2.rs new file mode 100644 index 0000000..d1c1831 --- /dev/null +++ b/va416xx/src/watch_dog/wdogpcellid2.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPCELLID2` reader"] +pub type R = crate::R; +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub type PcellidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PcellidR { + PcellidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogpcellid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogpcellid2Spec; +impl crate::RegisterSpec for Wdogpcellid2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogpcellid2::R`](R) reader structure"] +impl crate::Readable for Wdogpcellid2Spec {} +#[doc = "`reset()` method sets WDOGPCELLID2 to value 0x05"] +impl crate::Resettable for Wdogpcellid2Spec { + const RESET_VALUE: u32 = 0x05; +} diff --git a/va416xx/src/watch_dog/wdogpcellid3.rs b/va416xx/src/watch_dog/wdogpcellid3.rs new file mode 100644 index 0000000..ae59c49 --- /dev/null +++ b/va416xx/src/watch_dog/wdogpcellid3.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPCELLID3` reader"] +pub type R = crate::R; +#[doc = "Field `PCELLID` reader - Prime Cell ID"] +pub type PcellidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Prime Cell ID"] + #[inline(always)] + pub fn pcellid(&self) -> PcellidR { + PcellidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "PrimeCell ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogpcellid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogpcellid3Spec; +impl crate::RegisterSpec for Wdogpcellid3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogpcellid3::R`](R) reader structure"] +impl crate::Readable for Wdogpcellid3Spec {} +#[doc = "`reset()` method sets WDOGPCELLID3 to value 0xb1"] +impl crate::Resettable for Wdogpcellid3Spec { + const RESET_VALUE: u32 = 0xb1; +} diff --git a/va416xx/src/watch_dog/wdogperiphid0.rs b/va416xx/src/watch_dog/wdogperiphid0.rs new file mode 100644 index 0000000..8bad2f1 --- /dev/null +++ b/va416xx/src/watch_dog/wdogperiphid0.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPERIPHID0` reader"] +pub type R = crate::R; +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub type PeriphidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PeriphidR { + PeriphidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogperiphid0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogperiphid0Spec; +impl crate::RegisterSpec for Wdogperiphid0Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogperiphid0::R`](R) reader structure"] +impl crate::Readable for Wdogperiphid0Spec {} +#[doc = "`reset()` method sets WDOGPERIPHID0 to value 0x24"] +impl crate::Resettable for Wdogperiphid0Spec { + const RESET_VALUE: u32 = 0x24; +} diff --git a/va416xx/src/watch_dog/wdogperiphid1.rs b/va416xx/src/watch_dog/wdogperiphid1.rs new file mode 100644 index 0000000..d4ca76a --- /dev/null +++ b/va416xx/src/watch_dog/wdogperiphid1.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPERIPHID1` reader"] +pub type R = crate::R; +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub type PeriphidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PeriphidR { + PeriphidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogperiphid1::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogperiphid1Spec; +impl crate::RegisterSpec for Wdogperiphid1Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogperiphid1::R`](R) reader structure"] +impl crate::Readable for Wdogperiphid1Spec {} +#[doc = "`reset()` method sets WDOGPERIPHID1 to value 0xb8"] +impl crate::Resettable for Wdogperiphid1Spec { + const RESET_VALUE: u32 = 0xb8; +} diff --git a/va416xx/src/watch_dog/wdogperiphid2.rs b/va416xx/src/watch_dog/wdogperiphid2.rs new file mode 100644 index 0000000..c277ee4 --- /dev/null +++ b/va416xx/src/watch_dog/wdogperiphid2.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPERIPHID2` reader"] +pub type R = crate::R; +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub type PeriphidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PeriphidR { + PeriphidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogperiphid2::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogperiphid2Spec; +impl crate::RegisterSpec for Wdogperiphid2Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogperiphid2::R`](R) reader structure"] +impl crate::Readable for Wdogperiphid2Spec {} +#[doc = "`reset()` method sets WDOGPERIPHID2 to value 0x1b"] +impl crate::Resettable for Wdogperiphid2Spec { + const RESET_VALUE: u32 = 0x1b; +} diff --git a/va416xx/src/watch_dog/wdogperiphid3.rs b/va416xx/src/watch_dog/wdogperiphid3.rs new file mode 100644 index 0000000..1ec1ad4 --- /dev/null +++ b/va416xx/src/watch_dog/wdogperiphid3.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGPERIPHID3` reader"] +pub type R = crate::R; +#[doc = "Field `PERIPHID` reader - Peripheral ID"] +pub type PeriphidR = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Peripheral ID"] + #[inline(always)] + pub fn periphid(&self) -> PeriphidR { + PeriphidR::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral ID\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogperiphid3::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct Wdogperiphid3Spec; +impl crate::RegisterSpec for Wdogperiphid3Spec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogperiphid3::R`](R) reader structure"] +impl crate::Readable for Wdogperiphid3Spec {} +#[doc = "`reset()` method sets WDOGPERIPHID3 to value 0"] +impl crate::Resettable for Wdogperiphid3Spec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/watch_dog/wdogris.rs b/va416xx/src/watch_dog/wdogris.rs new file mode 100644 index 0000000..3e8dfd4 --- /dev/null +++ b/va416xx/src/watch_dog/wdogris.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGRIS` reader"] +pub type R = crate::R; +#[doc = "Field `INTERRUPT` reader - Interrupt Status"] +pub type InterruptR = crate::BitReader; +impl R { + #[doc = "Bit 0 - Interrupt Status"] + #[inline(always)] + pub fn interrupt(&self) -> InterruptR { + InterruptR::new((self.bits & 1) != 0) + } +} +#[doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogris::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogrisSpec; +impl crate::RegisterSpec for WdogrisSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogris::R`](R) reader structure"] +impl crate::Readable for WdogrisSpec {} +#[doc = "`reset()` method sets WDOGRIS to value 0"] +impl crate::Resettable for WdogrisSpec { + const RESET_VALUE: u32 = 0; +} diff --git a/va416xx/src/watch_dog/wdogvalue.rs b/va416xx/src/watch_dog/wdogvalue.rs new file mode 100644 index 0000000..cf1335e --- /dev/null +++ b/va416xx/src/watch_dog/wdogvalue.rs @@ -0,0 +1,22 @@ +#[doc = "Register `WDOGVALUE` reader"] +pub type R = crate::R; +#[doc = "Field `CNT` reader - Actual Count"] +pub type CntR = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Actual Count"] + #[inline(always)] + pub fn cnt(&self) -> CntR { + CntR::new(self.bits) + } +} +#[doc = "Down Counter Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wdogvalue::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct WdogvalueSpec; +impl crate::RegisterSpec for WdogvalueSpec { + type Ux = u32; +} +#[doc = "`read()` method returns [`wdogvalue::R`](R) reader structure"] +impl crate::Readable for WdogvalueSpec {} +#[doc = "`reset()` method sets WDOGVALUE to value 0xffff_ffff"] +impl crate::Resettable for WdogvalueSpec { + const RESET_VALUE: u32 = 0xffff_ffff; +} diff --git a/va416xx/svd/va416xx-patch.yml b/va416xx/svd/va416xx-patch.yml new file mode 100644 index 0000000..3eae97a --- /dev/null +++ b/va416xx/svd/va416xx-patch.yml @@ -0,0 +1,8 @@ +_svd: va416xx.svd + +# Read-only access for a write-only register does not really make sense.. +DMA: + CFG: + _modify: + MASTER_ENABLE: + access: read-write diff --git a/va416xx/svd/va416xx.svd b/va416xx/svd/va416xx.svd new file mode 100644 index 0000000..8427204 --- /dev/null +++ b/va416xx/svd/va416xx.svd @@ -0,0 +1,12884 @@ + + + VORAGO TECHNOLOGIES + SST + va416xx + M4 + 1.3 + + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 100MHz + + VORAGO Technologies \n +\n +----------------------------------------------------------------------------\n + Copyright (c) 2013-2020 VORAGO Technologies\n +\n + BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND BY ALL THE TERMS\n + AND CONDITIONS OF THE VORAGO TECHNOLOGIES END USER LICENSE AGREEMENT. \n +\n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + VORAGO TECHNOLOGIES SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE\n + FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n + + + CM4 + r0p1 + little + false + true + 4 + false + + system_va416xx + VOR_ + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + + CLKGEN + 1.0 + Clock Generation Peripheral + 0x40006000 + + 0 + 0x00000100 + registers + + + LoCLK + 45 + + + + CTRL0 + Clock Generation Module Control Register 0 + 0x000 + 0x00000030 + + + SYS_CLK_LOST_DET_EN + Enable the circuit that detects loss of SYS_CLK + [31:31] + + + PLL_RESET + Writing this bit to 1 puts the PLL into reset + [30:30] + + + CLK_DIV_SEL + Selects the PLL out divider to divide by 1/2/4/8 + [29:28] + + + PLL_CLKR + PLL Symbol; selects the values 1-16 for the reference divider + [27:24] + + + PLL_CLKF + PLL Symbol; selects the values 1-64 for the multiplication factor + [23:18] + + + PLL_CLKOD + PLL Symbol; selects the values 1-16 for the post VCO divider + [17:14] + + + PLL_BWADJ + PLL Symbol; selects the values 1-64 for the bandwidth divider + [13:8] + + + PLL_TEST + PLL Symbol; Reference-to-counters-to-output bypass when high + [7:7] + + + PLL_BYPASS + PLL Symbol; reference-to-output bypass when high + [6:6] + + + PLL_PWDN + PLL Symbol; power down when high + [5:5] + + + PLL_INTFB + PLL Symbol; select internal feedback path when high rather than FCLK + [4:4] + + + CLKSEL_SYS + Input clock select to PLL + [3:2] + + + REF_CLK_SEL + PLL Reference Clock Select + [1:0] + + + + + STAT + Clock Generation Module Status Register + 0x004 + read-only + 0x00000000 + + + SYSCLKLOST + Set when SYS_CLK has dropped to less than 1MHz + [3:3] + read-only + + + LOCKLOST + LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles + [2:2] + read-only + + + RFSLIP + Reference cycle slip output (CLKOUT frequency high) + [1:1] + read-only + + + FBSLIP + Feedback cycle slip output (CLKOUT frequency low) + [0:0] + read-only + + + + + CTRL1 + Clock Generation Module Control Register 1 + 0x008 + read-write + 0x00000000 + + + ADC_CLK_DIV_SEL + Clock divider select for ADC + [6:5] + + + XTAL_N_EN + Enables XTAL_N output + [4:4] + + + XTAL_EN + Enables the crystal oscillator + [3:3] + + + PLL_LOST_LOCK_DET_EN + Enables the PLL lock lost detection circuit + [2:2] + + + PLL_LCK_DET_REARM + Resets/Rearms the PLL lock detect circuit + [1:1] + + + SYS_CLK_LOST_DET_REARM + Resets/Rearms the SYS_CLK lost detection feature + [0:0] + + + + + + + + SYSCONFIG + 1.0 + System Configuration Peripheral + 0x40010000 + + 0 + 0x00001000 + registers + + + LVD + 46 + + + EDAC_MBE + 76 + + + EDAC_SBE + 77 + + + + RST_STAT + System Reset Status + 0x000 + read-write + 0x00000000 + + + POR + Power On Reset Status + [0:0] + + + EXTRST + External Reset Status + [1:1] + + + SYSRSTREQ + SYSRESETREQ Reset Status + [2:2] + + + LOOKUP + LOOKUP Reset Status + [3:3] + + + WATCHDOG + WATCHDOG Reset Status + [4:4] + + + MEMERR + Memory Error Reset Status + [5:5] + read-only + + + + + RST_CNTL_ROM + ROM Reset Control + 0x004 + 0x0000003F + + + RST_CNTL_RAM0 + RAM Reset Control + 0x008 + 0x0000003F + + + RST_CNTL_RAM1 + RAM Reset Control + 0x00C + 0x0000003F + + + ROM_PROT + ROM Protection Configuration + 0x010 + 0x00000000 + + + WREN + ROM Write Enable Bit + [0:0] + + + + + ROM_SCRUB + ROM Scrub Period Configuration + 0x014 + read-write + 0x00000000 + + + VALUE + Counter divide value + [23:0] + + + RESET + Reset Counter + [31:31] + write-only + + oneToClear + + + + + + RAM0_SCRUB + RAM0 Scrub Period Configuration + 0x018 + + + RAM1_SCRUB + RAM1 Scrub Period Configuration + 0x01C + + + IRQ_ENB + Enable EDAC Error Interrupt Register + 0x020 + read-write + 0x00000000 + + + ROMMBE + ROM Multi Bit Interrupt + [0:0] + + + ROMSBE + ROM Single Bit Interrupt + [1:1] + + + RAM0MBE + RAM0 Multi Bit Interrupt + [2:2] + + + RAM0SBE + RAM0 Single Bit Interrupt + [3:3] + + + RAM1MBE + RAM1 Multi Bit Interrupt + [4:4] + + + RAM1SBE + RAM1 Single Bit Interrupt + [5:5] + + + + + IRQ_RAW + Raw EDAC Error Interrupt Status + 0x024 + read-only + 0x00000000 + + + IRQ_END + Enabled EDAC Error Interrupt Status + 0x028 + read-only + 0x00000000 + + + IRQ_CLR + Clear EDAC Error Interrupt Status + 0x02C + write-only + 0x00000000 + + oneToClear + + + + RAM0_SBE + Count of RAM0 EDAC Single Bit Errors + 0x030 + 0x00000000 + + + COUNT + RAM0 EDAC Single Bit Errors + [15:0] + + + + + RAM1_SBE + Count of RAM1 EDAC Single Bit Errors + 0x034 + + + RAM0_MBE + Count of RAM0 EDAC Multi Bit Errors + 0x038 + 0x00000000 + + + COUNT + RAM0 Multi Bit Errors + [15:0] + + + + + RAM1_MBE + Count of RAM1 EDAC Multi Bit Errors + 0x03C + + + ROM_SBE + Count of ROM EDAC Single Bit Errors + 0x040 + + + ROM_MBE + Count of ROM EDAC Multi Bit Errors + 0x044 + + + ROM_RETRIES + ROM BOOT Retry count + 0x048 + read-only + 0x00000000 + + + COUNT + Count of ROM block Retries + [7:0] + + + + + REFRESH_CONFIG_H + Register Refresh Rate for TMR registers + 0x04C + 0x00000000 + + + DIVCOUNT + Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles + [7:0] + + + TESTMODE + Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly. + [31:30] + + + + + TIM_RESET + TIM Reset Control + 0x050 + 0xFFFFFFFF + + + TIM_RESET + Reset of a given TIMER + [23:0] + + + + + TIM_CLK_ENABLE + TIM Enable Control + 0x054 + 0x00000000 + + + TIMERS + Clock enable of a given TIMER + [23:0] + + + + + PERIPHERAL_RESET + Peripheral Reset Control + 0x058 + 0x7F7BEFFF + + + SPI0 + Resetn of SPI0 + [0:0] + + + SPI1 + Resetn of SPI1 + [1:1] + + + SPI2 + Resetn of SPI2 + [2:2] + + + SPI3 + Resetn of SPI3 + [3:3] + + + UART0 + Resetn of UART0 + [4:4] + + + UART1 + Resetn of UART1 + [5:5] + + + UART2 + Resetn of UART2 + [6:6] + + + I2C0 + Resetn of I2C0 + [7:7] + + + I2C1 + Resetn of I2C1 + [8:8] + + + I2C2 + Resetn of I2C2 + [9:9] + + + CAN0 + Resetn of CAN0 + [10:10] + + + CAN1 + Resetn of CAN1 + [11:11] + + + TRNG + Resetn of TRNG + [12:12] + + + ADC + Resetn of ADC + [13:13] + + + DAC + Resetn of DAC + [14:14] + + + DMA + Resetn of DMA + [15:15] + + + EBI + Resetn of EBI + [16:16] + + + ETH + Resetn of Ethernet + [17:17] + + + SPW + Resetn of SpaceWire + [18:18] + + + CLKGEN + RESETn of PLL in Clock Generation Module + [19:19] + + + IRQ + Resetn of IRQ Router + [20:20] + + + IOCONFIG + Resetn of IO CONFIG + [21:21] + + + UTILITY + Resetn of UTILITY peripheral + [22:22] + + + WDOG + Resetn of WDOG + [23:23] + + + PORTA + Resetn of PORTA + [24:24] + + + PORTB + Resetn of PORTB + [25:25] + + + PORTC + Resetn of PORTC + [26:26] + + + PORTD + Resetn of PORTD + [27:27] + + + PORTE + Resetn of PORTE + [28:28] + + + PORTF + Resetn of PORTF + [29:29] + + + PORTG + Resetn of PORTG + [30:30] + + + + + PERIPHERAL_CLK_ENABLE + Peripheral Enable Control + 0x05C + 0x00880000 + + + SPW_M4_CTRL + SPW M4 control register + 0x060 + 0x00030000 + + + LREN + Lockup reset enable + [17:17] + + + SPW_PAD_EN + SPW pad enable + [16:16] + + + REG_WR_KEY + Fuse-analog register writes enabled when key = 0xfeed + [15:0] + + + + + PMU_CTRL + PMU Control Register + 0x064 + 0x00000000 + + + LVL_SLCT + Select the POK detect level + [1:0] + + + + + WAKEUP_CNT + Wakeup Control + 0x068 + 0x00000007 + + + CNTSTRT + Launch SLP mode in analog block + [3:3] + + + WKUP_CNT + Used to set a time to wake up the processor after the device has been put in a low power state + [2:0] + + + + + EBI_CFG0 + EBI Config Register 0 + 0x06C + 0x00000000 + + + ADDRLOW0 + Lower bound address for CEN0 + [7:0] + + + ADDRHIGH0 + Upper bound address for CEN0 + [15:8] + + + CFGREADCYCLE + Number of cycles for a read - N plus 1 + [18:16] + + + CFGWRITECYCLE + Number of cycles for a write - N plus 1 + [21:19] + + + CFGTURNAROUNDCYCLE + Number of cycles for turnaround - N plus 1 + [24:22] + + + CFGSIZE + 8 bit (0) or 16 bit (1) port size + [25:25] + + + + + EBI_CFG1 + EBI Config Register 1 + 0x070 + 0x00000000 + + + EBI_CFG2 + EBI Config Register 2 + 0x074 + 0x00000000 + + + EBI_CFG3 + EBI Config Register 3 + 0x078 + 0x00000000 + + + ANALOG_CNTL + Analog Control Register + 0x07C + 0x00000000 + + + TMOSC + Test Mode + [0:0] + + + TMPOKDIS + Test Mode + [1:1] + + + TM_ADCMUX_N + Test Mode + [2:2] + + + TM_ADCMUX_P + Test Mode + [3:3] + + + TMRATIO + Test Mode + [4:4] + + + TMATOMUX + Test Mode + [6:5] + + + ADC_STEST + Number of clocks for sample time + [12:9] + + + RCLK_POS_EN + Enable normal test clock + [14:14] + + + RCLK_NEG_EN + Enable inverted test clock + [15:15] + + + APB2CLK_POS_EN + Enable normal APB2CLK for test output + [16:16] + + + APB2CLK_NEG_EN + Enable inverted APB2CLK for test output + [17:17] + + + TM_ANALOG_PD_EN + Enables pull down on analog pads + [18:18] + + + JMP2BOOT + Enables a skip of all delay counters and eFuse read + [19:19] + + SKIPBOOT + Enables a skip of all delay counters, eFuse read, and boot + [20:20] + + + + + SW_CLKDIV10 + Initial SpW Clock Divider Value + 0x080 + read-write + 0x00000009 + + + SW_CLKDIV10 + Defines the initial value for the SpW clock, defaults to divide by ten + [7:0] + + + + + REFRESH_CONFIG_L + Register Refresh Rate for TMR registers + 0x084 + read-write + 0x0000000f + + + DIVCOUNT + Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles + [31:0] + + + + + DAC0_CAL + DAC0 Calibration Register + 0xFD0 + read-only + 0x00000000 + + + DAC0_CAL + DAC0 Calibration bits + [4:0] + + + + + DAC1_CAL + DAC1 Calibration Register + 0xFD4 + read-only + 0x00000000 + + + DAC1_CAL + DAC1 Calibration bits + [4:0] + + + + + ADC_CAL + ADC Calibration Register + 0xFD8 + read-only + 0x00000000 + + + ADC_CAL + ADC Calibration bits + [4:0] + + + + + BG_CAL + Bandgap Calibration Register + 0xFDC + read-only + 0x00000000 + + + BG_CAL + Bandgap Calibration bits + [2:0] + + + + + DREG_CAL + Digital LDO Regulator Calibration Register + 0xFE0 + read-only + 0x00000000 + + + DREG_CAL + Digital LDO Regulator Calibration bits + [8:0] + + + + + AREG_CAL + Analog LDO Regulator Calibration Register + 0xFE4 + read-only + 0x00000000 + + + AREG_CAL + Analog LDO Regulator Calibration bits + [8:0] + + + + + HBO_CAL + Heart Beat OSC Calibration Register + 0xFE8 + read-only + 0x00000000 + + + OSC_CAL + 1MHz OSC Calibration bit + [3:3] + + + HBO_CAL + Heart Beat OSC Calibration bits + [2:0] + + + + + EF_CONFIG + EFuse Config Register + 0xFEC + read-only + 0x0A800C40 + + + ROM_SPEED + Specifies the speed of ROM_SCK + [1:0] + + + ROM_SIZE + Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset + [5:2] + + + ROM_NOCHECK + When set to 1, the ROM check is skipped + [6:6] + + + BOOT_DELAY + Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset + [9:7] + + + ROM_READ + SPI ROM read instruction code + [17:10] + + + ROM_LATENCY + Number of bits of latency from Address until data from the SPI ROM + [22:18] + + + ROM_ADDRESS + ROM Address Mode + [24:23] + + + ROM_DLYCAP + ROM SPI Delayed capture + [25:25] + + + ROM_STATUS + The first data byte from the SPI ROM following an address is taken as a status byte + [26:26] + + + RM + This bit controls the internal RAM read timing and must be maintained at this value + [27:27] + + + WM + This bit controls the internal RAM write timing and must be maintained at this value + [28:28] + + + + + EF_ID0 + EFuse ID0 Register + 0xFF0 + read-only + 0x00000000 + + + EF_ID1 + EFuse ID1 Register + 0xFF4 + read-only + 0x00000000 + + + PROCID + Processor ID Register + 0xFF8 + read-only + 0x040057e3 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x028007e9 + + + MANUFACTURER_ID + MANUFACTURER_ID + [11:0] + read-only + + + PERIPHERAL_ID + PERIPHERAL_ID + [23:16] + read-only + + + PERIPHERAL_VER + PERIPHERAL_VER + [31:24] + read-only + + + + + + + DMA + 1.0 + DMA Controller Block + 0x40001000 + + 0 + 0x00001000 + registers + + + DMA_ERROR + 43 + + + DMA_ACTIVE0 + 174 + + + DMA_ACTIVE1 + 175 + + + DMA_ACTIVE2 + 176 + + + DMA_ACTIVE3 + 177 + + + DMA_DONE0 + 178 + + + DMA_DONE1 + 179 + + + DMA_DONE2 + 180 + + + DMA_DONE3 + 181 + + + + STATUS + DMA Status + 0x000 + 0x00000000 + read-only + + + TEST_STATUS + Test Status Logic Included + [31:28] + read-write + + + CHNLS_MINUS1 + Number of Available Channels Minus 1 + [20:16] + + + STATE + Current State of the control state machine + [7:4] + + + MASTER_ENABLE + Enable status of the controller + [0:0] + + + + + CFG + DMA Configuration + 0x004 + write-only + 0x00000000 + + + CHNL_PROT_CTRL + HPROT[3:0] + [7:5] + + + MASTER_ENABLE + PLL Symbol; Feedback cycle slip output (CLKOUT frequency low) + [0:0] + read-only + + + + + CTRL_BASE_PTR + Base Pointer for DMA Control Registers + 0x008 + 0x00000000 + + + CTRL_BASE_PTR + Base Pointer for DMA Control Registers + [31:7] + + + + + ALT_CTRL_BASE_PTR + DMA Channel alternate control data base pointer + 0x00C + read-write + 0x00000000 + + + ALT_CTRL_BASE_PTR + Base Pointer for Alternate DMA Control Register + [31:0] + + + + + WAITONREQ_STATUS + DMA channel wait on request status + 0x010 + read-only + 0x00000000 + + + CH3 + DMA wait on request + [3:3] + read-write + + + CH2 + DMA wait on request + [2:2] + read-write + + + CH1 + DMA wait on request + [1:1] + read-write + + + CH0 + DMA wait on request + [0:0] + read-write + + + + + CHNL_SW_REQUEST + DMA channel software request + 0x014 + write-only + 0x00000000 + + + CH3 + Channel SW request + [3:3] + read-write + + + CH2 + Channel SW request + [2:2] + read-write + + + CH1 + Channel SW request + [1:1] + read-write + + + CH0 + Channel SW request + [0:0] + read-write + + + + + CHNL_USEBURST_SET + DMA channel useburst set + 0x018 + 0x00000000 + + + CH3 + Channel use burst set + [3:3] + read-write + + + CH2 + Channel use burst set + [2:2] + read-write + + + CH1 + Channel use burst set + [1:1] + read-write + + + CH0 + Channel use burst set + [0:0] + read-write + + + + + CHNL_USEBURST_CLR + DMA channel useburst clear + 0x01C + 0x00000000 + + + CH3 + Channel use burst clear + [3:3] + read-write + + + CH2 + Channel use burst clear + [2:2] + read-write + + + CH1 + Channel use burst clear + [1:1] + read-write + + + CH0 + Channel use burst clear + [0:0] + read-write + + + + + CHNL_REQ_MASK_SET + DMA channel request mask set + 0x020 + 0x00000000 + + + CH3 + Channel Request Mask set + [3:3] + read-write + + + CH2 + Channel Request Mask set + [2:2] + read-write + + + CH1 + Channel Request Mask set + [1:1] + read-write + + + CH0 + Channel Request Mask set + [0:0] + read-write + + + + + CHNL_REQ_MASK_CLR + DMA channel request mask clear + 0x024 + 0x00000000 + + + CH3 + Channel Request Mask clear + [3:3] + read-write + + + CH2 + Channel Request Mask clear + [2:2] + read-write + + + CH1 + Channel Request Mask clear + [1:1] + read-write + + + CH0 + Channel Request Mask clear + [0:0] + read-write + + + + + CHNL_ENABLE_SET + DMA channel enable set + 0x028 + 0x00000000 + + + CH3 + Channel Enable set + [3:3] + read-write + + + CH2 + Channel Enable set + [2:2] + read-write + + + CH1 + Channel Enable set + [1:1] + read-write + + + CH0 + Channel Enable set + [0:0] + read-write + + + + + CHNL_ENABLE_CLR + DMA channel enable clear + 0x02C + 0x00000000 + + + CH3 + Channel Enable clear + [3:3] + read-write + + + CH2 + Channel Enable clear + [2:2] + read-write + + + CH1 + Channel Enable clear + [1:1] + read-write + + + CH0 + Channel Enable clear + [0:0] + read-write + + + + + CHNL_PRI_ALT_SET + DMA channel primary alternate set + 0x030 + 0x00000000 + + + CH3 + Channel PRI_ALT set + [3:3] + read-write + + + CH2 + Channel PRI_ALT set + [2:2] + read-write + + + CH1 + Channel PRI_ALT set + [1:1] + read-write + + + CH0 + Channel PRI_ALT set + [0:0] + read-write + + + + + CHNL_PRI_ALT_CLR + DMA channel primary alternate clear + 0x034 + 0x00000000 + + + CH3 + Channel PRI_ALT clear + [3:3] + read-write + + + CH2 + Channel PRI_ALT clear + [2:2] + read-write + + + CH1 + Channel PRI_ALT clear + [1:1] + read-write + + + CH0 + Channel PRI_ALT clear + [0:0] + read-write + + + + + CHNL_PRIORITY_SET + DMA channel priority set + 0x038 + read-write + 0x00000000 + + + CH3 + Channel PRIORITY set + [3:3] + read-write + + + CH2 + Channel PRIORITY set + [2:2] + read-write + + + CH1 + Channel PRIORITY set + [1:1] + read-write + + + CH0 + Channel PRIORITY set + [0:0] + read-write + + + + + CHNL_PRIORITY_CLR + DMA channel priority clear + 0x03C + write-only + 0x00000000 + + + CH3 + Channel PRIORITY clear + [3:3] + write-only + + + CH2 + Channel PRIORITY clear + [2:2] + write-only + + + CH1 + Channel PRIORITY clear + [1:1] + write-only + + + CH0 + Channel PRIORITY clear + [0:0] + write-only + + + + + ERR_CLR + DMA bus error clear + 0x04C + 0x00000000 + + + ERR_CLR + Error Clear + [0:0] + read-write + + + + + INTEGRATION_CFG + DMA integration configuration + 0xE00 + 0x00000000 + + + INT_TEST_EN + Error Clear + [0:0] + read-write + + + + + STALL_STATUS + DMA stall status + 0xE08 + 0x00000000 + + + STALL_STATUS + DMA is stalled + [0:0] + read-only + + + + + DMA_REQ_STATUS + DMA Configuration + 0xE10 + 0x00000000 + + + CH3 + DMA Request Status for this CH + [3:3] + read-write + + + CH2 + DMA Request Status for this CH + [2:2] + read-write + + + CH1 + DMA Request Status for this CH + [1:1] + read-write + + + CH0 + DMA Request Status for this CH + [0:0] + read-write + + + + + DMA_SREQ_STATUS + DMA single request status + 0xE18 + 0x00000000 + + + CH3 + DMA SRequest Status for this CH + [3:3] + read-write + + + CH2 + DMA SRequest Status for this CH + [2:2] + read-write + + + CH1 + DMA SRequest Status for this CH + [1:1] + read-write + + + CH0 + DMA SRequest Status for this CH + [0:0] + read-write + + + + + DMA_DONE_SET + DMA done set + 0xE20 + 0x00000000 + + + CH3 + DMA Done Set for this CH + [3:3] + read-write + + + CH2 + DMA Done Set for this CH + [2:2] + read-write + + + CH1 + DMA Done Set for this CH + [1:1] + read-write + + + CH0 + DMA Done Set for this CH + [0:0] + read-write + + + + + DMA_DONE_CLR + DMA done clear + 0xE24 + 0x00000000 + + + CH3 + DMA Done clear for this CH + [3:3] + read-write + + + CH2 + DMA Done clear for this CH + [2:2] + read-write + + + CH1 + DMA Done clear for this CH + [1:1] + read-write + + + CH0 + DMA Done clear for this CH + [0:0] + read-write + + + + + DMA_ACTIVE_SET + DMA active set + 0xE28 + 0x00000000 + + + CH3 + DMA Active Set + [3:3] + read-write + + + CH2 + DMA Active Set + [2:2] + read-write + + + CH1 + DMA Active Set + [1:1] + read-write + + + CH0 + DMA Active Set + [0:0] + read-write + + + + + DMA_ACTIVE_CLR + DMA active clear + 0xE2C + 0x00000000 + + + CH3 + DMA Active clear + [3:3] + read-write + + + CH2 + DMA Active clear + [2:2] + read-write + + + CH1 + DMA Active clear + [1:1] + read-write + + + CH0 + DMA Active clear + [0:0] + read-write + + + + + ERR_SET + DMA bus error set + 0xE48 + 0x00000000 + + + ERR_SET + Set Error + [0:0] + read-only + + + + + PERIPH_ID_4 + DMA Peripheral ID 4 + 0xFD0 + 0x00000004 + + + BLOCK_COUNT + The Number of 4k Address Blocks Required + [7:4] + + + JEP106_C_CODE + JEP106 + [3:0] + + + + + PERIPH_ID_0 + DMA Peripheral ID 0 + 0xFE0 + 0x00000030 + + + PART_NUMBER_0 + Part Number + [7:0] + + + + + PERIPH_ID_1 + DMA Peripheral ID 1 + 0xFE4 + read-only + 0x000000B2 + + + JEP106_ID_3_0 + Indentity Code + [7:4] + + + PART_NUMBER_1 + Part Number 1 + [3:0] + + + + + PERIPH_ID_2 + DMA Peripheral ID 2 + 0xFE8 + 0x000000BC + + + REVISION + Revision + [7:4] + + + JEDEC_USED + JEDEC + [3:3] + + + JEP106_ID_6_4 + JEP106 + [2:0] + + + + + PERIPH_ID_3 + DMA Peripheral ID 3 + 0xFEC + 0x00000000 + + + MOD_NUMBER + Controller Modifications + [3:0] + + + + + PRIMECELL_ID_0 + DMA PrimeCell ID 0 + 0xFF0 + 0x0000000D + + + PRIMECELL_ID_0 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_1 + DMA PrimeCell ID 1 + 0xFF4 + 0x000000F0 + + + PRIMECELL_ID_1 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_2 + DMA PrimeCell ID 2 + 0xFF8 + 0x00000005 + + + PRIMECELL_ID_2 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_3 + DMA PrimeCell ID 3 + 0xFFC + 0x000000B1 + + + PRIMECELL_ID_3 + PrimeCell Identification + [7:0] + + + + + + + + IOCONFIG + 1.0 + IO Pin Configuration Peripheral + 0x40011000 + + 0 + 0x00001000 + registers + + + + 16 + 4 + PORTA[%s] + PORTA Pin Configuration Register + 0x000 + 0x00000000 + + + FLTTYPE + Input Filter Selectoin + [2:0] + + + SYNC + Synchronize to system clock + 0 + + + DIRECT + Direct input, no synchronization + 1 + + + FILTER1 + Require 2 samples to have the same value + 2 + + + FILTER2 + Require 3 samples to have the same value + 3 + + + FILTER3 + Require 4 samples to have the same value + 4 + + + FILTER4 + Require 5 samples to have the same value + 5 + + + + + FLTCLK + Input Filter Clock Selection + [5:3] + + + INVINP + Input Invert Selection + [6:6] + + + IEWO + Input Enable While Output enabled + [7:7] + + + OPENDRN + Output Open Drain Mode + [8:8] + + + INVOUT + Output Invert Selection + [9:9] + + + PLEVEL + Internal Pull up/down level + [10:10] + + + PEN + Enable Internal Pull up/down + [11:11] + + + PWOA + Enable Pull when output active + [12:12] + + + FUNSEL + Pin Function Selection + [15:13] + + + IODIS + IO Pin Disable + [16:16] + + + + + PORTB[%s] + PORTB Pin Configuration Register + 0x0040 + 0x00000000 + + + PORTC[%s] + PORTC Pin Configuration Register + 0x0080 + 0x00000000 + + + PORTD[%s] + PORTD Pin Configuration Register + 0x00C0 + 0x00000000 + + + PORTE[%s] + PORTE Pin Configuration Register + 0x0100 + 0x00000000 + + + PORTF[%s] + PORTF Pin Configuration Register + 0x0140 + 0x00000000 + + + 8 + 4 + PORTG[%s] + PORTG Pin Configuration Register + 0x0180 + 0x00000000 + + + CLKDIV0 + Clock divide value. 0 will disable the clock + 0x1C0 + read-only + 0x00000000 + + + CLKDIV1 + Clock divide value. 0 will disable the clock + 0x1C4 + read-write + 0x00000000 + + + CLKDIV2 + Clock divide value. 0 will disable the clock + 0x1C8 + read-write + 0x00000000 + + + CLKDIV3 + Clock divide value. 0 will disable the clock + 0x1CC + read-write + 0x00000000 + + + CLKDIV4 + Clock divide value. 0 will disable the clock + 0x1D0 + read-write + 0x00000000 + + + CLKDIV5 + Clock divide value. 0 will disable the clock + 0x1D4 + read-write + 0x00000000 + + + CLKDIV6 + Clock divide value. 0 will disable the clock + 0x1D8 + read-write + 0x00000000 + + + CLKDIV7 + Clock divide value. 0 will disable the clock + 0x1DC + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x028207e9 + + + + + + + UTILITY + 1.0 + Utility Peripheral + 0x40020000 + + 0 + 0x00001000 + registers + + + + SYND_DATA + Data Register + 0x000 + read-write + 0x00000000 + + + SYND_SYND + Syndrome Data Register + 0x004 + read-write + 0x00000000 + + + SYND_SYND + Provides bits 11:0 for syndrome, 2x6-bit + [11:0] + + + + + SYND_ENC_32_44 + EDAC Encode + 0x008 + read-write + 0x00000000 + + + SYND_ENC_31_16 + Computed syndrome value for bits 31-16 + [11:6] + + + SYND_ENC_7_0 + Computed syndrome value for bits 15-0 + [5:0] + + + + + SYND_CHECK_32_44_DATA + EDAC Decode Data + 0x00c + read-only + 0x00000000 + + + SYND_CHECK_32_44_SYND + EDAC Decode Syndrome + 0x010 + read-only + 0x00000000 + + + MBE + Multiple bit error detect status + [15:14] + + + SBE + Single bit error detect status + [13:12] + + + SYND_CHECK_32_44_SYND + Correct syndrome value + [11:0] + + + + + ROM_TRAP_ADDRESS + ROM EDAC Trap Address + 0x014 + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + ROM_TRAP_SYND + ROM EDAC Trap Syndrome + 0x018 + read-write + 0x00000000 + + + R0M_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + ROM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + RAM_TRAP_ADDR0 + RAM0 EDAC Trap Address + 0x01c + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + RAM_TRAP_SYND0 + RAM0 EDAC Trap Syndrome + 0x020 + read-write + 0x00000000 + + + RAM_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + RAM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + RAM_TRAP_ADDR1 + RAM1 EDAC Trap Address + 0x024 + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + RAM_TRAP_SYND1 + RAM1 EDAC Trap Syndrome + 0x028 + read-write + 0x00000000 + + + RAM_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + RAM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + SYND_ENC_32_52 + EDAC Encode + 0x120 + read-only + 0x00000000 + + + SYND_ENC_32_52 + Computed syndrome value for bits 15-0 + [19:0] + + + + + SYND_CHECK_32_52_DATA + EDAC Decode Data + 0x124 + read-only + 0x00000000 + + + SYND_CHECK_32_52_SYND + EDAC Decode Syndrome + 0x128 + read-only + 0x00000000 + + + MBE + Multiple bit error detect status + [31:28] + + + SBE + Single bit error detect status + [27:24] + + + SYND_CHECK_32_52_SYND + Corrected syndrome value + [19:0] + + + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x028407e9 + + + + + + + PORTA + 1.0 + GPIO Peripheral + GPIO + 0x40012000 + + 0 + 0x00000400 + registers + + + PORTA0 + 78 + + + PORTA1 + 79 + + + PORTA2 + 80 + + + PORTA3 + 81 + + + PORTA4 + 82 + + + PORTA5 + 83 + + + PORTA6 + 84 + + + PORTA7 + 85 + + + PORTA8 + 86 + + + PORTA9 + 87 + + + PORTA10 + 88 + + + PORTA11 + 89 + + + PORTA12 + 90 + + + PORTA13 + 91 + + + PORTA14 + 92 + + + PORTA15 + 93 + + + PORTB0 + 94 + + + PORTB1 + 95 + + + PORTB2 + 96 + + + PORTB3 + 97 + + + PORTB4 + 98 + + + PORTB5 + 99 + + + PORTB6 + 100 + + + PORTB7 + 101 + + + PORTB8 + 102 + + + PORTB9 + 103 + + + PORTB10 + 104 + + + PORTB11 + 105 + + + PORTB12 + 106 + + + PORTB13 + 107 + + + PORTB14 + 108 + + + PORTB15 + 109 + + + PORTC0 + 110 + + + PORTC1 + 111 + + + PORTC2 + 112 + + + PORTC3 + 113 + + + PORTC4 + 114 + + + PORTC5 + 115 + + + PORTC6 + 116 + + + PORTC7 + 117 + + + PORTC8 + 118 + + + PORTC9 + 119 + + + PORTC10 + 120 + + + PORTC11 + 121 + + + PORTC12 + 122 + + + PORTC13 + 123 + + + PORTC14 + 124 + + + PORTC15 + 125 + + + PORTD0 + 126 + + + PORTD1 + 127 + + + PORTD2 + 128 + + + PORTD3 + 129 + + + PORTD4 + 130 + + + PORTD5 + 131 + + + PORTD6 + 132 + + + PORTD7 + 133 + + + PORTD8 + 134 + + + PORTD9 + 135 + + + PORTD10 + 136 + + + PORTD11 + 137 + + + PORTD12 + 138 + + + PORTD13 + 139 + + + PORTD14 + 140 + + + PORTD15 + 141 + + + PORTE0 + 142 + + + PORTE1 + 143 + + + PORTE2 + 144 + + + PORTE3 + 145 + + + PORTE4 + 146 + + + PORTE5 + 147 + + + PORTE6 + 148 + + + PORTE7 + 149 + + + PORTE8 + 150 + + + PORTE9 + 151 + + + PORTE10 + 152 + + + PORTE11 + 153 + + + PORTE12 + 154 + + + PORTE13 + 155 + + + PORTE14 + 156 + + + PORTE15 + 157 + + + PORTF0 + 158 + + + PORTF1 + 159 + + + PORTF2 + 160 + + + PORTF3 + 161 + + + PORTF4 + 162 + + + PORTF5 + 163 + + + PORTF6 + 164 + + + PORTF7 + 165 + + + PORTF8 + 166 + + + PORTF9 + 167 + + + PORTF10 + 168 + + + PORTF11 + 169 + + + PORTF12 + 170 + + + PORTF13 + 171 + + + PORTF14 + 172 + + + PORTF15 + 173 + + GPIO + + + DATAIN + Data In Register + 0x000 + read-only + 0x00000000 + + + 4 + 1 + DATAINBYTE[%s] + Data In Register by Byte + DATAIN + 0x000 + 8 + read-only + 0x00000000 + + + DATAINRAW + Data In Raw Register + 0x004 + 0x00000000 + + + DATAINRAWBYTE[%s] + Data In Raw Register by Byte + DATAINRAW + 0x004 + 0x00000000 + + + DATAOUT + Data Out Register + 0x008 + write-only + 0x00000000 + + + 4 + 1 + DATAOUTBYTE[%s] + Data Out Register by Byte + DATAOUT + 0x008 + 8 + write-only + 0x00000000 + + + DATAOUTRAW + Data Out Register + 0x00c + 0x00000000 + + + DATAOUTRAWBYTE[%s] + Data Out Register by Byte + DATAOUTRAW + 0x00c + 0x00000000 + + + SETOUT + Set Out Register + 0x010 + 0x00000000 + + + SETOUTBYTE[%s] + Set Out Register by Byte + SETOUT + 0x010 + 0x00000000 + + + CLROUT + Clear Out Register + 0x014 + 0x00000000 + + + CLROUTBYTE[%s] + Clear Out Register by Byte + CLROUT + 0x014 + 0x00000000 + + + TOGOUT + Toggle Out Register + 0x018 + 0x00000000 + + + TOGOUTBYTE[%s] + Toggle Out Register by Byte + TOGOUT + 0x018 + 0x00000000 + + + DATAMASK + Data mask Register + 0x01c + 0x00000000 + + + 4 + 1 + DATAMASKBYTE[%s] + Data Out Register by Byte + DATAMASK + 0x01c + 8 + 0x00000000 + + + DIR + Direction Register (1:Output, 0:Input) + 0x020 + 0x00000000 + + + DIRBYTE[%s] + Direction Register by Byte + DIR + 0x020 + 0x00000000 + + + PULSE + Pulse Mode Register + 0x024 + 0x00000000 + + + PULSEBYTE[%s] + Pulse Mode Register by Byte + PULSE + 0x024 + 0x00000000 + + + PULSEBASE + Pulse Base Value Register + 0x028 + 0x00000000 + + + PULSEBASEBYTE[%s] + Pulse Base Mode Register by Byte + PULSEBASE + 0x028 + 0x00000000 + + + DELAY1 + Delay1 Register + 0x02c + 0x00000000 + + + DELAY1BYTE[%s] + Delay1 Register by Byte + DELAY1 + 0x02c + 0x00000000 + + + DELAY2 + Delay2 Register + 0x030 + 32 + read-write + 0x00000000 + + + DELAY2BYTE[%s] + Delay2 Register by Byte + DELAY2 + 0x030 + 0x00000000 + + + IRQ_SEN + Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive) + 0x034 + 0x00000000 + + + IRQ_EDGE + Interrupt Both Edge Register (1:Both Edges, 0:Single Edge) + 0x038 + 0x00000000 + + + IRQ_EVT + Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) + 0x03c + 0x00000000 + + + IRQ_ENB + Interrupt Enable Register + 0x040 + 0x00000000 + + + IRQ_RAW + Raw Interrupt Status + 0x044 + read-only + 0x00000000 + + + IRQ_END + Masked Interrupt Status + 0x048 + read-only + 0x00000000 + + + EDGE_STATUS + Edge Status Register + 0x04c + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0x3fc + 32 + read-only + 0x021007e9 + + + + + PORTB + 0x40012400 + + + PORTC + 0x40012800 + + + PORTD + 0x40012C00 + + + PORTE + 0x40013000 + + + PORTF + 0x40013400 + + + PORTG + 0x40013800 + + + + + TIM0 + 1.0 + Timer/Counter Peripheral + Timer_Counter + 0x40018000 + + 0 + 0x00000400 + registers + + + TIM0 + 48 + + + TIM1 + 49 + + + TIM2 + 50 + + + TIM3 + 51 + + + TIM4 + 52 + + + TIM5 + 53 + + + TIM6 + 54 + + + TIM7 + 55 + + + TIM8 + 56 + + + TIM9 + 57 + + + TIM10 + 58 + + + TIM11 + 59 + + + TIM12 + 60 + + + TIM13 + 61 + + + TIM14 + 62 + + + TIM15 + 63 + + + TIM16 + 64 + + + TIM17 + 65 + + + TIM18 + 66 + + + TIM19 + 67 + + + TIM20 + 68 + + + TIM21 + 69 + + + TIM22 + 70 + + + TIM23 + 71 + + TIM + + + CTRL + Control Register + 0x000 + read-write + + + ENABLE + Counter Enable + [0:0] + + + ACTIVE + Counter Active + [1:1] + read-only + + + AUTO_DISABLE + Auto Disables the counter (set ENABLE to 0) when the count reaches 0 + [2:2] + + + AUTO_DEACTIVATE + Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0 + [3:3] + + + IRQ_ENB + Interrupt Enable + [4:4] + + + STATUS_SEL + Counter Status Selection + [7:5] + + + DONE + Single cycle pulse when the counter reaches 0 + 0 + + + ACTIVE + Returns the counter ACTIVE bit + 1 + + + TOGGLE + Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output. + 2 + + + PWMA + Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE + 3 + + + PWMB + Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE + 4 + + + ENABLED + Returns the counter ENABLED bit + 5 + + + PWMA_ACTIVE + Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0 + 6 + + + + + STATUS_INV + Invert the Output Status + [8:8] + + + REQ_STOP + Stop Request + [9:9] + + + + + RST_VALUE + The value that counter start from after reaching 0. + 0x004 + + + CNT_VALUE + The current value of the counter + 0x008 + + + ENABLE + Alternate access to the Counter ENABLE bit in the CTRL Register + 0x00c + + + ENABLE + Counter Enable + [0:0] + + + + + CSD_CTRL + The Cascade Control Register. Controls the counter external enable signals + 0x010 + + + CSDEN0 + Cascade 0 Enable + [0:0] + + + CSDINV0 + Cascade 0 Invert + [1:1] + + + CSDEN1 + Cascade 1 Enable + [2:2] + + + CSDINV1 + Cascade 1 Invert + [3:3] + + + DCASOP + Dual Cascade Operation (0:AND, 1:OR) + [4:4] + + + CSDTRG0 + Cascade 0 Enabled as Trigger + [6:6] + + + CSDTRG1 + Cascade 1 Enabled as Trigger + [7:7] + + + CSDEN2 + Cascade 2 Enable + [8:8] + + + CSDINV2 + Cascade 2 Invert + [9:9] + + + CSDTRG2 + Cascade 2 Trigger mode + [10:10] + + + + + CASCADE0 + Cascade Enable Selection + 0x014 + + + CASSEL + Cascade Selection + [7:0] + + + + + CASCADE1 + Cascade Enable Selection + 0x018 + + + CASCADE2 + Cascade Enable Selection + 0x01c + + + PWM_VALUE + The Pulse Width Modulation Value + 0x020 + + + PWMA_VALUE + The Pulse Width Modulation ValueA + PWM_VALUE + 0x020 + + + PWMB_VALUE + The Pulse Width Modulation ValueB + 0x024 + + + PERID + Peripheral ID Register + 0x3fc + read-only + 0x021107e9 + + + + + TIM1 + 0x40018400 + + + TIM2 + 0x40018800 + + + TIM3 + 0x40018C00 + + + TIM4 + 0x40019000 + + + TIM5 + 0x40019400 + + + TIM6 + 0x40019800 + + + TIM7 + 0x40019C00 + + + TIM8 + 0x4001A000 + + + TIM9 + 0x4001A400 + + + TIM10 + 0x4001A800 + + + TIM11 + 0x4001AC00 + + + TIM12 + 0x4001B000 + + + TIM13 + 0x4001B400 + + + TIM14 + 0x4001B800 + + + TIM15 + 0x4001BC00 + + + TIM16 + 0x40028000 + + + TIM17 + 0x40028400 + + + TIM18 + 0x40028800 + + + TIM19 + 0x40028C00 + + + TIM20 + 0x40029000 + + + TIM21 + 0x40029400 + + + TIM22 + 0x40029800 + + + TIM23 + 0x40029C00 + + + + + UART0 + 1.0 + UART Peripheral + UART + 0x40024000 + + 0 + 0x00001000 + registers + + + UART0_TX + 24 + + + UART0_RX + 25 + + + UART1_TX + 26 + + + UART1_RX + 27 + + + UART2_TX + 28 + + + UART2_RX + 29 + + UART + + + DATA + Data In/Out Register + 0x000 + 0x00000000 + + + ENABLE + Enable Register + 0x004 + 0x00000000 + + + RXENABLE + Rx Enable + [0:0] + + + TXENABLE + Tx Enable + [1:1] + + + + + CTRL + Control Register + 0x008 + 0x00000000 + + + PAREN + Parity Enable + [0:0] + + + PAREVEN + Parity Even/Odd(1/0) + [1:1] + + + PARSTK + Parity Sticky + [2:2] + + + STOPBITS + Stop Bits 1/2(0/1) + [3:3] + + + WORDSIZE + Word Size in Bits 5/6/7/8(00/01/10/11) + [5:4] + + + LOOPBACK + Loopback Enable + [6:6] + + + LOOPBACKBLK + Loopback Block + [7:7] + + + AUTOCTS + Enable Auto CTS mode + [8:8] + + + DEFRTS + Default RTSn value + [9:9] + + + AUTORTS + Enable Auto RTS mode + [10:10] + + + BAUD8 + Enable BAUD8 mode + [11:11] + + + + + CLKSCALE + Clock Scale Register + 0x00c + 0x00000000 + + + FRAC + Fractional Divide (64ths) + [5:0] + + + INT + Integer Divide + [23:6] + + + RESET + Reset Baud Counter + [31:31] + write-only + + + + + RXSTATUS + Status Register + 0x010 + read-only + 0x00000000 + + + RDAVL + Read Data Available + [0:0] + + + RDNFULL + Read Fifo NOT Full + [1:1] + + + RXBUSY + RX Busy Receiving + [2:2] + + + RXTO + RX Receive Timeout + [3:3] + + + RXOVR + Read Fifo Overflow + [4:4] + + + RXFRM + RX Framing Error + [5:5] + + + RXPAR + RX Parity Error + [6:6] + + + RXBRK + RX Break Error + [7:7] + + + RXBUSYBRK + RX Busy Receiving Break + [8:8] + + + RXADDR9 + Address Match for 9 bit mode + [9:9] + + + RXRTSN + RX RTSn Output Value + [15:15] + + + + + TXSTATUS + Status Register + 0x014 + read-only + 0x00000000 + + + WRRDY + Write Fifo NOT Full + [0:0] + + + WRBUSY + Write Fifo Full + [1:1] + + + TXBUSY + TX Busy Transmitting + [2:2] + + + WRLOST + Write Data Lost (Fifo Overflow) + [3:3] + + + TXCTSN + TX CTSn Input Value + [15:15] + + + + + FIFO_CLR + Clear FIFO Register + 0x018 + write-only + 0x00000000 + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TXBREAK + Break Transmit Register + 0x01c + write-only + 0x00000000 + + + ADDR9 + Address9 Register + 0x020 + read-write + 0x00000000 + + + ADDR9MASK + Address9 Mask Register + 0x024 + read-write + 0x00000000 + + + IRQ_ENB + IRQ Enable Register + 0x028 + read-write + 0x00000000 + + + IRQ_RX + RX Interrupt + [0:0] + + + IRQ_RX_STATUS + RX Status Interrupt + [1:1] + + + IRQ_RX_TO + RX Timeout Interrupt + [2:2] + + + IRQ_TX + TX Interrupt + [4:4] + + + IRQ_TX_STATUS + TX Status Interrupt + [5:5] + + + IRQ_TX_EMPTY + TX Empty Interrupt + [6:6] + + + IRQ_TX_CTS + TX CTS Change Interrupt + [7:7] + + + + + IRQ_RAW + IRQ Raw Status Register + 0x02c + read-only + 0x00000000 + + + IRQ_END + IRQ Enabled Status Register + 0x030 + read-only + 0x00000000 + + + IRQ_CLR + IRQ Clear Status Register + 0x034 + write-only + 0x00000000 + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x038 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x03c + + + RXFIFORTSTRG + Rx FIFO RTS Trigger Level + 0x040 + + + STATE + Internal STATE of UART Controller + 0x044 + 32 + read-only + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x021207e9 + + + + + UART1 + 0x40025000 + + + UART2 + 0x40017000 + + + + + SPI0 + 1.0 + SPI Peripheral + SPI + 0x40015000 + + 0 + 0x00000400 + registers + + + SPI0_TX + 16 + + + SPI0_RX + 17 + + + SPI1_TX + 18 + + + SPI1_RX + 19 + + + SPI2_TX + 20 + + + SPI2_RX + 21 + + + SPI3_TX + 22 + + + SPI3_RX + 23 + + SPI + + + CTRL0 + Control Register 0 + 0x000 + 0x00000000 + + + SIZE + Data Size(0x3=>4, 0xf=>16) + [3:0] + + + SPO + SPI Clock Polarity + [6:6] + + + SPH + SPI Clock Phase + [7:7] + + + SCRDV + Serial Clock Rate divide+1 value + [15:8] + + + + + CTRL1 + Control Register 1 + 0x004 + 0x00000000 + + + LBM + Loop Back + [0:0] + + + ENABLE + Enable + [1:1] + + + MS + Master/Slave (0:Master, 1:Slave) + [2:2] + + + SOD + Slave output Disable + [3:3] + + + SS + Slave Select + [6:4] + + + BLOCKMODE + Block Mode Enable + [7:7] + + + BMSTART + Block Mode Start Status Enable + [8:8] + + + BMSTALL + Block Mode Stall Enable + [9:9] + + + MDLYCAP + Master Delayed Capture Enable + [10:10] + + + MTXPAUSE + Master Tx Pause Enable + [11:11] + + + + + DATA + Data Input/Output + 0x008 + + + STATUS + Status Register + 0x00C + read-only + 0x00000000 + + + TFE + Transmit FIFO empty + [0:0] + + + TNF + Transmit FIFO not full + [1:1] + + + RNE + Receive FIFO not empty + [2:2] + + + RFF + Receive FIFO Full + [3:3] + + + BUSY + Busy + [4:4] + + + RXDATAFIRST + Pending Data is first Byte in BLOCKMODE + [5:5] + + + RXTRIGGER + RX FIFO Above Trigger Level + [6:6] + + + TXTRIGGER + TX FIFO Below Trigger Level + [7:7] + + + + + CLKPRESCALE + Clock Pre Scale divide value + 0x010 + + + IRQ_ENB + Interrupt Enable Register + 0x014 + read-write + 0x00000000 + + + RORIM + RX Overrun + [0:0] + + + RTIM + RX Timeout + [1:1] + + + RXIM + RX Fifo is at least half full + [2:2] + + + TXIM + TX Fifo is at least half empty + [3:3] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x018 + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x01C + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x020 + write-only + + oneToClear + + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x024 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x028 + + + FIFO_CLR + Clear FIFO Register + 0x02c + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + STATE + Internal STATE of SPI Controller + 0x030 + read-only + + + PERID + Peripheral ID Register + 0x3fc + read-only + 0x021307e9 + + + + + SPI1 + 0x40015400 + + + SPI2 + 0x40015800 + + + SPI3 + 0x40015C00 + + + + + I2C0 + 1.0 + I2C Peripheral + I2C + 0x40016000 + + 0 + 0x00000400 + registers + + + I2C0_MS + 30 + + + I2C0_SL + 31 + + + I2C1_MS + 32 + + + I2C1_SL + 33 + + + I2C2_MS + 34 + + + I2C2_SL + 35 + + + I2C0_MS_RX + 182 + + + I2C0_MS_TX + 183 + + + I2C0_SL_RX + 184 + + + I2C0_SL_TX + 185 + + + I2C1_MS_RX + 186 + + + I2C1_MS_TX + 187 + + + I2C1_SL_RX + 188 + + + I2C1_SL_TX + 189 + + + I2C2_MS_RX + 190 + + + I2C2_MS_TX + 191 + + + I2C2_SL_RX + 192 + + + I2C2_SL_TX + 193 + + I2C + + + + CTRL + Control Register + 0x000 + 0x00000000 + + + CLKENABLED + I2C CLK Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + ALGFILTER + Enable Input Analog Glitch Filter + [5:5] + + + DLGFILTER + Enable Input Digital Glitch Filter + [6:6] + + + LOOPBACK + Enable LoopBack Mode + [8:8] + + + TMCONFIGENB + Enable Timing Config Register + [9:9] + + + + + CLKSCALE + Clock Scale divide value + 0x004 + + + VALUE + Enable FastMode + [30:0] + + + FASTMODE + Enable FastMode + [31:31] + + + + + WORDS + Word Count value + 0x008 + + + ADDRESS + I2C Address value + 0x00c + + + DATA + Data Input/Output + 0x010 + + + CMD + Command Register + 0x014 + + + STATUS + I2C Controller Status Register + 0x018 + + + I2CIDLE + I2C bus is idle + [0:0] + + + IDLE + I2C controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + STATE + Internal STATE of I2C Master Controller + 0x01c + read-only + + + TXCOUNT + TX Count Register + 0x020 + read-only + + + RXCOUNT + RX Count Register + 0x024 + read-only + + + IRQ_ENB + Interrupt Enable Register + 0x028 + read-write + 0x00000000 + + + I2CIDLE + I2C Bus is Idle + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + CLKLOTO + I2C Clock Low Timeout + [7:7] + + + TXOVERFLOW + TX FIFO Overflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x02c + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x030 + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x034 + write-only + + oneToClear + + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x038 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x03c + + + FIFO_CLR + Clear FIFO Register + 0x040 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TMCONFIG + Timing Config Register + 0x044 + + + CLKTOLIMIT + Clock Low Timeout Limit Register + 0x048 + + + + S0_CTRL + Slave Control Register + 0x100 + 0x00000000 + + + CLKENABLED + I2C Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + + + S0_MAXWORDS + Slave MaxWords Register + 0x104 + 0x00000000 + + + MAXWORD + Max Word Count + [10:0] + + + ENABLE + Enables the max word count + [31:31] + + + + + S0_ADDRESS + Slave I2C Address Value + 0x108 + 0x00000000 + + + A10MODE + Enable 10b address mode + [15:15] + + + ADDRESS + Address value + [10:1] + + + RW + Read/Write value + [0:0] + + + + + S0_ADDRESSMASK + Slave I2C Address Mask value + 0x10c + 0x00000000 + + + MASK + Address mask value + [10:1] + + + RWMASK + Read/Write mask + [0:0] + + + + + S0_DATA + Slave Data Input/Output + 0x110 + 0x00000000 + + + VALUE + I2C data value + [7:0] + + + + + S0_LASTADDRESS + Slave I2C Last Address value + 0x114 + read-only + 0x00000000 + + + ADDRESS + Address value + [10:1] + + + DIRECTION + Transaction direction 0=master send, 1=master receive + [0:0] + + + + + S0_STATUS + Slave I2C Controller Status Register + 0x118 + read-only + 0x00000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_BUSY + I2C Raw Busy value + [29:29] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + S0_STATE + Internal STATE of I2C Slave Controller + 0x11c + read-only + + + S0_TXCOUNT + Slave TX Count Register + 0x120 + read-only + 0x00000000 + + + VALUE + Count value + [10:0] + + + + + S0_RXCOUNT + Slave RX Count Register + 0x124 + read-only + 0x00000000 + + + VALUE + Count value + [10:0] + + + + + S0_IRQ_ENB + Slave Interrupt Enable Register + 0x128 + read-write + 0x00000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + I2C_START + I2C Start Condition + [8:8] + + + I2C_STOP + I2C Stop Condition + [9:9] + + + TXUNDERFLOW + TX FIFO Underflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + S0_IRQ_RAW + Slave Raw Interrupt Status Register + 0x12c + read-only + + + S0_IRQ_END + Slave Enabled Interrupt Status Register + 0x130 + read-only + + + S0_IRQ_CLR + Slave Clear Interrupt Status Register + 0x134 + write-only + + oneToClear + + + + S0_RXFIFOIRQTRG + Slave Rx FIFO IRQ Trigger Level + 0x138 + 0x00000000 + + + LEVEL + Half full level for the Rx FIFO + [4:0] + + + + + S0_TXFIFOIRQTRG + Slave Tx FIFO IRQ Trigger Level + 0x13c + 0x00000008 + + + LEVEL + Half full level for the Rx FIFO + [4:0] + + + + + S0_FIFO_CLR + Slave Clear FIFO Register + 0x140 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + S0_ADDRESSB + Slave I2C Address B Value + 0x144 + 0x00000000 + + + RW + Read write value + [0:0] + + + ADDRESS + Address value + [10:1] + + + ADDRESSBEN + Enable Address B + [15:15] + + + + + S0_ADDRESSMASKB + Slave I2C Address B Mask value + 0x148 + 0x000007FE + + + RWMASK + Read write mask + [0:0] + + + MASK + Address mask value + [10:1] + + + + + PERID + Peripheral ID Register + 0x3fc + read-only + 0x021407e9 + + + + + I2C1 + 0x40016400 + + + I2C2 + 0x40016800 + + + + + CAN0 + 1.0 + CAN Peripheral + CAN + 0x40014000 + + 0 + 0x00000400 + registers + + + CAN0 + 72 + + + CAN1 + 74 + + CAN + + + CNSTAT_CMB0 + Buffer Status / Control Register + 0x000 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB0 + CAN Frame Timestamp + 0x004 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB0 + CAN Frame Data Word 3 + 0x008 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB0 + CAN Frame Data Word 2 + 0x00C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB0 + CAN Frame Data Word 1 + 0x010 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB0 + CAN Frame Data Word 0 + 0x014 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB0 + CAN Frame Identifier Word 0 + 0x018 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB0 + CAN Frame Identifier Word 1 + 0x01C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB1 + Buffer Status / Control Register + 0x020 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB1 + CAN Frame Timestamp + 0x024 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB1 + CAN Frame Data Word 3 + 0x028 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB1 + CAN Frame Data Word 2 + 0x02C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB1 + CAN Frame Data Word 2 + 0x030 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB1 + CAN Frame Data Word 0 + 0x034 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB1 + CAN Frame Identifier Word 0 + 0x038 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB1 + CAN Frame Identifier Word 1 + 0x03C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB2 + Buffer Status / Control Register + 0x040 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB2 + CAN Frame Timestamp + 0x044 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB2 + CAN Frame Data Word 3 + 0x048 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB2 + CAN Frame Data Word 2 + 0x04C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB2 + CAN Frame Data Word 2 + 0x050 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB2 + CAN Frame Data Word 0 + 0x054 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB2 + CAN Frame Identifier Word 0 + 0x058 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB2 + CAN Frame Identifier Word 1 + 0x05C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB3 + Buffer Status / Control Register + 0x060 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB3 + CAN Frame Timestamp + 0x064 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB3 + CAN Frame Data Word 3 + 0x068 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB3 + CAN Frame Data Word 2 + 0x06C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB3 + CAN Frame Data Word 2 + 0x070 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB3 + CAN Frame Data Word 0 + 0x074 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB3 + CAN Frame Identifier Word 0 + 0x078 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB3 + CAN Frame Identifier Word 1 + 0x07C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB4 + Buffer Status / Control Register + 0x080 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB4 + CAN Frame Timestamp + 0x084 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB4 + CAN Frame Data Word 3 + 0x088 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB4 + CAN Frame Data Word 2 + 0x08C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB4 + CAN Frame Data Word 2 + 0x090 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB4 + CAN Frame Data Word 0 + 0x094 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB4 + CAN Frame Identifier Word 0 + 0x098 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB4 + CAN Frame Identifier Word 1 + 0x09C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB5 + Buffer Status / Control Register + 0x0A0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB5 + CAN Frame Timestamp + 0x0A4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB5 + CAN Frame Data Word 3 + 0x0A8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB5 + CAN Frame Data Word 2 + 0x0AC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB5 + CAN Frame Data Word 2 + 0x0B0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB5 + CAN Frame Data Word 0 + 0x0B4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB5 + CAN Frame Identifier Word 0 + 0x0B8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB5 + CAN Frame Identifier Word 1 + 0x0BC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB6 + Buffer Status / Control Register + 0x0C0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB6 + CAN Frame Timestamp + 0x0C4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB6 + CAN Frame Data Word 3 + 0x0C8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB6 + CAN Frame Data Word 2 + 0x0CC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB6 + CAN Frame Data Word 2 + 0x0D0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB6 + CAN Frame Data Word 0 + 0x0D4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB6 + CAN Frame Identifier Word 0 + 0x0D8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB6 + CAN Frame Identifier Word 1 + 0x0DC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB7 + Buffer Status / Control Register + 0x0E0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB7 + CAN Frame Timestamp + 0x0E4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB7 + CAN Frame Data Word 3 + 0x0E8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB7 + CAN Frame Data Word 2 + 0x0EC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB7 + CAN Frame Data Word 2 + 0x0F0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB7 + CAN Frame Data Word 0 + 0x0F4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB7 + CAN Frame Identifier Word 0 + 0x0F8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB7 + CAN Frame Identifier Word 1 + 0x0FC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB8 + Buffer Status / Control Register + 0x100 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB8 + CAN Frame Timestamp + 0x104 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB8 + CAN Frame Data Word 3 + 0x108 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB8 + CAN Frame Data Word 2 + 0x10C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB8 + CAN Frame Data Word 2 + 0x110 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB8 + CAN Frame Data Word 0 + 0x114 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB8 + CAN Frame Identifier Word 0 + 0x118 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB8 + CAN Frame Identifier Word 1 + 0x11C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB9 + Buffer Status / Control Register + 0x120 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB9 + CAN Frame Timestamp + 0x124 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB9 + CAN Frame Data Word 3 + 0x128 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB9 + CAN Frame Data Word 2 + 0x12C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB9 + CAN Frame Data Word 2 + 0x130 + 0x00000000 + + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB9 + CAN Frame Data Word 0 + 0x134 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB9 + CAN Frame Identifier Word 0 + 0x138 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB9 + CAN Frame Identifier Word 1 + 0x13C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB10 + Buffer Status / Control Register + 0x140 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB10 + CAN Frame Timestamp + 0x144 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB10 + CAN Frame Data Word 3 + 0x148 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB10 + CAN Frame Data Word 2 + 0x14C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB10 + CAN Frame Data Word 2 + 0x150 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB10 + CAN Frame Data Word 0 + 0x154 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB10 + CAN Frame Identifier Word 0 + 0x158 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB10 + CAN Frame Identifier Word 1 + 0x15C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB11 + Buffer Status / Control Register + 0x160 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB11 + CAN Frame Timestamp + 0x164 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB11 + CAN Frame Data Word 3 + 0x168 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB11 + CAN Frame Data Word 2 + 0x16C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB11 + CAN Frame Data Word 2 + 0x170 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB11 + CAN Frame Data Word 0 + 0x174 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB11 + CAN Frame Identifier Word 0 + 0x178 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB11 + CAN Frame Identifier Word 1 + 0x17C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB12 + Buffer Status / Control Register + 0x180 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB12 + CAN Frame Timestamp + 0x184 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB12 + CAN Frame Data Word 3 + 0x188 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB12 + CAN Frame Data Word 2 + 0x18C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB12 + CAN Frame Data Word 2 + 0x190 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB12 + CAN Frame Data Word 0 + 0x194 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB12 + CAN Frame Identifier Word 0 + 0x198 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB12 + CAN Frame Identifier Word 1 + 0x19C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB13 + Buffer Status / Control Register + 0x1A0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB13 + CAN Frame Timestamp + 0x1A4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB13 + CAN Frame Data Word 3 + 0x1A8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB13 + CAN Frame Data Word 2 + 0x1AC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB13 + CAN Frame Data Word 2 + 0x1B0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB13 + CAN Frame Data Word 0 + 0x1B4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB13 + CAN Frame Identifier Word 0 + 0x1B8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB13 + CAN Frame Identifier Word 1 + 0x1BC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB14 + Buffer Status / Control Register + 0x1C0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB14 + CAN Frame Timestamp + 0x1C4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB14 + CAN Frame Data Word 3 + 0x1C8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB14 + CAN Frame Data Word 2 + 0x1CC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB14 + CAN Frame Data Word 2 + 0x1D0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB14 + CAN Frame Data Word 0 + 0x1D4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB14 + CAN Frame Identifier Word 0 + 0x1D8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB14 + CAN Frame Identifier Word 1 + 0x1DC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_HCMB + Buffer Status / Control Register + 0x1E0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_HCMB + CAN Frame Timestamp + 0x1E4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_HCMB + CAN Frame Data Word 3 + 0x1E8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_HCMB + CAN Frame Data Word 2 + 0x1EC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_HCMB + CAN Frame Data Word 2 + 0x1F0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_HCMB + CAN Frame Data Word 0 + 0x1F4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_HCMB + CAN Frame Identifier Word 0 + 0x1F8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_HCMB + CAN Frame Identifier Word 1 + 0x1FC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CGCR + CAN Global Configuration Register + 0x200 + 0x00000000 + + + EIT + Error Interrupt Type + [11:11] + + + DIAGEN + Diagnostic Enable + [10:10] + + + INTERNAL + Internal + [9:9] + + + LOOPBACK + Loopback + [8:8] + + + IGNACK + Ignore Acknowledge + [7:7] + + + LO + Listen Only + [6:6] + + + DDIR + Data Direction + [5:5] + + + TSTPEN + Time Sync Enable + [4:4] + + + BUFFLOCK + Buffer Lock + [3:3] + + + CTX + RW,Control Transmit + [2:2] + + + CRX + RW,Control Receive + [1:1] + + + CANEN + CAN Enable + [0:0] + + + + + CTIM + CAN Timing Register + 0x204 + 0x00000000 + + + PSC + Prescaler Configuration + [15:9] + + + SJW + Synchronization Jump Width + [8:7] + + + TSEG1 + Time Segment 1 + [6:3] + + + TSEG2 + Time Segment 2 + [2:0] + + + + + GMSKX + CAN Global Mask Extension + 0x208 + 0x00000000 + + + GM + GM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard + [15:1] + + + XRTR + Extended Remote transmission Request Bit + [0:0] + + + + + GMSKB + CAN Global Mask Base + 0x20C + 0x00000000 + + + GM1 + GM[28:18] - ID[10:0] in standard, ID[28:18] in extended + [15:5] + + + RTR + Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended + [4:4] + + + IDE + Identifier Extension Bit + [3:3] + + + GM0 + GM[17:15] - Unused in standard, ID[17:15] in extended + [2:0] + + + + + BMSKX + CAN Basic Mask Extension + 0x210 + 0x00000000 + + + BM + BM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard + [15:1] + + + XRTR + Extended Remote transmission Request Bit + [0:0] + + + + + BMSKB + CAN Basic Mask Base + 0x214 + 0x00000000 + + + BM1 + BM[28:18] - ID[10:0] in standard, ID[28:18] in extended + [15:5] + + + RTR + Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended + [4:4] + + + IDE + Identifier Extension Bit + [3:3] + + + BM0 + BM[17:15] - Unused in standard, ID[17:15] in extended + [2:0] + + + + + CIEN + CAN Interrupt Enable Register + 0x218 + 0x00000000 + + + EIEN + Error Interrupt Enable + [15:15] + + + IEN + Buffer Interrupt Enable[14:0] + [14:0] + + + + + CIPND + CAN Interrupt Pending Register + 0x21C + 0x00000000 + + + EIPND + Error Interrupt Pending + [15:15] + + + IPND + Buffer Interrupt Pending[14:0] + [14:0] + + + + + CICLR + CAN Interrupt Clear Register + 0x220 + 0x00000000 + + + EICLR + Error Interrupt Clear + [15:15] + + + ICLR + Buffer Interrupt Clear[14:0] + [14:0] + + + + + CICEN + CAN Interrupt Code Enable Register + 0x224 + 0x00000000 + + + EICEN + Error Interrupt Code Enable + [15:15] + + + ICEN + Buffer Interrupt Code Enable[14:0] + [14:0] + + + + + CSTPND + CAN Status Pending Register + 0x228 + 0x00000000 + + + NS + CAN Node Status + [7:5] + + + IRQ + Interrupt Request portion of Interrupt Code + [4:4] + + + IST + Interrupt Source portion of Interrupt Code + [3:0] + + + + + CANEC + CAN Error Counter Register + 0x22C + 0x00000000 + + + REC + Receive Error Counter + [15:8] + + + TEC + Transmit Error Counter + [7:0] + + + + + CEDIAG + CAN Error Diagnostic Register + 0x230 + 0x00000000 + + + DRIVE + Drive + [14:14] + + + MON + Monitor + [13:13] + + + CRC + CRC + [12:12] + + + STUFF + Stuff Error + [11:11] + + + TXE + Transmit Error + [10:10] + + + EBID + Error Bit Identifier + [9:4] + + + EFID + Error Field Identifier + [3:0] + + + + + CTMR + CAN Timer Register + 0x234 + 0x00000000 + + + CTMR + Time Stamp Counter + [15:0] + read-only + + + + + + + CAN1 + 0x40014400 + + + + + ADC + 1.0 + Analog to Digital Converter Peripheral + ADC + 0x40022000 + + 0 + 0x00001000 + registers + + + ADC + 44 + + ADC + + + CTRL + Control Register + 0x000 + 0x00000000 + + + CONV_CNT + Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions) + [23:20] + + + MANUAL_TRIG + Starts analog acquisition + [19:19] + + + EXT_TRIG_EN + Allows the external trigger to start analog acquisition + [18:18] + + + SWEEP_EN + ADC data acquisition for all enabled channel + [17:17] + + + CHAN_TAG_EN + Enables the channel tag to be saved with the ADC data + [16:16] + + + CHAN_EN + Enables the channel for data collection + [15:0] + + + + + FIFO_DATA + FIFO data + 0x004 + read-only + 0x00000000 + + + CHAN_TAG + If enabled, this will include the number of the channel corresponding to the measurement + [15:12] + read-only + + + ADC_DATA + ADC acquisition data from the FIFO + [11:0] + + + + + STATUS + Status + 0x008 + read-only + 0x00000000 + + + ADC_BUSY + Indicates an ADC data acquisition is in process + [7:7] + + + FIFO_ENTRY_CNT + Indicates the number of entries in the FIFO + [5:0] + + + + + IRQ_ENB + Interrupt Enable + 0x00C + 0x00000000 + + + FIFO_DEPTH_TRIG + Enables the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Enables the interrupt for a trigger error + [5:5] + + + ADC_DONE + Enables the interrupt for an ADC data acquisition completion + [4:4] + + + FIFO_UFLOW + Enables the interrupt for a FIFO underflow + [3:3] + + + FIFO_OFLOW + Enables the interrupt for a FIFO overflow + [2:2] + + + FIFO_FULL + Enables the interrupt for FIFO full + [1:1] + + + FIFO_EMPTY + Enables the interrupt for FIFO empty + [0:0] + + + + + IRQ_RAW + Raw Interrupt Status + 0x010 + read-only + 0x00000001 + + + FIFO_DEPTH_TRIG + Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion + [5:5] + + + ADC_DONE + Indicates that a ADC conversion is done + [4:4] + + + FIFO_UFLOW + Indicates data was unavailable when a new trigger for ADC update is received + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred (FIFO was full when new data was written) + [2:2] + + + FIFO_FULL + Indicates the FIFO is full + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty + [0:0] + + + + + IRQ_END + Enabled Interrupt Status + 0x014 + read-only + 0x00000000 + + + FIFO_DEPTH_TRIG + Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled + [5:5] + + + ADC_DONE + Indicates that a ADC conversion is done and the interrupt is enabled + [4:4] + + + FIFO_UFLOW + Indicates a FIFO underflow occurred and the interrupt is enabled + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred and the interrupt is enabled + [2:2] + + + FIFO_FULL + Indicates the FIFO is full and the interrupt is enabled + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty and the interrupt is enabled + [0:0] + + + + + IRQ_CLR + Clear Interrupt + 0x018 + write-only + 0x00000000 + + + TRIG_ERROR + Clears the trigger error interrupt status. Always reads 0 + [3:3] + + + ADC_DONE + Clears the ADC done interrupt status. Always reads 0 + [2:2] + + + FIFO_UFLOW + Clears the FIFO underflow interrupt status. Always reads 0 + [1:1] + + + FIFO_OFLOW + Clears the FIFO overflow interrupt status. Always reads 0 + [0:0] + + + + + RXFIFOIRQTRG + Receive FIFO Interrupt Trigger Value + 0x01C + 0x00000010 + + + LEVEL + Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt + [4:0] + + + + + FIFO_CLR + FIFO Clear + 0x020 + 0x00000000 + + + FIFO_CLR + Clears the ADC FIFO. Always reads 0 + [0:0] + write-only + + + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x001907e9 + + + + + + + DAC0 + 1.0 + Digital to Analog Converter Peripheral + DAC + 0x40023000 + + 0 + 0x00000800 + registers + + + DAC0 + 40 + + + DAC1 + 41 + + DAC + + + CTRL0 + Control Register 0 + 0x000 + 0x00000000 + + + MAN_TRIG_EN + Enables manual trigger + [11:11] + + + EXT_TRIG_EN + Enables external trigger + [10:10] + + + + + CTRL1 + Control Register 1 + 0x004 + 0x00000000 + + + DAC_EN + Enables the DAC analog block + [8:8] + + + DAC_SETTLING + Sets the the amount of time in microseconds the control FSM waits for the DAC settling time + [7:5] + + + + + FIFO_DATA + FIFO data + 0x008 + read-write + 0x00000000 + + + DATA + Data for FIFO write + [11:0] + write-only + + + + + STATUS + Status + 0x00C + read-only + 0x00000000 + + + DAC_BUSY + Indicates a DAC data acquisition is in process + [7:7] + + + FIFO_ENTRY_CNT + Indicates the number of entries in the FIFO + [5:0] + + + + + IRQ_ENB + Interrupt Enable + 0x010 + 0x00000000 + + + FIFO_DEPTH_TRIG + Enables the interrupt for the FIFO entry count is less than or equal to the trigger level + [6:6] + + + TRIG_ERROR + Enables the interrupt for a trigger error + [5:5] + + + DAC_DONE + Enables the interrupt for a DAC data acquisition completion + [4:4] + + + FIFO_UFLOW + Enables the interrupt for a FIFO underflow + [3:3] + + + FIFO_OFLOW + Enables the interrupt for a FIFO overflow + [2:2] + + + FIFO_FULL + Enables the interrupt for FIFO full + [1:1] + + + FIFO_EMPTY + Enables the interrupt for FIFO empty + [0:0] + + + + + IRQ_RAW + Raw Interrupt Status + 0x014 + read-only + 0x00000041 + + + FIFO_DEPTH_TRIG + Indicates the FIFO entry count is less than or equal to the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion + [5:5] + + + DAC_DONE + Indicates that a DAC conversion is done + [4:4] + + + FIFO_UFLOW + Indicates data was unavailable when a new trigger for DAC update is received + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred (FIFO was full when new data was written) + [2:2] + + + FIFO_FULL + Indicates the FIFO is full + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty + [0:0] + + + + + IRQ_END + Enabled Interrupt Status + 0x018 + read-only + 0x00000000 + + + FIFO_DEPTH_TRIG + Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled + [5:5] + + + DAC_DONE + Indicates that a DAC conversion is done and the interrupt is enabled + [4:4] + + + FIFO_UFLOW + Indicates a FIFO underflow occurred and the interrupt is enabled + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred and the interrupt is enabled + [2:2] + + + FIFO_FULL + Indicates the FIFO is full and the interrupt is enabled + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty and the interrupt is enabled + [0:0] + + + + + IRQ_CLR + Clear Interrupt + 0x01C + write-only + 0x00000000 + + + TRIG_ERROR + Clears the trigger error interrupt status. Always reads 0 + [3:3] + + + DAC_DONE + Clears the DAC done interrupt status. Always reads 0 + [2:2] + + + FIFO_UFLOW + Clears the FIFO underflow interrupt status. Always reads 0 + [1:1] + + + FIFO_OFLOW + Clears the FIFO overflow interrupt status. Always reads 0 + [0:0] + + + + + TXFIFOIRQTRG + Receive FIFO Interrupt Trigger Value + 0x020 + 0x00000010 + + + LEVEL + Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt + [4:0] + + + + + FIFO_CLR + FIFO Clear + 0x024 + 0x00000000 + + + FIFO_CLR + Clears the DAC FIFO. Always reads 0 + [0:0] + write-only + + + + + PERID + Peripheral ID Register + 0x7fc + read-only + 0x002007e9 + + + + + DAC1 + 0x40023800 + + + + + SPW + 1.0 + SpaceWire Peripheral + SPW + 0x40003000 + + 0 + 0x00000400 + registers + + + SpW + 38 + + SPW + + + CTRL + Control Register + 0x000 + 0xA2010004 + + + RA + Reads as 1 if the RMAP command handler is available + [31:31] + read-only + + + RX + Reads as 1 if unaligned writes are available for the receiver + [30:30] + read-only + + + RC + Reads as 1 if RMAP CRC is enabled in the core + [29:29] + read-only + + + NCH + Number of DMA Channels minus one + [28:27] + read-only + + + PO + The number of available SpaceWire ports minus one + [26:26] + read-only + + + CC + CCSDS/CCITT CRC-16 + [25:25] + read-only + + + ID + Interrupt distribution available + [24:24] + read-only + + + LE + Loop-back Enable + [22:22] + read-write + + + PS + Selects the active port when the no port force bit is zero + [21:21] + read-write + + + NP + Disable port force + [20:20] + read-write + + + PNPA + SpW Plug-and-Play Available + [19:18] + read-only + + + RD + If set only one RMAP buffer is used + [17:17] + read-write + + + RE + Enable RMAP command handler + [16:16] + read-write + + + PE + SpW Plug-and-Play Enable + [15:15] + read-write + + + TL + Transmitter Enable Lock Control + [13:13] + read-write + + + TF + Time-code Flag Filter + [12:12] + read-write + + + TR + Enable time-code receptions + [11:11] + + + TT + Enable time-code transmissions + [10:10] + + + LI + Generate interrupt when link error occurs + [9:9] + + + TQ + Generate interrupt when a valid time-code is received + [8:8] + + RS + Make complete reset of the SpaceWire node. Self-clearing + [6:6] + + PM + Enable Promiscuous mode + [5:5] + + TI + The host can generate a tick by writing a one to this field + [4:4] + + + IE + If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs + [3:3] + + + AS + Automatically start the link when a NULL has been received + [2:2] + + + LS + Start the link + [1:1] + + + LD + Disable the SpaceWire CODEC + [0:0] + + + + + STS + Status/Interrupt Source Register + 0x004 + 0x06400000 + + + NRXD + Number of Receive Descriptors + [27:26] + + + NTXD + Number of Transmit Descriptors + [25:24] + + + LS + Link State + [23:21] + + + AP + Active port + [9:9] + + + EE + Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet + [8:8] + + + IA + Packet is received with an invalid destination address field + [7:7] + + + WE + A synchronization problem has occurred when receiving NChars + [6:6] + + + PE + Parity error has occurred + [4:4] + + + DE + Disconnection error has occurred + [3:3] + + + ER + Escape error has occurred + [2:2] + + + CE + Credit has occurred + [1:1] + + + TO + A new time count value was received + [0:0] + + + + + DEFADDR + Node Address Register + 0x008 + read-write + 0x000000FE + + + DEFMASK + 8-bit default mask used for node identification on the SpaceWire network + [15:8] + + + DEFADDR + 8-bit node address used for node identification on the SpaceWire network + [7:0] + + + + + CLKDIV + Clock Divisor Register + 0x00C + read-write + 0x00000909 + + + CLKDIVSTART + 8-bit Clock divisor value used for the clock-divider during startup + [15:8] + + + CLKDIVRUN + 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state + [7:0] + + + + + DKEY + Destination Key + 0x010 + 0x00000000 + + + DESTKEY + RMAP destination key + [7:0] + + + + + TC + Time Code Register + 0x014 + read-write + 0x00000000 + + + TIRQ_END + The current value of the time control flags + [7:6] + + + TIMECNT + The current value of the system time counter + [5:0] + + + + + TDR + Timer and Disconnect Register + 0x018 + read-only + 0x00000000 + + + DISCONNECT + Used to generate the 850 ns disconnect time period + [21:12] + + + TIMER64 + Used to generate the 6.4 and 12.8 us time periods + [11:0] + + + + + DMACTRL0 + DMA Control Register + 0x020 + read-write + 0x00000000 + + + INTNUM + Interrupt number used for this channel + [31:26] + + + EP + EEP Termination + [23:23] + + + TR + Truncated + [22:22] + + + IE + Interrupt code transmit enable on EEP + [21:21] + + + IT + Interrupt code transmit enable on truncation + [20:20] + + + RP + Receive Packet IRQ + [19:19] + + + TP + Transmit Packet IRQ + [18:18] + + + TL + Transmit Enable Lock + [17:17] + + + LE + Disable transmitter when a link error occurs + [16:16] + + + SP + Strip PID + [15:15] + + + SA + Strip Address + [14:14] + + + EN + Enable Address + [13:13] + + + NS + If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated + [12:12] + + + RD + Indicates to the GRSPW that there are enabled descriptors in the descriptor table + [11:11] + + + RX + Reception to the DMA channel is currently active + [10:10] + read-only + + + AT + Abort the currently transmitting packet and disable transmissions + [9:9] + read-only + + + RA + An error response was detected on the AHB bus - DMA receive + [8:8] + + + TA + An error response was detected on the AHB bus - DMA transmit + [7:7] + + + PR + Set each time a packet has been received + [6:6] + + + PS + Set each time a packet has been sent + [5:5] + + + AI + An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus + [4:4] + + + RI + An interrupt will be generated each time a packet has been received + [3:3] + + + TI + An interrupt will be generated each time a packet is transmitted + [2:2] + + + RE + Packets are allowed to be received to this channel + [1:1] + + + TE + Write a one to this bit each time new descriptors are activated in the table + [0:0] + + + + + DMAMAXLEN0 + DMA RX Maximum Length Register + 0x024 + read-write + 0x00000000 + + + RXMAXLEN + Receiver packet maximum length in bytes + [24:2] + + + + + DMATXDESC0 + DMA Transmitter Descriptor Table Address Register + 0x028 + read-write + 0x00000000 + + + DESCBASEADDR + Sets the base address of the descriptor table + [31:10] + + + DESCSEL + Offset into the descriptor table + [9:4] + + + + + DMARXDESC0 + DMA Receiver Table Destination Register + 0x02C + read-write + 0x00000000 + + + DESCBASEADDR + Sets the base address of the descriptor table + [31:10] + + + DESCSEL + Offset into the descriptor table + [9:3] + + + + + DMAADDR0 + DMA Receiver Table Address Register + 0x030 + read-write + 0x00000000 + + + MASK + Mask + [15:8] + + + ADDR + Address + [7:0] + + + + + + + + + + + + IRQ_ROUTER + 1.0 + Interrupt Router Peripheral + 0x40002000 + + 0 + 0x00001000 + registers + + + U0 + 0 + + + U1 + 1 + + + U2 + 2 + + + U3 + 3 + + + U4 + 4 + + + U5 + 5 + + + U6 + 6 + + + U7 + 7 + + + U8 + 8 + + + U9 + 9 + + + U10 + 10 + + + U11 + 11 + + + U12 + 12 + + + U13 + 13 + + + U14 + 14 + + + U15 + 15 + + + U37 + 37 + + + U39 + 39 + + + U73 + 73 + + + U75 + 75 + + + FPU + 194 + + + TXEV + 195 + + IRQ + + + DMASEL0 + Interrupt select for DMA channel 0 + 0x0000 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL1 + Interrupt select for DMA channel 1 + 0x0004 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL2 + Interrupt select for DMA channel 2 + 0x0008 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL3 + Interrupt select for DMA channel 3 + 0x000C + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMATTSEL + Trigger select for the DMA channels + 0x0010 + read-write + 0x00000000 + + + DMATTSEL + DMA trigger type selection value + [3:0] + + + + + ADCSEL + Interrupt select for ADC + 0x0014 + read-write + 0x0000001F + + + ADCSEL + ADC trigger source selection value + [4:0] + + + + + DACSEL0 + Interrupt select for DAC0 + 0x0018 + read-write + 0x0000001F + + + DACSEL + DAC trigger source selection value + [4:0] + + + + + DACSEL1 + Interrupt select for DAC1 + 0x001C + read-write + 0x0000001F + + + DACSEL + DAC trigger source selection value + [4:0] + + + + + IRQ_OUT0 + DEBUG IRQ_OUT[31:0] + 0x0020 + read-only + 0x00000000 + + + IRQ_OUT0 + IRQ_OUT[31:0] + [31:0] + + + + + IRQ_OUT1 + DEBUG IRQ_OUT[63:32] + 0x0024 + read-only + 0x00000000 + + + IRQ_OUT1 + IRQ_OUT[63:32] + [31:0] + + + + + IRQ_OUT2 + DEBUG IRQ_OUT[95:64] + 0x0028 + read-only + 0x00000000 + + + IRQ_OUT2 + IRQ_OUT[95:64] + [31:0] + + + + + IRQ_OUT3 + DEBUG IRQ_OUT[127:96] + 0x002c + read-only + 0x00000000 + + + IRQ_OUT3 + IRQ_OUT[127:96] + [31:0] + + + + + IRQ_OUT4 + DEBUG IRQ_OUT[159:128] + 0x0030 + read-only + 0x00000000 + + + IRQ_OUT4 + IRQ_OUT[159:128] + [31:0] + + + + + IRQ_OUT5 + DEBUG IRQ_OUT[179:160] + 0x0034 + read-only + 0x00000000 + + + IRQ_OUT5 + IRQ_OUT[179:160] + [19:0] + + + + + PERID + Peripheral ID Register + 0xffc + read-only + 0x028107e9 + + + + + + + WATCH_DOG + 1.0 + Watchdog Block Peripheral + 0x40021000 + + 0 + 0x00001000 + registers + + + WATCHDOG + 47 + + WDOG + + + WDOGLOAD + Counter Start Value + 0x0000 + read-write + 0xFFFFFFFF + + + CNT + Count to load + [31:0] + + + + + WDOGVALUE + Down Counter Value + 0x0004 + read-only + 0xFFFFFFFF + + + CNT + Actual Count + [31:0] + + + + + WDOGCONTROL + Enable for block reset and interrupt + 0x0008 + read-write + 0x00000000 + + + RESEN + Enable watchdog reset output + [1:1] + + + INTEN + Enable watchdog interrupt + [0:0] + + + + + WDOGINTCLR + A write of any value clears the WDT module interrupt, and reloads +the counter from the value in the WDOGLOAD Register + 0x000C + read-write + 0x00000000 + + + CLEAR + Write any value to clear interrupt + [31:0] + + + + + WDOGRIS + Raw interrupt status + 0x0010 + read-only + 0x00000000 + + + INTERRUPT + Interrupt Status + [0:0] + + + + + WDOGMIS + Interrupt status + 0x0014 + read-only + 0x00000000 + + + INTERRUPT + Masked Interrupt Status + [0:0] + + + + + WDOGLOCK + Lock + 0x00C0 + read-write + 0x00000000 + + + REG_WR_EN + Register write enable status + [31:0] + + + + + WDOGITCR + Integration test control + 0x0F00 + read-write + 0x00000000 + + + TEST_MODE_EN + Enable test mode of WDOGINT and WDOGRES + [0:0] + + + + + WDOGITOP + Integration test output set + 0x0F04 + read-write + 0x00000000 + + + WDOGINT + Set output value + [1:1] + + + WDOGRES + Set output value + [0:0] + + + + + WDOGPERIPHID0 + Peripheral ID + 0x0FE0 + read-only + 0x00000024 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID1 + Peripheral ID + 0x0FE4 + read-only + 0x000000B8 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID2 + Peripheral ID + 0x0FE8 + read-only + 0x0000001B + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID3 + Peripheral ID + 0x0FEC + read-only + 0x00000000 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPCELLID0 + PrimeCell ID + 0x0FF0 + read-only + 0x0000000D + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID1 + PrimeCell ID + 0x0FF4 + read-only + 0x000000F0 + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID2 + PrimeCell ID + 0x0FF8 + read-only + 0x00000005 + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID3 + PrimeCell ID + 0x0FFC + read-only + 0x000000B1 + + + PCELLID + Prime Cell ID + [7:0] + + + + + + + + + TRNG + 1.0 + True Random Number Generator + 0x40027000 + + 0 + 0x00000400 + registers + + + TRNG + 42 + + TRNG + + + IMR + Interrupt Mask Register + 0x0100 + read-write + 0x0000000F + + + VN_ERR_INT_MASK + Mask the Von Neumann error + [3:3] + + + CRNGT_ERR_INT_MASK + Mask the CRNGT error + [2:2] + + + AUTOCORR_ERR_INT_MASK + Mask the Autocorrelation error + [1:1] + + + EHR_VALID_INT_MASK + Mask when the TRNG has collected 192 bits + [0:0] + + + + + ISR + Interrupt Status Register + 0x0104 + read-only + 0x00000000 + + + VN_ERR + Indicates a Von Neumann error + [3:3] + + + CRNGT_ERR + Indicates a Continuous Random Number Generation Testing (CRNGT) error + [2:2] + + + AUTOCORR_ERR + Indicates that the Autocorrelation test failed four times in a row + [1:1] + + + EHR_VALID + 192 bits have been collected in the TRNG + [0:0] + + + + + ICR + Interrupt Clear Register + 0x0108 + read-write + 0x00000000 + + + VN_ERR + Clears a Von Neumann error + [3:3] + + + CRNGT_ERR + Clear a Continuous Random Number Generation Testing (CRNGT) error + [2:2] + + + AUTOCORR_ERR + Software cannot clear this bit. Only a TRNG reset can clear this bit + [1:1] + + + EHR_VALID + Set to 1 after the EHR_DATA[0,1,2,3,4,5] registers have been read + [0:0] + + + + + CONFIG + Configuration Register + 0x010C + read-write + 0x00000000 + + + RND_SRC_SEL + Selects the number of inverters (out of four possible selections) in the ring oscillator + [1:0] + + + + + VALID + Valid Register + 0x0110 + read-only + 0x00000000 + + + EHR_VALID + Indicates that the collection of bits in the TRNG is complete + [0:0] + + + + + EHR_DATA0 + Entropy Holding Register Data Register + 0x0114 + read-only + 0x00000000 + + + EHR_DATA + 32 Bits of Entropy Holding Register + [31:0] + + + + + EHR_DATA1 + Entropy Holding Register Data Register + 0x0118 + + + EHR_DATA2 + Entropy Holding Register Data Register + 0x011C + + + EHR_DATA3 + Entropy Holding Register Data Register + 0x0120 + + + EHR_DATA4 + Entropy Holding Register Data Register + 0x0124 + + + EHR_DATA5 + Entropy Holding Register Data Register + 0x0128 + + + RND_SOURCE_ENABLE + Random Source Enable Register + 0x012C + read-write + 0x00000000 + + + RND_SRC_EN + The entropy source, ring oscillator, is enabled + [0:0] + + + + + SAMPLE_CNT1 + Section TBD + 0x0130 + read-write + 0x0000FFFF + + + SAMPLE_CNTR1 + Sets the number of clk cycles between two consecutive ring oscillator samples + [31:0] + + + + + AUTOCORR_STATISTIC + Auto-correlator Statistic Register + 0x0134 + read-write + 0x00000000 + + + AUTOCORR_FAILS + Count each time an autocorrelation test fails + [21:14] + + + AUTOCORR_TRYS + Count each time an autocorrelation test starts + [13:0] + + + + + DEBUG_CONTROL + Section TBD + 0x0138 + read-write + 0x00000000 + + + AUTO_CORRELATE_BYPASS + The autocorrelation test in the TRNG module is bypassed + [3:3] + + + CRNGT_BYPASS + The CRNGT test in the TRNG is bypassed + [2:2] + + + VNC_PYPASS + The Von Neumann balancer is bypassed + [1:1] + + + + + SW_RESET + Reset Register + 0x0140 + read-write + 0x00000000 + + + SW_RESET + Writing 1 to this register causes an internal TRNG reset + [0:0] + + + + + BUSY + Busy Register + 0x01B8 + read-only + 0x00000000 + + + BUSY + Reflects the status of the rng_busy signal + [0:0] + + + + + RST_BITS_COUNTER + Reset Bits Counter Register + 0x01BC + read-write + 0x00000000 + + + RST_BITS_COUNTER + Writing any value to this bit resets the bits counter and TRNG valid registers + [0:0] + + + + + BIST_CNTR0 + BIST Counter Register + 0x01E0 + read-only + 0x00000000 + + + ROSC_CNTR_VAL + Returns the results of the TRNG BIST counter + [21:0] + + + + + BIST_CNTR1 + BIST Counter Register + 0x01E4 + + + BIST_CNTR2 + BIST Counter Register + 0x01E8 + + + + + + + ETH + 1.1 + Ethernet Block + 0x40004000 + + 0 + 0x00002000 + registers + + + Ethernet + 36 + + ETH + + + + MAC_CONFIG + Operation mode register for the MAC + 0x0000 + read-write + 0x00000000 + + + WD + Watchdog disable + [23:23] + + + JD + Jabber Disable + [22:22] + + + BE + Frame Burst Enable + [21:21] + + + JE + Jumbo Frame Enable + [20:20] + + + IFG + Inter-Frame Gap + [19:17] + + + DCRS + Disable Carrier Sense During Transmission + [16:16] + + + PS + Port Select + [15:15] + + + FES + Speed + [14:14] + + + DRO + Disable Receive Own + [13:13] + + + LM + Loopback Mode + [12:12] + + + DM + Duplex Mode + [11:11] + + + IPC + Checksum Offload + [10:10] + + + DR + Disable Retry + [9:9] + + + ACS + Automatic Pad, or CRC Stripping + [7:7] + + + BL + Back-Off-Limit + [6:5] + + + DC + Deferral Check + [4:4] + + + TE + Transmitter Enable + [3:3] + + + RE + Receiver Enable + [2:2] + + + PRELEN + Preamble Length for Transmit frames + [1:0] + + + + + MAC_FRAME_FLTR + Contains the frame filtering controls + 0x0004 + read-write + 0x00000000 + + + RA + Receive All + [31:31] + + + DNTU + Drop non TCP/UDP over IP Frames + [21:21] + + + VFTE + VLAN Tag Filter Enable + [16:16] + + + HDF + Hash or Perfect Filter + [10:10] + + + SAF + Source Address Filter Enable + [9:9] + + + SAIF + SA Inverse Filtering + [8:8] + + + PCF + Pass Control Frames + [7:6] + + + DBF + Disable Broadcast Frames + [5:5] + + + PM + Pass All Multicast + [4:4] + + + DAIF + DA Inverse Filtering + [3:3] + + + HMC + Hash Multicast + [2:2] + + + HUC + Hash Unicast + [1:1] + + + PR + Promiscuous Mode + [0:0] + + + + + MAC_GMII_ADDR + Controls the management cycles to an external PHY + 0x0010 + read-write + 0x00000000 + + + PA + Physical Layer Address + [15:11] + + + GR + GMII Register + [10:6] + + + CR + CSR Clock Range + [5:2] + + + GW + GMII Write/Read + [1:1] + + + GB + GMII Busy + [0:0] + + + + + MAC_GMII_DATA + Contains the data to be written to or read from the PHY register + 0x0014 + read-write + 0x00000000 + + + GD + GMII Data + [15:0] + + + + + MAC_FLOW_CTRL + Controls the generation of control frames + 0x0018 + read-write + 0x00000000 + + + PT + Pause time + [31:16] + + + DZPQ + Disable Zero-Quanta Pause + [7:7] + + + PLT + Pause Low Threshold + [5:4] + + + UP + Unicast Pause Frame Detect + [3:3] + + + RFE + Receive Flow Control Enable + [2:2] + + + TFE + Transmit Flow Control Enable + [1:1] + + + FCB_BPA + Flow Control Busy or Backpressure Activate + [0:0] + + + + + MAC_VLAN_TAG + Identifies IEEE 802.1Q VLAN type frames + 0x001C + read-write + 0x00000000 + + + ESVL + Enable S-VLAN + [18:18] + + + VTIM + VLAN Tag Inverse Match Enable + [17:17] + + + ETV + Enable 12-Bit VLAN Tag Comparison + [16:16] + + + VL + VLAN Tag identifier for Receive Frames + [15:0] + + + + + MAC_DEBUG + Gives the status of the various internal blocks for debugging + 0x0024 + read-only + 0x00000000 + + + TXSTSFSTS + MTL TxStatus FIFO Full Status + [25:25] + + + TXFSTS + MTL Tx FIFO Not Empty Status + [24:24] + + + TWCSTS + MTL Tx FIFO Write Controller Status + [22:22] + + + TRCSTS + MTL Tx FIFO Read Controller Status + [21:20] + + + TXPAUSED + MAC Transmitter in Pause + [19:19] + + + TFCSTS + PAC Transmit Frame Controller Status + [18:17] + + + TPESTS + MAC GMII or MII Transmit Protocol Engine Status + [16:16] + + + RXFSTS + MTL RxFIFO Fill-Level Status + [9:8] + + + RRCSTS + MTL RxFIFO Read Controller State + [6:5] + + + RWCSTS + MTL Rx FIFO Write Controller Active Status + [4:4] + + + RFCFCSTS + MAC Receive Frame FIFO Controller Status + [2:1] + + + RPESTS + MAC GMII or MII Receive Protocol Engine Status + [0:0] + + + + + MAC_INTR_STAT + Contains the interrupt status + 0x0038 + read-only + 0x00000000 + + + TSIS + Timestamp Interrupt Status + [9:9] + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status + [7:7] + + + MMCTXIS + MMC Transmit Interrupt Status + [6:6] + + + MMCRXIS + MMC Receive Interrupt Status + [5:5] + + + MMCIS + MMC Interrupt Status + [4:4] + + + + + MAC_INTR_MASK + Contains the masks for generating interrupt + 0x003C + read-write + 0x00000000 + + + TSIM + Timestamp Interrupt Mask + [9:9] + + + + + MAC_ADDR_H + Contains the high 16-bits of the first MAC Address + 0x0040 + read-write + 0x8000FFFF + + + AE + Address Enable, This bit is always set to 1 + [31:31] + read-only + + + ADDRHI + MAC Address0[47:32] + [15:0] + read-only + + + + + MAC_ADDR_L + Contains the Low 32-bits of the first MAC Address + 0x0044 + read-write + 0xFFFFFFFF + + + ADDRLO + MAC Address0[31:0] + [31:0] + read-only + + + + + MAC_WDOG_TO + Controls the watchdog time-out for received frames + 0x00DC + read-write + 0x00000000 + + + PWE + Programmable Watchdog Enable + [16:16] + + + WTO + Watchdog Timeout + [13:0] + + + + + + MMC_CNTRL + MMC Control Register + 0x0100 + read-write + 0x00000000 + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames + [8:8] + + + CNTPRSTLVL + Full-Half Preset + [5:5] + + + CNTPRST + Counters Preset + [4:4] + + + CNTFREEZ + MMC Counter Freeze + [3:3] + + + RSTONRD + Reset on Read + [2:2] + + + CNTSTOPRO + Counter Stop Rollover + [1:1] + + + CNTRST + Counters Reset + [0:0] + + + + + MMC_INTR_RX + MMC Receive Interrupt Register + 0x0104 + read-write + 0x00000000 + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status + [25:25] + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status + [24:24] + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status + [23:23] + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status + [22:22] + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status + [21:21] + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status + [20:20] + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status. + [19:19] + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status + [18:18] + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status + [17:17] + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. + [16:16] + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + [15:15] + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status + [14:14] + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status + [13:13] + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status + [12:12] + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status + [11:11] + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status + [10:10] + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status + [9:9] + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status + [8:8] + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status + [7:7] + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status + [6:6] + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status + [5:5] + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status + [4:4] + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status + [3:3] + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status + [2:2] + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status + [1:1] + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status + [0:0] + + + + + MMC_INTR_TX + MMC Transmit Interrupt Register + 0x0108 + read-write + 0x00000000 + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status + [25:25] + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status + [24:24] + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status + [23:23] + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status + [22:22] + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status + [21:21] + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status + [20:20] + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status + [19:19] + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status + [18:18] + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status + [17:17] + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status + [16:16] + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status + [15:15] + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status + [14:14] + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status + [13:13] + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status + [12:12] + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status + [11:11] + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status + [10:10] + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter + [9:9] + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + [8:8] + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status + [7:7] + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status + [6:6] + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status + [5:5] + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status + [4:4] + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status + [3:3] + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status + [2:2] + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status + [1:1] + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status + [0:0] + + + + + MMC_INTR_MASK_RX + MMC Receive Interrupt Mask Register + 0x010c + read-write + 0x00000000 + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask + [25:25] + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask + [24:24] + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask + [23:23] + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask + [22:22] + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask + [21:21] + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask + [20:20] + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask + [19:19] + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask + [18:18] + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask + [17:17] + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. + [16:16] + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + [15:15] + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + [14:14] + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + [13:13] + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + [12:12] + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask + [11:11] + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask + [10:10] + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask + [9:9] + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask + [8:8] + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask + [7:7] + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask + [6:6] + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask + [5:5] + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask + [4:4] + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask + [3:3] + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask + [2:2] + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask. + [1:1] + + + RXGBFRMIM + MMC Receive Good Bad Frame Counter Interrupt Mask + [0:0] + + + + + MMC_INTR_MASK_TX + MMC Transmit Interrupt Mask Register + 0x0110 + read-write + 0x00000000 + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask + [25:25] + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask + [24:24] + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask + [23:23] + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask + [22:22] + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask + [21:21] + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask + [20:20] + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask + [19:19] + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask + [18:18] + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask + [17:17] + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask + [16:16] + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask + [15:15] + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask + [14:14] + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask + [13:13] + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask + [12:12] + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask + [11:11] + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask + [10:10] + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + [9:9] + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + [8:8] + + + TX256T511OCTGBFIM + MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + [7:7] + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + [6:6] + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + [5:5] + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask + [4:4] + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask + [3:3] + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask + [2:2] + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask + [1:1] + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask + [0:0] + + + + + TXOCTETCOUNT_GB + MMC Transmit Count + 0x0114 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + TXFRAMECOUNT_GB + MMC Frame Count Register + 0x0118 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXBCASTFRAMES_G + MMC Good Broadcast Frames Register + 0x011c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMCASTFRAMES_G + MMC Good Multicast Frames Register + 0x0120 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX64OCT_GB + MMC Good and bad Frames transmitted with length 64 + 0x0124 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX65TO127OCT_GB + MMC Good and bad Frames transmitted with length 65 to 127 + 0x0128 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX128TO255OCT_GB + MMC Good and bad Frames transmitted with length 128 to 255 + 0x012c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX256TO511OCT_GB + MMC Good and bad Frames transmitted with length 256 to 511 + 0x0130 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX512TO1023OCT_GB + MMC Good and bad Frames transmitted with length 512 to 1023 + 0x0134 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX1024MAXOCT_GB + MMC Good and bad Frames transmitted with length 1024 to max bytes + 0x0138 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXUCASTFRAME_GB + MMC number of good and bad unicast frames transmitted + 0x013c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMCASTFRAME_GB + MMC number of good and bad MULTIcast frames transmitted + 0x0140 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXBCASTFRAME_GB + MMC number of good and bad broadcast frames transmitted + 0x0144 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXUNDERERR + MMC number of frames aborted because of frame underflow error + 0x0148 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXSINGLECOL_G + MMC Number of successfully transmitted frames after a single collision + 0x014c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMULTICOL_G + MMC Number of successfully transmitted frames after multiple collisions + 0x0150 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXDEFERRED + MMC Number of successfully transmitted frames after a deferral + 0x0154 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXLATECOL + MMC Number of aborted frames because of late collision error + 0x0158 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXEXESSCOL + MMC Number of aborted frames because of excessive collision errors + 0x015c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXCARRIERERROR + MMC Number of aborted frames because of carrier sense error + 0x0160 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXOCTETCOUNT_G + MMC Number of bytes transmitted frames only in good frames + 0x0164 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + TXFRAMECOUNT_G + MMC Number of good frames transmitted + 0x0168 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXEXCESSDEF + MMC Number of frames aborted because of excessive deferral error + 0x016c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXPAUSEFRAMES + MMC Number of good pause frames transmitted + 0x0170 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXLANFRAMES_G + MMC Number of good VLAN frames transmitted + 0x0174 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXOVERSIZE_G + MMC Number of frames transmitted without errors + 0x0178 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXFRAMECOUNT_GB + MMC Number of good and bad frames received + 0x0180 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOCTETCOUNT_GB + MMC Number of bytes received in good and bad frames + 0x0184 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + RXOCTETCOUNT_G + MMC Number of bytes received in good frames only + 0x0188 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + RXBCASTFRAMES_G + MMC Number of good broadcast frames received + 0x018c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXMCASTFRAMES_G + MMC Number of good multicast frames received + 0x0190 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXCRCERROR + MMC Number of frames received with CRC error + 0x0194 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXALIGNERROR + MMC Number of frames received with alignment error + 0x0198 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXRUNTERROR + MMC Number of frames received with runt error + 0x019c + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXJABBERERROR + MMC Number of giant frames received with length greater than 1518 bytes and with CRC error + 0x01a0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXUNDERSIZE_G + MMC Number of frames received with length less than 64 bytes + 0x01a4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOVERSIZE_G + MMC Number of frames received without errors with length greater than the max size + 0x01a8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX64OCTETS_GB + MMC Number of good and bad frames received with length 64 bytes + 0x01ac + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX65TO127OCT_GB + MMC Number of good and bad frames received with length between 65 and 127 bytes + 0x01b0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX128TO255OCT_GB + MMC Number of good and bad frames received with length between 128 and 255 bytes + 0x01b4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX256TO511OCT_GB + MMC Number of good and bad frames received with length between 256 and 511 bytes + 0x01b8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX512TO1023OCT_GB + MMC Number of good and bad frames received with length between 512 and 1023 bytes + 0x01bc + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX1024MAXOCT_GB + MMC Number of good and bad frames received with length between 1024 and max size bytes + 0x01C0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXUCASTFRAMES_G + MMC Number of received good unicast frames + 0x01C4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXLENGTHERROR + MMC Number of frames received with length error + 0x01C8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOUTRANGETYPE + MMC Number of frames received with length field not equal to the valid frame size + 0x01CC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXPAUSEFRAMES + MMC Number of good and valid Pause frames received + 0x01D0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXFIFOOVERFLOW + MMC Number of missed received frames because of FIFO overflow + 0x01D4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXVLANFRAMES_GB + MMC Number of good and bad VLAN frames received + 0x01D8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXWDOGERROR + MMC Number of frames received with error because of watchdog timeout error + 0x01DC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXRCVERROR + MMC Number of frames received with Receive error or Frame Extension error + 0x01E0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXCTRLFRAMES_G + MMC Number of received good control frames + 0x01E4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + VLAN_INCREPLACE + Holds the VLAN Tag for insertion into or replacement in the transmit frames + 0x0584 + read-write + 0x00000000 + + + CSVL + C-VLAN or S-VLAN + [19:19] + + + VLP + VLAN Priority Control + [18:18] + + + VLC + VLAN Tag Control in Transmit Frames + [17:16] + + + VLT + VLAN Tag for Transmit Frames + [15:0] + + + + + VLAN_HASHTABLE + Holds the VLAN Hash Table + 0x0588 + read-write + 0x00000000 + + + VLHT + VLAN Hash Table + [15:0] + + + + + TIMESTAMP_CTRL + Controls the IEEE 1588 timestamp generation and update logic + 0x0700 + read-write + 0x00000000 + + + ATSEN3 + Auxiliary Snapshot 3 Enable + [28:28] + + + ATSEN2 + Auxiliary Snapshot 2 Enable + [27:27] + + + ATSEN1 + Auxiliary Snapshot 1 Enable + [26:26] + + + ATSEN0 + Auxiliary Snapshot 0 Enable + [25:25] + + + ATSFC + Auxiliary Snapshot FIFO Clear + [24:24] + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering + [18:18] + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + [17:16] + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master + [15:15] + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages + [14:14] + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + [13:13] + + + TSIPV6ENA + Enable Processing of PTP Frames Sent over IPv6-UDP + [12:12] + + + TSIPENA + Enable Processing of PTP over Ethernet Frames + [11:11] + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format + [10:10] + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control + [9:9] + + + TSENALL + Enable Timestamp for All Frames + [8:8] + + + TSADDRREG + Addend Reg Update + [5:5] + + + TSTRIG + Timestamp Interrupt Trigger Enable + [4:4] + + + TSUPDT + Timestamp Update + [3:3] + + + TSINIT + Timestamp Initialize + [2:2] + + + TSCFUPDT + Timestamp Fine or Coarse Update + [1:1] + + + TSENA + Timestamp Enable + [0:0] + + + + + SUBSEC_INC + Holds the 8-bit value by which the Sub-Second register is incremented + 0x0704 + read-write + 0x00000000 + + + SSINC + Sub-Second Increment Valuee + [7:0] + + + + + SYSTIME_SECONDS + Holds the lower 32 bits of the second field of the system time + 0x0708 + read-only + 0x00000000 + + + TSS + Timestamp Second + [31:0] + + + + + SYSTIME_NANOSEC + Holds 32 bits of the nano-second field of the system time + 0x070C + read-only + 0x00000000 + + + TSSS + Timestamp Sub Seconds + [30:0] + + + + + SYSTIME_SECSUPDAT + Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value + 0x0710 + read-write + 0x00000000 + + + TSS + Timestamp Second + [31:0] + + + + + SYSTIME_NSECUP + Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value + 0x0714 + read-write + 0x00000000 + + + ADDSUB + Add or Subtract Time + [31:31] + + + TSSS + Timestamp Sub Seconds + [30:0] + + + + + TIMESTAMPADDEND + This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency + 0x0718 + read-write + 0x00000000 + + + TSAR + Timestamp Addend Register + [31:0] + + + + + TARGET_TIME_SECS + Holds the high 32-bits of time to be compared with the system time + 0x071C + read-write + 0x00000000 + + + TSTR + Target Time Seconds Registe + [31:0] + + + + + TARGET_TIME_NSEC + Holds the lower 32-bits of time to be compared with the system time + 0x0720 + read-write + 0x00000000 + + + TRGTBUSY + 32 Bits of Hash Table + [31:31] + + + TTSLO + Target Timestamp Low Register + [30:0] + + + + + + DMA_BUS_MODE + Controls the DMA Host Interface Mode + 0x1000 + read-write + 0x00020101 + + + RIB + Rebuild INCRx Burst + [31:31] + + + PRWG + Channel Priority Weights + [29:28] + + + TXPR + Transmit Priority + [27:27] + + + MB + Mixed Burst + [26:26] + + + AAL + Address-Aligned Beats + [25:25] + + + PBLx8 + PBLx8 Mode + [24:24] + + + USP + Use Separate PBL + [23:23] + + + RPBL + Rx DMA PBL + [22:17] + + + FB + Fixed Burste + [16:16] + + + PR + Priority Ratio + [15:14] + + + PBL + Programmable Burst Lengthe + [13:8] + + + DSL + Descriptor Skip Length + [6:2] + + + DA + DMA Arbitration Scheme + [1:1] + + + SWR + Software Reset (Read, Write Set, and Self Clear) + [0:0] + + + + + DMA_TX_POLL_DEMAND + Used by the host to instruct the DMA to poll the transmit Descriptor list + 0x1004 + read-write + 0x00000000 + + + TPD + Transmit Poll Demand (Read Only and Write Trigger) + [31:0] + + + + + DMA_RX_POLL_DEMAND + Used by the host to instruct the DMA to poll the Receive Descriptor list + 0x1008 + read-write + 0x00000000 + + + RPD + Receive Poll Demand (Read Only and Write Trigger) + [31:0] + + + + + DMA_RX_DESC_LIST_ADDR + Points the DMA to the start of the Receive Descriptor list + 0x100C + read-write + 0x00000000 + + + RDESLA + Start of Receive List + [31:0] + + + + + DMA_TX_DESC_LIST_ADDR + Points the DMA to the start of the Transmit Descriptor list + 0x1010 + read-write + 0x00000000 + + + TDESLA + Start of Transmit List + [31:0] + + + + + DMA_STATUS + Used to determine the status of the DMA + 0x1014 + read-only + 0x00000000 + + + TTI + Timestamp Trigger Interrupt + [29:29] + + + GMI + GMAC MMC Interrupt + [27:27] + + + EB + Error Bits + [25:23] + + + TS + Transmit Process State + [22:20] + + + RS + Receive Process State + [19:17] + + + NIS + Normal Interrupt Summary + [16:16] + + + AIS + Abnormal Interrupt Summary + [15:15] + + + ERI + Early Receive Interrupt + [14:14] + + + FBI + Fatal Bus Error Interruptble + [13:13] + + + ETI + Early Transmit Interrupt + [10:10] + + + RWT + Receive Watchdog Timeout + [9:9] + + + RPS + Receive Process Stopped + [8:8] + + + RU + Receive Buffer Unavailable + [7:7] + + + RI + Receive Interrupt + [6:6] + + + UNF + Transmit Underflow + [5:5] + + + OVF + Receive Underflow + [4:4] + + + TJT + Transmit Jabber Timeout + [3:3] + + + TU + Transmit Buffer Unavailable + [2:2] + + + TPS + Transmit Process Stopped + [1:1] + + + TI + Transmit Interrupt + [0:0] + + + + + DMA_OPER_MODE + Sets the Receive and Transmit operation mode and command + 0x1018 + read-write + 0x00000000 + + + DT + Disable Dropping of TCP/IP Checksum Error Frames + [26:26] + + + RSF + Receive Store and Forward + [25:25] + + + DFF + Disable Flushing of Received Frames + [24:24] + + + TSF + Transmit Store and Forward + [21:21] + + + FTF + Flush Transmit FIFO + [20:20] + + + TTC + Transmit Threshold Control + [16:14] + + + ST + Start or Stop Transmission Command + [13:13] + + + RFD + Threshold for Deactivating Flow Control + [12:11] + + + RFA + Threshold for Activating Flow Control + [10:9] + + + FEF + Forward Error Frames + [7:7] + + + FUF + Forward Undersized Good Frames + [6:6] + + + DGF + Drop Giant Frames + [5:5] + + + RTC + Receive Threshold Control + [4:3] + + + OSF + Operate on Second Frame + [2:2] + + + SR + Start or Stop Receive + [1:1] + + + + + DMA_INTR_EN + Enables the interrupts reported in the status register + 0x101C + read-write + 0x00000000 + + + NIE + Normal Interrupt Summary Enable + [16:16] + + + AIE + Abnormal Interrupt Summary Enable + [15:15] + + + ERE + Early Receive Interrupt Enable + [14:14] + + + FBE + Fatal Bus Error Enable + [13:13] + + + ETE + Early Transmit Interrupt Enable + [10:10] + + + RWE + Receive Watchdog Timeout Enable + [9:9] + + + RSE + Receive Stopped Enable + [8:8] + + + RUE + Receive Buffer Unavailable Enable + [7:7] + + + RIE + Receive Interrupt Enable + [6:6] + + + UNE + Underflow Interrupt Enable + [5:5] + + + OVE + Overflow Interrupt Enable + [4:4] + + + THE + Transmit Jabber Timeout Enable + [3:3] + + + TUE + Transmit Buffer Unavailable Enable + [2:2] + + + TSE + Transmit Stopped Enable + [1:1] + + + TIE + Transmit Interrupt Enable + [0:0] + + + + + DMA_MISS_OVER_COUNTER + Contains the counters for discarded frames because no Receive Descriptor is available + 0x1020 + read-write + 0x00000000 + + + OVFCNTOVF + This bit is set every time the Overflow Frame Counter (Bits[27:17])overflows + [28:28] + + + OVFFRMCNT + This field indicates the number of frames missed by the application + [27:17] + + + MISCNTOVF + This bit is set every time Missed Frame Counter (Bits[15:0]) overflows + [16:16] + + + MISFRMCNT + This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. + [15:0] + + + + + DMA_RX_INTR_WDOG_TIMER + Watchdog timeout for Receive Interrupt from DMA + 0x1024 + read-write + 0x00000000 + + + RIWT + These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set. + [7:0] + + + + + DMA_AHB_STATUS + Provides the active status of the read and write channels of the AHB master interface + 0x102C + read-write + 0x00000000 + + + AHBMASTRSTS + When high, indicates that the AHB master interface FSMs are in the non-idle state + [0:0] + + + + + DMA_CURR_TX_DESC + Contains the start address of the current Transmit Descriptor read by the DMA + 0x1048 + read-write + 0x00000000 + + + CURTDESAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_RX_DESC + Contains the start address of the current Receive Descriptor read by the DMA + 0x104C + read-write + 0x00000000 + + + CURRDESAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_TX_BUFR_ADDR + Contains the start address of the current Receive Descriptor read by the DMA + 0x1050 + read-write + 0x00000000 + + + CURTBUFAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_RX_BUFR_ADDR + Contains the current Receive Buffer address read by the DMA + 0x1054 + read-write + 0x00000000 + + + CURTBUFAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + + + \ No newline at end of file diff --git a/va416xx/svd/va416xx.svd.patched b/va416xx/svd/va416xx.svd.patched new file mode 100644 index 0000000..5e7a24a --- /dev/null +++ b/va416xx/svd/va416xx.svd.patched @@ -0,0 +1,12271 @@ + + + VORAGO TECHNOLOGIES + SST + va416xx + M4 + 1.3 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 100MHz + VORAGO Technologies \n +\n +----------------------------------------------------------------------------\n + Copyright (c) 2013-2020 VORAGO Technologies\n +\n + BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND BY ALL THE TERMS\n + AND CONDITIONS OF THE VORAGO TECHNOLOGIES END USER LICENSE AGREEMENT. \n +\n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + VORAGO TECHNOLOGIES SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE\n + FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\n + + CM4 + r0p1 + little + false + true + 4 + false + + system_va416xx + VOR_ + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + CLKGEN + 1.0 + Clock Generation Peripheral + 0x40006000 + + 0x0 + 0x100 + registers + + + LoCLK + 45 + + + + CTRL0 + Clock Generation Module Control Register 0 + 0x0 + 0x00000030 + + + SYS_CLK_LOST_DET_EN + Enable the circuit that detects loss of SYS_CLK + [31:31] + + + PLL_RESET + Writing this bit to 1 puts the PLL into reset + [30:30] + + + CLK_DIV_SEL + Selects the PLL out divider to divide by 1/2/4/8 + [29:28] + + + PLL_CLKR + PLL Symbol; selects the values 1-16 for the reference divider + [27:24] + + + PLL_CLKF + PLL Symbol; selects the values 1-64 for the multiplication factor + [23:18] + + + PLL_CLKOD + PLL Symbol; selects the values 1-16 for the post VCO divider + [17:14] + + + PLL_BWADJ + PLL Symbol; selects the values 1-64 for the bandwidth divider + [13:8] + + + PLL_TEST + PLL Symbol; Reference-to-counters-to-output bypass when high + [7:7] + + + PLL_BYPASS + PLL Symbol; reference-to-output bypass when high + [6:6] + + + PLL_PWDN + PLL Symbol; power down when high + [5:5] + + + PLL_INTFB + PLL Symbol; select internal feedback path when high rather than FCLK + [4:4] + + + CLKSEL_SYS + Input clock select to PLL + [3:2] + + + REF_CLK_SEL + PLL Reference Clock Select + [1:0] + + + + + STAT + Clock Generation Module Status Register + 0x4 + read-only + 0x00000000 + + + SYSCLKLOST + Set when SYS_CLK has dropped to less than 1MHz + [3:3] + read-only + + + LOCKLOST + LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles + [2:2] + read-only + + + RFSLIP + Reference cycle slip output (CLKOUT frequency high) + [1:1] + read-only + + + FBSLIP + Feedback cycle slip output (CLKOUT frequency low) + [0:0] + read-only + + + + + CTRL1 + Clock Generation Module Control Register 1 + 0x8 + read-write + 0x00000000 + + + ADC_CLK_DIV_SEL + Clock divider select for ADC + [6:5] + + + XTAL_N_EN + Enables XTAL_N output + [4:4] + + + XTAL_EN + Enables the crystal oscillator + [3:3] + + + PLL_LOST_LOCK_DET_EN + Enables the PLL lock lost detection circuit + [2:2] + + + PLL_LCK_DET_REARM + Resets/Rearms the PLL lock detect circuit + [1:1] + + + SYS_CLK_LOST_DET_REARM + Resets/Rearms the SYS_CLK lost detection feature + [0:0] + + + + + + + SYSCONFIG + 1.0 + System Configuration Peripheral + 0x40010000 + + 0x0 + 0x1000 + registers + + + LVD + 46 + + + EDAC_MBE + 76 + + + EDAC_SBE + 77 + + + + RST_STAT + System Reset Status + 0x0 + read-write + 0x00000000 + + + POR + Power On Reset Status + [0:0] + + + EXTRST + External Reset Status + [1:1] + + + SYSRSTREQ + SYSRESETREQ Reset Status + [2:2] + + + LOOKUP + LOOKUP Reset Status + [3:3] + + + WATCHDOG + WATCHDOG Reset Status + [4:4] + + + MEMERR + Memory Error Reset Status + [5:5] + read-only + + + + + RST_CNTL_ROM + ROM Reset Control + 0x4 + 0x0000003F + + + RST_CNTL_RAM0 + RAM Reset Control + 0x8 + 0x0000003F + + + RST_CNTL_RAM1 + RAM Reset Control + 0xC + 0x0000003F + + + ROM_PROT + ROM Protection Configuration + 0x10 + 0x00000000 + + + WREN + ROM Write Enable Bit + [0:0] + + + + + ROM_SCRUB + ROM Scrub Period Configuration + 0x14 + read-write + 0x00000000 + + + VALUE + Counter divide value + [23:0] + + + RESET + Reset Counter + [31:31] + write-only + oneToClear + + + + + RAM0_SCRUB + RAM0 Scrub Period Configuration + 0x18 + + + RAM1_SCRUB + RAM1 Scrub Period Configuration + 0x1C + + + IRQ_ENB + Enable EDAC Error Interrupt Register + 0x20 + read-write + 0x00000000 + + + ROMMBE + ROM Multi Bit Interrupt + [0:0] + + + ROMSBE + ROM Single Bit Interrupt + [1:1] + + + RAM0MBE + RAM0 Multi Bit Interrupt + [2:2] + + + RAM0SBE + RAM0 Single Bit Interrupt + [3:3] + + + RAM1MBE + RAM1 Multi Bit Interrupt + [4:4] + + + RAM1SBE + RAM1 Single Bit Interrupt + [5:5] + + + + + IRQ_RAW + Raw EDAC Error Interrupt Status + 0x24 + read-only + 0x00000000 + + + IRQ_END + Enabled EDAC Error Interrupt Status + 0x28 + read-only + 0x00000000 + + + IRQ_CLR + Clear EDAC Error Interrupt Status + 0x2C + write-only + 0x00000000 + oneToClear + + + RAM0_SBE + Count of RAM0 EDAC Single Bit Errors + 0x30 + 0x00000000 + + + COUNT + RAM0 EDAC Single Bit Errors + [15:0] + + + + + RAM1_SBE + Count of RAM1 EDAC Single Bit Errors + 0x34 + + + RAM0_MBE + Count of RAM0 EDAC Multi Bit Errors + 0x38 + 0x00000000 + + + COUNT + RAM0 Multi Bit Errors + [15:0] + + + + + RAM1_MBE + Count of RAM1 EDAC Multi Bit Errors + 0x3C + + + ROM_SBE + Count of ROM EDAC Single Bit Errors + 0x40 + + + ROM_MBE + Count of ROM EDAC Multi Bit Errors + 0x44 + + + ROM_RETRIES + ROM BOOT Retry count + 0x48 + read-only + 0x00000000 + + + COUNT + Count of ROM block Retries + [7:0] + + + + + REFRESH_CONFIG_H + Register Refresh Rate for TMR registers + 0x4C + 0x00000000 + + + DIVCOUNT + Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles + [7:0] + + + TESTMODE + Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly. + [31:30] + + + + + TIM_RESET + TIM Reset Control + 0x50 + 0xFFFFFFFF + + + TIM_RESET + Reset of a given TIMER + [23:0] + + + + + TIM_CLK_ENABLE + TIM Enable Control + 0x54 + 0x00000000 + + + TIMERS + Clock enable of a given TIMER + [23:0] + + + + + PERIPHERAL_RESET + Peripheral Reset Control + 0x58 + 0x7F7BEFFF + + + SPI0 + Resetn of SPI0 + [0:0] + + + SPI1 + Resetn of SPI1 + [1:1] + + + SPI2 + Resetn of SPI2 + [2:2] + + + SPI3 + Resetn of SPI3 + [3:3] + + + UART0 + Resetn of UART0 + [4:4] + + + UART1 + Resetn of UART1 + [5:5] + + + UART2 + Resetn of UART2 + [6:6] + + + I2C0 + Resetn of I2C0 + [7:7] + + + I2C1 + Resetn of I2C1 + [8:8] + + + I2C2 + Resetn of I2C2 + [9:9] + + + CAN0 + Resetn of CAN0 + [10:10] + + + CAN1 + Resetn of CAN1 + [11:11] + + + TRNG + Resetn of TRNG + [12:12] + + + ADC + Resetn of ADC + [13:13] + + + DAC + Resetn of DAC + [14:14] + + + DMA + Resetn of DMA + [15:15] + + + EBI + Resetn of EBI + [16:16] + + + ETH + Resetn of Ethernet + [17:17] + + + SPW + Resetn of SpaceWire + [18:18] + + + CLKGEN + RESETn of PLL in Clock Generation Module + [19:19] + + + IRQ + Resetn of IRQ Router + [20:20] + + + IOCONFIG + Resetn of IO CONFIG + [21:21] + + + UTILITY + Resetn of UTILITY peripheral + [22:22] + + + WDOG + Resetn of WDOG + [23:23] + + + PORTA + Resetn of PORTA + [24:24] + + + PORTB + Resetn of PORTB + [25:25] + + + PORTC + Resetn of PORTC + [26:26] + + + PORTD + Resetn of PORTD + [27:27] + + + PORTE + Resetn of PORTE + [28:28] + + + PORTF + Resetn of PORTF + [29:29] + + + PORTG + Resetn of PORTG + [30:30] + + + + + PERIPHERAL_CLK_ENABLE + Peripheral Enable Control + 0x5C + 0x00880000 + + + SPW_M4_CTRL + SPW M4 control register + 0x60 + 0x00030000 + + + LREN + Lockup reset enable + [17:17] + + + SPW_PAD_EN + SPW pad enable + [16:16] + + + REG_WR_KEY + Fuse-analog register writes enabled when key = 0xfeed + [15:0] + + + + + PMU_CTRL + PMU Control Register + 0x64 + 0x00000000 + + + LVL_SLCT + Select the POK detect level + [1:0] + + + + + WAKEUP_CNT + Wakeup Control + 0x68 + 0x00000007 + + + CNTSTRT + Launch SLP mode in analog block + [3:3] + + + WKUP_CNT + Used to set a time to wake up the processor after the device has been put in a low power state + [2:0] + + + + + EBI_CFG0 + EBI Config Register 0 + 0x6C + 0x00000000 + + + ADDRLOW0 + Lower bound address for CEN0 + [7:0] + + + ADDRHIGH0 + Upper bound address for CEN0 + [15:8] + + + CFGREADCYCLE + Number of cycles for a read - N plus 1 + [18:16] + + + CFGWRITECYCLE + Number of cycles for a write - N plus 1 + [21:19] + + + CFGTURNAROUNDCYCLE + Number of cycles for turnaround - N plus 1 + [24:22] + + + CFGSIZE + 8 bit (0) or 16 bit (1) port size + [25:25] + + + + + EBI_CFG1 + EBI Config Register 1 + 0x70 + 0x00000000 + + + EBI_CFG2 + EBI Config Register 2 + 0x74 + 0x00000000 + + + EBI_CFG3 + EBI Config Register 3 + 0x78 + 0x00000000 + + + ANALOG_CNTL + Analog Control Register + 0x7C + 0x00000000 + + + TMOSC + Test Mode + [0:0] + + + TMPOKDIS + Test Mode + [1:1] + + + TM_ADCMUX_N + Test Mode + [2:2] + + + TM_ADCMUX_P + Test Mode + [3:3] + + + TMRATIO + Test Mode + [4:4] + + + TMATOMUX + Test Mode + [6:5] + + + ADC_STEST + Number of clocks for sample time + [12:9] + + + RCLK_POS_EN + Enable normal test clock + [14:14] + + + RCLK_NEG_EN + Enable inverted test clock + [15:15] + + + APB2CLK_POS_EN + Enable normal APB2CLK for test output + [16:16] + + + APB2CLK_NEG_EN + Enable inverted APB2CLK for test output + [17:17] + + + TM_ANALOG_PD_EN + Enables pull down on analog pads + [18:18] + + + JMP2BOOT + Enables a skip of all delay counters and eFuse read + [19:19] + + + SKIPBOOT + Enables a skip of all delay counters, eFuse read, and boot + [20:20] + + + + + SW_CLKDIV10 + Initial SpW Clock Divider Value + 0x80 + read-write + 0x00000009 + + + SW_CLKDIV10 + Defines the initial value for the SpW clock, defaults to divide by ten + [7:0] + + + + + REFRESH_CONFIG_L + Register Refresh Rate for TMR registers + 0x84 + read-write + 0x0000000F + + + DIVCOUNT + Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles + [31:0] + + + + + DAC0_CAL + DAC0 Calibration Register + 0xFD0 + read-only + 0x00000000 + + + DAC0_CAL + DAC0 Calibration bits + [4:0] + + + + + DAC1_CAL + DAC1 Calibration Register + 0xFD4 + read-only + 0x00000000 + + + DAC1_CAL + DAC1 Calibration bits + [4:0] + + + + + ADC_CAL + ADC Calibration Register + 0xFD8 + read-only + 0x00000000 + + + ADC_CAL + ADC Calibration bits + [4:0] + + + + + BG_CAL + Bandgap Calibration Register + 0xFDC + read-only + 0x00000000 + + + BG_CAL + Bandgap Calibration bits + [2:0] + + + + + DREG_CAL + Digital LDO Regulator Calibration Register + 0xFE0 + read-only + 0x00000000 + + + DREG_CAL + Digital LDO Regulator Calibration bits + [8:0] + + + + + AREG_CAL + Analog LDO Regulator Calibration Register + 0xFE4 + read-only + 0x00000000 + + + AREG_CAL + Analog LDO Regulator Calibration bits + [8:0] + + + + + HBO_CAL + Heart Beat OSC Calibration Register + 0xFE8 + read-only + 0x00000000 + + + OSC_CAL + 1MHz OSC Calibration bit + [3:3] + + + HBO_CAL + Heart Beat OSC Calibration bits + [2:0] + + + + + EF_CONFIG + EFuse Config Register + 0xFEC + read-only + 0x0A800C40 + + + ROM_SPEED + Specifies the speed of ROM_SCK + [1:0] + + + ROM_SIZE + Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset + [5:2] + + + ROM_NOCHECK + When set to 1, the ROM check is skipped + [6:6] + + + BOOT_DELAY + Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset + [9:7] + + + ROM_READ + SPI ROM read instruction code + [17:10] + + + ROM_LATENCY + Number of bits of latency from Address until data from the SPI ROM + [22:18] + + + ROM_ADDRESS + ROM Address Mode + [24:23] + + + ROM_DLYCAP + ROM SPI Delayed capture + [25:25] + + + ROM_STATUS + The first data byte from the SPI ROM following an address is taken as a status byte + [26:26] + + + RM + This bit controls the internal RAM read timing and must be maintained at this value + [27:27] + + + WM + This bit controls the internal RAM write timing and must be maintained at this value + [28:28] + + + + + EF_ID0 + EFuse ID0 Register + 0xFF0 + read-only + 0x00000000 + + + EF_ID1 + EFuse ID1 Register + 0xFF4 + read-only + 0x00000000 + + + PROCID + Processor ID Register + 0xFF8 + read-only + 0x040057E3 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x028007E9 + + + MANUFACTURER_ID + MANUFACTURER_ID + [11:0] + read-only + + + PERIPHERAL_ID + PERIPHERAL_ID + [23:16] + read-only + + + PERIPHERAL_VER + PERIPHERAL_VER + [31:24] + read-only + + + + + + + DMA + 1.0 + DMA Controller Block + 0x40001000 + + 0x0 + 0x1000 + registers + + + DMA_ERROR + 43 + + + DMA_ACTIVE0 + 174 + + + DMA_ACTIVE1 + 175 + + + DMA_ACTIVE2 + 176 + + + DMA_ACTIVE3 + 177 + + + DMA_DONE0 + 178 + + + DMA_DONE1 + 179 + + + DMA_DONE2 + 180 + + + DMA_DONE3 + 181 + + + + STATUS + DMA Status + 0x0 + read-only + 0x00000000 + + + TEST_STATUS + Test Status Logic Included + [31:28] + read-write + + + CHNLS_MINUS1 + Number of Available Channels Minus 1 + [20:16] + + + STATE + Current State of the control state machine + [7:4] + + + MASTER_ENABLE + Enable status of the controller + [0:0] + + + + + CFG + DMA Configuration + 0x4 + write-only + 0x00000000 + + + CHNL_PROT_CTRL + HPROT[3:0] + [7:5] + + + MASTER_ENABLE + PLL Symbol; Feedback cycle slip output (CLKOUT frequency low) + [0:0] + read-write + + + + + CTRL_BASE_PTR + Base Pointer for DMA Control Registers + 0x8 + 0x00000000 + + + CTRL_BASE_PTR + Base Pointer for DMA Control Registers + [31:7] + + + + + ALT_CTRL_BASE_PTR + DMA Channel alternate control data base pointer + 0xC + read-write + 0x00000000 + + + ALT_CTRL_BASE_PTR + Base Pointer for Alternate DMA Control Register + [31:0] + + + + + WAITONREQ_STATUS + DMA channel wait on request status + 0x10 + read-only + 0x00000000 + + + CH3 + DMA wait on request + [3:3] + read-write + + + CH2 + DMA wait on request + [2:2] + read-write + + + CH1 + DMA wait on request + [1:1] + read-write + + + CH0 + DMA wait on request + [0:0] + read-write + + + + + CHNL_SW_REQUEST + DMA channel software request + 0x14 + write-only + 0x00000000 + + + CH3 + Channel SW request + [3:3] + read-write + + + CH2 + Channel SW request + [2:2] + read-write + + + CH1 + Channel SW request + [1:1] + read-write + + + CH0 + Channel SW request + [0:0] + read-write + + + + + CHNL_USEBURST_SET + DMA channel useburst set + 0x18 + 0x00000000 + + + CH3 + Channel use burst set + [3:3] + read-write + + + CH2 + Channel use burst set + [2:2] + read-write + + + CH1 + Channel use burst set + [1:1] + read-write + + + CH0 + Channel use burst set + [0:0] + read-write + + + + + CHNL_USEBURST_CLR + DMA channel useburst clear + 0x1C + 0x00000000 + + + CH3 + Channel use burst clear + [3:3] + read-write + + + CH2 + Channel use burst clear + [2:2] + read-write + + + CH1 + Channel use burst clear + [1:1] + read-write + + + CH0 + Channel use burst clear + [0:0] + read-write + + + + + CHNL_REQ_MASK_SET + DMA channel request mask set + 0x20 + 0x00000000 + + + CH3 + Channel Request Mask set + [3:3] + read-write + + + CH2 + Channel Request Mask set + [2:2] + read-write + + + CH1 + Channel Request Mask set + [1:1] + read-write + + + CH0 + Channel Request Mask set + [0:0] + read-write + + + + + CHNL_REQ_MASK_CLR + DMA channel request mask clear + 0x24 + 0x00000000 + + + CH3 + Channel Request Mask clear + [3:3] + read-write + + + CH2 + Channel Request Mask clear + [2:2] + read-write + + + CH1 + Channel Request Mask clear + [1:1] + read-write + + + CH0 + Channel Request Mask clear + [0:0] + read-write + + + + + CHNL_ENABLE_SET + DMA channel enable set + 0x28 + 0x00000000 + + + CH3 + Channel Enable set + [3:3] + read-write + + + CH2 + Channel Enable set + [2:2] + read-write + + + CH1 + Channel Enable set + [1:1] + read-write + + + CH0 + Channel Enable set + [0:0] + read-write + + + + + CHNL_ENABLE_CLR + DMA channel enable clear + 0x2C + 0x00000000 + + + CH3 + Channel Enable clear + [3:3] + read-write + + + CH2 + Channel Enable clear + [2:2] + read-write + + + CH1 + Channel Enable clear + [1:1] + read-write + + + CH0 + Channel Enable clear + [0:0] + read-write + + + + + CHNL_PRI_ALT_SET + DMA channel primary alternate set + 0x30 + 0x00000000 + + + CH3 + Channel PRI_ALT set + [3:3] + read-write + + + CH2 + Channel PRI_ALT set + [2:2] + read-write + + + CH1 + Channel PRI_ALT set + [1:1] + read-write + + + CH0 + Channel PRI_ALT set + [0:0] + read-write + + + + + CHNL_PRI_ALT_CLR + DMA channel primary alternate clear + 0x34 + 0x00000000 + + + CH3 + Channel PRI_ALT clear + [3:3] + read-write + + + CH2 + Channel PRI_ALT clear + [2:2] + read-write + + + CH1 + Channel PRI_ALT clear + [1:1] + read-write + + + CH0 + Channel PRI_ALT clear + [0:0] + read-write + + + + + CHNL_PRIORITY_SET + DMA channel priority set + 0x38 + read-write + 0x00000000 + + + CH3 + Channel PRIORITY set + [3:3] + read-write + + + CH2 + Channel PRIORITY set + [2:2] + read-write + + + CH1 + Channel PRIORITY set + [1:1] + read-write + + + CH0 + Channel PRIORITY set + [0:0] + read-write + + + + + CHNL_PRIORITY_CLR + DMA channel priority clear + 0x3C + write-only + 0x00000000 + + + CH3 + Channel PRIORITY clear + [3:3] + write-only + + + CH2 + Channel PRIORITY clear + [2:2] + write-only + + + CH1 + Channel PRIORITY clear + [1:1] + write-only + + + CH0 + Channel PRIORITY clear + [0:0] + write-only + + + + + ERR_CLR + DMA bus error clear + 0x4C + 0x00000000 + + + ERR_CLR + Error Clear + [0:0] + read-write + + + + + INTEGRATION_CFG + DMA integration configuration + 0xE00 + 0x00000000 + + + INT_TEST_EN + Error Clear + [0:0] + read-write + + + + + STALL_STATUS + DMA stall status + 0xE08 + 0x00000000 + + + STALL_STATUS + DMA is stalled + [0:0] + read-only + + + + + DMA_REQ_STATUS + DMA Configuration + 0xE10 + 0x00000000 + + + CH3 + DMA Request Status for this CH + [3:3] + read-write + + + CH2 + DMA Request Status for this CH + [2:2] + read-write + + + CH1 + DMA Request Status for this CH + [1:1] + read-write + + + CH0 + DMA Request Status for this CH + [0:0] + read-write + + + + + DMA_SREQ_STATUS + DMA single request status + 0xE18 + 0x00000000 + + + CH3 + DMA SRequest Status for this CH + [3:3] + read-write + + + CH2 + DMA SRequest Status for this CH + [2:2] + read-write + + + CH1 + DMA SRequest Status for this CH + [1:1] + read-write + + + CH0 + DMA SRequest Status for this CH + [0:0] + read-write + + + + + DMA_DONE_SET + DMA done set + 0xE20 + 0x00000000 + + + CH3 + DMA Done Set for this CH + [3:3] + read-write + + + CH2 + DMA Done Set for this CH + [2:2] + read-write + + + CH1 + DMA Done Set for this CH + [1:1] + read-write + + + CH0 + DMA Done Set for this CH + [0:0] + read-write + + + + + DMA_DONE_CLR + DMA done clear + 0xE24 + 0x00000000 + + + CH3 + DMA Done clear for this CH + [3:3] + read-write + + + CH2 + DMA Done clear for this CH + [2:2] + read-write + + + CH1 + DMA Done clear for this CH + [1:1] + read-write + + + CH0 + DMA Done clear for this CH + [0:0] + read-write + + + + + DMA_ACTIVE_SET + DMA active set + 0xE28 + 0x00000000 + + + CH3 + DMA Active Set + [3:3] + read-write + + + CH2 + DMA Active Set + [2:2] + read-write + + + CH1 + DMA Active Set + [1:1] + read-write + + + CH0 + DMA Active Set + [0:0] + read-write + + + + + DMA_ACTIVE_CLR + DMA active clear + 0xE2C + 0x00000000 + + + CH3 + DMA Active clear + [3:3] + read-write + + + CH2 + DMA Active clear + [2:2] + read-write + + + CH1 + DMA Active clear + [1:1] + read-write + + + CH0 + DMA Active clear + [0:0] + read-write + + + + + ERR_SET + DMA bus error set + 0xE48 + 0x00000000 + + + ERR_SET + Set Error + [0:0] + read-only + + + + + PERIPH_ID_4 + DMA Peripheral ID 4 + 0xFD0 + 0x00000004 + + + BLOCK_COUNT + The Number of 4k Address Blocks Required + [7:4] + + + JEP106_C_CODE + JEP106 + [3:0] + + + + + PERIPH_ID_0 + DMA Peripheral ID 0 + 0xFE0 + 0x00000030 + + + PART_NUMBER_0 + Part Number + [7:0] + + + + + PERIPH_ID_1 + DMA Peripheral ID 1 + 0xFE4 + read-only + 0x000000B2 + + + JEP106_ID_3_0 + Indentity Code + [7:4] + + + PART_NUMBER_1 + Part Number 1 + [3:0] + + + + + PERIPH_ID_2 + DMA Peripheral ID 2 + 0xFE8 + 0x000000BC + + + REVISION + Revision + [7:4] + + + JEDEC_USED + JEDEC + [3:3] + + + JEP106_ID_6_4 + JEP106 + [2:0] + + + + + PERIPH_ID_3 + DMA Peripheral ID 3 + 0xFEC + 0x00000000 + + + MOD_NUMBER + Controller Modifications + [3:0] + + + + + PRIMECELL_ID_0 + DMA PrimeCell ID 0 + 0xFF0 + 0x0000000D + + + PRIMECELL_ID_0 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_1 + DMA PrimeCell ID 1 + 0xFF4 + 0x000000F0 + + + PRIMECELL_ID_1 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_2 + DMA PrimeCell ID 2 + 0xFF8 + 0x00000005 + + + PRIMECELL_ID_2 + PrimeCell Identification + [7:0] + + + + + PRIMECELL_ID_3 + DMA PrimeCell ID 3 + 0xFFC + 0x000000B1 + + + PRIMECELL_ID_3 + PrimeCell Identification + [7:0] + + + + + + + IOCONFIG + 1.0 + IO Pin Configuration Peripheral + 0x40011000 + + 0x0 + 0x1000 + registers + + + + 16 + 0x4 + PORTA[%s] + PORTA Pin Configuration Register + 0x0 + 0x00000000 + + + FLTTYPE + Input Filter Selectoin + [2:0] + + + SYNC + Synchronize to system clock + 0 + + + DIRECT + Direct input, no synchronization + 1 + + + FILTER1 + Require 2 samples to have the same value + 2 + + + FILTER2 + Require 3 samples to have the same value + 3 + + + FILTER3 + Require 4 samples to have the same value + 4 + + + FILTER4 + Require 5 samples to have the same value + 5 + + + + + FLTCLK + Input Filter Clock Selection + [5:3] + + + INVINP + Input Invert Selection + [6:6] + + + IEWO + Input Enable While Output enabled + [7:7] + + + OPENDRN + Output Open Drain Mode + [8:8] + + + INVOUT + Output Invert Selection + [9:9] + + + PLEVEL + Internal Pull up/down level + [10:10] + + + PEN + Enable Internal Pull up/down + [11:11] + + + PWOA + Enable Pull when output active + [12:12] + + + FUNSEL + Pin Function Selection + [15:13] + + + IODIS + IO Pin Disable + [16:16] + + + + + PORTB[%s] + PORTB Pin Configuration Register + 0x40 + 0x00000000 + + + PORTC[%s] + PORTC Pin Configuration Register + 0x80 + 0x00000000 + + + PORTD[%s] + PORTD Pin Configuration Register + 0xC0 + 0x00000000 + + + PORTE[%s] + PORTE Pin Configuration Register + 0x100 + 0x00000000 + + + PORTF[%s] + PORTF Pin Configuration Register + 0x140 + 0x00000000 + + + 8 + 0x4 + PORTG[%s] + PORTG Pin Configuration Register + 0x180 + 0x00000000 + + + CLKDIV0 + Clock divide value. 0 will disable the clock + 0x1C0 + read-only + 0x00000000 + + + CLKDIV1 + Clock divide value. 0 will disable the clock + 0x1C4 + read-write + 0x00000000 + + + CLKDIV2 + Clock divide value. 0 will disable the clock + 0x1C8 + read-write + 0x00000000 + + + CLKDIV3 + Clock divide value. 0 will disable the clock + 0x1CC + read-write + 0x00000000 + + + CLKDIV4 + Clock divide value. 0 will disable the clock + 0x1D0 + read-write + 0x00000000 + + + CLKDIV5 + Clock divide value. 0 will disable the clock + 0x1D4 + read-write + 0x00000000 + + + CLKDIV6 + Clock divide value. 0 will disable the clock + 0x1D8 + read-write + 0x00000000 + + + CLKDIV7 + Clock divide value. 0 will disable the clock + 0x1DC + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x028207E9 + + + + + UTILITY + 1.0 + Utility Peripheral + 0x40020000 + + 0x0 + 0x1000 + registers + + + + SYND_DATA + Data Register + 0x0 + read-write + 0x00000000 + + + SYND_SYND + Syndrome Data Register + 0x4 + read-write + 0x00000000 + + + SYND_SYND + Provides bits 11:0 for syndrome, 2x6-bit + [11:0] + + + + + SYND_ENC_32_44 + EDAC Encode + 0x8 + read-write + 0x00000000 + + + SYND_ENC_31_16 + Computed syndrome value for bits 31-16 + [11:6] + + + SYND_ENC_7_0 + Computed syndrome value for bits 15-0 + [5:0] + + + + + SYND_CHECK_32_44_DATA + EDAC Decode Data + 0xC + read-only + 0x00000000 + + + SYND_CHECK_32_44_SYND + EDAC Decode Syndrome + 0x10 + read-only + 0x00000000 + + + MBE + Multiple bit error detect status + [15:14] + + + SBE + Single bit error detect status + [13:12] + + + SYND_CHECK_32_44_SYND + Correct syndrome value + [11:0] + + + + + ROM_TRAP_ADDRESS + ROM EDAC Trap Address + 0x14 + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + ROM_TRAP_SYND + ROM EDAC Trap Syndrome + 0x18 + read-write + 0x00000000 + + + R0M_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + ROM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + RAM_TRAP_ADDR0 + RAM0 EDAC Trap Address + 0x1C + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + RAM_TRAP_SYND0 + RAM0 EDAC Trap Syndrome + 0x20 + read-write + 0x00000000 + + + RAM_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + RAM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + RAM_TRAP_ADDR1 + RAM1 EDAC Trap Address + 0x24 + read-write + 0x00000000 + + + ENABLE + Enable Trap mode + [31:31] + + + ADDR + Address bits for trap match + [30:2] + + + + + RAM_TRAP_SYND1 + RAM1 EDAC Trap Syndrome + 0x28 + read-write + 0x00000000 + + + RAM_SYND_31_16 + 6-bit syndrome value for bits 31-16 + [11:6] + + + RAM_SYND_7_0 + 6-bit syndrome value for bits 15-0 + [5:0] + + + + + SYND_ENC_32_52 + EDAC Encode + 0x120 + read-only + 0x00000000 + + + SYND_ENC_32_52 + Computed syndrome value for bits 15-0 + [19:0] + + + + + SYND_CHECK_32_52_DATA + EDAC Decode Data + 0x124 + read-only + 0x00000000 + + + SYND_CHECK_32_52_SYND + EDAC Decode Syndrome + 0x128 + read-only + 0x00000000 + + + MBE + Multiple bit error detect status + [31:28] + + + SBE + Single bit error detect status + [27:24] + + + SYND_CHECK_32_52_SYND + Corrected syndrome value + [19:0] + + + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x028407E9 + + + + + PORTA + 1.0 + GPIO Peripheral + GPIO + GPIO + 0x40012000 + + 0x0 + 0x400 + registers + + + PORTA0 + 78 + + + PORTA1 + 79 + + + PORTA2 + 80 + + + PORTA3 + 81 + + + PORTA4 + 82 + + + PORTA5 + 83 + + + PORTA6 + 84 + + + PORTA7 + 85 + + + PORTA8 + 86 + + + PORTA9 + 87 + + + PORTA10 + 88 + + + PORTA11 + 89 + + + PORTA12 + 90 + + + PORTA13 + 91 + + + PORTA14 + 92 + + + PORTA15 + 93 + + + PORTB0 + 94 + + + PORTB1 + 95 + + + PORTB2 + 96 + + + PORTB3 + 97 + + + PORTB4 + 98 + + + PORTB5 + 99 + + + PORTB6 + 100 + + + PORTB7 + 101 + + + PORTB8 + 102 + + + PORTB9 + 103 + + + PORTB10 + 104 + + + PORTB11 + 105 + + + PORTB12 + 106 + + + PORTB13 + 107 + + + PORTB14 + 108 + + + PORTB15 + 109 + + + PORTC0 + 110 + + + PORTC1 + 111 + + + PORTC2 + 112 + + + PORTC3 + 113 + + + PORTC4 + 114 + + + PORTC5 + 115 + + + PORTC6 + 116 + + + PORTC7 + 117 + + + PORTC8 + 118 + + + PORTC9 + 119 + + + PORTC10 + 120 + + + PORTC11 + 121 + + + PORTC12 + 122 + + + PORTC13 + 123 + + + PORTC14 + 124 + + + PORTC15 + 125 + + + PORTD0 + 126 + + + PORTD1 + 127 + + + PORTD2 + 128 + + + PORTD3 + 129 + + + PORTD4 + 130 + + + PORTD5 + 131 + + + PORTD6 + 132 + + + PORTD7 + 133 + + + PORTD8 + 134 + + + PORTD9 + 135 + + + PORTD10 + 136 + + + PORTD11 + 137 + + + PORTD12 + 138 + + + PORTD13 + 139 + + + PORTD14 + 140 + + + PORTD15 + 141 + + + PORTE0 + 142 + + + PORTE1 + 143 + + + PORTE2 + 144 + + + PORTE3 + 145 + + + PORTE4 + 146 + + + PORTE5 + 147 + + + PORTE6 + 148 + + + PORTE7 + 149 + + + PORTE8 + 150 + + + PORTE9 + 151 + + + PORTE10 + 152 + + + PORTE11 + 153 + + + PORTE12 + 154 + + + PORTE13 + 155 + + + PORTE14 + 156 + + + PORTE15 + 157 + + + PORTF0 + 158 + + + PORTF1 + 159 + + + PORTF2 + 160 + + + PORTF3 + 161 + + + PORTF4 + 162 + + + PORTF5 + 163 + + + PORTF6 + 164 + + + PORTF7 + 165 + + + PORTF8 + 166 + + + PORTF9 + 167 + + + PORTF10 + 168 + + + PORTF11 + 169 + + + PORTF12 + 170 + + + PORTF13 + 171 + + + PORTF14 + 172 + + + PORTF15 + 173 + + + + DATAIN + Data In Register + 0x0 + read-only + 0x00000000 + + + 4 + 0x1 + DATAINBYTE[%s] + Data In Register by Byte + DATAIN + 0x0 + 0x8 + read-only + 0x00000000 + + + DATAINRAW + Data In Raw Register + 0x4 + 0x00000000 + + + DATAINRAWBYTE[%s] + Data In Raw Register by Byte + DATAINRAW + 0x4 + 0x00000000 + + + DATAOUT + Data Out Register + 0x8 + write-only + 0x00000000 + + + 4 + 0x1 + DATAOUTBYTE[%s] + Data Out Register by Byte + DATAOUT + 0x8 + 0x8 + write-only + 0x00000000 + + + DATAOUTRAW + Data Out Register + 0xC + 0x00000000 + + + DATAOUTRAWBYTE[%s] + Data Out Register by Byte + DATAOUTRAW + 0xC + 0x00000000 + + + SETOUT + Set Out Register + 0x10 + 0x00000000 + + + SETOUTBYTE[%s] + Set Out Register by Byte + SETOUT + 0x10 + 0x00000000 + + + CLROUT + Clear Out Register + 0x14 + 0x00000000 + + + CLROUTBYTE[%s] + Clear Out Register by Byte + CLROUT + 0x14 + 0x00000000 + + + TOGOUT + Toggle Out Register + 0x18 + 0x00000000 + + + TOGOUTBYTE[%s] + Toggle Out Register by Byte + TOGOUT + 0x18 + 0x00000000 + + + DATAMASK + Data mask Register + 0x1C + 0x00000000 + + + 4 + 0x1 + DATAMASKBYTE[%s] + Data Out Register by Byte + DATAMASK + 0x1C + 0x8 + 0x00000000 + + + DIR + Direction Register (1:Output, 0:Input) + 0x20 + 0x00000000 + + + DIRBYTE[%s] + Direction Register by Byte + DIR + 0x20 + 0x00000000 + + + PULSE + Pulse Mode Register + 0x24 + 0x00000000 + + + PULSEBYTE[%s] + Pulse Mode Register by Byte + PULSE + 0x24 + 0x00000000 + + + PULSEBASE + Pulse Base Value Register + 0x28 + 0x00000000 + + + PULSEBASEBYTE[%s] + Pulse Base Mode Register by Byte + PULSEBASE + 0x28 + 0x00000000 + + + DELAY1 + Delay1 Register + 0x2C + 0x00000000 + + + DELAY1BYTE[%s] + Delay1 Register by Byte + DELAY1 + 0x2C + 0x00000000 + + + DELAY2 + Delay2 Register + 0x30 + 0x20 + read-write + 0x00000000 + + + DELAY2BYTE[%s] + Delay2 Register by Byte + DELAY2 + 0x30 + 0x00000000 + + + IRQ_SEN + Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive) + 0x34 + 0x00000000 + + + IRQ_EDGE + Interrupt Both Edge Register (1:Both Edges, 0:Single Edge) + 0x38 + 0x00000000 + + + IRQ_EVT + Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) + 0x3C + 0x00000000 + + + IRQ_ENB + Interrupt Enable Register + 0x40 + 0x00000000 + + + IRQ_RAW + Raw Interrupt Status + 0x44 + read-only + 0x00000000 + + + IRQ_END + Masked Interrupt Status + 0x48 + read-only + 0x00000000 + + + EDGE_STATUS + Edge Status Register + 0x4C + read-write + 0x00000000 + + + PERID + Peripheral ID Register + 0x3FC + 0x20 + read-only + 0x021007E9 + + + + + PORTB + 0x40012400 + + + PORTC + 0x40012800 + + + PORTD + 0x40012C00 + + + PORTE + 0x40013000 + + + PORTF + 0x40013400 + + + PORTG + 0x40013800 + + + TIM0 + 1.0 + Timer/Counter Peripheral + Timer_Counter + TIM + 0x40018000 + + 0x0 + 0x400 + registers + + + TIM0 + 48 + + + TIM1 + 49 + + + TIM2 + 50 + + + TIM3 + 51 + + + TIM4 + 52 + + + TIM5 + 53 + + + TIM6 + 54 + + + TIM7 + 55 + + + TIM8 + 56 + + + TIM9 + 57 + + + TIM10 + 58 + + + TIM11 + 59 + + + TIM12 + 60 + + + TIM13 + 61 + + + TIM14 + 62 + + + TIM15 + 63 + + + TIM16 + 64 + + + TIM17 + 65 + + + TIM18 + 66 + + + TIM19 + 67 + + + TIM20 + 68 + + + TIM21 + 69 + + + TIM22 + 70 + + + TIM23 + 71 + + + + CTRL + Control Register + 0x0 + read-write + + + ENABLE + Counter Enable + [0:0] + + + ACTIVE + Counter Active + [1:1] + read-only + + + AUTO_DISABLE + Auto Disables the counter (set ENABLE to 0) when the count reaches 0 + [2:2] + + + AUTO_DEACTIVATE + Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0 + [3:3] + + + IRQ_ENB + Interrupt Enable + [4:4] + + + STATUS_SEL + Counter Status Selection + [7:5] + + + DONE + Single cycle pulse when the counter reaches 0 + 0 + + + ACTIVE + Returns the counter ACTIVE bit + 1 + + + TOGGLE + Toggles the STATUS bit everytime the counter reaches 0. Basically a divide by 2 counter output. + 2 + + + PWMA + Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE + 3 + + + PWMB + Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE + 4 + + + ENABLED + Returns the counter ENABLED bit + 5 + + + PWMA_ACTIVE + Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0 + 6 + + + + + STATUS_INV + Invert the Output Status + [8:8] + + + REQ_STOP + Stop Request + [9:9] + + + + + RST_VALUE + The value that counter start from after reaching 0. + 0x4 + + + CNT_VALUE + The current value of the counter + 0x8 + + + ENABLE + Alternate access to the Counter ENABLE bit in the CTRL Register + 0xC + + + ENABLE + Counter Enable + [0:0] + + + + + CSD_CTRL + The Cascade Control Register. Controls the counter external enable signals + 0x10 + + + CSDEN0 + Cascade 0 Enable + [0:0] + + + CSDINV0 + Cascade 0 Invert + [1:1] + + + CSDEN1 + Cascade 1 Enable + [2:2] + + + CSDINV1 + Cascade 1 Invert + [3:3] + + + DCASOP + Dual Cascade Operation (0:AND, 1:OR) + [4:4] + + + CSDTRG0 + Cascade 0 Enabled as Trigger + [6:6] + + + CSDTRG1 + Cascade 1 Enabled as Trigger + [7:7] + + + CSDEN2 + Cascade 2 Enable + [8:8] + + + CSDINV2 + Cascade 2 Invert + [9:9] + + + CSDTRG2 + Cascade 2 Trigger mode + [10:10] + + + + + CASCADE0 + Cascade Enable Selection + 0x14 + + + CASSEL + Cascade Selection + [7:0] + + + + + CASCADE1 + Cascade Enable Selection + 0x18 + + + CASCADE2 + Cascade Enable Selection + 0x1C + + + PWM_VALUE + The Pulse Width Modulation Value + 0x20 + + + PWMA_VALUE + The Pulse Width Modulation ValueA + PWM_VALUE + 0x20 + + + PWMB_VALUE + The Pulse Width Modulation ValueB + 0x24 + + + PERID + Peripheral ID Register + 0x3FC + read-only + 0x021107E9 + + + + + TIM1 + 0x40018400 + + + TIM2 + 0x40018800 + + + TIM3 + 0x40018C00 + + + TIM4 + 0x40019000 + + + TIM5 + 0x40019400 + + + TIM6 + 0x40019800 + + + TIM7 + 0x40019C00 + + + TIM8 + 0x4001A000 + + + TIM9 + 0x4001A400 + + + TIM10 + 0x4001A800 + + + TIM11 + 0x4001AC00 + + + TIM12 + 0x4001B000 + + + TIM13 + 0x4001B400 + + + TIM14 + 0x4001B800 + + + TIM15 + 0x4001BC00 + + + TIM16 + 0x40028000 + + + TIM17 + 0x40028400 + + + TIM18 + 0x40028800 + + + TIM19 + 0x40028C00 + + + TIM20 + 0x40029000 + + + TIM21 + 0x40029400 + + + TIM22 + 0x40029800 + + + TIM23 + 0x40029C00 + + + UART0 + 1.0 + UART Peripheral + UART + UART + 0x40024000 + + 0x0 + 0x1000 + registers + + + UART0_TX + 24 + + + UART0_RX + 25 + + + UART1_TX + 26 + + + UART1_RX + 27 + + + UART2_TX + 28 + + + UART2_RX + 29 + + + + DATA + Data In/Out Register + 0x0 + 0x00000000 + + + ENABLE + Enable Register + 0x4 + 0x00000000 + + + RXENABLE + Rx Enable + [0:0] + + + TXENABLE + Tx Enable + [1:1] + + + + + CTRL + Control Register + 0x8 + 0x00000000 + + + PAREN + Parity Enable + [0:0] + + + PAREVEN + Parity Even/Odd(1/0) + [1:1] + + + PARSTK + Parity Sticky + [2:2] + + + STOPBITS + Stop Bits 1/2(0/1) + [3:3] + + + WORDSIZE + Word Size in Bits 5/6/7/8(00/01/10/11) + [5:4] + + + LOOPBACK + Loopback Enable + [6:6] + + + LOOPBACKBLK + Loopback Block + [7:7] + + + AUTOCTS + Enable Auto CTS mode + [8:8] + + + DEFRTS + Default RTSn value + [9:9] + + + AUTORTS + Enable Auto RTS mode + [10:10] + + + BAUD8 + Enable BAUD8 mode + [11:11] + + + + + CLKSCALE + Clock Scale Register + 0xC + 0x00000000 + + + FRAC + Fractional Divide (64ths) + [5:0] + + + INT + Integer Divide + [23:6] + + + RESET + Reset Baud Counter + [31:31] + write-only + + + + + RXSTATUS + Status Register + 0x10 + read-only + 0x00000000 + + + RDAVL + Read Data Available + [0:0] + + + RDNFULL + Read Fifo NOT Full + [1:1] + + + RXBUSY + RX Busy Receiving + [2:2] + + + RXTO + RX Receive Timeout + [3:3] + + + RXOVR + Read Fifo Overflow + [4:4] + + + RXFRM + RX Framing Error + [5:5] + + + RXPAR + RX Parity Error + [6:6] + + + RXBRK + RX Break Error + [7:7] + + + RXBUSYBRK + RX Busy Receiving Break + [8:8] + + + RXADDR9 + Address Match for 9 bit mode + [9:9] + + + RXRTSN + RX RTSn Output Value + [15:15] + + + + + TXSTATUS + Status Register + 0x14 + read-only + 0x00000000 + + + WRRDY + Write Fifo NOT Full + [0:0] + + + WRBUSY + Write Fifo Full + [1:1] + + + TXBUSY + TX Busy Transmitting + [2:2] + + + WRLOST + Write Data Lost (Fifo Overflow) + [3:3] + + + TXCTSN + TX CTSn Input Value + [15:15] + + + + + FIFO_CLR + Clear FIFO Register + 0x18 + write-only + 0x00000000 + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TXBREAK + Break Transmit Register + 0x1C + write-only + 0x00000000 + + + ADDR9 + Address9 Register + 0x20 + read-write + 0x00000000 + + + ADDR9MASK + Address9 Mask Register + 0x24 + read-write + 0x00000000 + + + IRQ_ENB + IRQ Enable Register + 0x28 + read-write + 0x00000000 + + + IRQ_RX + RX Interrupt + [0:0] + + + IRQ_RX_STATUS + RX Status Interrupt + [1:1] + + + IRQ_RX_TO + RX Timeout Interrupt + [2:2] + + + IRQ_TX + TX Interrupt + [4:4] + + + IRQ_TX_STATUS + TX Status Interrupt + [5:5] + + + IRQ_TX_EMPTY + TX Empty Interrupt + [6:6] + + + IRQ_TX_CTS + TX CTS Change Interrupt + [7:7] + + + + + IRQ_RAW + IRQ Raw Status Register + 0x2C + read-only + 0x00000000 + + + IRQ_END + IRQ Enabled Status Register + 0x30 + read-only + 0x00000000 + + + IRQ_CLR + IRQ Clear Status Register + 0x34 + write-only + 0x00000000 + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x38 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x3C + + + RXFIFORTSTRG + Rx FIFO RTS Trigger Level + 0x40 + + + STATE + Internal STATE of UART Controller + 0x44 + 0x20 + read-only + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x021207E9 + + + + + UART1 + 0x40025000 + + + UART2 + 0x40017000 + + + SPI0 + 1.0 + SPI Peripheral + SPI + SPI + 0x40015000 + + 0x0 + 0x400 + registers + + + SPI0_TX + 16 + + + SPI0_RX + 17 + + + SPI1_TX + 18 + + + SPI1_RX + 19 + + + SPI2_TX + 20 + + + SPI2_RX + 21 + + + SPI3_TX + 22 + + + SPI3_RX + 23 + + + + CTRL0 + Control Register 0 + 0x0 + 0x00000000 + + + SIZE + Data Size(0x3=>4, 0xf=>16) + [3:0] + + + SPO + SPI Clock Polarity + [6:6] + + + SPH + SPI Clock Phase + [7:7] + + + SCRDV + Serial Clock Rate divide+1 value + [15:8] + + + + + CTRL1 + Control Register 1 + 0x4 + 0x00000000 + + + LBM + Loop Back + [0:0] + + + ENABLE + Enable + [1:1] + + + MS + Master/Slave (0:Master, 1:Slave) + [2:2] + + + SOD + Slave output Disable + [3:3] + + + SS + Slave Select + [6:4] + + + BLOCKMODE + Block Mode Enable + [7:7] + + + BMSTART + Block Mode Start Status Enable + [8:8] + + + BMSTALL + Block Mode Stall Enable + [9:9] + + + MDLYCAP + Master Delayed Capture Enable + [10:10] + + + MTXPAUSE + Master Tx Pause Enable + [11:11] + + + + + DATA + Data Input/Output + 0x8 + + + STATUS + Status Register + 0xC + read-only + 0x00000000 + + + TFE + Transmit FIFO empty + [0:0] + + + TNF + Transmit FIFO not full + [1:1] + + + RNE + Receive FIFO not empty + [2:2] + + + RFF + Receive FIFO Full + [3:3] + + + BUSY + Busy + [4:4] + + + RXDATAFIRST + Pending Data is first Byte in BLOCKMODE + [5:5] + + + RXTRIGGER + RX FIFO Above Trigger Level + [6:6] + + + TXTRIGGER + TX FIFO Below Trigger Level + [7:7] + + + + + CLKPRESCALE + Clock Pre Scale divide value + 0x10 + + + IRQ_ENB + Interrupt Enable Register + 0x14 + read-write + 0x00000000 + + + RORIM + RX Overrun + [0:0] + + + RTIM + RX Timeout + [1:1] + + + RXIM + RX Fifo is at least half full + [2:2] + + + TXIM + TX Fifo is at least half empty + [3:3] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x18 + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x1C + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x20 + write-only + oneToClear + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x24 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x28 + + + FIFO_CLR + Clear FIFO Register + 0x2C + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + STATE + Internal STATE of SPI Controller + 0x30 + read-only + + + PERID + Peripheral ID Register + 0x3FC + read-only + 0x021307E9 + + + + + SPI1 + 0x40015400 + + + SPI2 + 0x40015800 + + + SPI3 + 0x40015C00 + + + I2C0 + 1.0 + I2C Peripheral + I2C + I2C + 0x40016000 + + 0x0 + 0x400 + registers + + + I2C0_MS + 30 + + + I2C0_SL + 31 + + + I2C1_MS + 32 + + + I2C1_SL + 33 + + + I2C2_MS + 34 + + + I2C2_SL + 35 + + + I2C0_MS_RX + 182 + + + I2C0_MS_TX + 183 + + + I2C0_SL_RX + 184 + + + I2C0_SL_TX + 185 + + + I2C1_MS_RX + 186 + + + I2C1_MS_TX + 187 + + + I2C1_SL_RX + 188 + + + I2C1_SL_TX + 189 + + + I2C2_MS_RX + 190 + + + I2C2_MS_TX + 191 + + + I2C2_SL_RX + 192 + + + I2C2_SL_TX + 193 + + + + CTRL + Control Register + 0x0 + 0x00000000 + + + CLKENABLED + I2C CLK Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + ALGFILTER + Enable Input Analog Glitch Filter + [5:5] + + + DLGFILTER + Enable Input Digital Glitch Filter + [6:6] + + + LOOPBACK + Enable LoopBack Mode + [8:8] + + + TMCONFIGENB + Enable Timing Config Register + [9:9] + + + + + CLKSCALE + Clock Scale divide value + 0x4 + + + VALUE + Enable FastMode + [30:0] + + + FASTMODE + Enable FastMode + [31:31] + + + + + WORDS + Word Count value + 0x8 + + + ADDRESS + I2C Address value + 0xC + + + DATA + Data Input/Output + 0x10 + + + CMD + Command Register + 0x14 + + + STATUS + I2C Controller Status Register + 0x18 + + + I2CIDLE + I2C bus is idle + [0:0] + + + IDLE + I2C controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + STATE + Internal STATE of I2C Master Controller + 0x1C + read-only + + + TXCOUNT + TX Count Register + 0x20 + read-only + + + RXCOUNT + RX Count Register + 0x24 + read-only + + + IRQ_ENB + Interrupt Enable Register + 0x28 + read-write + 0x00000000 + + + I2CIDLE + I2C Bus is Idle + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + STALLED + Controller is Stalled + [3:3] + + + ARBLOST + I2C Arbitration was lost + [4:4] + + + NACKADDR + I2C Address was not Acknowledged + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + CLKLOTO + I2C Clock Low Timeout + [7:7] + + + TXOVERFLOW + TX FIFO Overflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + IRQ_RAW + Raw Interrupt Status Register + 0x2C + read-only + + + IRQ_END + Enabled Interrupt Status Register + 0x30 + read-only + + + IRQ_CLR + Clear Interrupt Status Register + 0x34 + write-only + oneToClear + + + RXFIFOIRQTRG + Rx FIFO IRQ Trigger Level + 0x38 + + + TXFIFOIRQTRG + Tx FIFO IRQ Trigger Level + 0x3C + + + FIFO_CLR + Clear FIFO Register + 0x40 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + TMCONFIG + Timing Config Register + 0x44 + + + CLKTOLIMIT + Clock Low Timeout Limit Register + 0x48 + + + S0_CTRL + Slave Control Register + 0x100 + 0x00000000 + + + CLKENABLED + I2C Enabled + [0:0] + + + ENABLED + I2C Activated + [1:1] + + + ENABLE + I2C Active + [2:2] + + + TXFEMD + TX FIFIO Empty Mode + [3:3] + + + RXFFMD + RX FIFO Full Mode + [4:4] + + + + + S0_MAXWORDS + Slave MaxWords Register + 0x104 + 0x00000000 + + + MAXWORD + Max Word Count + [10:0] + + + ENABLE + Enables the max word count + [31:31] + + + + + S0_ADDRESS + Slave I2C Address Value + 0x108 + 0x00000000 + + + A10MODE + Enable 10b address mode + [15:15] + + + ADDRESS + Address value + [10:1] + + + RW + Read/Write value + [0:0] + + + + + S0_ADDRESSMASK + Slave I2C Address Mask value + 0x10C + 0x00000000 + + + MASK + Address mask value + [10:1] + + + RWMASK + Read/Write mask + [0:0] + + + + + S0_DATA + Slave Data Input/Output + 0x110 + 0x00000000 + + + VALUE + I2C data value + [7:0] + + + + + S0_LASTADDRESS + Slave I2C Last Address value + 0x114 + read-only + 0x00000000 + + + ADDRESS + Address value + [10:1] + + + DIRECTION + Transaction direction 0=master send, 1=master receive + [0:0] + + + + + S0_STATUS + Slave I2C Controller Status Register + 0x118 + read-only + 0x00000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + RXNEMPTY + RX FIFO is Not Empty + [8:8] + + + RXFULL + RX FIFO is Full + [9:9] + + + RXTRIGGER + RX FIFO Above Trigger Level + [11:11] + + + TXEMPTY + TX FIFO is Empty + [12:12] + + + TXNFULL + TX FIFO is Full + [13:13] + + + TXTRIGGER + TX FIFO Below Trigger Level + [15:15] + + + RAW_BUSY + I2C Raw Busy value + [29:29] + + + RAW_SDA + I2C Raw SDA value + [30:30] + + + RAW_SCL + I2C Raw SCL value + [31:31] + + + + + S0_STATE + Internal STATE of I2C Slave Controller + 0x11C + read-only + + + S0_TXCOUNT + Slave TX Count Register + 0x120 + read-only + 0x00000000 + + + VALUE + Count value + [10:0] + + + + + S0_RXCOUNT + Slave RX Count Register + 0x124 + read-only + 0x00000000 + + + VALUE + Count value + [10:0] + + + + + S0_IRQ_ENB + Slave Interrupt Enable Register + 0x128 + read-write + 0x00000000 + + + COMPLETED + Controller Complted a Transaction + [0:0] + + + IDLE + Controller is Idle + [1:1] + + + WAITING + Controller is Waiting + [2:2] + + + TXSTALLED + Controller is Tx Stalled + [3:3] + + + RXSTALLED + Controller is Rx Stalled + [4:4] + + + ADDRESSMATCH + I2C Address Match + [5:5] + + + NACKDATA + I2C Data was not Acknowledged + [6:6] + + + RXDATAFIRST + Pending Data is first Byte following Address + [7:7] + + + I2C_START + I2C Start Condition + [8:8] + + + I2C_STOP + I2C Stop Condition + [9:9] + + + TXUNDERFLOW + TX FIFO Underflowed + [10:10] + + + RXOVERFLOW + TX FIFO Overflowed + [11:11] + + + TXREADY + TX FIFO Ready + [12:12] + + + RXREADY + RX FIFO Ready + [13:13] + + + TXEMPTY + TX FIFO Empty + [14:14] + + + RXFULL + RX FIFO Full + [15:15] + + + + + S0_IRQ_RAW + Slave Raw Interrupt Status Register + 0x12C + read-only + + + S0_IRQ_END + Slave Enabled Interrupt Status Register + 0x130 + read-only + + + S0_IRQ_CLR + Slave Clear Interrupt Status Register + 0x134 + write-only + oneToClear + + + S0_RXFIFOIRQTRG + Slave Rx FIFO IRQ Trigger Level + 0x138 + 0x00000000 + + + LEVEL + Half full level for the Rx FIFO + [4:0] + + + + + S0_TXFIFOIRQTRG + Slave Tx FIFO IRQ Trigger Level + 0x13C + 0x00000008 + + + LEVEL + Half full level for the Rx FIFO + [4:0] + + + + + S0_FIFO_CLR + Slave Clear FIFO Register + 0x140 + write-only + + + RXFIFO + Clear Rx FIFO + [0:0] + + + TXFIFO + Clear Tx FIFO + [1:1] + + + + + S0_ADDRESSB + Slave I2C Address B Value + 0x144 + 0x00000000 + + + RW + Read write value + [0:0] + + + ADDRESS + Address value + [10:1] + + + ADDRESSBEN + Enable Address B + [15:15] + + + + + S0_ADDRESSMASKB + Slave I2C Address B Mask value + 0x148 + 0x000007FE + + + RWMASK + Read write mask + [0:0] + + + MASK + Address mask value + [10:1] + + + + + PERID + Peripheral ID Register + 0x3FC + read-only + 0x021407E9 + + + + + I2C1 + 0x40016400 + + + I2C2 + 0x40016800 + + + CAN0 + 1.0 + CAN Peripheral + CAN + CAN + 0x40014000 + + 0x0 + 0x400 + registers + + + CAN0 + 72 + + + CAN1 + 74 + + + + CNSTAT_CMB0 + Buffer Status / Control Register + 0x0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB0 + CAN Frame Timestamp + 0x4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB0 + CAN Frame Data Word 3 + 0x8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB0 + CAN Frame Data Word 2 + 0xC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB0 + CAN Frame Data Word 1 + 0x10 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB0 + CAN Frame Data Word 0 + 0x14 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB0 + CAN Frame Identifier Word 0 + 0x18 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB0 + CAN Frame Identifier Word 1 + 0x1C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB1 + Buffer Status / Control Register + 0x20 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB1 + CAN Frame Timestamp + 0x24 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB1 + CAN Frame Data Word 3 + 0x28 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB1 + CAN Frame Data Word 2 + 0x2C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB1 + CAN Frame Data Word 2 + 0x30 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB1 + CAN Frame Data Word 0 + 0x34 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB1 + CAN Frame Identifier Word 0 + 0x38 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB1 + CAN Frame Identifier Word 1 + 0x3C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB2 + Buffer Status / Control Register + 0x40 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB2 + CAN Frame Timestamp + 0x44 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB2 + CAN Frame Data Word 3 + 0x48 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB2 + CAN Frame Data Word 2 + 0x4C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB2 + CAN Frame Data Word 2 + 0x50 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB2 + CAN Frame Data Word 0 + 0x54 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB2 + CAN Frame Identifier Word 0 + 0x58 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB2 + CAN Frame Identifier Word 1 + 0x5C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB3 + Buffer Status / Control Register + 0x60 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB3 + CAN Frame Timestamp + 0x64 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB3 + CAN Frame Data Word 3 + 0x68 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB3 + CAN Frame Data Word 2 + 0x6C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB3 + CAN Frame Data Word 2 + 0x70 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB3 + CAN Frame Data Word 0 + 0x74 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB3 + CAN Frame Identifier Word 0 + 0x78 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB3 + CAN Frame Identifier Word 1 + 0x7C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB4 + Buffer Status / Control Register + 0x80 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB4 + CAN Frame Timestamp + 0x84 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB4 + CAN Frame Data Word 3 + 0x88 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB4 + CAN Frame Data Word 2 + 0x8C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB4 + CAN Frame Data Word 2 + 0x90 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB4 + CAN Frame Data Word 0 + 0x94 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB4 + CAN Frame Identifier Word 0 + 0x98 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB4 + CAN Frame Identifier Word 1 + 0x9C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB5 + Buffer Status / Control Register + 0xA0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB5 + CAN Frame Timestamp + 0xA4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB5 + CAN Frame Data Word 3 + 0xA8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB5 + CAN Frame Data Word 2 + 0xAC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB5 + CAN Frame Data Word 2 + 0xB0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB5 + CAN Frame Data Word 0 + 0xB4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB5 + CAN Frame Identifier Word 0 + 0xB8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB5 + CAN Frame Identifier Word 1 + 0xBC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB6 + Buffer Status / Control Register + 0xC0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB6 + CAN Frame Timestamp + 0xC4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB6 + CAN Frame Data Word 3 + 0xC8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB6 + CAN Frame Data Word 2 + 0xCC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB6 + CAN Frame Data Word 2 + 0xD0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB6 + CAN Frame Data Word 0 + 0xD4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB6 + CAN Frame Identifier Word 0 + 0xD8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB6 + CAN Frame Identifier Word 1 + 0xDC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB7 + Buffer Status / Control Register + 0xE0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB7 + CAN Frame Timestamp + 0xE4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB7 + CAN Frame Data Word 3 + 0xE8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB7 + CAN Frame Data Word 2 + 0xEC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB7 + CAN Frame Data Word 2 + 0xF0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB7 + CAN Frame Data Word 0 + 0xF4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB7 + CAN Frame Identifier Word 0 + 0xF8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB7 + CAN Frame Identifier Word 1 + 0xFC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB8 + Buffer Status / Control Register + 0x100 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB8 + CAN Frame Timestamp + 0x104 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB8 + CAN Frame Data Word 3 + 0x108 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB8 + CAN Frame Data Word 2 + 0x10C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB8 + CAN Frame Data Word 2 + 0x110 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB8 + CAN Frame Data Word 0 + 0x114 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB8 + CAN Frame Identifier Word 0 + 0x118 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB8 + CAN Frame Identifier Word 1 + 0x11C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB9 + Buffer Status / Control Register + 0x120 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB9 + CAN Frame Timestamp + 0x124 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB9 + CAN Frame Data Word 3 + 0x128 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB9 + CAN Frame Data Word 2 + 0x12C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB9 + CAN Frame Data Word 2 + 0x130 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB9 + CAN Frame Data Word 0 + 0x134 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB9 + CAN Frame Identifier Word 0 + 0x138 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB9 + CAN Frame Identifier Word 1 + 0x13C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB10 + Buffer Status / Control Register + 0x140 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB10 + CAN Frame Timestamp + 0x144 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB10 + CAN Frame Data Word 3 + 0x148 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB10 + CAN Frame Data Word 2 + 0x14C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB10 + CAN Frame Data Word 2 + 0x150 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB10 + CAN Frame Data Word 0 + 0x154 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB10 + CAN Frame Identifier Word 0 + 0x158 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB10 + CAN Frame Identifier Word 1 + 0x15C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB11 + Buffer Status / Control Register + 0x160 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB11 + CAN Frame Timestamp + 0x164 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB11 + CAN Frame Data Word 3 + 0x168 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB11 + CAN Frame Data Word 2 + 0x16C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB11 + CAN Frame Data Word 2 + 0x170 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB11 + CAN Frame Data Word 0 + 0x174 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB11 + CAN Frame Identifier Word 0 + 0x178 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB11 + CAN Frame Identifier Word 1 + 0x17C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB12 + Buffer Status / Control Register + 0x180 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB12 + CAN Frame Timestamp + 0x184 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB12 + CAN Frame Data Word 3 + 0x188 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB12 + CAN Frame Data Word 2 + 0x18C + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB12 + CAN Frame Data Word 2 + 0x190 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB12 + CAN Frame Data Word 0 + 0x194 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB12 + CAN Frame Identifier Word 0 + 0x198 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB12 + CAN Frame Identifier Word 1 + 0x19C + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB13 + Buffer Status / Control Register + 0x1A0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB13 + CAN Frame Timestamp + 0x1A4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB13 + CAN Frame Data Word 3 + 0x1A8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB13 + CAN Frame Data Word 2 + 0x1AC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB13 + CAN Frame Data Word 2 + 0x1B0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB13 + CAN Frame Data Word 0 + 0x1B4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB13 + CAN Frame Identifier Word 0 + 0x1B8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB13 + CAN Frame Identifier Word 1 + 0x1BC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_CMB14 + Buffer Status / Control Register + 0x1C0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_CMB14 + CAN Frame Timestamp + 0x1C4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_CMB14 + CAN Frame Data Word 3 + 0x1C8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_CMB14 + CAN Frame Data Word 2 + 0x1CC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_CMB14 + CAN Frame Data Word 2 + 0x1D0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_CMB14 + CAN Frame Data Word 0 + 0x1D4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_CMB14 + CAN Frame Identifier Word 0 + 0x1D8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_CMB14 + CAN Frame Identifier Word 1 + 0x1DC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CNSTAT_HCMB + Buffer Status / Control Register + 0x1E0 + 0x00000000 + + + DLC + Data Length Code + [15:12] + + + PRI + Transmit Priority Code + [7:4] + + + ST + Buffer Status + [3:0] + + + + + TSTP_HCMB + CAN Frame Timestamp + 0x1E4 + 0x00000000 + + + TIMESTAMP + Timestamp + [15:0] + + + + + DATA3_HCMB + CAN Frame Data Word 3 + 0x1E8 + 0x00000000 + + + BYTE7 + Data Byte 7 + [15:8] + + + BYTE8 + Data Byte 8 + [7:0] + + + + + DATA2_HCMB + CAN Frame Data Word 2 + 0x1EC + read-write + 0x00000000 + + + BYTE5 + Data Byte 5 + [15:8] + + + BYTE6 + Data Byte 6 + [7:0] + + + + + DATA1_HCMB + CAN Frame Data Word 2 + 0x1F0 + 0x00000000 + + + BYTE3 + Data Byte 3 + [15:8] + + + BYTE4 + Data Byte 4 + [7:0] + + + + + DATA0_HCMB + CAN Frame Data Word 0 + 0x1F4 + read-write + 0x00000000 + + + BYTE1 + Data Byte 1 + [15:8] + + + BYTE2 + Data Byte 2 + [7:0] + + + + + ID0_HCMB + CAN Frame Identifier Word 0 + 0x1F8 + 0x00000000 + + + ID0 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + ID1_HCMB + CAN Frame Identifier Word 1 + 0x1FC + 0x00000000 + + + ID1 + Half of CAN Frame ID. Format Varies for Standard or Extended Frames + [15:0] + + + + + CGCR + CAN Global Configuration Register + 0x200 + 0x00000000 + + + EIT + Error Interrupt Type + [11:11] + + + DIAGEN + Diagnostic Enable + [10:10] + + + INTERNAL + Internal + [9:9] + + + LOOPBACK + Loopback + [8:8] + + + IGNACK + Ignore Acknowledge + [7:7] + + + LO + Listen Only + [6:6] + + + DDIR + Data Direction + [5:5] + + + TSTPEN + Time Sync Enable + [4:4] + + + BUFFLOCK + Buffer Lock + [3:3] + + + CTX + RW,Control Transmit + [2:2] + + + CRX + RW,Control Receive + [1:1] + + + CANEN + CAN Enable + [0:0] + + + + + CTIM + CAN Timing Register + 0x204 + 0x00000000 + + + PSC + Prescaler Configuration + [15:9] + + + SJW + Synchronization Jump Width + [8:7] + + + TSEG1 + Time Segment 1 + [6:3] + + + TSEG2 + Time Segment 2 + [2:0] + + + + + GMSKX + CAN Global Mask Extension + 0x208 + 0x00000000 + + + GM + GM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard + [15:1] + + + XRTR + Extended Remote transmission Request Bit + [0:0] + + + + + GMSKB + CAN Global Mask Base + 0x20C + 0x00000000 + + + GM1 + GM[28:18] - ID[10:0] in standard, ID[28:18] in extended + [15:5] + + + RTR + Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended + [4:4] + + + IDE + Identifier Extension Bit + [3:3] + + + GM0 + GM[17:15] - Unused in standard, ID[17:15] in extended + [2:0] + + + + + BMSKX + CAN Basic Mask Extension + 0x210 + 0x00000000 + + + BM + BM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard + [15:1] + + + XRTR + Extended Remote transmission Request Bit + [0:0] + + + + + BMSKB + CAN Basic Mask Base + 0x214 + 0x00000000 + + + BM1 + BM[28:18] - ID[10:0] in standard, ID[28:18] in extended + [15:5] + + + RTR + Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended + [4:4] + + + IDE + Identifier Extension Bit + [3:3] + + + BM0 + BM[17:15] - Unused in standard, ID[17:15] in extended + [2:0] + + + + + CIEN + CAN Interrupt Enable Register + 0x218 + 0x00000000 + + + EIEN + Error Interrupt Enable + [15:15] + + + IEN + Buffer Interrupt Enable[14:0] + [14:0] + + + + + CIPND + CAN Interrupt Pending Register + 0x21C + 0x00000000 + + + EIPND + Error Interrupt Pending + [15:15] + + + IPND + Buffer Interrupt Pending[14:0] + [14:0] + + + + + CICLR + CAN Interrupt Clear Register + 0x220 + 0x00000000 + + + EICLR + Error Interrupt Clear + [15:15] + + + ICLR + Buffer Interrupt Clear[14:0] + [14:0] + + + + + CICEN + CAN Interrupt Code Enable Register + 0x224 + 0x00000000 + + + EICEN + Error Interrupt Code Enable + [15:15] + + + ICEN + Buffer Interrupt Code Enable[14:0] + [14:0] + + + + + CSTPND + CAN Status Pending Register + 0x228 + 0x00000000 + + + NS + CAN Node Status + [7:5] + + + IRQ + Interrupt Request portion of Interrupt Code + [4:4] + + + IST + Interrupt Source portion of Interrupt Code + [3:0] + + + + + CANEC + CAN Error Counter Register + 0x22C + 0x00000000 + + + REC + Receive Error Counter + [15:8] + + + TEC + Transmit Error Counter + [7:0] + + + + + CEDIAG + CAN Error Diagnostic Register + 0x230 + 0x00000000 + + + DRIVE + Drive + [14:14] + + + MON + Monitor + [13:13] + + + CRC + CRC + [12:12] + + + STUFF + Stuff Error + [11:11] + + + TXE + Transmit Error + [10:10] + + + EBID + Error Bit Identifier + [9:4] + + + EFID + Error Field Identifier + [3:0] + + + + + CTMR + CAN Timer Register + 0x234 + 0x00000000 + + + CTMR + Time Stamp Counter + [15:0] + read-only + + + + + + + CAN1 + 0x40014400 + + + ADC + 1.0 + Analog to Digital Converter Peripheral + ADC + ADC + 0x40022000 + + 0x0 + 0x1000 + registers + + + ADC + 44 + + + + CTRL + Control Register + 0x0 + 0x00000000 + + + CONV_CNT + Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions) + [23:20] + + + MANUAL_TRIG + Starts analog acquisition + [19:19] + + + EXT_TRIG_EN + Allows the external trigger to start analog acquisition + [18:18] + + + SWEEP_EN + ADC data acquisition for all enabled channel + [17:17] + + + CHAN_TAG_EN + Enables the channel tag to be saved with the ADC data + [16:16] + + + CHAN_EN + Enables the channel for data collection + [15:0] + + + + + FIFO_DATA + FIFO data + 0x4 + read-only + 0x00000000 + + + CHAN_TAG + If enabled, this will include the number of the channel corresponding to the measurement + [15:12] + read-only + + + ADC_DATA + ADC acquisition data from the FIFO + [11:0] + + + + + STATUS + Status + 0x8 + read-only + 0x00000000 + + + ADC_BUSY + Indicates an ADC data acquisition is in process + [7:7] + + + FIFO_ENTRY_CNT + Indicates the number of entries in the FIFO + [5:0] + + + + + IRQ_ENB + Interrupt Enable + 0xC + 0x00000000 + + + FIFO_DEPTH_TRIG + Enables the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Enables the interrupt for a trigger error + [5:5] + + + ADC_DONE + Enables the interrupt for an ADC data acquisition completion + [4:4] + + + FIFO_UFLOW + Enables the interrupt for a FIFO underflow + [3:3] + + + FIFO_OFLOW + Enables the interrupt for a FIFO overflow + [2:2] + + + FIFO_FULL + Enables the interrupt for FIFO full + [1:1] + + + FIFO_EMPTY + Enables the interrupt for FIFO empty + [0:0] + + + + + IRQ_RAW + Raw Interrupt Status + 0x10 + read-only + 0x00000001 + + + FIFO_DEPTH_TRIG + Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion + [5:5] + + + ADC_DONE + Indicates that a ADC conversion is done + [4:4] + + + FIFO_UFLOW + Indicates data was unavailable when a new trigger for ADC update is received + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred (FIFO was full when new data was written) + [2:2] + + + FIFO_FULL + Indicates the FIFO is full + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty + [0:0] + + + + + IRQ_END + Enabled Interrupt Status + 0x14 + read-only + 0x00000000 + + + FIFO_DEPTH_TRIG + Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled + [5:5] + + + ADC_DONE + Indicates that a ADC conversion is done and the interrupt is enabled + [4:4] + + + FIFO_UFLOW + Indicates a FIFO underflow occurred and the interrupt is enabled + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred and the interrupt is enabled + [2:2] + + + FIFO_FULL + Indicates the FIFO is full and the interrupt is enabled + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty and the interrupt is enabled + [0:0] + + + + + IRQ_CLR + Clear Interrupt + 0x18 + write-only + 0x00000000 + + + TRIG_ERROR + Clears the trigger error interrupt status. Always reads 0 + [3:3] + + + ADC_DONE + Clears the ADC done interrupt status. Always reads 0 + [2:2] + + + FIFO_UFLOW + Clears the FIFO underflow interrupt status. Always reads 0 + [1:1] + + + FIFO_OFLOW + Clears the FIFO overflow interrupt status. Always reads 0 + [0:0] + + + + + RXFIFOIRQTRG + Receive FIFO Interrupt Trigger Value + 0x1C + 0x00000010 + + + LEVEL + Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt + [4:0] + + + + + FIFO_CLR + FIFO Clear + 0x20 + 0x00000000 + + + FIFO_CLR + Clears the ADC FIFO. Always reads 0 + [0:0] + write-only + + + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x001907E9 + + + + + DAC0 + 1.0 + Digital to Analog Converter Peripheral + DAC + DAC + 0x40023000 + + 0x0 + 0x800 + registers + + + DAC0 + 40 + + + DAC1 + 41 + + + + CTRL0 + Control Register 0 + 0x0 + 0x00000000 + + + MAN_TRIG_EN + Enables manual trigger + [11:11] + + + EXT_TRIG_EN + Enables external trigger + [10:10] + + + + + CTRL1 + Control Register 1 + 0x4 + 0x00000000 + + + DAC_EN + Enables the DAC analog block + [8:8] + + + DAC_SETTLING + Sets the the amount of time in microseconds the control FSM waits for the DAC settling time + [7:5] + + + + + FIFO_DATA + FIFO data + 0x8 + read-write + 0x00000000 + + + DATA + Data for FIFO write + [11:0] + write-only + + + + + STATUS + Status + 0xC + read-only + 0x00000000 + + + DAC_BUSY + Indicates a DAC data acquisition is in process + [7:7] + + + FIFO_ENTRY_CNT + Indicates the number of entries in the FIFO + [5:0] + + + + + IRQ_ENB + Interrupt Enable + 0x10 + 0x00000000 + + + FIFO_DEPTH_TRIG + Enables the interrupt for the FIFO entry count is less than or equal to the trigger level + [6:6] + + + TRIG_ERROR + Enables the interrupt for a trigger error + [5:5] + + + DAC_DONE + Enables the interrupt for a DAC data acquisition completion + [4:4] + + + FIFO_UFLOW + Enables the interrupt for a FIFO underflow + [3:3] + + + FIFO_OFLOW + Enables the interrupt for a FIFO overflow + [2:2] + + + FIFO_FULL + Enables the interrupt for FIFO full + [1:1] + + + FIFO_EMPTY + Enables the interrupt for FIFO empty + [0:0] + + + + + IRQ_RAW + Raw Interrupt Status + 0x14 + read-only + 0x00000041 + + + FIFO_DEPTH_TRIG + Indicates the FIFO entry count is less than or equal to the trigger level + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion + [5:5] + + + DAC_DONE + Indicates that a DAC conversion is done + [4:4] + + + FIFO_UFLOW + Indicates data was unavailable when a new trigger for DAC update is received + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred (FIFO was full when new data was written) + [2:2] + + + FIFO_FULL + Indicates the FIFO is full + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty + [0:0] + + + + + IRQ_END + Enabled Interrupt Status + 0x18 + read-only + 0x00000000 + + + FIFO_DEPTH_TRIG + Indicates the FIFO entry count is less than or equal to the trigger level and the interrupt is enabled + [6:6] + + + TRIG_ERROR + Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled + [5:5] + + + DAC_DONE + Indicates that a DAC conversion is done and the interrupt is enabled + [4:4] + + + FIFO_UFLOW + Indicates a FIFO underflow occurred and the interrupt is enabled + [3:3] + + + FIFO_OFLOW + Indicates a FIFO overflow occurred and the interrupt is enabled + [2:2] + + + FIFO_FULL + Indicates the FIFO is full and the interrupt is enabled + [1:1] + + + FIFO_EMPTY + Indicates the FIFO is empty and the interrupt is enabled + [0:0] + + + + + IRQ_CLR + Clear Interrupt + 0x1C + write-only + 0x00000000 + + + TRIG_ERROR + Clears the trigger error interrupt status. Always reads 0 + [3:3] + + + DAC_DONE + Clears the DAC done interrupt status. Always reads 0 + [2:2] + + + FIFO_UFLOW + Clears the FIFO underflow interrupt status. Always reads 0 + [1:1] + + + FIFO_OFLOW + Clears the FIFO overflow interrupt status. Always reads 0 + [0:0] + + + + + TXFIFOIRQTRG + Receive FIFO Interrupt Trigger Value + 0x20 + 0x00000010 + + + LEVEL + Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt + [4:0] + + + + + FIFO_CLR + FIFO Clear + 0x24 + 0x00000000 + + + FIFO_CLR + Clears the DAC FIFO. Always reads 0 + [0:0] + write-only + + + + + PERID + Peripheral ID Register + 0x7FC + read-only + 0x002007E9 + + + + + DAC1 + 0x40023800 + + + SPW + 1.0 + SpaceWire Peripheral + SPW + SPW + 0x40003000 + + 0x0 + 0x400 + registers + + + SpW + 38 + + + + CTRL + Control Register + 0x0 + 0xA2010004 + + + RA + Reads as 1 if the RMAP command handler is available + [31:31] + read-only + + + RX + Reads as 1 if unaligned writes are available for the receiver + [30:30] + read-only + + + RC + Reads as 1 if RMAP CRC is enabled in the core + [29:29] + read-only + + + NCH + Number of DMA Channels minus one + [28:27] + read-only + + + PO + The number of available SpaceWire ports minus one + [26:26] + read-only + + + CC + CCSDS/CCITT CRC-16 + [25:25] + read-only + + + ID + Interrupt distribution available + [24:24] + read-only + + + LE + Loop-back Enable + [22:22] + read-write + + + PS + Selects the active port when the no port force bit is zero + [21:21] + read-write + + + NP + Disable port force + [20:20] + read-write + + + PNPA + SpW Plug-and-Play Available + [19:18] + read-only + + + RD + If set only one RMAP buffer is used + [17:17] + read-write + + + RE + Enable RMAP command handler + [16:16] + read-write + + + PE + SpW Plug-and-Play Enable + [15:15] + read-write + + + TL + Transmitter Enable Lock Control + [13:13] + read-write + + + TF + Time-code Flag Filter + [12:12] + read-write + + + TR + Enable time-code receptions + [11:11] + + + TT + Enable time-code transmissions + [10:10] + + + LI + Generate interrupt when link error occurs + [9:9] + + + TQ + Generate interrupt when a valid time-code is received + [8:8] + + + RS + Make complete reset of the SpaceWire node. Self-clearing + [6:6] + + + PM + Enable Promiscuous mode + [5:5] + + + TI + The host can generate a tick by writing a one to this field + [4:4] + + + IE + If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs + [3:3] + + + AS + Automatically start the link when a NULL has been received + [2:2] + + + LS + Start the link + [1:1] + + + LD + Disable the SpaceWire CODEC + [0:0] + + + + + STS + Status/Interrupt Source Register + 0x4 + 0x06400000 + + + NRXD + Number of Receive Descriptors + [27:26] + + + NTXD + Number of Transmit Descriptors + [25:24] + + + LS + Link State + [23:21] + + + AP + Active port + [9:9] + + + EE + Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet + [8:8] + + + IA + Packet is received with an invalid destination address field + [7:7] + + + WE + A synchronization problem has occurred when receiving NChars + [6:6] + + + PE + Parity error has occurred + [4:4] + + + DE + Disconnection error has occurred + [3:3] + + + ER + Escape error has occurred + [2:2] + + + CE + Credit has occurred + [1:1] + + + TO + A new time count value was received + [0:0] + + + + + DEFADDR + Node Address Register + 0x8 + read-write + 0x000000FE + + + DEFMASK + 8-bit default mask used for node identification on the SpaceWire network + [15:8] + + + DEFADDR + 8-bit node address used for node identification on the SpaceWire network + [7:0] + + + + + CLKDIV + Clock Divisor Register + 0xC + read-write + 0x00000909 + + + CLKDIVSTART + 8-bit Clock divisor value used for the clock-divider during startup + [15:8] + + + CLKDIVRUN + 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state + [7:0] + + + + + DKEY + Destination Key + 0x10 + 0x00000000 + + + DESTKEY + RMAP destination key + [7:0] + + + + + TC + Time Code Register + 0x14 + read-write + 0x00000000 + + + TIRQ_END + The current value of the time control flags + [7:6] + + + TIMECNT + The current value of the system time counter + [5:0] + + + + + TDR + Timer and Disconnect Register + 0x18 + read-only + 0x00000000 + + + DISCONNECT + Used to generate the 850 ns disconnect time period + [21:12] + + + TIMER64 + Used to generate the 6.4 and 12.8 us time periods + [11:0] + + + + + DMACTRL0 + DMA Control Register + 0x20 + read-write + 0x00000000 + + + INTNUM + Interrupt number used for this channel + [31:26] + + + EP + EEP Termination + [23:23] + + + TR + Truncated + [22:22] + + + IE + Interrupt code transmit enable on EEP + [21:21] + + + IT + Interrupt code transmit enable on truncation + [20:20] + + + RP + Receive Packet IRQ + [19:19] + + + TP + Transmit Packet IRQ + [18:18] + + + TL + Transmit Enable Lock + [17:17] + + + LE + Disable transmitter when a link error occurs + [16:16] + + + SP + Strip PID + [15:15] + + + SA + Strip Address + [14:14] + + + EN + Enable Address + [13:13] + + + NS + If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated + [12:12] + + + RD + Indicates to the GRSPW that there are enabled descriptors in the descriptor table + [11:11] + + + RX + Reception to the DMA channel is currently active + [10:10] + read-only + + + AT + Abort the currently transmitting packet and disable transmissions + [9:9] + read-only + + + RA + An error response was detected on the AHB bus - DMA receive + [8:8] + + + TA + An error response was detected on the AHB bus - DMA transmit + [7:7] + + + PR + Set each time a packet has been received + [6:6] + + + PS + Set each time a packet has been sent + [5:5] + + + AI + An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus + [4:4] + + + RI + An interrupt will be generated each time a packet has been received + [3:3] + + + TI + An interrupt will be generated each time a packet is transmitted + [2:2] + + + RE + Packets are allowed to be received to this channel + [1:1] + + + TE + Write a one to this bit each time new descriptors are activated in the table + [0:0] + + + + + DMAMAXLEN0 + DMA RX Maximum Length Register + 0x24 + read-write + 0x00000000 + + + RXMAXLEN + Receiver packet maximum length in bytes + [24:2] + + + + + DMATXDESC0 + DMA Transmitter Descriptor Table Address Register + 0x28 + read-write + 0x00000000 + + + DESCBASEADDR + Sets the base address of the descriptor table + [31:10] + + + DESCSEL + Offset into the descriptor table + [9:4] + + + + + DMARXDESC0 + DMA Receiver Table Destination Register + 0x2C + read-write + 0x00000000 + + + DESCBASEADDR + Sets the base address of the descriptor table + [31:10] + + + DESCSEL + Offset into the descriptor table + [9:3] + + + + + DMAADDR0 + DMA Receiver Table Address Register + 0x30 + read-write + 0x00000000 + + + MASK + Mask + [15:8] + + + ADDR + Address + [7:0] + + + + + + + IRQ_ROUTER + 1.0 + Interrupt Router Peripheral + IRQ + 0x40002000 + + 0x0 + 0x1000 + registers + + + U0 + 0 + + + U1 + 1 + + + U2 + 2 + + + U3 + 3 + + + U4 + 4 + + + U5 + 5 + + + U6 + 6 + + + U7 + 7 + + + U8 + 8 + + + U9 + 9 + + + U10 + 10 + + + U11 + 11 + + + U12 + 12 + + + U13 + 13 + + + U14 + 14 + + + U15 + 15 + + + U37 + 37 + + + U39 + 39 + + + U73 + 73 + + + U75 + 75 + + + FPU + 194 + + + TXEV + 195 + + + + DMASEL0 + Interrupt select for DMA channel 0 + 0x0 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL1 + Interrupt select for DMA channel 1 + 0x4 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL2 + Interrupt select for DMA channel 2 + 0x8 + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMASEL3 + Interrupt select for DMA channel 3 + 0xC + read-write + 0x0000007F + + + DMASEL + DMA trigger source selection value + [6:0] + + + + + DMATTSEL + Trigger select for the DMA channels + 0x10 + read-write + 0x00000000 + + + DMATTSEL + DMA trigger type selection value + [3:0] + + + + + ADCSEL + Interrupt select for ADC + 0x14 + read-write + 0x0000001F + + + ADCSEL + ADC trigger source selection value + [4:0] + + + + + DACSEL0 + Interrupt select for DAC0 + 0x18 + read-write + 0x0000001F + + + DACSEL + DAC trigger source selection value + [4:0] + + + + + DACSEL1 + Interrupt select for DAC1 + 0x1C + read-write + 0x0000001F + + + DACSEL + DAC trigger source selection value + [4:0] + + + + + IRQ_OUT0 + DEBUG IRQ_OUT[31:0] + 0x20 + read-only + 0x00000000 + + + IRQ_OUT0 + IRQ_OUT[31:0] + [31:0] + + + + + IRQ_OUT1 + DEBUG IRQ_OUT[63:32] + 0x24 + read-only + 0x00000000 + + + IRQ_OUT1 + IRQ_OUT[63:32] + [31:0] + + + + + IRQ_OUT2 + DEBUG IRQ_OUT[95:64] + 0x28 + read-only + 0x00000000 + + + IRQ_OUT2 + IRQ_OUT[95:64] + [31:0] + + + + + IRQ_OUT3 + DEBUG IRQ_OUT[127:96] + 0x2C + read-only + 0x00000000 + + + IRQ_OUT3 + IRQ_OUT[127:96] + [31:0] + + + + + IRQ_OUT4 + DEBUG IRQ_OUT[159:128] + 0x30 + read-only + 0x00000000 + + + IRQ_OUT4 + IRQ_OUT[159:128] + [31:0] + + + + + IRQ_OUT5 + DEBUG IRQ_OUT[179:160] + 0x34 + read-only + 0x00000000 + + + IRQ_OUT5 + IRQ_OUT[179:160] + [19:0] + + + + + PERID + Peripheral ID Register + 0xFFC + read-only + 0x028107E9 + + + + + WATCH_DOG + 1.0 + Watchdog Block Peripheral + WDOG + 0x40021000 + + 0x0 + 0x1000 + registers + + + WATCHDOG + 47 + + + + WDOGLOAD + Counter Start Value + 0x0 + read-write + 0xFFFFFFFF + + + CNT + Count to load + [31:0] + + + + + WDOGVALUE + Down Counter Value + 0x4 + read-only + 0xFFFFFFFF + + + CNT + Actual Count + [31:0] + + + + + WDOGCONTROL + Enable for block reset and interrupt + 0x8 + read-write + 0x00000000 + + + RESEN + Enable watchdog reset output + [1:1] + + + INTEN + Enable watchdog interrupt + [0:0] + + + + + WDOGINTCLR + A write of any value clears the WDT module interrupt, and reloads +the counter from the value in the WDOGLOAD Register + 0xC + read-write + 0x00000000 + + + CLEAR + Write any value to clear interrupt + [31:0] + + + + + WDOGRIS + Raw interrupt status + 0x10 + read-only + 0x00000000 + + + INTERRUPT + Interrupt Status + [0:0] + + + + + WDOGMIS + Interrupt status + 0x14 + read-only + 0x00000000 + + + INTERRUPT + Masked Interrupt Status + [0:0] + + + + + WDOGLOCK + Lock + 0xC0 + read-write + 0x00000000 + + + REG_WR_EN + Register write enable status + [31:0] + + + + + WDOGITCR + Integration test control + 0xF00 + read-write + 0x00000000 + + + TEST_MODE_EN + Enable test mode of WDOGINT and WDOGRES + [0:0] + + + + + WDOGITOP + Integration test output set + 0xF04 + read-write + 0x00000000 + + + WDOGINT + Set output value + [1:1] + + + WDOGRES + Set output value + [0:0] + + + + + WDOGPERIPHID0 + Peripheral ID + 0xFE0 + read-only + 0x00000024 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID1 + Peripheral ID + 0xFE4 + read-only + 0x000000B8 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID2 + Peripheral ID + 0xFE8 + read-only + 0x0000001B + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPERIPHID3 + Peripheral ID + 0xFEC + read-only + 0x00000000 + + + PERIPHID + Peripheral ID + [7:0] + + + + + WDOGPCELLID0 + PrimeCell ID + 0xFF0 + read-only + 0x0000000D + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID1 + PrimeCell ID + 0xFF4 + read-only + 0x000000F0 + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID2 + PrimeCell ID + 0xFF8 + read-only + 0x00000005 + + + PCELLID + Prime Cell ID + [7:0] + + + + + WDOGPCELLID3 + PrimeCell ID + 0xFFC + read-only + 0x000000B1 + + + PCELLID + Prime Cell ID + [7:0] + + + + + + + TRNG + 1.0 + True Random Number Generator + TRNG + 0x40027000 + + 0x0 + 0x400 + registers + + + TRNG + 42 + + + + IMR + Interrupt Mask Register + 0x100 + read-write + 0x0000000F + + + VN_ERR_INT_MASK + Mask the Von Neumann error + [3:3] + + + CRNGT_ERR_INT_MASK + Mask the CRNGT error + [2:2] + + + AUTOCORR_ERR_INT_MASK + Mask the Autocorrelation error + [1:1] + + + EHR_VALID_INT_MASK + Mask when the TRNG has collected 192 bits + [0:0] + + + + + ISR + Interrupt Status Register + 0x104 + read-only + 0x00000000 + + + VN_ERR + Indicates a Von Neumann error + [3:3] + + + CRNGT_ERR + Indicates a Continuous Random Number Generation Testing (CRNGT) error + [2:2] + + + AUTOCORR_ERR + Indicates that the Autocorrelation test failed four times in a row + [1:1] + + + EHR_VALID + 192 bits have been collected in the TRNG + [0:0] + + + + + ICR + Interrupt Clear Register + 0x108 + read-write + 0x00000000 + + + VN_ERR + Clears a Von Neumann error + [3:3] + + + CRNGT_ERR + Clear a Continuous Random Number Generation Testing (CRNGT) error + [2:2] + + + AUTOCORR_ERR + Software cannot clear this bit. Only a TRNG reset can clear this bit + [1:1] + + + EHR_VALID + Set to 1 after the EHR_DATA[0,1,2,3,4,5] registers have been read + [0:0] + + + + + CONFIG + Configuration Register + 0x10C + read-write + 0x00000000 + + + RND_SRC_SEL + Selects the number of inverters (out of four possible selections) in the ring oscillator + [1:0] + + + + + VALID + Valid Register + 0x110 + read-only + 0x00000000 + + + EHR_VALID + Indicates that the collection of bits in the TRNG is complete + [0:0] + + + + + EHR_DATA0 + Entropy Holding Register Data Register + 0x114 + read-only + 0x00000000 + + + EHR_DATA + 32 Bits of Entropy Holding Register + [31:0] + + + + + EHR_DATA1 + Entropy Holding Register Data Register + 0x118 + + + EHR_DATA2 + Entropy Holding Register Data Register + 0x11C + + + EHR_DATA3 + Entropy Holding Register Data Register + 0x120 + + + EHR_DATA4 + Entropy Holding Register Data Register + 0x124 + + + EHR_DATA5 + Entropy Holding Register Data Register + 0x128 + + + RND_SOURCE_ENABLE + Random Source Enable Register + 0x12C + read-write + 0x00000000 + + + RND_SRC_EN + The entropy source, ring oscillator, is enabled + [0:0] + + + + + SAMPLE_CNT1 + Section TBD + 0x130 + read-write + 0x0000FFFF + + + SAMPLE_CNTR1 + Sets the number of clk cycles between two consecutive ring oscillator samples + [31:0] + + + + + AUTOCORR_STATISTIC + Auto-correlator Statistic Register + 0x134 + read-write + 0x00000000 + + + AUTOCORR_FAILS + Count each time an autocorrelation test fails + [21:14] + + + AUTOCORR_TRYS + Count each time an autocorrelation test starts + [13:0] + + + + + DEBUG_CONTROL + Section TBD + 0x138 + read-write + 0x00000000 + + + AUTO_CORRELATE_BYPASS + The autocorrelation test in the TRNG module is bypassed + [3:3] + + + CRNGT_BYPASS + The CRNGT test in the TRNG is bypassed + [2:2] + + + VNC_PYPASS + The Von Neumann balancer is bypassed + [1:1] + + + + + SW_RESET + Reset Register + 0x140 + read-write + 0x00000000 + + + SW_RESET + Writing 1 to this register causes an internal TRNG reset + [0:0] + + + + + BUSY + Busy Register + 0x1B8 + read-only + 0x00000000 + + + BUSY + Reflects the status of the rng_busy signal + [0:0] + + + + + RST_BITS_COUNTER + Reset Bits Counter Register + 0x1BC + read-write + 0x00000000 + + + RST_BITS_COUNTER + Writing any value to this bit resets the bits counter and TRNG valid registers + [0:0] + + + + + BIST_CNTR0 + BIST Counter Register + 0x1E0 + read-only + 0x00000000 + + + ROSC_CNTR_VAL + Returns the results of the TRNG BIST counter + [21:0] + + + + + BIST_CNTR1 + BIST Counter Register + 0x1E4 + + + BIST_CNTR2 + BIST Counter Register + 0x1E8 + + + + + ETH + 1.1 + Ethernet Block + ETH + 0x40004000 + + 0x0 + 0x2000 + registers + + + Ethernet + 36 + + + + MAC_CONFIG + Operation mode register for the MAC + 0x0 + read-write + 0x00000000 + + + WD + Watchdog disable + [23:23] + + + JD + Jabber Disable + [22:22] + + + BE + Frame Burst Enable + [21:21] + + + JE + Jumbo Frame Enable + [20:20] + + + IFG + Inter-Frame Gap + [19:17] + + + DCRS + Disable Carrier Sense During Transmission + [16:16] + + + PS + Port Select + [15:15] + + + FES + Speed + [14:14] + + + DRO + Disable Receive Own + [13:13] + + + LM + Loopback Mode + [12:12] + + + DM + Duplex Mode + [11:11] + + + IPC + Checksum Offload + [10:10] + + + DR + Disable Retry + [9:9] + + + ACS + Automatic Pad, or CRC Stripping + [7:7] + + + BL + Back-Off-Limit + [6:5] + + + DC + Deferral Check + [4:4] + + + TE + Transmitter Enable + [3:3] + + + RE + Receiver Enable + [2:2] + + + PRELEN + Preamble Length for Transmit frames + [1:0] + + + + + MAC_FRAME_FLTR + Contains the frame filtering controls + 0x4 + read-write + 0x00000000 + + + RA + Receive All + [31:31] + + + DNTU + Drop non TCP/UDP over IP Frames + [21:21] + + + VFTE + VLAN Tag Filter Enable + [16:16] + + + HDF + Hash or Perfect Filter + [10:10] + + + SAF + Source Address Filter Enable + [9:9] + + + SAIF + SA Inverse Filtering + [8:8] + + + PCF + Pass Control Frames + [7:6] + + + DBF + Disable Broadcast Frames + [5:5] + + + PM + Pass All Multicast + [4:4] + + + DAIF + DA Inverse Filtering + [3:3] + + + HMC + Hash Multicast + [2:2] + + + HUC + Hash Unicast + [1:1] + + + PR + Promiscuous Mode + [0:0] + + + + + MAC_GMII_ADDR + Controls the management cycles to an external PHY + 0x10 + read-write + 0x00000000 + + + PA + Physical Layer Address + [15:11] + + + GR + GMII Register + [10:6] + + + CR + CSR Clock Range + [5:2] + + + GW + GMII Write/Read + [1:1] + + + GB + GMII Busy + [0:0] + + + + + MAC_GMII_DATA + Contains the data to be written to or read from the PHY register + 0x14 + read-write + 0x00000000 + + + GD + GMII Data + [15:0] + + + + + MAC_FLOW_CTRL + Controls the generation of control frames + 0x18 + read-write + 0x00000000 + + + PT + Pause time + [31:16] + + + DZPQ + Disable Zero-Quanta Pause + [7:7] + + + PLT + Pause Low Threshold + [5:4] + + + UP + Unicast Pause Frame Detect + [3:3] + + + RFE + Receive Flow Control Enable + [2:2] + + + TFE + Transmit Flow Control Enable + [1:1] + + + FCB_BPA + Flow Control Busy or Backpressure Activate + [0:0] + + + + + MAC_VLAN_TAG + Identifies IEEE 802.1Q VLAN type frames + 0x1C + read-write + 0x00000000 + + + ESVL + Enable S-VLAN + [18:18] + + + VTIM + VLAN Tag Inverse Match Enable + [17:17] + + + ETV + Enable 12-Bit VLAN Tag Comparison + [16:16] + + + VL + VLAN Tag identifier for Receive Frames + [15:0] + + + + + MAC_DEBUG + Gives the status of the various internal blocks for debugging + 0x24 + read-only + 0x00000000 + + + TXSTSFSTS + MTL TxStatus FIFO Full Status + [25:25] + + + TXFSTS + MTL Tx FIFO Not Empty Status + [24:24] + + + TWCSTS + MTL Tx FIFO Write Controller Status + [22:22] + + + TRCSTS + MTL Tx FIFO Read Controller Status + [21:20] + + + TXPAUSED + MAC Transmitter in Pause + [19:19] + + + TFCSTS + PAC Transmit Frame Controller Status + [18:17] + + + TPESTS + MAC GMII or MII Transmit Protocol Engine Status + [16:16] + + + RXFSTS + MTL RxFIFO Fill-Level Status + [9:8] + + + RRCSTS + MTL RxFIFO Read Controller State + [6:5] + + + RWCSTS + MTL Rx FIFO Write Controller Active Status + [4:4] + + + RFCFCSTS + MAC Receive Frame FIFO Controller Status + [2:1] + + + RPESTS + MAC GMII or MII Receive Protocol Engine Status + [0:0] + + + + + MAC_INTR_STAT + Contains the interrupt status + 0x38 + read-only + 0x00000000 + + + TSIS + Timestamp Interrupt Status + [9:9] + + + MMCRXIPIS + MMC Receive Checksum Offload Interrupt Status + [7:7] + + + MMCTXIS + MMC Transmit Interrupt Status + [6:6] + + + MMCRXIS + MMC Receive Interrupt Status + [5:5] + + + MMCIS + MMC Interrupt Status + [4:4] + + + + + MAC_INTR_MASK + Contains the masks for generating interrupt + 0x3C + read-write + 0x00000000 + + + TSIM + Timestamp Interrupt Mask + [9:9] + + + + + MAC_ADDR_H + Contains the high 16-bits of the first MAC Address + 0x40 + read-write + 0x8000FFFF + + + AE + Address Enable, This bit is always set to 1 + [31:31] + read-only + + + ADDRHI + MAC Address0[47:32] + [15:0] + read-only + + + + + MAC_ADDR_L + Contains the Low 32-bits of the first MAC Address + 0x44 + read-write + 0xFFFFFFFF + + + ADDRLO + MAC Address0[31:0] + [31:0] + read-only + + + + + MAC_WDOG_TO + Controls the watchdog time-out for received frames + 0xDC + read-write + 0x00000000 + + + PWE + Programmable Watchdog Enable + [16:16] + + + WTO + Watchdog Timeout + [13:0] + + + + + MMC_CNTRL + MMC Control Register + 0x100 + read-write + 0x00000000 + + + UCDBC + Update MMC Counters for Dropped Broadcast Frames + [8:8] + + + CNTPRSTLVL + Full-Half Preset + [5:5] + + + CNTPRST + Counters Preset + [4:4] + + + CNTFREEZ + MMC Counter Freeze + [3:3] + + + RSTONRD + Reset on Read + [2:2] + + + CNTSTOPRO + Counter Stop Rollover + [1:1] + + + CNTRST + Counters Reset + [0:0] + + + + + MMC_INTR_RX + MMC Receive Interrupt Register + 0x104 + read-write + 0x00000000 + + + RXCTRLFIS + MMC Receive Control Frame Counter Interrupt Status + [25:25] + + + RXRCVERRFIS + MMC Receive Error Frame Counter Interrupt Status + [24:24] + + + RXWDOGFIS + MMC Receive Watchdog Error Frame Counter Interrupt Status + [23:23] + + + RXVLANGBFIS + MMC Receive VLAN Good Bad Frame Counter Interrupt Status + [22:22] + + + RXFOVFIS + MMC Receive FIFO Overflow Frame Counter Interrupt Status + [21:21] + + + RXPAUSFIS + MMC Receive Pause Frame Counter Interrupt Status + [20:20] + + + RXORANGEFIS + MMC Receive Out Of Range Error Frame Counter Interrupt Status. + [19:19] + + + RXLENERFIS + MMC Receive Length Error Frame Counter Interrupt Status + [18:18] + + + RXUCGFIS + MMC Receive Unicast Good Frame Counter Interrupt Status + [17:17] + + + RX1024TMAXOCTGBFIS + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. + [16:16] + + + RX512T1023OCTGBFIS + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + [15:15] + + + RX256T511OCTGBFIS + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status + [14:14] + + + RX128T255OCTGBFIS + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status + [13:13] + + + RX65T127OCTGBFIS + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status + [12:12] + + + RX64OCTGBFIS + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status + [11:11] + + + RXOSIZEGFIS + MMC Receive Oversize Good Frame Counter Interrupt Status + [10:10] + + + RXUSIZEGFIS + MMC Receive Undersize Good Frame Counter Interrupt Status + [9:9] + + + RXJABERFIS + MMC Receive Jabber Error Frame Counter Interrupt Status + [8:8] + + + RXRUNTFIS + MMC Receive Runt Frame Counter Interrupt Status + [7:7] + + + RXALGNERFIS + MMC Receive Alignment Error Frame Counter Interrupt Status + [6:6] + + + RXCRCERFIS + MMC Receive CRC Error Frame Counter Interrupt Status + [5:5] + + + RXMCGFIS + MMC Receive Multicast Good Frame Counter Interrupt Status + [4:4] + + + RXBCGFIS + MMC Receive Broadcast Good Frame Counter Interrupt Status + [3:3] + + + RXGOCTIS + MMC Receive Good Octet Counter Interrupt Status + [2:2] + + + RXGBOCTIS + MMC Receive Good Bad Octet Counter Interrupt Status + [1:1] + + + RXGBFRMIS + MMC Receive Good Bad Frame Counter Interrupt Status + [0:0] + + + + + MMC_INTR_TX + MMC Transmit Interrupt Register + 0x108 + read-write + 0x00000000 + + + TXOSIZEGFIS + MMC Transmit Oversize Good Frame Counter Interrupt Status + [25:25] + + + TXVLANGFIS + MMC Transmit VLAN Good Frame Counter Interrupt Status + [24:24] + + + TXPAUSFIS + MMC Transmit Pause Frame Counter Interrupt Status + [23:23] + + + TXEXDEFFIS + MMC Transmit Excessive Deferral Frame Counter Interrupt Status + [22:22] + + + TXGFRMIS + MMC Transmit Good Frame Counter Interrupt Status + [21:21] + + + TXGOCTIS + MMC Transmit Good Octet Counter Interrupt Status + [20:20] + + + TXCARERFIS + MMC Transmit Carrier Error Frame Counter Interrupt Status + [19:19] + + + TXEXCOLFIS + MMC Transmit Excessive Collision Frame Counter Interrupt Status + [18:18] + + + TXLATCOLFIS + MMC Transmit Late Collision Frame Counter Interrupt Status + [17:17] + + + TXDEFFIS + MMC Transmit Deferred Frame Counter Interrupt Status + [16:16] + + + TXMCOLGFIS + MMC Transmit Multiple Collision Good Frame Counter Interrupt Status + [15:15] + + + TXSCOLGFIS + MMC Transmit Single Collision Good Frame Counter Interrupt Status + [14:14] + + + TXUFLOWERFIS + MMC Transmit Underflow Error Frame Counter Interrupt Status + [13:13] + + + TXBCGBFIS + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status + [12:12] + + + TXMCGBFIS + MMC Transmit Multicast Good Bad Frame Counter Interrupt Status + [11:11] + + + TXUCGBFIS + MMC Transmit Unicast Good Bad Frame Counter Interrupt Status + [10:10] + + + TX1024TMAXOCTGBFIS + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter + [9:9] + + + TX512T1023OCTGBFIS + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status + [8:8] + + + TX256T511OCTGBFIS + MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status + [7:7] + + + TX128T255OCTGBFIS + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status + [6:6] + + + TX65T127OCTGBFIS + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status + [5:5] + + + TX64OCTGBFIS + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status + [4:4] + + + TXMCGFIS + MMC Transmit Multicast Good Frame Counter Interrupt Status + [3:3] + + + TXBCGFIS + MMC Transmit Broadcast Good Frame Counter Interrupt Status + [2:2] + + + TXGBFRMIS + MMC Transmit Good Bad Frame Counter Interrupt Status + [1:1] + + + TXGBOCTIS + MMC Transmit Good Bad Octet Counter Interrupt Status + [0:0] + + + + + MMC_INTR_MASK_RX + MMC Receive Interrupt Mask Register + 0x10C + read-write + 0x00000000 + + + RXCTRLFIM + MMC Receive Control Frame Counter Interrupt Mask + [25:25] + + + RXRCVERRFIM + MMC Receive Error Frame Counter Interrupt Mask + [24:24] + + + RXWDOGFIM + MMC Receive Watchdog Error Frame Counter Interrupt Mask + [23:23] + + + RXVLANGBFIM + MMC Receive VLAN Good Bad Frame Counter Interrupt Mask + [22:22] + + + RXFOVFIM + MMC Receive FIFO Overflow Frame Counter Interrupt Mask + [21:21] + + + RXPAUSFIM + MMC Receive Pause Frame Counter Interrupt Mask + [20:20] + + + RXORANGEFIM + MMC Receive Out Of Range Error Frame Counter Interrupt Mask + [19:19] + + + RXLENERFIM + MMC Receive Length Error Frame Counter Interrupt Mask + [18:18] + + + RXUCGFIM + MMC Receive Unicast Good Frame Counter Interrupt Mask + [17:17] + + + RX1024TMAXOCTGBFIM + MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. + [16:16] + + + RX512T1023OCTGBFIM + MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + [15:15] + + + RX256T511OCTGBFIM + MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + [14:14] + + + RX128T255OCTGBFIM + MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + [13:13] + + + RX65T127OCTGBFIM + MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + [12:12] + + + RX64OCTGBFIM + MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask + [11:11] + + + RXOSIZEGFIM + MMC Receive Oversize Good Frame Counter Interrupt Mask + [10:10] + + + RXUSIZEGFIM + MMC Receive Undersize Good Frame Counter Interrupt Mask + [9:9] + + + RXJABERFIM + MMC Receive Jabber Error Frame Counter Interrupt Mask + [8:8] + + + RXRUNTFIM + MMC Receive Runt Frame Counter Interrupt Mask + [7:7] + + + RXALGNERFIM + MMC Receive Alignment Error Frame Counter Interrupt Mask + [6:6] + + + RXCRCERFIM + MMC Receive CRC Error Frame Counter Interrupt Mask + [5:5] + + + RXMCGFIM + MMC Receive Multicast Good Frame Counter Interrupt Mask + [4:4] + + + RXBCGFIM + MMC Receive Broadcast Good Frame Counter Interrupt Mask + [3:3] + + + RXGOCTIM + MMC Receive Good Octet Counter Interrupt Mask + [2:2] + + + RXGBOCTIM + MMC Receive Good Bad Octet Counter Interrupt Mask. + [1:1] + + + RXGBFRMIM + MMC Receive Good Bad Frame Counter Interrupt Mask + [0:0] + + + + + MMC_INTR_MASK_TX + MMC Transmit Interrupt Mask Register + 0x110 + read-write + 0x00000000 + + + TXOSIZEGFIM + MMC Transmit Oversize Good Frame Counter Interrupt Mask + [25:25] + + + TXVLANGFIM + MMC Transmit VLAN Good Frame Counter Interrupt Mask + [24:24] + + + TXPAUSFIM + MMC Transmit Pause Frame Counter Interrupt Mask + [23:23] + + + TXEXDEFFIM + MMC Transmit Excessive Deferral Frame Counter Interrupt Mask + [22:22] + + + TXGFRMIM + MMC Transmit Good Frame Counter Interrupt Mask + [21:21] + + + TXGOCTIM + MMC Transmit Good Octet Counter Interrupt Mask + [20:20] + + + TXCARERFIM + MMC Transmit Carrier Error Frame Counter Interrupt Mask + [19:19] + + + TXEXCOLFIM + MMC Transmit Excessive Collision Frame Counter Interrupt Mask + [18:18] + + + TXLATCOLFIM + MMC Transmit Late Collision Frame Counter Interrupt Mask + [17:17] + + + TXDEFFIM + MMC Transmit Deferred Frame Counter Interrupt Mask + [16:16] + + + TXMCOLGFIM + MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask + [15:15] + + + TXSCOLGFIM + MMC Transmit Single Collision Good Frame Counter Interrupt Mask + [14:14] + + + TXUFLOWERFIM + MMC Transmit Underflow Error Frame Counter Interrupt Mask + [13:13] + + + TXBCGBFIM + MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask + [12:12] + + + TXMCGBFIM + MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask + [11:11] + + + TXUCGBFIM + MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask + [10:10] + + + TX1024TMAXOCTGBFIM + MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask + [9:9] + + + TX512T1023OCTGBFIM + MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask + [8:8] + + + TX256T511OCTGBFIM + MC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask + [7:7] + + + TX128T255OCTGBFIM + MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask + [6:6] + + + TX65T127OCTGBFIM + MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask + [5:5] + + + TX64OCTGBFIM + MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask + [4:4] + + + TXMCGFIM + MMC Transmit Multicast Good Frame Counter Interrupt Mask + [3:3] + + + TXBCGFIM + MMC Transmit Broadcast Good Frame Counter Interrupt Mask + [2:2] + + + TXGBFRMIM + MMC Transmit Good Bad Frame Counter Interrupt Mask + [1:1] + + + TXGBOCTIM + MMC Transmit Good Bad Octet Counter Interrupt Mask + [0:0] + + + + + TXOCTETCOUNT_GB + MMC Transmit Count + 0x114 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + TXFRAMECOUNT_GB + MMC Frame Count Register + 0x118 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXBCASTFRAMES_G + MMC Good Broadcast Frames Register + 0x11C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMCASTFRAMES_G + MMC Good Multicast Frames Register + 0x120 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX64OCT_GB + MMC Good and bad Frames transmitted with length 64 + 0x124 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX65TO127OCT_GB + MMC Good and bad Frames transmitted with length 65 to 127 + 0x128 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX128TO255OCT_GB + MMC Good and bad Frames transmitted with length 128 to 255 + 0x12C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX256TO511OCT_GB + MMC Good and bad Frames transmitted with length 256 to 511 + 0x130 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX512TO1023OCT_GB + MMC Good and bad Frames transmitted with length 512 to 1023 + 0x134 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TX1024MAXOCT_GB + MMC Good and bad Frames transmitted with length 1024 to max bytes + 0x138 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXUCASTFRAME_GB + MMC number of good and bad unicast frames transmitted + 0x13C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMCASTFRAME_GB + MMC number of good and bad MULTIcast frames transmitted + 0x140 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXBCASTFRAME_GB + MMC number of good and bad broadcast frames transmitted + 0x144 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXUNDERERR + MMC number of frames aborted because of frame underflow error + 0x148 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXSINGLECOL_G + MMC Number of successfully transmitted frames after a single collision + 0x14C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXMULTICOL_G + MMC Number of successfully transmitted frames after multiple collisions + 0x150 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXDEFERRED + MMC Number of successfully transmitted frames after a deferral + 0x154 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXLATECOL + MMC Number of aborted frames because of late collision error + 0x158 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXEXESSCOL + MMC Number of aborted frames because of excessive collision errors + 0x15C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXCARRIERERROR + MMC Number of aborted frames because of carrier sense error + 0x160 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXOCTETCOUNT_G + MMC Number of bytes transmitted frames only in good frames + 0x164 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + TXFRAMECOUNT_G + MMC Number of good frames transmitted + 0x168 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXEXCESSDEF + MMC Number of frames aborted because of excessive deferral error + 0x16C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXPAUSEFRAMES + MMC Number of good pause frames transmitted + 0x170 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXLANFRAMES_G + MMC Number of good VLAN frames transmitted + 0x174 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + TXOVERSIZE_G + MMC Number of frames transmitted without errors + 0x178 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXFRAMECOUNT_GB + MMC Number of good and bad frames received + 0x180 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOCTETCOUNT_GB + MMC Number of bytes received in good and bad frames + 0x184 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + RXOCTETCOUNT_G + MMC Number of bytes received in good frames only + 0x188 + read-only + 0x00000000 + + + COUNT + Number of bytes + [31:0] + + + + + RXBCASTFRAMES_G + MMC Number of good broadcast frames received + 0x18C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXMCASTFRAMES_G + MMC Number of good multicast frames received + 0x190 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXCRCERROR + MMC Number of frames received with CRC error + 0x194 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXALIGNERROR + MMC Number of frames received with alignment error + 0x198 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXRUNTERROR + MMC Number of frames received with runt error + 0x19C + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXJABBERERROR + MMC Number of giant frames received with length greater than 1518 bytes and with CRC error + 0x1A0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXUNDERSIZE_G + MMC Number of frames received with length less than 64 bytes + 0x1A4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOVERSIZE_G + MMC Number of frames received without errors with length greater than the max size + 0x1A8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX64OCTETS_GB + MMC Number of good and bad frames received with length 64 bytes + 0x1AC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX65TO127OCT_GB + MMC Number of good and bad frames received with length between 65 and 127 bytes + 0x1B0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX128TO255OCT_GB + MMC Number of good and bad frames received with length between 128 and 255 bytes + 0x1B4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX256TO511OCT_GB + MMC Number of good and bad frames received with length between 256 and 511 bytes + 0x1B8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX512TO1023OCT_GB + MMC Number of good and bad frames received with length between 512 and 1023 bytes + 0x1BC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RX1024MAXOCT_GB + MMC Number of good and bad frames received with length between 1024 and max size bytes + 0x1C0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXUCASTFRAMES_G + MMC Number of received good unicast frames + 0x1C4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXLENGTHERROR + MMC Number of frames received with length error + 0x1C8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXOUTRANGETYPE + MMC Number of frames received with length field not equal to the valid frame size + 0x1CC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXPAUSEFRAMES + MMC Number of good and valid Pause frames received + 0x1D0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXFIFOOVERFLOW + MMC Number of missed received frames because of FIFO overflow + 0x1D4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXVLANFRAMES_GB + MMC Number of good and bad VLAN frames received + 0x1D8 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXWDOGERROR + MMC Number of frames received with error because of watchdog timeout error + 0x1DC + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXRCVERROR + MMC Number of frames received with Receive error or Frame Extension error + 0x1E0 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + RXCTRLFRAMES_G + MMC Number of received good control frames + 0x1E4 + read-only + 0x00000000 + + + COUNT + Number of frames + [31:0] + + + + + VLAN_INCREPLACE + Holds the VLAN Tag for insertion into or replacement in the transmit frames + 0x584 + read-write + 0x00000000 + + + CSVL + C-VLAN or S-VLAN + [19:19] + + + VLP + VLAN Priority Control + [18:18] + + + VLC + VLAN Tag Control in Transmit Frames + [17:16] + + + VLT + VLAN Tag for Transmit Frames + [15:0] + + + + + VLAN_HASHTABLE + Holds the VLAN Hash Table + 0x588 + read-write + 0x00000000 + + + VLHT + VLAN Hash Table + [15:0] + + + + + TIMESTAMP_CTRL + Controls the IEEE 1588 timestamp generation and update logic + 0x700 + read-write + 0x00000000 + + + ATSEN3 + Auxiliary Snapshot 3 Enable + [28:28] + + + ATSEN2 + Auxiliary Snapshot 2 Enable + [27:27] + + + ATSEN1 + Auxiliary Snapshot 1 Enable + [26:26] + + + ATSEN0 + Auxiliary Snapshot 0 Enable + [25:25] + + + ATSFC + Auxiliary Snapshot FIFO Clear + [24:24] + + + TSENMACADDR + Enable MAC address for PTP Frame Filtering + [18:18] + + + SNAPTYPSEL + Select PTP packets for Taking Snapshots + [17:16] + + + TSMSTRENA + Enable Snapshot for Messages Relevant to Master + [15:15] + + + TSEVNTENA + Enable Timestamp Snapshot for Event Messages + [14:14] + + + TSIPV4ENA + Enable Processing of PTP Frames Sent over IPv4-UDP + [13:13] + + + TSIPV6ENA + Enable Processing of PTP Frames Sent over IPv6-UDP + [12:12] + + + TSIPENA + Enable Processing of PTP over Ethernet Frames + [11:11] + + + TSVER2ENA + Enable PTP packet Processing for Version 2 Format + [10:10] + + + TSCTRLSSR + Timestamp Digital or Binary Rollover Control + [9:9] + + + TSENALL + Enable Timestamp for All Frames + [8:8] + + + TSADDRREG + Addend Reg Update + [5:5] + + + TSTRIG + Timestamp Interrupt Trigger Enable + [4:4] + + + TSUPDT + Timestamp Update + [3:3] + + + TSINIT + Timestamp Initialize + [2:2] + + + TSCFUPDT + Timestamp Fine or Coarse Update + [1:1] + + + TSENA + Timestamp Enable + [0:0] + + + + + SUBSEC_INC + Holds the 8-bit value by which the Sub-Second register is incremented + 0x704 + read-write + 0x00000000 + + + SSINC + Sub-Second Increment Valuee + [7:0] + + + + + SYSTIME_SECONDS + Holds the lower 32 bits of the second field of the system time + 0x708 + read-only + 0x00000000 + + + TSS + Timestamp Second + [31:0] + + + + + SYSTIME_NANOSEC + Holds 32 bits of the nano-second field of the system time + 0x70C + read-only + 0x00000000 + + + TSSS + Timestamp Sub Seconds + [30:0] + + + + + SYSTIME_SECSUPDAT + Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value + 0x710 + read-write + 0x00000000 + + + TSS + Timestamp Second + [31:0] + + + + + SYSTIME_NSECUP + Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value + 0x714 + read-write + 0x00000000 + + + ADDSUB + Add or Subtract Time + [31:31] + + + TSSS + Timestamp Sub Seconds + [30:0] + + + + + TIMESTAMPADDEND + This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency + 0x718 + read-write + 0x00000000 + + + TSAR + Timestamp Addend Register + [31:0] + + + + + TARGET_TIME_SECS + Holds the high 32-bits of time to be compared with the system time + 0x71C + read-write + 0x00000000 + + + TSTR + Target Time Seconds Registe + [31:0] + + + + + TARGET_TIME_NSEC + Holds the lower 32-bits of time to be compared with the system time + 0x720 + read-write + 0x00000000 + + + TRGTBUSY + 32 Bits of Hash Table + [31:31] + + + TTSLO + Target Timestamp Low Register + [30:0] + + + + + DMA_BUS_MODE + Controls the DMA Host Interface Mode + 0x1000 + read-write + 0x00020101 + + + RIB + Rebuild INCRx Burst + [31:31] + + + PRWG + Channel Priority Weights + [29:28] + + + TXPR + Transmit Priority + [27:27] + + + MB + Mixed Burst + [26:26] + + + AAL + Address-Aligned Beats + [25:25] + + + PBLx8 + PBLx8 Mode + [24:24] + + + USP + Use Separate PBL + [23:23] + + + RPBL + Rx DMA PBL + [22:17] + + + FB + Fixed Burste + [16:16] + + + PR + Priority Ratio + [15:14] + + + PBL + Programmable Burst Lengthe + [13:8] + + + DSL + Descriptor Skip Length + [6:2] + + + DA + DMA Arbitration Scheme + [1:1] + + + SWR + Software Reset (Read, Write Set, and Self Clear) + [0:0] + + + + + DMA_TX_POLL_DEMAND + Used by the host to instruct the DMA to poll the transmit Descriptor list + 0x1004 + read-write + 0x00000000 + + + TPD + Transmit Poll Demand (Read Only and Write Trigger) + [31:0] + + + + + DMA_RX_POLL_DEMAND + Used by the host to instruct the DMA to poll the Receive Descriptor list + 0x1008 + read-write + 0x00000000 + + + RPD + Receive Poll Demand (Read Only and Write Trigger) + [31:0] + + + + + DMA_RX_DESC_LIST_ADDR + Points the DMA to the start of the Receive Descriptor list + 0x100C + read-write + 0x00000000 + + + RDESLA + Start of Receive List + [31:0] + + + + + DMA_TX_DESC_LIST_ADDR + Points the DMA to the start of the Transmit Descriptor list + 0x1010 + read-write + 0x00000000 + + + TDESLA + Start of Transmit List + [31:0] + + + + + DMA_STATUS + Used to determine the status of the DMA + 0x1014 + read-only + 0x00000000 + + + TTI + Timestamp Trigger Interrupt + [29:29] + + + GMI + GMAC MMC Interrupt + [27:27] + + + EB + Error Bits + [25:23] + + + TS + Transmit Process State + [22:20] + + + RS + Receive Process State + [19:17] + + + NIS + Normal Interrupt Summary + [16:16] + + + AIS + Abnormal Interrupt Summary + [15:15] + + + ERI + Early Receive Interrupt + [14:14] + + + FBI + Fatal Bus Error Interruptble + [13:13] + + + ETI + Early Transmit Interrupt + [10:10] + + + RWT + Receive Watchdog Timeout + [9:9] + + + RPS + Receive Process Stopped + [8:8] + + + RU + Receive Buffer Unavailable + [7:7] + + + RI + Receive Interrupt + [6:6] + + + UNF + Transmit Underflow + [5:5] + + + OVF + Receive Underflow + [4:4] + + + TJT + Transmit Jabber Timeout + [3:3] + + + TU + Transmit Buffer Unavailable + [2:2] + + + TPS + Transmit Process Stopped + [1:1] + + + TI + Transmit Interrupt + [0:0] + + + + + DMA_OPER_MODE + Sets the Receive and Transmit operation mode and command + 0x1018 + read-write + 0x00000000 + + + DT + Disable Dropping of TCP/IP Checksum Error Frames + [26:26] + + + RSF + Receive Store and Forward + [25:25] + + + DFF + Disable Flushing of Received Frames + [24:24] + + + TSF + Transmit Store and Forward + [21:21] + + + FTF + Flush Transmit FIFO + [20:20] + + + TTC + Transmit Threshold Control + [16:14] + + + ST + Start or Stop Transmission Command + [13:13] + + + RFD + Threshold for Deactivating Flow Control + [12:11] + + + RFA + Threshold for Activating Flow Control + [10:9] + + + FEF + Forward Error Frames + [7:7] + + + FUF + Forward Undersized Good Frames + [6:6] + + + DGF + Drop Giant Frames + [5:5] + + + RTC + Receive Threshold Control + [4:3] + + + OSF + Operate on Second Frame + [2:2] + + + SR + Start or Stop Receive + [1:1] + + + + + DMA_INTR_EN + Enables the interrupts reported in the status register + 0x101C + read-write + 0x00000000 + + + NIE + Normal Interrupt Summary Enable + [16:16] + + + AIE + Abnormal Interrupt Summary Enable + [15:15] + + + ERE + Early Receive Interrupt Enable + [14:14] + + + FBE + Fatal Bus Error Enable + [13:13] + + + ETE + Early Transmit Interrupt Enable + [10:10] + + + RWE + Receive Watchdog Timeout Enable + [9:9] + + + RSE + Receive Stopped Enable + [8:8] + + + RUE + Receive Buffer Unavailable Enable + [7:7] + + + RIE + Receive Interrupt Enable + [6:6] + + + UNE + Underflow Interrupt Enable + [5:5] + + + OVE + Overflow Interrupt Enable + [4:4] + + + THE + Transmit Jabber Timeout Enable + [3:3] + + + TUE + Transmit Buffer Unavailable Enable + [2:2] + + + TSE + Transmit Stopped Enable + [1:1] + + + TIE + Transmit Interrupt Enable + [0:0] + + + + + DMA_MISS_OVER_COUNTER + Contains the counters for discarded frames because no Receive Descriptor is available + 0x1020 + read-write + 0x00000000 + + + OVFCNTOVF + This bit is set every time the Overflow Frame Counter (Bits[27:17])overflows + [28:28] + + + OVFFRMCNT + This field indicates the number of frames missed by the application + [27:17] + + + MISCNTOVF + This bit is set every time Missed Frame Counter (Bits[15:0]) overflows + [16:16] + + + MISFRMCNT + This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. + [15:0] + + + + + DMA_RX_INTR_WDOG_TIMER + Watchdog timeout for Receive Interrupt from DMA + 0x1024 + read-write + 0x00000000 + + + RIWT + These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set. + [7:0] + + + + + DMA_AHB_STATUS + Provides the active status of the read and write channels of the AHB master interface + 0x102C + read-write + 0x00000000 + + + AHBMASTRSTS + When high, indicates that the AHB master interface FSMs are in the non-idle state + [0:0] + + + + + DMA_CURR_TX_DESC + Contains the start address of the current Transmit Descriptor read by the DMA + 0x1048 + read-write + 0x00000000 + + + CURTDESAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_RX_DESC + Contains the start address of the current Receive Descriptor read by the DMA + 0x104C + read-write + 0x00000000 + + + CURRDESAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_TX_BUFR_ADDR + Contains the start address of the current Receive Descriptor read by the DMA + 0x1050 + read-write + 0x00000000 + + + CURTBUFAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + DMA_CURR_RX_BUFR_ADDR + Contains the current Receive Buffer address read by the DMA + 0x1054 + read-write + 0x00000000 + + + CURTBUFAPTR + Cleared on Reset. Pointer updated by the DMA during operation. + [31:0] + + + + + + + \ No newline at end of file diff --git a/vorago-peb1/.cargo/def-config.toml b/vorago-peb1/.cargo/def-config.toml new file mode 100644 index 0000000..74cd913 --- /dev/null +++ b/vorago-peb1/.cargo/def-config.toml @@ -0,0 +1,39 @@ +[target.'cfg(all(target_arch = "arm", target_os = "none"))'] +# uncomment ONE of these three option to make `cargo run` start a GDB session +# which option to pick depends on your system +# If the RevA board is used, replace jlink.gdb with jlink-reva.gdb +# runner = "arm-none-eabi-gdb -q -x jlink/jlink.gdb" +# runner = "gdb-multiarch -q -x jlink/jlink.gdb" + +# runner = "arm-none-eabi-gdb -q -x jlink/jlink-reva.gdb" +# runner = "gdb-multiarch -q -x jlink/jlink-reva.gdb" + +rustflags = [ + # This is needed if your flash or ram addresses are not aligned to 0x10000 in memory.x + # See https://github.com/rust-embedded/cortex-m-quickstart/pull/95 + "-C", "link-arg=--nmagic", + + # LLD (shipped with the Rust toolchain) is used as the default linker + "-C", "link-arg=-Tlink.x", + + # if you run into problems with LLD switch to the GNU linker by commenting out + # this line + # "-C", "linker=arm-none-eabi-ld", + + # if you need to link to pre-compiled C libraries provided by a C toolchain + # use GCC as the linker by commenting out both lines above and then + # uncommenting the three lines below + # "-C", "linker=arm-none-eabi-gcc", + # "-C", "link-arg=-Wl,-Tlink.x", + # "-C", "link-arg=-nostartfiles", +] + +[build] +# Pick ONE of these compilation targets +# target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ +# target = "thumbv7m-none-eabi" # Cortex-M3 +# target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) +target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) +# target = "thumbv8m.base-none-eabi" # Cortex-M23 +# target = "thumbv8m.main-none-eabi" # Cortex-M33 (no FPU) +# target = "thumbv8m.main-none-eabihf" # Cortex-M33 (with FPU) \ No newline at end of file diff --git a/vorago-peb1/.gitignore b/vorago-peb1/.gitignore new file mode 100644 index 0000000..962b190 --- /dev/null +++ b/vorago-peb1/.gitignore @@ -0,0 +1,4 @@ +/target +Cargo.lock + +/.cargo/config.toml diff --git a/vorago-peb1/Cargo.toml b/vorago-peb1/Cargo.toml new file mode 100644 index 0000000..a777ee1 --- /dev/null +++ b/vorago-peb1/Cargo.toml @@ -0,0 +1,34 @@ +[package] +name = "vorago-peb1" +version = "0.1.0" +authors = ["Robin Mueller "] +edition = "2021" +description = "Board Support Crate for the Vorago PEB1 development board" +homepage = "https://egit.irs.uni-stuttgart.de/rust/vorago-peb1" +repository = "https://egit.irs.uni-stuttgart.de/rust/vorago-peb1" +license = "Apache-2.0" +keywords = ["no-std", "peb1", "cortex-m", "vorago", "va416xx"] +categories = ["embedded", "no-std", "hardware-support"] + +[dependencies] +cortex-m = "0.7" +cortex-m-rt = "0.7" +embedded-hal = "1" + +[dependencies.va416xx-hal] +path = "../va416xx-hal" +version = "0.1.0" + +[dependencies.lis2dh12] +git = "https://github.com/us-irs/lis2dh12.git" +# path = "../../lis2dh12" +branch = "all-features" +version = "0.7" +features = ["out_f32"] + +[features] +rt = ["va416xx-hal/rt"] + +[package.metadata.docs.rs] +all-features = true +rustdoc-args = ["--generate-link-to-definition"] diff --git a/vorago-peb1/LICENSE-APACHE b/vorago-peb1/LICENSE-APACHE new file mode 100644 index 0000000..16fe87b --- /dev/null +++ b/vorago-peb1/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + +Copyright [yyyy] [name of copyright owner] + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/vorago-peb1/NOTICE b/vorago-peb1/NOTICE new file mode 100644 index 0000000..c95b309 --- /dev/null +++ b/vorago-peb1/NOTICE @@ -0,0 +1,3 @@ +Rust Board Support Package (BSP) crate for the Vorago PEB1 development board + +This software contains code developed at the University of Stuttgart. \ No newline at end of file diff --git a/vorago-peb1/README.md b/vorago-peb1/README.md new file mode 100644 index 0000000..59de734 --- /dev/null +++ b/vorago-peb1/README.md @@ -0,0 +1,20 @@ +# Rust BSP for the Vorago PEB1 development board + +## Using the `.cargo/config.toml` file + +Use the following command to have a starting `config.toml` file + +```sh +cp .cargo/def-config.toml .cargo/config.toml +``` + +You then can adapt the `config.toml` to your needs. For example, you can configure runners +to conveniently flash with `cargo run`. + +## Notes on board revisions + +On RevA, issuing the `monitor reset` command in the GDB application is problematic and will prevent +the flashed binary from working properly. On board revision B, this was not an issue. +For that reason, two different `*.gdb` files were provided in the `jlink` folder for each +board revision. If you are not using these files, make sure to correctly configure your flash +tools depending on which tool or board your are using. diff --git a/vorago-peb1/jlink-gdb.sh b/vorago-peb1/jlink-gdb.sh new file mode 100755 index 0000000..65e187f --- /dev/null +++ b/vorago-peb1/jlink-gdb.sh @@ -0,0 +1,5 @@ +#!/bin/bash +# Start the JLinkGDBServer while also specifying the JLinkScript file. The JLinkScript is necessary +# to disable ROM protection to allow flashing +JLinkGDBServer -select USB -device Cortex-M4 -endian little -if SWD -speed 2000 \ + -LocalhostOnly -vd -jlinkscriptfile ./jlink/JLinkSettings.JLinkScript diff --git a/vorago-peb1/jlink/JLinkSettings.JLinkScript b/vorago-peb1/jlink/JLinkSettings.JLinkScript new file mode 100644 index 0000000..59cff80 --- /dev/null +++ b/vorago-peb1/jlink/JLinkSettings.JLinkScript @@ -0,0 +1,77 @@ +/********************************************************************* +* SEGGER Microcontroller GmbH * +* Solutions for real time microcontroller applications * +********************************************************************** +* * +* (c) 1995 - 2018 SEGGER Microcontroller GmbH * +* * +* www.segger.com Support: support@segger.com * +* * +********************************************************************** +---------------------------------------------------------------------- +File : JLinkSettings.JLinkScript +Purpose : J-Link target setup file for VORAGO VA416xx +---------------------------END-OF-HEADER------------------------------ +*/ + +int DisableRomProt(void) { + JLINK_SYS_Report("VA416XX: Disabling ROM protection"); + return JLINK_MEM_WriteU32(0x40010010, 0x1); // ROM_PROT = 0x1 +} + +int DisableWatchdog(void) { + JLINK_MEM_WriteU32(0x400210C0, 0x1ACCE551); // WDOGLOCK = 0x1ACCE551 + JLINK_MEM_WriteU32(0x40021008, 0x0); // WDOGCONTROL = 0x0 (diable) +} + +int SetupTarget (void) { + JLINK_SYS_Report("SetupTarget()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* AfterResetTarget +*/ +int AfterResetTarget (void) { + JLINK_SYS_Report("AfterResetTarget()"); + // disable watchdog and unlock code RAM for write + DisableWatchdog(); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* BeforeTargetDownload +*/ +int BeforeTargetDownload (void) { + JLINK_SYS_Report("BeforeTargetDownload()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* AfterTargetDownload +*/ +int AfterTargetDownload (void) { + JLINK_SYS_Report("AfterTargetDownload()"); + return DisableRomProt(); // ROM_PROT = 0x0 +} + +/********************************************************************* +* +* HandleBeforeFlashProg +*/ +int HandleBeforeFlashProg(void) { + JLINK_SYS_Report("HandleBeforeFlashProg()"); + return DisableRomProt(); // ROM_PROT = 0x1 +} + +/********************************************************************* +* +* HandleAfterFlashProg +*/ +int HandleAfterFlashProg(void) { + JLINK_SYS_Report("HandleAfterFlashProg()"); + return DisableRomProt(); // ROM_PROT = 0x0 +} \ No newline at end of file diff --git a/vorago-peb1/jlink/jlink-reva.gdb b/vorago-peb1/jlink/jlink-reva.gdb new file mode 100644 index 0000000..8712a8e --- /dev/null +++ b/vorago-peb1/jlink/jlink-reva.gdb @@ -0,0 +1,13 @@ +target remote localhost:2331 + +# For some reason, this is problematic even if the JLinkScript disabled the remote +# write protection. Therefore, don't do it for now +# This is only problematic on board RevA +# monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/vorago-peb1/jlink/jlink.gdb b/vorago-peb1/jlink/jlink.gdb new file mode 100644 index 0000000..615efdc --- /dev/null +++ b/vorago-peb1/jlink/jlink.gdb @@ -0,0 +1,11 @@ +target remote localhost:2331 + +# Reset is problematic on RevA, okay for RevB +monitor reset + +# *try* to stop at the user entry point (it might be gone due to inlining) +break main + +load + +continue diff --git a/vorago-peb1/memory.x b/vorago-peb1/memory.x new file mode 100644 index 0000000..b9011d5 --- /dev/null +++ b/vorago-peb1/memory.x @@ -0,0 +1,14 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 256K + /* RAM is a mandatory region. This RAM refers to the SRAM_0 */ + RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K + SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K +} + +/* This is where the call stack will be allocated. */ +/* The stack is of the full descending type. */ +/* NOTE Do NOT modify `_stack_start` unless you know what you are doing */ +/* SRAM_0 can be used for all busses: Instruction, Data and System */ +/* SRAM_1 only supports the system bus */ +_stack_start = ORIGIN(RAM) + LENGTH(RAM); diff --git a/vorago-peb1/src/lib.rs b/vorago-peb1/src/lib.rs new file mode 100644 index 0000000..fe12701 --- /dev/null +++ b/vorago-peb1/src/lib.rs @@ -0,0 +1,51 @@ +//! Board support crate for the VORAGO PEB1 board. +#![no_std] +#![cfg_attr(docsrs, feature(doc_auto_cfg))] + +pub use lis2dh12; + +/// Support for the LIS2DH12 accelerometer on the GPIO board. +pub mod accelerometer { + + use lis2dh12::{self, detect_i2c_addr, AddrDetectionError, Lis2dh12}; + use va416xx_hal::{ + clock::Clocks, + i2c::{self, ClockTooSlowForFastI2c, I2cMaster, I2cSpeed, MasterConfig}, + pac, + }; + + // Accelerometer located on the GPIO board. + pub type Accelerometer = Lis2dh12>; + + #[derive(Debug)] + pub enum ConstructorError { + ClkError(ClockTooSlowForFastI2c), + AddrDetectionError(AddrDetectionError), + AccelerometerError(lis2dh12::Error), + } + + pub fn new_with_addr_detection( + i2c: pac::I2c0, + sysconfig: &mut pac::Sysconfig, + clocks: &Clocks, + ) -> Result { + let mut i2c_master = I2cMaster::new( + i2c, + sysconfig, + MasterConfig::default(), + clocks, + I2cSpeed::Regular100khz, + ) + .map_err(ConstructorError::ClkError)?; + let slave_addr = + detect_i2c_addr(&mut i2c_master).map_err(ConstructorError::AddrDetectionError)?; + Lis2dh12::new(i2c_master, slave_addr).map_err(ConstructorError::AccelerometerError) + } + + pub fn new_with_i2cm( + i2c: I2cMaster, + addr: lis2dh12::SlaveAddr, + ) -> Result> { + Lis2dh12::new(i2c, addr) + } +} diff --git a/vscode/.cortex-debug.peripherals.state.json b/vscode/.cortex-debug.peripherals.state.json new file mode 100644 index 0000000..0637a08 --- /dev/null +++ b/vscode/.cortex-debug.peripherals.state.json @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/vscode/.cortex-debug.registers.state.json b/vscode/.cortex-debug.registers.state.json new file mode 100644 index 0000000..0637a08 --- /dev/null +++ b/vscode/.cortex-debug.registers.state.json @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/vscode/extensions.json b/vscode/extensions.json new file mode 100644 index 0000000..d2cfd28 --- /dev/null +++ b/vscode/extensions.json @@ -0,0 +1,12 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=827846 to learn about workspace recommendations. + // Extension identifier format: ${publisher}.${name}. Example: vscode.csharp + // List of extensions which should be recommended for users of this workspace. + "recommendations": [ + "rust-lang.rust", + "marus25.cortex-debug" + // "probe-rs.probe-rs-debugger" + ], + // List of extensions recommended by VS Code that should not be recommended for users of this workspace. + "unwantedRecommendations": [] +} \ No newline at end of file diff --git a/vscode/launch.json b/vscode/launch.json new file mode 100644 index 0000000..c2763cc --- /dev/null +++ b/vscode/launch.json @@ -0,0 +1,189 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug LED Blinky", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "blinky-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/blinky-hal", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + // Have to use exact address unfortunately. "auto" does not work for some reason.. + "address": "0x1fff8000", + "decoders": [ + { + "port": 0, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug RTT Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "rtt-log-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/rtt-log", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + // Have to use exact address unfortunately. "auto" does not work for some reason.. + "address": "0x1fff8000", + "decoders": [ + { + "port": 0, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug UART Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "uart-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/uart", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + // Have to use exact address unfortunately. "auto" does not work for some reason.. + "address": "0x1fff8000", + "decoders": [ + { + "port": 0, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug WDT Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "wdt-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/wdt", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + // Have to use exact address unfortunately. "auto" does not work for some reason.. + "address": "0x1fff8000", + "decoders": [ + { + "port": 0, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug SPI Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "spi-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/spi", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + // Have to use exact address unfortunately. "auto" does not work for some reason.. + "address": "0x1fff8000", + "decoders": [ + { + "port": 0, + "type": "console" + } + ] + } + }, + { + "type": "cortex-debug", + "request": "launch", + "name": "Debug Timer/Ticks Example", + "servertype": "jlink", + "jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript", + "cwd": "${workspaceRoot}", + "device": "Cortex-M4", + "svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched", + "preLaunchTask": "timer-ticks-example", + "overrideLaunchCommands": [ + "monitor halt", + "monitor reset", + "load", + ], + "executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/examples/timer-ticks", + "interface": "swd", + "runToEntryPoint": "main", + "rttConfig": { + "enabled": true, + // Have to use exact address unfortunately. "auto" does not work for some reason.. + "address": "0x1fff8000", + "decoders": [ + { + "port": 0, + "timestamp": true, + "type": "console" + } + ] + } + }, + ] +} \ No newline at end of file diff --git a/vscode/settings.json b/vscode/settings.json new file mode 100644 index 0000000..e78c4ec --- /dev/null +++ b/vscode/settings.json @@ -0,0 +1,3 @@ +{ + "cortex-debug.gdbPath.linux": "gdb-multiarch" +} diff --git a/vscode/tasks.json b/vscode/tasks.json new file mode 100644 index 0000000..3474f1f --- /dev/null +++ b/vscode/tasks.json @@ -0,0 +1,86 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "blinky-pac-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "blinky-pac" + ], + "group": { + "kind": "build", + } + }, + { + "label": "rtt-log-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "rtt-log" + ], + "group": { + "kind": "build", + } + }, + { + "label": "blinky-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "blinky-hal" + ], + "group": { + "kind": "build", + "isDefault": true + } + }, + { + "label": "uart-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "uart" + ], + "group": { + "kind": "build", + } + }, + { + "label": "wdt-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "wdt" + ], + "group": { + "kind": "build", + } + }, + { + "label": "spi-example", + "type": "shell", + "command": "~/.cargo/bin/cargo", // note: full path to the cargo + "args": [ + "build", + "--example", + "spi" + ], + "group": { + "kind": "build", + } + }, + ] +} \ No newline at end of file