finished basic ADC and DAC HAL
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@ -51,12 +51,7 @@ impl WdtController {
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wdt_freq_ms: u32,
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) -> Self {
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syscfg.enable_peripheral_clock(PeripheralSelect::Watchdog);
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// It's done like that in Vorago examples. Not exactly sure why the reset is necessary
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// though..
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syscfg.assert_periph_reset(PeripheralSelect::Watchdog);
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cortex_m::asm::nop();
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cortex_m::asm::nop();
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syscfg.deassert_periph_reset(PeripheralSelect::Watchdog);
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syscfg.assert_periph_reset_for_two_cycles(PeripheralSelect::Watchdog);
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let wdt_clock = clocks.apb2();
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let mut wdt_ctrl = Self {
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