diff --git a/va416xx-hal/CHANGELOG.md b/va416xx-hal/CHANGELOG.md
index df3c743..aef3f7a 100644
--- a/va416xx-hal/CHANGELOG.md
+++ b/va416xx-hal/CHANGELOG.md
@@ -8,6 +8,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 # [unreleased]
 
+# [v0.5.1] 2025-03-10
+
+## Fixed
+
+- Fix `embedded_io` UART implementation to implement the documented contract properly.
+  The implementation will now block until at least one byte is available or can be written, unless
+  the send or receive buffer is empty.
+
 # [v0.5.0] 2025-03-07
 
 - Bugfix for I2C `TimingCfg::reg`
@@ -111,6 +119,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Initial release with basic HAL drivers
 
 [unreleased]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.5.0...HEAD
+[v0.5.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.5.0...va416xx-hal-v0.5.1
 [v0.5.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.4.1...va416xx-hal-v0.5.0
 [v0.4.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.4.0...va416xx-hal-v0.4.1
 [v0.4.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.3.0...va416xx-hal-v0.4.0
diff --git a/va416xx-hal/Cargo.toml b/va416xx-hal/Cargo.toml
index adcb078..1a14d1e 100644
--- a/va416xx-hal/Cargo.toml
+++ b/va416xx-hal/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "va416xx-hal"
-version = "0.5.0"
+version = "0.5.1"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "HAL for the Vorago VA416xx family of MCUs"
diff --git a/va416xx-hal/src/uart/mod.rs b/va416xx-hal/src/uart/mod.rs
index cd18c79..e3d1ee6 100644
--- a/va416xx-hal/src/uart/mod.rs
+++ b/va416xx-hal/src/uart/mod.rs
@@ -868,7 +868,15 @@ impl<Uart: Instance> embedded_hal_nb::serial::Read<u8> for Rx<Uart> {
 
 impl<Uart: Instance> embedded_io::Read for Rx<Uart> {
     fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
+        if buf.is_empty() {
+            return Ok(0);
+        }
         let mut read = 0;
+        loop {
+            if self.0.rxstatus().read().rdavl().bit_is_set() {
+                break;
+            }
+        }
         for byte in buf.iter_mut() {
             match <Self as embedded_hal_nb::serial::Read<u8>>::read(self) {
                 Ok(w) => {
@@ -1038,14 +1046,19 @@ impl<Uart: Instance> embedded_io::Write for Tx<Uart> {
         if buf.is_empty() {
             return Ok(0);
         }
-
-        for byte in buf.iter() {
-            nb::block!(<Self as embedded_hal_nb::serial::Write<u8>>::write(
-                self, *byte
-            ))?;
+        loop {
+            if self.0.txstatus().read().wrrdy().bit_is_set() {
+                break;
+            }
         }
-
-        Ok(buf.len())
+        let mut written = 0;
+        for byte in buf.iter() {
+            match <Self as embedded_hal_nb::serial::Write<u8>>::write(self, *byte) {
+                Ok(_) => written += 1,
+                Err(nb::Error::WouldBlock) => return Ok(written),
+            }
+        }
+        Ok(written)
     }
 
     fn flush(&mut self) -> Result<(), Self::Error> {