diff --git a/va416xx/svd/va416xx-base.svd b/va416xx/svd/va416xx-base.svd index 15d895f..da85ebf 100644 --- a/va416xx/svd/va416xx-base.svd +++ b/va416xx/svd/va416xx-base.svd @@ -1,15 +1,15 @@ - + VORAGO TECHNOLOGIES SST va416xx M4 1.3 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 100MHz @@ -38,13 +38,18 @@ V1.0 - Original release Dec 2015 system_va416xx VOR_ - 8 - 32 + 8 + + 32 + 32 - read-write - 0x00000000 - 0xFFFFFFFF + read-write + + 0x00000000 + + 0xFFFFFFFF + @@ -61,7 +66,7 @@ V1.0 - Original release Dec 2015 LoCLK 45 - + CTRL0 @@ -69,17 +74,17 @@ V1.0 - Original release Dec 2015 0x000 0x00000030 - + SYS_CLK_LOST_DET_EN Enable the circuit that detects loss of SYS_CLK [31:31] - - + + PLL_RESET Writing this bit to 1 puts the PLL into reset [30:30] - - + + CLK_DIV_SEL Selects the PLL out divider to divide by 1/2/4/8 [29:28] @@ -113,12 +118,12 @@ V1.0 - Original release Dec 2015 PLL_BYPASS PLL Symbol; reference-to-output bypass when high [6:6] - + PLL_PWDN PLL Symbol; power down when high [5:5] - + PLL_INTFB PLL Symbol; select internal feedback path when high rather than FCLK @@ -128,89 +133,89 @@ V1.0 - Original release Dec 2015 CLKSEL_SYS Input clock select to PLL [3:2] - + REF_CLK_SEL PLL Reference Clock Select [1:0] - - + + STAT Clock Generation Module Status Register 0x004 - read-only + read-only 0x00000000 SYSCLKLOST Set when SYS_CLK has dropped to less than 1MHz [3:3] - read-only - + read-only + LOCKLOST LOCK high Symbol indicates that RFLSIP or FBSLIP have occurred for 64 consecutive cycles [2:2] - read-only - + read-only + RFSLIP Reference cycle slip output (CLKOUT frequency high) [1:1] - read-only - + read-only + FBSLIP Feedback cycle slip output (CLKOUT frequency low) [0:0] - read-only - - - + read-only + + + CTRL1 Clock Generation Module Control Register 1 0x008 - read-write + read-write 0x00000000 - - + + ADC_CLK_DIV_SEL Clock divider select for ADC - [6:5] + [6:5] XTAL_N_EN Enables XTAL_N output - [4:4] - + [4:4] + XTAL_EN Enables the crystal oscillator - [3:3] - + [3:3] + PLL_LOST_LOCK_DET_EN Enables the PLL lock lost detection circuit - [2:2] - + [2:2] + PLL_LCK_DET_REARM Resets/Rearms the PLL lock detect circuit - [1:1] - + [1:1] + SYS_CLK_LOST_DET_REARM Resets/Rearms the SYS_CLK lost detection feature - [0:0] - - - - - - + [0:0] + + + + + + SYSCONFIG 1.0 @@ -221,18 +226,18 @@ V1.0 - Original release Dec 2015 0x00001000 registers - + LVD 46 - - + + EDAC_MBE 76 - - + + EDAC_SBE 77 - + RST_STAT @@ -270,7 +275,7 @@ V1.0 - Original release Dec 2015 MEMERR Memory Error Reset Status [5:5] - read-only + read-only @@ -291,7 +296,7 @@ V1.0 - Original release Dec 2015 RAM Reset Control 0x00C 0x0000003F - + ROM_PROT ROM Protection Configuration @@ -335,8 +340,8 @@ V1.0 - Original release Dec 2015 RAM1_SCRUB RAM1 Scrub Period Configuration 0x01C - - + + IRQ_ENB Enable EDAC Error Interrupt Register 0x020 @@ -347,7 +352,7 @@ V1.0 - Original release Dec 2015 ROMMBE ROM Multi Bit Interrupt [0:0] - + ROMSBE ROM Single Bit Interrupt @@ -373,7 +378,7 @@ V1.0 - Original release Dec 2015 RAM1 Single Bit Interrupt [5:5] - + IRQ_RAW @@ -408,14 +413,14 @@ V1.0 - Original release Dec 2015 RAM0 EDAC Single Bit Errors [15:0] - + RAM1_SBE Count of RAM1 EDAC Single Bit Errors 0x034 - - + + RAM0_MBE Count of RAM0 EDAC Multi Bit Errors 0x038 @@ -426,8 +431,8 @@ V1.0 - Original release Dec 2015 RAM0 Multi Bit Errors [15:0] - - + + RAM1_MBE Count of RAM1 EDAC Multi Bit Errors @@ -455,58 +460,58 @@ V1.0 - Original release Dec 2015 Count of ROM block Retries [7:0] - - + + REFRESH_CONFIG_H Register Refresh Rate for TMR registers 0x04C 0x00000000 - + DIVCOUNT Upper 8-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles [7:0] - + TESTMODE Special Test Mode Configuration. 00/01=normal. 10=Force refresh off. 11=Force refresh on constantly. [31:30] - - + + TIM_RESET TIM Reset Control 0x050 0xFFFFFFFF - + TIM_RESET Reset of a given TIMER [23:0] - + TIM_CLK_ENABLE TIM Enable Control 0x054 0x00000000 - + TIMERS Clock enable of a given TIMER [23:0] - + PERIPHERAL_RESET Peripheral Reset Control 0x058 - 0x7F7BEFFF - + 0x7F7BEFFF + SPI0 Resetn of SPI0 @@ -516,7 +521,7 @@ V1.0 - Original release Dec 2015 SPI1 Resetn of SPI1 [1:1] - + SPI2 Resetn of SPI2 @@ -526,42 +531,42 @@ V1.0 - Original release Dec 2015 SPI3 Resetn of SPI3 [3:3] - + UART0 Resetn of UART0 [4:4] - + UART1 Resetn of UART1 [5:5] - + UART2 Resetn of UART2 [6:6] - + I2C0 Resetn of I2C0 [7:7] - + I2C1 Resetn of I2C1 [8:8] - + I2C2 Resetn of I2C2 [9:9] - + CAN0 Resetn of CAN0 [10:10] - + CAN1 Resetn of CAN1 @@ -601,7 +606,7 @@ V1.0 - Original release Dec 2015 SPW Resetn of SpaceWire [18:18] - + CLKGEN RESETn of PLL in Clock Generation Module @@ -661,8 +666,8 @@ V1.0 - Original release Dec 2015 PORTG Resetn of PORTG [30:30] - - + + PERIPHERAL_CLK_ENABLE @@ -690,9 +695,9 @@ V1.0 - Original release Dec 2015 REG_WR_KEY Fuse-analog register writes enabled when key = 0xfeed [15:0] - + - + PMU_CTRL PMU Control Register @@ -703,9 +708,9 @@ V1.0 - Original release Dec 2015 LVL_SLCT Select the POK detect level [1:0] - + - + WAKEUP_CNT Wakeup Control @@ -716,13 +721,13 @@ V1.0 - Original release Dec 2015 CNTSTRT Launch SLP mode in analog block [3:3] - + WKUP_CNT Used to set a time to wake up the processor after the device has been put in a low power state [2:0] - - + + EBI_CFG0 @@ -734,12 +739,12 @@ V1.0 - Original release Dec 2015 ADDRLOW0 Lower bound address for CEN0 [7:0] - + ADDRHIGH0 Upper bound address for CEN0 [15:8] - + CFGREADCYCLE Number of cycles for a read - N plus 1 @@ -759,8 +764,8 @@ V1.0 - Original release Dec 2015 CFGSIZE 8 bit (0) or 16 bit (1) port size [25:25] - - + + EBI_CFG1 @@ -780,7 +785,7 @@ V1.0 - Original release Dec 2015 0x078 0x00000000 - + ANALOG_CNTL Analog Control Register 0x07C @@ -790,12 +795,12 @@ V1.0 - Original release Dec 2015 TMOSC Test Mode [0:0] - + TMPOKDIS Test Mode [1:1] - + TM_ADCMUX_N Test Mode @@ -805,7 +810,7 @@ V1.0 - Original release Dec 2015 TM_ADCMUX_P Test Mode [3:3] - + TMRATIO Test Mode @@ -820,237 +825,238 @@ V1.0 - Original release Dec 2015 ADC_STEST Number of clocks for sample time [12:9] - + RCLK_POS_EN Enable normal test clock [14:14] - + RCLK_NEG_EN Enable inverted test clock [15:15] - + APB2CLK_POS_EN Enable normal APB2CLK for test output [16:16] - + APB2CLK_NEG_EN Enable inverted APB2CLK for test output [17:17] - + TM_ANALOG_PD_EN Enables pull down on analog pads [18:18] - + JMP2BOOT Enables a skip of all delay counters and eFuse read [19:19] - + + SKIPBOOT Enables a skip of all delay counters, eFuse read, and boot [20:20] - - + + - + SW_CLKDIV10 Initial SpW Clock Divider Value - 0x080 - read-write + 0x080 + read-write 0x00000009 - + SW_CLKDIV10 Defines the initial value for the SpW clock, defaults to divide by ten [7:0] - - - - + + + + REFRESH_CONFIG_L Register Refresh Rate for TMR registers - 0x084 - read-write + 0x084 + read-write 0x0000000f - + DIVCOUNT Lower 32-bits of the Refresh Rate Counter. Registers are refreshed every DIVCOUNT+1 cycles [31:0] - - - - + + + + DAC0_CAL DAC0 Calibration Register - 0xFD0 - read-only + 0xFD0 + read-only 0x00000000 - + DAC0_CAL DAC0 Calibration bits [4:0] - - + + - + DAC1_CAL DAC1 Calibration Register 0xFD4 - read-only + read-only 0x00000000 - + DAC1_CAL DAC1 Calibration bits [4:0] - - - - + + + + ADC_CAL ADC Calibration Register 0xFD8 - read-only + read-only 0x00000000 - + ADC_CAL ADC Calibration bits [4:0] - - - - + + + + BG_CAL Bandgap Calibration Register - 0xFDC - read-only + 0xFDC + read-only 0x00000000 - + BG_CAL Bandgap Calibration bits [2:0] - - - - + + + + DREG_CAL Digital LDO Regulator Calibration Register - 0xFE0 - read-only + 0xFE0 + read-only 0x00000000 - + DREG_CAL Digital LDO Regulator Calibration bits [8:0] - - - - + + + + AREG_CAL Analog LDO Regulator Calibration Register 0xFE4 - read-only + read-only 0x00000000 - + AREG_CAL Analog LDO Regulator Calibration bits [8:0] - - - + + + HBO_CAL Heart Beat OSC Calibration Register 0xFE8 - read-only + read-only 0x00000000 - + OSC_CAL 1MHz OSC Calibration bit [3:3] - + HBO_CAL Heart Beat OSC Calibration bits [2:0] - - - + + + EF_CONFIG EFuse Config Register 0xFEC read-only 0x0A800C40 - + ROM_SPEED Specifies the speed of ROM_SCK [1:0] - + ROM_SIZE Specifies how much of the full 128K byte address space is loaded from the external SPI memory after a reset [5:2] - + ROM_NOCHECK When set to 1, the ROM check is skipped [6:6] - + BOOT_DELAY Specifies the boot delay from the end of the Power-On-Sequence to the release of Reset [9:7] - + ROM_READ SPI ROM read instruction code [17:10] - + ROM_LATENCY Number of bits of latency from Address until data from the SPI ROM [22:18] - + ROM_ADDRESS ROM Address Mode [24:23] - + ROM_DLYCAP ROM SPI Delayed capture [25:25] - + ROM_STATUS The first data byte from the SPI ROM following an address is taken as a status byte [26:26] - + RM This bit controls the internal RAM read timing and must be maintained at this value [27:27] - + WM This bit controls the internal RAM write timing and must be maintained at this value [28:28] - - + + EF_ID0 @@ -1065,7 +1071,7 @@ V1.0 - Original release Dec 2015 0xFF4 read-only 0x00000000 - + PROCID Processor ID Register @@ -1079,30 +1085,30 @@ V1.0 - Original release Dec 2015 0xFFC read-only 0x028007e9 - + MANUFACTURER_ID MANUFACTURER_ID [11:0] - read-only + read-only PERIPHERAL_ID PERIPHERAL_ID [23:16] - read-only - + read-only + PERIPHERAL_VER PERIPHERAL_VER [31:24] - read-only - - + read-only + + - - + + DMA 1.0 DMA Controller Block @@ -1112,55 +1118,55 @@ V1.0 - Original release Dec 2015 0x00001000 registers - + DMA_ERROR 43 - - + + DMA_ACTIVE0 174 - - + + DMA_ACTIVE1 175 - - + + DMA_ACTIVE2 176 - - + + DMA_ACTIVE3 177 - - + + DMA_DONE0 178 - - + + DMA_DONE1 179 - - + + DMA_DONE2 180 - - + + DMA_DONE3 181 - + STATUS DMA Status 0x000 0x00000000 - read-only + read-only TEST_STATUS Test Status Logic Included [31:28] - read-write + read-write CHNLS_MINUS1 @@ -1177,28 +1183,28 @@ V1.0 - Original release Dec 2015 Enable status of the controller [0:0] - + CFG DMA Configuration 0x004 - write-only + write-only 0x00000000 CHNL_PROT_CTRL HPROT[3:0] [7:5] - + MASTER_ENABLE PLL Symbol; Feedback cycle slip output (CLKOUT frequency low) [0:0] - read-only - - - + read-only + + + CTRL_BASE_PTR Base Pointer for DMA Control Registers @@ -1209,14 +1215,14 @@ V1.0 - Original release Dec 2015 CTRL_BASE_PTR Base Pointer for DMA Control Registers [31:7] - - - + + + ALT_CTRL_BASE_PTR DMA Channel alternate control data base pointer 0x00C - read-write + read-write 0x00000000 @@ -1224,74 +1230,74 @@ V1.0 - Original release Dec 2015 Base Pointer for Alternate DMA Control Register [31:0] - - + + WAITONREQ_STATUS DMA channel wait on request status 0x010 - read-only + read-only 0x00000000 CH3 DMA wait on request [3:3] - read-write - + read-write + CH2 DMA wait on request [2:2] - read-write - + read-write + CH1 DMA wait on request [1:1] - read-write - - + read-write + + CH0 DMA wait on request [0:0] - read-write - - - + read-write + + + CHNL_SW_REQUEST DMA channel software request 0x014 - write-only + write-only 0x00000000 CH3 Channel SW request [3:3] - read-write - + read-write + CH2 Channel SW request [2:2] - read-write - + read-write + CH1 Channel SW request [1:1] - read-write + read-write - + CH0 Channel SW request [0:0] - read-write - - - + read-write + + + CHNL_USEBURST_SET DMA channel useburst set @@ -1302,28 +1308,28 @@ V1.0 - Original release Dec 2015 CH3 Channel use burst set [3:3] - read-write - + read-write + CH2 Channel use burst set [2:2] - read-write - + read-write + CH1 Channel use burst set [1:1] - read-write + read-write - + CH0 Channel use burst set [0:0] - read-write - - - + read-write + + + CHNL_USEBURST_CLR DMA channel useburst clear @@ -1334,124 +1340,124 @@ V1.0 - Original release Dec 2015 CH3 Channel use burst clear [3:3] - read-write - + read-write + CH2 Channel use burst clear [2:2] - read-write - + read-write + CH1 Channel use burst clear [1:1] - read-write + read-write - + CH0 Channel use burst clear [0:0] - read-write - - - + read-write + + + CHNL_REQ_MASK_SET DMA channel request mask set 0x020 0x00000000 - + CH3 Channel Request Mask set [3:3] - read-write - + read-write + CH2 Channel Request Mask set [2:2] - read-write - + read-write + CH1 Channel Request Mask set [1:1] - read-write - - + read-write + + CH0 Channel Request Mask set [0:0] - read-write - - - + read-write + + + CHNL_REQ_MASK_CLR DMA channel request mask clear 0x024 0x00000000 - + CH3 Channel Request Mask clear [3:3] - read-write - + read-write + CH2 Channel Request Mask clear [2:2] - read-write - + read-write + CH1 Channel Request Mask clear [1:1] - read-write - - + read-write + + CH0 Channel Request Mask clear [0:0] - read-write - - - + read-write + + + CHNL_ENABLE_SET DMA channel enable set 0x028 0x00000000 - + CH3 Channel Enable set [3:3] - read-write - + read-write + CH2 Channel Enable set [2:2] - read-write - + read-write + CH1 Channel Enable set [1:1] - read-write + read-write - + CH0 Channel Enable set [0:0] - read-write - - - + read-write + + + CHNL_ENABLE_CLR DMA channel enable clear @@ -1462,28 +1468,28 @@ V1.0 - Original release Dec 2015 CH3 Channel Enable clear [3:3] - read-write - + read-write + CH2 Channel Enable clear [2:2] - read-write - + read-write + CH1 Channel Enable clear [1:1] - read-write - - + read-write + + CH0 Channel Enable clear [0:0] - read-write - - - + read-write + + + CHNL_PRI_ALT_SET DMA channel primary alternate set @@ -1494,28 +1500,28 @@ V1.0 - Original release Dec 2015 CH3 Channel PRI_ALT set [3:3] - read-write - + read-write + CH2 Channel PRI_ALT set [2:2] - read-write - + read-write + CH1 Channel PRI_ALT set [1:1] - read-write + read-write - + CH0 Channel PRI_ALT set [0:0] - read-write - - - + read-write + + + CHNL_PRI_ALT_CLR DMA channel primary alternate clear @@ -1526,94 +1532,94 @@ V1.0 - Original release Dec 2015 CH3 Channel PRI_ALT clear [3:3] - read-write - + read-write + CH2 Channel PRI_ALT clear [2:2] - read-write - + read-write + CH1 Channel PRI_ALT clear [1:1] - read-write - - + read-write + + CH0 Channel PRI_ALT clear [0:0] - read-write - - - + read-write + + + CHNL_PRIORITY_SET DMA channel priority set 0x038 - read-write + read-write 0x00000000 CH3 Channel PRIORITY set [3:3] - read-write - + read-write + CH2 Channel PRIORITY set [2:2] - read-write - + read-write + CH1 Channel PRIORITY set [1:1] - read-write + read-write - + CH0 Channel PRIORITY set [0:0] - read-write - - - + read-write + + + CHNL_PRIORITY_CLR DMA channel priority clear 0x03C - write-only + write-only 0x00000000 CH3 Channel PRIORITY clear [3:3] - write-only - + write-only + CH2 Channel PRIORITY clear [2:2] - write-only - + write-only + CH1 Channel PRIORITY clear [1:1] - write-only - - + write-only + + CH0 Channel PRIORITY clear [0:0] - write-only - - - + write-only + + + ERR_CLR DMA bus error clear @@ -1624,10 +1630,10 @@ V1.0 - Original release Dec 2015 ERR_CLR Error Clear [0:0] - read-write - - - + read-write + + + INTEGRATION_CFG DMA integration configuration @@ -1638,10 +1644,10 @@ V1.0 - Original release Dec 2015 INT_TEST_EN Error Clear [0:0] - read-write - - - + read-write + + + STALL_STATUS DMA stall status @@ -1652,10 +1658,10 @@ V1.0 - Original release Dec 2015 STALL_STATUS DMA is stalled [0:0] - read-only - - - + read-only + + + DMA_REQ_STATUS DMA Configuration @@ -1666,28 +1672,28 @@ V1.0 - Original release Dec 2015 CH3 DMA Request Status for this CH [3:3] - read-write - + read-write + CH2 DMA Request Status for this CH [2:2] - read-write - + read-write + CH1 DMA Request Status for this CH [1:1] - read-write - - + read-write + + CH0 DMA Request Status for this CH [0:0] - read-write - - - + read-write + + + DMA_SREQ_STATUS DMA single request status @@ -1698,28 +1704,28 @@ V1.0 - Original release Dec 2015 CH3 DMA SRequest Status for this CH [3:3] - read-write - + read-write + CH2 DMA SRequest Status for this CH [2:2] - read-write - + read-write + CH1 DMA SRequest Status for this CH [1:1] - read-write + read-write - + CH0 DMA SRequest Status for this CH [0:0] - read-write - - - + read-write + + + DMA_DONE_SET DMA done set @@ -1730,28 +1736,28 @@ V1.0 - Original release Dec 2015 CH3 DMA Done Set for this CH [3:3] - read-write - + read-write + CH2 DMA Done Set for this CH [2:2] - read-write - + read-write + CH1 DMA Done Set for this CH [1:1] - read-write - - + read-write + + CH0 DMA Done Set for this CH [0:0] - read-write - - - + read-write + + + DMA_DONE_CLR DMA done clear @@ -1762,28 +1768,28 @@ V1.0 - Original release Dec 2015 CH3 DMA Done clear for this CH [3:3] - read-write - + read-write + CH2 DMA Done clear for this CH [2:2] - read-write - + read-write + CH1 DMA Done clear for this CH [1:1] - read-write - - + read-write + + CH0 DMA Done clear for this CH [0:0] - read-write - - - + read-write + + + DMA_ACTIVE_SET DMA active set @@ -1794,28 +1800,28 @@ V1.0 - Original release Dec 2015 CH3 DMA Active Set [3:3] - read-write - + read-write + CH2 DMA Active Set [2:2] - read-write - + read-write + CH1 DMA Active Set [1:1] - read-write + read-write - + CH0 DMA Active Set [0:0] - read-write - - - + read-write + + + DMA_ACTIVE_CLR DMA active clear @@ -1826,28 +1832,28 @@ V1.0 - Original release Dec 2015 CH3 DMA Active clear [3:3] - read-write - + read-write + CH2 DMA Active clear [2:2] - read-write - + read-write + CH1 DMA Active clear [1:1] - read-write + read-write - + CH0 DMA Active clear [0:0] - read-write - - - + read-write + + + ERR_SET DMA bus error set @@ -1858,10 +1864,10 @@ V1.0 - Original release Dec 2015 ERR_SET Set Error [0:0] - read-only - - - + read-only + + + PERIPH_ID_4 DMA Peripheral ID 4 @@ -1872,14 +1878,14 @@ V1.0 - Original release Dec 2015 BLOCK_COUNT The Number of 4k Address Blocks Required [7:4] - + JEP106_C_CODE JEP106 [3:0] - - - + + + PERIPH_ID_0 DMA Peripheral ID 0 @@ -1890,28 +1896,28 @@ V1.0 - Original release Dec 2015 PART_NUMBER_0 Part Number [7:0] - - - + + + PERIPH_ID_1 DMA Peripheral ID 1 0xFE4 - read-only + read-only 0x000000B2 JEP106_ID_3_0 Indentity Code [7:4] - + PART_NUMBER_1 Part Number 1 [3:0] - - - + + + PERIPH_ID_2 DMA Peripheral ID 2 @@ -1922,19 +1928,19 @@ V1.0 - Original release Dec 2015 REVISION Revision [7:4] - + JEDEC_USED JEDEC [3:3] - + JEP106_ID_6_4 JEP106 [2:0] - - - + + + PERIPH_ID_3 DMA Peripheral ID 3 @@ -1945,9 +1951,9 @@ V1.0 - Original release Dec 2015 MOD_NUMBER Controller Modifications [3:0] - - - + + + PRIMECELL_ID_0 DMA PrimeCell ID 0 @@ -1958,9 +1964,9 @@ V1.0 - Original release Dec 2015 PRIMECELL_ID_0 PrimeCell Identification [7:0] - - - + + + PRIMECELL_ID_1 DMA PrimeCell ID 1 @@ -1971,10 +1977,10 @@ V1.0 - Original release Dec 2015 PRIMECELL_ID_1 PrimeCell Identification [7:0] - - - - + + + + PRIMECELL_ID_2 DMA PrimeCell ID 2 0xFF8 @@ -1984,10 +1990,10 @@ V1.0 - Original release Dec 2015 PRIMECELL_ID_2 PrimeCell Identification [7:0] - - - - + + + + PRIMECELL_ID_3 DMA PrimeCell ID 3 0xFFC @@ -1997,11 +2003,11 @@ V1.0 - Original release Dec 2015 PRIMECELL_ID_3 PrimeCell Identification [7:0] - - - - - + + + + + IOCONFIG @@ -2122,89 +2128,89 @@ V1.0 - Original release Dec 2015 PORTC Pin Configuration Register 0x0080 0x00000000 - + PORTD[%s] PORTD Pin Configuration Register 0x00C0 0x00000000 - + PORTE[%s] PORTE Pin Configuration Register 0x0100 0x00000000 - + PORTF[%s] PORTF Pin Configuration Register 0x0140 0x00000000 - - + + 8 - 4 - PORTG[%s] + 4 + PORTG[%s] PORTG Pin Configuration Register 0x0180 0x00000000 - + CLKDIV0 Clock divide value. 0 will disable the clock 0x1C0 read-only 0x00000000 - + CLKDIV1 Clock divide value. 0 will disable the clock 0x1C4 read-write 0x00000000 - + CLKDIV2 Clock divide value. 0 will disable the clock 0x1C8 read-write 0x00000000 - + CLKDIV3 Clock divide value. 0 will disable the clock 0x1CC read-write 0x00000000 - + CLKDIV4 Clock divide value. 0 will disable the clock 0x1D0 read-write 0x00000000 - + CLKDIV5 Clock divide value. 0 will disable the clock 0x1D4 read-write 0x00000000 - + CLKDIV6 Clock divide value. 0 will disable the clock 0x1D8 read-write 0x00000000 - + CLKDIV7 Clock divide value. 0 will disable the clock 0x1DC read-write 0x00000000 - + PERID Peripheral ID Register @@ -2231,22 +2237,22 @@ V1.0 - Original release Dec 2015 SYND_DATA Data Register 0x000 - read-write + read-write 0x00000000 SYND_SYND Syndrome Data Register 0x004 - read-write + read-write 0x00000000 - + SYND_SYND Provides bits 11:0 for syndrome, 2x6-bit [11:0] - - + + SYND_ENC_32_44 @@ -2254,17 +2260,17 @@ V1.0 - Original release Dec 2015 0x008 read-write 0x00000000 - + SYND_ENC_31_16 Computed syndrome value for bits 31-16 [11:6] - + SYND_ENC_7_0 Computed syndrome value for bits 15-0 [5:0] - + @@ -2280,23 +2286,23 @@ V1.0 - Original release Dec 2015 0x010 read-only 0x00000000 - + MBE Multiple bit error detect status [15:14] - + SBE Single bit error detect status [13:12] - + SYND_CHECK_32_44_SYND Correct syndrome value [11:0] - - + + ROM_TRAP_ADDRESS @@ -2304,18 +2310,18 @@ V1.0 - Original release Dec 2015 0x014 read-write 0x00000000 - + ENABLE Enable Trap mode [31:31] - + ADDR Address bits for trap match [30:2] - - + + ROM_TRAP_SYND @@ -2323,18 +2329,18 @@ V1.0 - Original release Dec 2015 0x018 read-write 0x00000000 - + R0M_SYND_31_16 6-bit syndrome value for bits 31-16 [11:6] - + ROM_SYND_7_0 6-bit syndrome value for bits 15-0 [5:0] - - + + RAM_TRAP_ADDR0 @@ -2342,18 +2348,18 @@ V1.0 - Original release Dec 2015 0x01c read-write 0x00000000 - + ENABLE Enable Trap mode [31:31] - + ADDR Address bits for trap match [30:2] - - + + RAM_TRAP_SYND0 @@ -2361,18 +2367,18 @@ V1.0 - Original release Dec 2015 0x020 read-write 0x00000000 - + RAM_SYND_31_16 6-bit syndrome value for bits 31-16 [11:6] - + RAM_SYND_7_0 6-bit syndrome value for bits 15-0 [5:0] - - + + RAM_TRAP_ADDR1 @@ -2380,18 +2386,18 @@ V1.0 - Original release Dec 2015 0x024 read-write 0x00000000 - + ENABLE Enable Trap mode [31:31] - + ADDR Address bits for trap match [30:2] - - + + RAM_TRAP_SYND1 @@ -2399,18 +2405,18 @@ V1.0 - Original release Dec 2015 0x028 read-write 0x00000000 - + RAM_SYND_31_16 6-bit syndrome value for bits 31-16 [11:6] - + RAM_SYND_7_0 6-bit syndrome value for bits 15-0 [5:0] - - + + SYND_ENC_32_52 @@ -2418,45 +2424,45 @@ V1.0 - Original release Dec 2015 0x120 read-only 0x00000000 - + SYND_ENC_32_52 Computed syndrome value for bits 15-0 [19:0] - - - + + + SYND_CHECK_32_52_DATA EDAC Decode Data 0x124 read-only 0x00000000 - + SYND_CHECK_32_52_SYND EDAC Decode Syndrome 0x128 read-only 0x00000000 - + MBE Multiple bit error detect status [31:28] - + SBE Single bit error detect status [27:24] - + SYND_CHECK_32_52_SYND Corrected syndrome value [19:0] - - - + + + PERID Peripheral ID Register @@ -2479,390 +2485,390 @@ V1.0 - Original release Dec 2015 0x00000400 registers - + PORTA0 78 - - + + PORTA1 79 - - + + PORTA2 80 - - + + PORTA3 81 - - + + PORTA4 82 - - + + PORTA5 83 - - + + PORTA6 84 - - + + PORTA7 85 - - + + PORTA8 86 - - + + PORTA9 87 - - + + PORTA10 88 - - + + PORTA11 89 - - + + PORTA12 90 - - + + PORTA13 91 - - + + PORTA14 92 - - + + PORTA15 93 - - + + PORTB0 94 - - + + PORTB1 95 - - + + PORTB2 96 - - + + PORTB3 97 - - + + PORTB4 98 - - + + PORTB5 99 - - + + PORTB6 100 - - + + PORTB7 101 - - + + PORTB8 102 - - + + PORTB9 103 - - + + PORTB10 104 - - + + PORTB11 105 - - + + PORTB12 106 - - + + PORTB13 107 - - + + PORTB14 108 - - + + PORTB15 109 - - + + PORTC0 110 - - + + PORTC1 111 - - + + PORTC2 112 - - + + PORTC3 113 - - + + PORTC4 114 - - + + PORTC5 115 - - + + PORTC6 116 - - + + PORTC7 117 - - + + PORTC8 118 - - + + PORTC9 119 - - + + PORTC10 120 - - + + PORTC11 121 - - + + PORTC12 122 - - + + PORTC13 123 - - + + PORTC14 124 - - + + PORTC15 125 - - + + PORTD0 126 - - + + PORTD1 127 - - + + PORTD2 128 - - + + PORTD3 129 - - + + PORTD4 130 - - + + PORTD5 131 - - + + PORTD6 132 - - + + PORTD7 133 - - + + PORTD8 134 - - + + PORTD9 135 - - + + PORTD10 136 - - + + PORTD11 137 - - + + PORTD12 138 - - + + PORTD13 139 - - + + PORTD14 140 - - + + PORTD15 141 - - + + PORTE0 142 - - + + PORTE1 143 - - + + PORTE2 144 - - + + PORTE3 145 - - + + PORTE4 146 - - + + PORTE5 147 - - + + PORTE6 148 - - + + PORTE7 149 - - + + PORTE8 150 - - + + PORTE9 151 - - + + PORTE10 152 - - + + PORTE11 153 - - + + PORTE12 154 - - + + PORTE13 155 - - + + PORTE14 156 - - + + PORTE15 157 - - + + PORTF0 158 - - + + PORTF1 159 - - + + PORTF2 160 - - + + PORTF3 161 - - + + PORTF4 162 - - + + PORTF5 163 - - + + PORTF6 164 - - + + PORTF7 165 - - + + PORTF8 166 - - + + PORTF9 167 - - + + PORTF10 168 - - + + PORTF11 169 - - + + PORTF12 170 - - + + PORTF13 171 - - + + PORTF14 172 - - + + PORTF15 173 - + GPIO @@ -3063,7 +3069,7 @@ V1.0 - Original release Dec 2015 IRQ_EVT - Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) + Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge) 0x03c 0x00000000 @@ -3126,8 +3132,8 @@ V1.0 - Original release Dec 2015 PORTG - 0x40013800 - + 0x40013800 + @@ -3144,99 +3150,99 @@ V1.0 - Original release Dec 2015 TIM0 48 - + TIM1 49 - + TIM2 50 - + TIM3 51 - + TIM4 52 - + TIM5 53 - + TIM6 54 - + TIM7 55 - + TIM8 56 - + TIM9 57 - + TIM10 58 - + TIM11 59 - + TIM12 60 - + TIM13 61 - + TIM14 62 - + TIM15 63 - + TIM16 64 - + TIM17 65 - + TIM18 66 - + TIM19 67 - + TIM20 68 - + TIM21 69 - + TIM22 70 - + TIM23 71 - + TIM @@ -3559,7 +3565,7 @@ V1.0 - Original release Dec 2015 UART0_TX 24 - + UART0_RX 25 @@ -3579,7 +3585,7 @@ V1.0 - Original release Dec 2015 UART2_RX 29 - + UART @@ -3934,7 +3940,7 @@ V1.0 - Original release Dec 2015 UART2 0x40017000 - + @@ -3951,7 +3957,7 @@ V1.0 - Original release Dec 2015 SPI0_TX 16 - + SPI0_RX 17 @@ -3975,11 +3981,11 @@ V1.0 - Original release Dec 2015 SPI3_TX 22 - + SPI3_RX 23 - + SPI @@ -3990,7 +3996,7 @@ V1.0 - Original release Dec 2015 SIZE - Data Size(0x3=>4, 0xf=>16) + Data Size(0x3=>4, 0xf=>16) [3:0] @@ -4229,7 +4235,7 @@ V1.0 - Original release Dec 2015 SPI3 0x40015C00 - + @@ -4243,78 +4249,78 @@ V1.0 - Original release Dec 2015 0x00000400 registers - + I2C0_MS 30 - - + + I2C0_SL 31 - - + + I2C1_MS 32 - - + + I2C1_SL 33 - - + + I2C2_MS 34 - - + + I2C2_SL 35 - - + + I2C0_MS_RX 182 - - + + I2C0_MS_TX 183 - - + + I2C0_SL_RX 184 - - + + I2C0_SL_TX 185 - - + + I2C1_MS_RX 186 - - + + I2C1_MS_TX 187 - - + + I2C1_SL_RX 188 - - + + I2C1_SL_TX 189 - - + + I2C2_MS_RX 190 - - + + I2C2_MS_TX 191 - - + + I2C2_SL_RX 192 - - + + I2C2_SL_TX 193 - + I2C @@ -4422,7 +4428,7 @@ V1.0 - Original release Dec 2015 IDLE I2C controller is Idle [1:1] - + WAITING Controller is Waiting @@ -4682,92 +4688,92 @@ V1.0 - Original release Dec 2015 S0_MAXWORDS Slave MaxWords Register 0x104 - 0x00000000 + 0x00000000 MAXWORD Max Word Count [10:0] - + ENABLE Enables the max word count [31:31] - - + + S0_ADDRESS Slave I2C Address Value 0x108 - 0x00000000 + 0x00000000 A10MODE Enable 10b address mode [15:15] - + ADDRESS Address value [10:1] - + RW Read/Write value [0:0] - - + + S0_ADDRESSMASK Slave I2C Address Mask value 0x10c - 0x00000000 + 0x00000000 MASK Address mask value [10:1] - + RWMASK Read/Write mask [0:0] - - + + S0_DATA Slave Data Input/Output 0x110 - 0x00000000 + 0x00000000 VALUE I2C data value [7:0] - - + + S0_LASTADDRESS Slave I2C Last Address value 0x114 read-only - 0x00000000 + 0x00000000 ADDRESS Address value [10:1] - + DIRECTION Transaction direction 0=master send, 1=master receive [0:0] - - + + S0_STATUS @@ -4874,28 +4880,28 @@ V1.0 - Original release Dec 2015 Slave TX Count Register 0x120 read-only - 0x00000000 - + 0x00000000 + VALUE Count value [10:0] - - + + S0_RXCOUNT Slave RX Count Register 0x124 read-only - 0x00000000 - + 0x00000000 + VALUE Count value [10:0] - - + + S0_IRQ_ENB @@ -5009,27 +5015,27 @@ V1.0 - Original release Dec 2015 S0_RXFIFOIRQTRG Slave Rx FIFO IRQ Trigger Level 0x138 - 0x00000000 - + 0x00000000 + LEVEL Half full level for the Rx FIFO [4:0] - - + + S0_TXFIFOIRQTRG Slave Tx FIFO IRQ Trigger Level 0x13c - 0x00000008 - + 0x00000008 + LEVEL Half full level for the Rx FIFO [4:0] - - + + S0_FIFO_CLR @@ -5053,7 +5059,7 @@ V1.0 - Original release Dec 2015 S0_ADDRESSB Slave I2C Address B Value 0x144 - 0x00000000 + 0x00000000 RW @@ -5069,14 +5075,14 @@ V1.0 - Original release Dec 2015 ADDRESSBEN Enable Address B [15:15] - - + + S0_ADDRESSMASKB Slave I2C Address B Mask value 0x148 - 0x000007FE + 0x000007FE RWMASK @@ -5087,8 +5093,8 @@ V1.0 - Original release Dec 2015 MASK Address mask value [10:1] - - + + PERID @@ -5106,8 +5112,8 @@ V1.0 - Original release Dec 2015 I2C2 0x40016800 - - + + CAN0 @@ -5120,14 +5126,14 @@ V1.0 - Original release Dec 2015 0x00000400 registers - + CAN0 72 - - + + CAN1 74 - + CAN @@ -5170,7 +5176,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB0 CAN Frame Data Word 3 0x008 - 0x00000000 + 0x00000000 BYTE7 @@ -5181,7 +5187,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -5200,8 +5206,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB0 @@ -5218,8 +5224,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB0 @@ -5237,34 +5243,34 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB0 CAN Frame Identifier Word 0 0x018 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB0 CAN Frame Identifier Word 1 0x01C - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + CNSTAT_CMB1 @@ -5306,7 +5312,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB1 CAN Frame Data Word 3 0x028 - 0x00000000 + 0x00000000 BYTE7 @@ -5317,7 +5323,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -5336,8 +5342,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB1 @@ -5354,8 +5360,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB1 @@ -5373,34 +5379,34 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB1 CAN Frame Identifier Word 0 0x038 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB1 CAN Frame Identifier Word 1 0x03C - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + CNSTAT_CMB2 @@ -5442,7 +5448,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB2 CAN Frame Data Word 3 0x048 - 0x00000000 + 0x00000000 BYTE7 @@ -5453,7 +5459,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -5472,8 +5478,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB2 @@ -5490,8 +5496,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB2 @@ -5509,34 +5515,34 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB2 CAN Frame Identifier Word 0 0x058 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB2 CAN Frame Identifier Word 1 0x05C - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + CNSTAT_CMB3 @@ -5567,7 +5573,7 @@ V1.0 - Original release Dec 2015 0x064 0x00000000 - + TIMESTAMP Timestamp [15:0] @@ -5578,7 +5584,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB3 CAN Frame Data Word 3 0x068 - 0x00000000 + 0x00000000 BYTE7 @@ -5589,7 +5595,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -5608,8 +5614,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB3 @@ -5626,8 +5632,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB3 @@ -5645,34 +5651,34 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB3 CAN Frame Identifier Word 0 0x078 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB3 CAN Frame Identifier Word 1 0x07C - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + CNSTAT_CMB4 @@ -5714,7 +5720,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB4 CAN Frame Data Word 3 0x088 - 0x00000000 + 0x00000000 BYTE7 @@ -5725,7 +5731,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -5744,8 +5750,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB4 @@ -5762,8 +5768,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB4 @@ -5781,36 +5787,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB4 CAN Frame Identifier Word 0 0x098 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB4 CAN Frame Identifier Word 1 0x09C - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CNSTAT_CMB5 Buffer Status / Control Register 0x0A0 @@ -5850,7 +5856,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB5 CAN Frame Data Word 3 0x0A8 - 0x00000000 + 0x00000000 BYTE7 @@ -5861,7 +5867,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -5880,8 +5886,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB5 @@ -5898,8 +5904,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB5 @@ -5917,36 +5923,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB5 CAN Frame Identifier Word 0 0x0B8 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB5 CAN Frame Identifier Word 1 0x0BC - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CNSTAT_CMB6 Buffer Status / Control Register 0x0C0 @@ -5986,7 +5992,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB6 CAN Frame Data Word 3 0x0C8 - 0x00000000 + 0x00000000 BYTE7 @@ -5997,7 +6003,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -6016,8 +6022,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB6 @@ -6034,8 +6040,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB6 @@ -6053,36 +6059,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB6 CAN Frame Identifier Word 0 0x0D8 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB6 CAN Frame Identifier Word 1 0x0DC - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + - + CNSTAT_CMB7 Buffer Status / Control Register 0x0E0 @@ -6122,7 +6128,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB7 CAN Frame Data Word 3 0x0E8 - 0x00000000 + 0x00000000 BYTE7 @@ -6133,7 +6139,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -6152,8 +6158,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB7 @@ -6170,8 +6176,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB7 @@ -6189,36 +6195,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB7 CAN Frame Identifier Word 0 0x0F8 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB7 CAN Frame Identifier Word 1 0x0FC - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CNSTAT_CMB8 Buffer Status / Control Register 0x100 @@ -6258,7 +6264,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB8 CAN Frame Data Word 3 0x108 - 0x00000000 + 0x00000000 BYTE7 @@ -6269,7 +6275,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -6288,8 +6294,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB8 @@ -6306,8 +6312,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB8 @@ -6325,36 +6331,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB8 CAN Frame Identifier Word 0 0x118 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB8 CAN Frame Identifier Word 1 0x11C - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CNSTAT_CMB9 Buffer Status / Control Register 0x120 @@ -6394,7 +6400,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB9 CAN Frame Data Word 3 0x128 - 0x00000000 + 0x00000000 BYTE7 @@ -6405,7 +6411,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -6424,8 +6430,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB9 @@ -6433,7 +6439,6 @@ V1.0 - Original release Dec 2015 0x130 0x00000000 - BYTE3 Data Byte 3 @@ -6443,8 +6448,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB9 @@ -6462,36 +6467,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB9 CAN Frame Identifier Word 0 0x138 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB9 CAN Frame Identifier Word 1 0x13C - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CNSTAT_CMB10 Buffer Status / Control Register 0x140 @@ -6531,7 +6536,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB10 CAN Frame Data Word 3 0x148 - 0x00000000 + 0x00000000 BYTE7 @@ -6542,7 +6547,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -6561,8 +6566,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB10 @@ -6579,8 +6584,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB10 @@ -6598,36 +6603,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB10 CAN Frame Identifier Word 0 0x158 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB10 CAN Frame Identifier Word 1 0x15C - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CNSTAT_CMB11 Buffer Status / Control Register 0x160 @@ -6638,7 +6643,6 @@ V1.0 - Original release Dec 2015 Data Length Code [15:12] - PRI Transmit Priority Code @@ -6668,7 +6672,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB11 CAN Frame Data Word 3 0x168 - 0x00000000 + 0x00000000 BYTE7 @@ -6679,7 +6683,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -6698,8 +6702,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB11 @@ -6716,8 +6720,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB11 @@ -6735,36 +6739,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB11 CAN Frame Identifier Word 0 0x178 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB11 CAN Frame Identifier Word 1 0x17C - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CNSTAT_CMB12 Buffer Status / Control Register 0x180 @@ -6804,7 +6808,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB12 CAN Frame Data Word 3 0x188 - 0x00000000 + 0x00000000 BYTE7 @@ -6815,7 +6819,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -6834,8 +6838,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB12 @@ -6852,8 +6856,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB12 @@ -6871,36 +6875,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB12 CAN Frame Identifier Word 0 0x198 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB12 CAN Frame Identifier Word 1 0x19C - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CNSTAT_CMB13 Buffer Status / Control Register 0x1A0 @@ -6940,7 +6944,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB13 CAN Frame Data Word 3 0x1A8 - 0x00000000 + 0x00000000 BYTE7 @@ -6951,7 +6955,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -6970,8 +6974,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB13 @@ -6988,8 +6992,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB13 @@ -7007,36 +7011,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB13 CAN Frame Identifier Word 0 0x1B8 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB13 CAN Frame Identifier Word 1 0x1BC - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CNSTAT_CMB14 Buffer Status / Control Register 0x1C0 @@ -7076,7 +7080,7 @@ V1.0 - Original release Dec 2015 DATA3_CMB14 CAN Frame Data Word 3 0x1C8 - 0x00000000 + 0x00000000 BYTE7 @@ -7087,7 +7091,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -7106,8 +7110,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_CMB14 @@ -7124,8 +7128,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_CMB14 @@ -7143,36 +7147,36 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_CMB14 CAN Frame Identifier Word 0 0x1D8 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_CMB14 CAN Frame Identifier Word 1 0x1DC - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CNSTAT_HCMB Buffer Status / Control Register 0x1E0 @@ -7212,7 +7216,7 @@ V1.0 - Original release Dec 2015 DATA3_HCMB CAN Frame Data Word 3 0x1E8 - 0x00000000 + 0x00000000 BYTE7 @@ -7223,7 +7227,7 @@ V1.0 - Original release Dec 2015 BYTE8 Data Byte 8 [7:0] - + @@ -7242,8 +7246,8 @@ V1.0 - Original release Dec 2015 BYTE6 Data Byte 6 [7:0] - - + + DATA1_HCMB @@ -7260,8 +7264,8 @@ V1.0 - Original release Dec 2015 BYTE4 Data Byte 4 [7:0] - - + + DATA0_HCMB @@ -7279,40 +7283,40 @@ V1.0 - Original release Dec 2015 BYTE2 Data Byte 2 [7:0] - - + + ID0_HCMB CAN Frame Identifier Word 0 0x1F8 - 0x00000000 + 0x00000000 ID0 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - + ID1_HCMB CAN Frame Identifier Word 1 0x1FC - 0x00000000 + 0x00000000 ID1 Half of CAN Frame ID. Format Varies for Standard or Extended Frames [15:0] - - - + + + CGCR CAN Global Configuration Register 0x200 - 0x00000000 + 0x00000000 EIT @@ -7373,14 +7377,14 @@ V1.0 - Original release Dec 2015 CANEN CAN Enable [0:0] - - - - + + + + CTIM CAN Timing Register 0x204 - 0x00000000 + 0x00000000 PSC @@ -7401,106 +7405,106 @@ V1.0 - Original release Dec 2015 TSEG2 Time Segment 2 [2:0] - - - - + + + + GMSKX CAN Global Mask Extension 0x208 - 0x00000000 + 0x00000000 GM GM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard [15:1] - + XRTR Extended Remote transmission Request Bit [0:0] - - - - + + + + GMSKB CAN Global Mask Base 0x20C - 0x00000000 + 0x00000000 GM1 GM[28:18] - ID[10:0] in standard, ID[28:18] in extended [15:5] - + RTR Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended [4:4] - + IDE Identifier Extension Bit [3:3] - + GM0 GM[17:15] - Unused in standard, ID[17:15] in extended [2:0] - - - - + + + + BMSKX CAN Basic Mask Extension 0x210 - 0x00000000 + 0x00000000 BM BM[14:0] used when an extended frame is received. ID[14:0] in extended, unused standard [15:1] - + XRTR Extended Remote transmission Request Bit [0:0] - - - - + + + + BMSKB CAN Basic Mask Base 0x214 - 0x00000000 + 0x00000000 BM1 BM[28:18] - ID[10:0] in standard, ID[28:18] in extended [15:5] - + RTR Remote Transmission Request in Standard, Substitute Remote Request (SRR) in extended [4:4] - + IDE Identifier Extension Bit [3:3] - + BM0 BM[17:15] - Unused in standard, ID[17:15] in extended [2:0] - - - - + + + + CIEN CAN Interrupt Enable Register 0x218 - 0x00000000 + 0x00000000 EIEN @@ -7511,14 +7515,14 @@ V1.0 - Original release Dec 2015 IEN Buffer Interrupt Enable[14:0] [14:0] - - - - + + + + CIPND CAN Interrupt Pending Register 0x21C - 0x00000000 + 0x00000000 EIPND @@ -7529,14 +7533,14 @@ V1.0 - Original release Dec 2015 IPND Buffer Interrupt Pending[14:0] [14:0] - - - - + + + + CICLR CAN Interrupt Clear Register 0x220 - 0x00000000 + 0x00000000 EICLR @@ -7547,14 +7551,14 @@ V1.0 - Original release Dec 2015 ICLR Buffer Interrupt Clear[14:0] [14:0] - - - - + + + + CICEN CAN Interrupt Code Enable Register 0x224 - 0x00000000 + 0x00000000 EICEN @@ -7565,14 +7569,14 @@ V1.0 - Original release Dec 2015 ICEN Buffer Interrupt Code Enable[14:0] [14:0] - - - - + + + + CSTPND CAN Status Pending Register 0x228 - 0x00000000 + 0x00000000 NS @@ -7588,14 +7592,14 @@ V1.0 - Original release Dec 2015 IST Interrupt Source portion of Interrupt Code [3:0] - - - - + + + + CANEC CAN Error Counter Register 0x22C - 0x00000000 + 0x00000000 REC @@ -7606,14 +7610,14 @@ V1.0 - Original release Dec 2015 TEC Transmit Error Counter [7:0] - - - - + + + + CEDIAG CAN Error Diagnostic Register 0x230 - 0x00000000 + 0x00000000 DRIVE @@ -7649,32 +7653,32 @@ V1.0 - Original release Dec 2015 EFID Error Field Identifier [3:0] - - - - + + + + CTMR CAN Timer Register 0x234 - 0x00000000 + 0x00000000 CTMR Time Stamp Counter [15:0] - read-only + read-only - - + + - + CAN1 0x40014400 - - - - + + + + ADC 1.0 Analog to Digital Converter Peripheral @@ -7685,10 +7689,10 @@ V1.0 - Original release Dec 2015 0x00001000 registers - + ADC 44 - + ADC @@ -7711,7 +7715,7 @@ V1.0 - Original release Dec 2015 EXT_TRIG_EN Allows the external trigger to start analog acquisition [18:18] - + SWEEP_EN ADC data acquisition for all enabled channel @@ -7726,27 +7730,27 @@ V1.0 - Original release Dec 2015 CHAN_EN Enables the channel for data collection [15:0] - + FIFO_DATA FIFO data 0x004 - read-only - 0x00000000 + read-only + 0x00000000 CHAN_TAG If enabled, this will include the number of the channel corresponding to the measurement [15:12] - read-only + read-only ADC_DATA ADC acquisition data from the FIFO [11:0] - + @@ -7765,8 +7769,8 @@ V1.0 - Original release Dec 2015 FIFO_ENTRY_CNT Indicates the number of entries in the FIFO [5:0] - - + + IRQ_ENB @@ -7783,33 +7787,33 @@ V1.0 - Original release Dec 2015 TRIG_ERROR Enables the interrupt for a trigger error [5:5] - + ADC_DONE Enables the interrupt for an ADC data acquisition completion [4:4] - + FIFO_UFLOW Enables the interrupt for a FIFO underflow [3:3] - + FIFO_OFLOW Enables the interrupt for a FIFO overflow [2:2] - + FIFO_FULL Enables the interrupt for FIFO full [1:1] - + FIFO_EMPTY Enables the interrupt for FIFO empty [0:0] - - + + IRQ_RAW @@ -7827,40 +7831,40 @@ V1.0 - Original release Dec 2015 TRIG_ERROR Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion [5:5] - + ADC_DONE Indicates that a ADC conversion is done [4:4] - + FIFO_UFLOW Indicates data was unavailable when a new trigger for ADC update is received [3:3] - + FIFO_OFLOW Indicates a FIFO overflow occurred (FIFO was full when new data was written) [2:2] - + FIFO_FULL Indicates the FIFO is full [1:1] - + FIFO_EMPTY Indicates the FIFO is empty [0:0] - - + + IRQ_END Enabled Interrupt Status 0x014 - read-only - 0x00000000 + read-only + 0x00000000 FIFO_DEPTH_TRIG @@ -7871,62 +7875,62 @@ V1.0 - Original release Dec 2015 TRIG_ERROR Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled [5:5] - + ADC_DONE Indicates that a ADC conversion is done and the interrupt is enabled [4:4] - + FIFO_UFLOW Indicates a FIFO underflow occurred and the interrupt is enabled [3:3] - + FIFO_OFLOW Indicates a FIFO overflow occurred and the interrupt is enabled [2:2] - + FIFO_FULL Indicates the FIFO is full and the interrupt is enabled [1:1] - + FIFO_EMPTY Indicates the FIFO is empty and the interrupt is enabled [0:0] - - + + IRQ_CLR Clear Interrupt 0x018 - write-only - 0x00000000 + write-only + 0x00000000 TRIG_ERROR Clears the trigger error interrupt status. Always reads 0 [3:3] - + ADC_DONE Clears the ADC done interrupt status. Always reads 0 [2:2] - + FIFO_UFLOW Clears the FIFO underflow interrupt status. Always reads 0 [1:1] - + FIFO_OFLOW Clears the FIFO overflow interrupt status. Always reads 0 [0:0] - - + + RXFIFOIRQTRG @@ -7945,13 +7949,13 @@ V1.0 - Original release Dec 2015 FIFO_CLR FIFO Clear 0x020 - 0x00000000 + 0x00000000 FIFO_CLR Clears the ADC FIFO. Always reads 0 [0:0] - write-only + write-only @@ -7961,12 +7965,12 @@ V1.0 - Original release Dec 2015 0xffc read-only 0x001907e9 - + - - - - + + + + DAC0 1.0 Digital to Analog Converter Peripheral @@ -7977,14 +7981,14 @@ V1.0 - Original release Dec 2015 0x00000800 registers - + DAC0 40 - - + + DAC1 41 - + DAC @@ -8002,7 +8006,7 @@ V1.0 - Original release Dec 2015 EXT_TRIG_EN Enables external trigger [10:10] - + @@ -8020,22 +8024,22 @@ V1.0 - Original release Dec 2015 DAC_SETTLING Sets the the amount of time in microseconds the control FSM waits for the DAC settling time [7:5] - + FIFO_DATA FIFO data 0x008 - read-write - 0x00000000 + read-write + 0x00000000 DATA Data for FIFO write [11:0] - write-only - + write-only + @@ -8054,8 +8058,8 @@ V1.0 - Original release Dec 2015 FIFO_ENTRY_CNT Indicates the number of entries in the FIFO [5:0] - - + + IRQ_ENB @@ -8072,33 +8076,33 @@ V1.0 - Original release Dec 2015 TRIG_ERROR Enables the interrupt for a trigger error [5:5] - + DAC_DONE Enables the interrupt for a DAC data acquisition completion [4:4] - + FIFO_UFLOW Enables the interrupt for a FIFO underflow [3:3] - + FIFO_OFLOW Enables the interrupt for a FIFO overflow [2:2] - + FIFO_FULL Enables the interrupt for FIFO full [1:1] - + FIFO_EMPTY Enables the interrupt for FIFO empty [0:0] - - + + IRQ_RAW @@ -8116,40 +8120,40 @@ V1.0 - Original release Dec 2015 TRIG_ERROR Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion [5:5] - + DAC_DONE Indicates that a DAC conversion is done [4:4] - + FIFO_UFLOW Indicates data was unavailable when a new trigger for DAC update is received [3:3] - + FIFO_OFLOW Indicates a FIFO overflow occurred (FIFO was full when new data was written) [2:2] - + FIFO_FULL Indicates the FIFO is full [1:1] - + FIFO_EMPTY Indicates the FIFO is empty [0:0] - - + + IRQ_END Enabled Interrupt Status 0x018 - read-only - 0x00000000 + read-only + 0x00000000 FIFO_DEPTH_TRIG @@ -8160,62 +8164,62 @@ V1.0 - Original release Dec 2015 TRIG_ERROR Indicates a manual or external trigger occurred when the DAC was BUSY doing a conversion and the interrupt is enabled [5:5] - + DAC_DONE Indicates that a DAC conversion is done and the interrupt is enabled [4:4] - + FIFO_UFLOW Indicates a FIFO underflow occurred and the interrupt is enabled [3:3] - + FIFO_OFLOW Indicates a FIFO overflow occurred and the interrupt is enabled [2:2] - + FIFO_FULL Indicates the FIFO is full and the interrupt is enabled [1:1] - + FIFO_EMPTY Indicates the FIFO is empty and the interrupt is enabled [0:0] - - + + IRQ_CLR Clear Interrupt 0x01C - write-only - 0x00000000 + write-only + 0x00000000 TRIG_ERROR Clears the trigger error interrupt status. Always reads 0 [3:3] - + DAC_DONE Clears the DAC done interrupt status. Always reads 0 [2:2] - + FIFO_UFLOW Clears the FIFO underflow interrupt status. Always reads 0 [1:1] - + FIFO_OFLOW Clears the FIFO overflow interrupt status. Always reads 0 [0:0] - - + + TXFIFOIRQTRG @@ -8234,32 +8238,32 @@ V1.0 - Original release Dec 2015 FIFO_CLR FIFO Clear 0x024 - 0x00000000 + 0x00000000 FIFO_CLR Clears the DAC FIFO. Always reads 0 [0:0] - write-only + write-only - + PERID Peripheral ID Register 0x7fc read-only 0x002007e9 - + - + DAC1 0x40023800 - - - - + + + + SPW 1.0 SpaceWire Peripheral @@ -8273,7 +8277,7 @@ V1.0 - Original release Dec 2015 SpW 38 - + SPW @@ -8286,153 +8290,156 @@ V1.0 - Original release Dec 2015 RA Reads as 1 if the RMAP command handler is available [31:31] - read-only + read-only RX Reads as 1 if unaligned writes are available for the receiver [30:30] - read-only - + read-only + RC Reads as 1 if RMAP CRC is enabled in the core [29:29] - read-only + read-only NCH Number of DMA Channels minus one [28:27] - read-only - + read-only + PO The number of available SpaceWire ports minus one [26:26] - read-only + read-only CC CCSDS/CCITT CRC-16 [25:25] - read-only - + read-only + ID Interrupt distribution available [24:24] - read-only + read-only LE Loop-back Enable [22:22] - read-write - + read-write + PS Selects the active port when the no port force bit is zero [21:21] - read-write - + read-write + NP Disable port force [20:20] - read-write - + read-write + PNPA SpW Plug-and-Play Available [19:18] - read-only - + read-only + RD If set only one RMAP buffer is used [17:17] - read-write - + read-write + RE Enable RMAP command handler [16:16] - read-write - + read-write + PE SpW Plug-and-Play Enable [15:15] - read-write + read-write TL Transmitter Enable Lock Control [13:13] - read-write - + read-write + TF Time-code Flag Filter [12:12] - read-write - + read-write + TR Enable time-code receptions [11:11] - + TT Enable time-code transmissions [10:10] - + LI Generate interrupt when link error occurs [9:9] - + TQ Generate interrupt when a valid time-code is received [8:8] - + + RS Make complete reset of the SpaceWire node. Self-clearing [6:6] - + + PM Enable Promiscuous mode [5:5] - + + TI The host can generate a tick by writing a one to this field [4:4] - + IE If set, an interrupt is generated when one or both of bit 8 to 9 is set and its corresponding event occurs [3:3] - + AS Automatically start the link when a NULL has been received [2:2] - + LS Start the link [1:1] - + LD Disable the SpaceWire CODEC [0:0] - + - + STS Status/Interrupt Source Register 0x004 @@ -8442,12 +8449,12 @@ V1.0 - Original release Dec 2015 NRXD Number of Receive Descriptors [27:26] - + NTXD Number of Transmit Descriptors [25:24] - + LS Link State @@ -8457,12 +8464,12 @@ V1.0 - Original release Dec 2015 AP Active port [9:9] - + EE Set to one when a packet is received with an EOP after the first byte for a non-RMAP packet and after the second byte for a RMAP packet [8:8] - + IA Packet is received with an invalid destination address field @@ -8497,26 +8504,26 @@ V1.0 - Original release Dec 2015 TO A new time count value was received [0:0] - + DEFADDR Node Address Register 0x008 - read-write - 0x000000FE + read-write + 0x000000FE DEFMASK 8-bit default mask used for node identification on the SpaceWire network [15:8] - + DEFADDR 8-bit node address used for node identification on the SpaceWire network [7:0] - + @@ -8535,21 +8542,21 @@ V1.0 - Original release Dec 2015 CLKDIVRUN 8-bit Clock divisor value used for the clock-divider when the link-interface is in the run-state [7:0] - - + + DKEY Destination Key 0x010 0x00000000 - + DESTKEY RMAP destination key [7:0] - - + + TC @@ -8567,15 +8574,15 @@ V1.0 - Original release Dec 2015 TIMECNT The current value of the system time counter [5:0] - - + + - + TDR Timer and Disconnect Register 0x018 - read-only - 0x00000000 + read-only + 0x00000000 DISCONNECT @@ -8586,15 +8593,15 @@ V1.0 - Original release Dec 2015 TIMER64 Used to generate the 6.4 and 12.8 us time periods [11:0] - - + + DMACTRL0 DMA Control Register 0x020 - read-write - 0x00000000 + read-write + 0x00000000 INTNUM @@ -8605,42 +8612,42 @@ V1.0 - Original release Dec 2015 EP EEP Termination [23:23] - + TR Truncated [22:22] - + IE Interrupt code transmit enable on EEP [21:21] - + IT Interrupt code transmit enable on truncation [20:20] - + RP Receive Packet IRQ [19:19] - + TP Transmit Packet IRQ [18:18] - + TL Transmit Enable Lock [17:17] - + LE Disable transmitter when a link error occurs [16:16] - + SP Strip PID @@ -8655,81 +8662,81 @@ V1.0 - Original release Dec 2015 EN Enable Address [13:13] - + NS If cleared, packets will be discarded when a packet is arriving and there are no active descriptors. If set, the GRSPW will wait for a descriptor to be activated [12:12] - + RD Indicates to the GRSPW that there are enabled descriptors in the descriptor table [11:11] - + RX Reception to the DMA channel is currently active [10:10] - read-only - + read-only + AT Abort the currently transmitting packet and disable transmissions [9:9] - read-only - + read-only + RA An error response was detected on the AHB bus - DMA receive [8:8] - + TA An error response was detected on the AHB bus - DMA transmit [7:7] - + PR Set each time a packet has been received [6:6] - + PS Set each time a packet has been sent [5:5] - + AI An interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus [4:4] - + RI An interrupt will be generated each time a packet has been received [3:3] - + TI An interrupt will be generated each time a packet is transmitted [2:2] - + RE Packets are allowed to be received to this channel [1:1] - + TE Write a one to this bit each time new descriptors are activated in the table [0:0] - - + + DMAMAXLEN0 DMA RX Maximum Length Register 0x024 - read-write + read-write 0x00000000 @@ -8743,8 +8750,8 @@ V1.0 - Original release Dec 2015 DMATXDESC0 DMA Transmitter Descriptor Table Address Register 0x028 - read-write - 0x00000000 + read-write + 0x00000000 DESCBASEADDR @@ -8755,7 +8762,7 @@ V1.0 - Original release Dec 2015 DESCSEL Offset into the descriptor table [9:4] - + @@ -8775,8 +8782,8 @@ V1.0 - Original release Dec 2015 Offset into the descriptor table [9:3] - - + + DMAADDR0 DMA Receiver Table Address Register @@ -8794,9 +8801,9 @@ V1.0 - Original release Dec 2015 Address [7:0] - - - - - - - + + - + IRQ_ROUTER 1.0 Interrupt Router Peripheral @@ -9369,95 +9376,95 @@ V1.0 - Original release Dec 2015 0x00001000 registers - + U0 0 - - + + U1 1 - - + + U2 2 - - + + U3 3 - - + + U4 4 - - + + U5 5 - - + + U6 6 - - + + U7 7 - - + + U8 8 - - + + U9 9 - - + + U10 10 - - + + U11 11 - - + + U12 12 - - + + U13 13 - - + + U14 14 - - + + U15 15 - - + + U37 37 - - + + U39 39 - - + + U73 73 - - + + U75 75 - - + + FPU 194 - - + + TXEV 195 - - IRQ + + IRQ DMASEL0 @@ -9471,7 +9478,7 @@ V1.0 - Original release Dec 2015 DMA trigger source selection value [6:0] - + DMASEL1 @@ -9485,7 +9492,7 @@ V1.0 - Original release Dec 2015 DMA trigger source selection value [6:0] - + DMASEL2 @@ -9499,7 +9506,7 @@ V1.0 - Original release Dec 2015 DMA trigger source selection value [6:0] - + DMASEL3 @@ -9513,8 +9520,8 @@ V1.0 - Original release Dec 2015 DMA trigger source selection value [6:0] - - + + DMATTSEL Trigger select for the DMA channels @@ -9527,8 +9534,8 @@ V1.0 - Original release Dec 2015 DMA trigger type selection value [3:0] - - + + ADCSEL Interrupt select for ADC @@ -9541,8 +9548,8 @@ V1.0 - Original release Dec 2015 ADC trigger source selection value [4:0] - - + + DACSEL0 Interrupt select for DAC0 @@ -9555,8 +9562,8 @@ V1.0 - Original release Dec 2015 DAC trigger source selection value [4:0] - - + + DACSEL1 Interrupt select for DAC1 @@ -9569,8 +9576,8 @@ V1.0 - Original release Dec 2015 DAC trigger source selection value [4:0] - - + + IRQ_OUT0 DEBUG IRQ_OUT[31:0] @@ -9583,8 +9590,8 @@ V1.0 - Original release Dec 2015 IRQ_OUT[31:0] [31:0] - - + + IRQ_OUT1 DEBUG IRQ_OUT[63:32] @@ -9597,8 +9604,8 @@ V1.0 - Original release Dec 2015 IRQ_OUT[63:32] [31:0] - - + + IRQ_OUT2 DEBUG IRQ_OUT[95:64] @@ -9611,8 +9618,8 @@ V1.0 - Original release Dec 2015 IRQ_OUT[95:64] [31:0] - - + + IRQ_OUT3 DEBUG IRQ_OUT[127:96] @@ -9625,8 +9632,8 @@ V1.0 - Original release Dec 2015 IRQ_OUT[127:96] [31:0] - - + + IRQ_OUT4 DEBUG IRQ_OUT[159:128] @@ -9639,8 +9646,8 @@ V1.0 - Original release Dec 2015 IRQ_OUT[159:128] [31:0] - - + + IRQ_OUT5 DEBUG IRQ_OUT[179:160] @@ -9653,20 +9660,20 @@ V1.0 - Original release Dec 2015 IRQ_OUT[179:160] [19:0] - - + + PERID Peripheral ID Register 0xffc read-only 0x028107e9 - + - - + + - + WATCH_DOG 1.0 Watchdog Block Peripheral @@ -9676,11 +9683,11 @@ V1.0 - Original release Dec 2015 0x00001000 registers - + WATCHDOG 47 - - WDOG + + WDOG WDOGLOAD @@ -9694,8 +9701,8 @@ V1.0 - Original release Dec 2015 Count to load [31:0] - - + + WDOGVALUE Down Counter Value @@ -9708,8 +9715,8 @@ V1.0 - Original release Dec 2015 Actual Count [31:0] - - + + WDOGCONTROL Enable for block reset and interrupt @@ -9726,9 +9733,9 @@ V1.0 - Original release Dec 2015 INTEN Enable watchdog interrupt [0:0] - - - + + + WDOGINTCLR A write of any value clears the WDT module interrupt, and reloads @@ -9742,8 +9749,8 @@ the counter from the value in the WDOGLOAD Register Write any value to clear interrupt [31:0] - - + + WDOGRIS Raw interrupt status @@ -9756,8 +9763,8 @@ the counter from the value in the WDOGLOAD Register Interrupt Status [0:0] - - + + WDOGMIS Interrupt status @@ -9770,8 +9777,8 @@ the counter from the value in the WDOGLOAD Register Masked Interrupt Status [0:0] - - + + WDOGLOCK Lock @@ -9784,8 +9791,8 @@ the counter from the value in the WDOGLOAD Register Register write enable status [31:0] - - + + WDOGITCR Integration test control @@ -9798,8 +9805,8 @@ the counter from the value in the WDOGLOAD Register Enable test mode of WDOGINT and WDOGRES [0:0] - - + + WDOGITOP Integration test output set @@ -9816,9 +9823,9 @@ the counter from the value in the WDOGLOAD Register WDOGRES Set output value [0:0] - - - + + + WDOGPERIPHID0 Peripheral ID @@ -9831,8 +9838,8 @@ the counter from the value in the WDOGLOAD Register Peripheral ID [7:0] - - + + WDOGPERIPHID1 Peripheral ID @@ -9845,8 +9852,8 @@ the counter from the value in the WDOGLOAD Register Peripheral ID [7:0] - - + + WDOGPERIPHID2 Peripheral ID @@ -9859,8 +9866,8 @@ the counter from the value in the WDOGLOAD Register Peripheral ID [7:0] - - + + WDOGPERIPHID3 Peripheral ID @@ -9873,8 +9880,8 @@ the counter from the value in the WDOGLOAD Register Peripheral ID [7:0] - - + + WDOGPCELLID0 PrimeCell ID @@ -9887,8 +9894,8 @@ the counter from the value in the WDOGLOAD Register Prime Cell ID [7:0] - - + + WDOGPCELLID1 PrimeCell ID @@ -9901,8 +9908,8 @@ the counter from the value in the WDOGLOAD Register Prime Cell ID [7:0] - - + + WDOGPCELLID2 PrimeCell ID @@ -9915,8 +9922,8 @@ the counter from the value in the WDOGLOAD Register Prime Cell ID [7:0] - - + + WDOGPCELLID3 PrimeCell ID @@ -9929,13 +9936,13 @@ the counter from the value in the WDOGLOAD Register Prime Cell ID [7:0] - - + + - - + + - + TRNG 1.0 True Random Number Generator @@ -9945,11 +9952,11 @@ the counter from the value in the WDOGLOAD Register 0x00000400 registers - + TRNG 42 - - TRNG + + TRNG IMR @@ -9977,9 +9984,9 @@ the counter from the value in the WDOGLOAD Register EHR_VALID_INT_MASK Mask when the TRNG has collected 192 bits [0:0] - - - + + + ISR Interrupt Status Register @@ -10006,9 +10013,9 @@ the counter from the value in the WDOGLOAD Register EHR_VALID 192 bits have been collected in the TRNG [0:0] - - - + + + ICR Interrupt Clear Register @@ -10035,9 +10042,9 @@ the counter from the value in the WDOGLOAD Register EHR_VALID Set to 1 after the EHR_DATA[0,1,2,3,4,5] registers have been read [0:0] - - - + + + CONFIG Configuration Register @@ -10050,8 +10057,8 @@ the counter from the value in the WDOGLOAD Register Selects the number of inverters (out of four possible selections) in the ring oscillator [1:0] - - + + VALID Valid Register @@ -10064,8 +10071,8 @@ the counter from the value in the WDOGLOAD Register Indicates that the collection of bits in the TRNG is complete [0:0] - - + + EHR_DATA0 Entropy Holding Register Data Register @@ -10078,33 +10085,33 @@ the counter from the value in the WDOGLOAD Register 32 Bits of Entropy Holding Register [31:0] - - + + EHR_DATA1 Entropy Holding Register Data Register 0x0118 - + EHR_DATA2 Entropy Holding Register Data Register 0x011C - + EHR_DATA3 Entropy Holding Register Data Register 0x0120 - + EHR_DATA4 Entropy Holding Register Data Register 0x0124 - + EHR_DATA5 Entropy Holding Register Data Register 0x0128 - + RND_SOURCE_ENABLE Random Source Enable Register @@ -10117,8 +10124,8 @@ the counter from the value in the WDOGLOAD Register The entropy source, ring oscillator, is enabled [0:0] - - + + SAMPLE_CNT1 Section TBD @@ -10131,8 +10138,8 @@ the counter from the value in the WDOGLOAD Register Sets the number of clk cycles between two consecutive ring oscillator samples [31:0] - - + + AUTOCORR_STATISTIC Auto-correlator Statistic Register @@ -10149,9 +10156,9 @@ the counter from the value in the WDOGLOAD Register AUTOCORR_TRYS Count each time an autocorrelation test starts [13:0] - - - + + + DEBUG_CONTROL Section TBD @@ -10173,9 +10180,9 @@ the counter from the value in the WDOGLOAD Register VNC_PYPASS The Von Neumann balancer is bypassed [1:1] - - - + + + SW_RESET Reset Register @@ -10188,8 +10195,8 @@ the counter from the value in the WDOGLOAD Register Writing 1 to this register causes an internal TRNG reset [0:0] - - + + BUSY Busy Register @@ -10202,8 +10209,8 @@ the counter from the value in the WDOGLOAD Register Reflects the status of the rng_busy signal [0:0] - - + + RST_BITS_COUNTER Reset Bits Counter Register @@ -10216,8 +10223,8 @@ the counter from the value in the WDOGLOAD Register Writing any value to this bit resets the bits counter and TRNG valid registers [0:0] - - + + BIST_CNTR0 BIST Counter Register @@ -10230,23 +10237,23 @@ the counter from the value in the WDOGLOAD Register Returns the results of the TRNG BIST counter [21:0] - - - + + + BIST_CNTR1 BIST Counter Register 0x01E4 - - + + BIST_CNTR2 BIST Counter Register 0x01E8 - + - - + + - + ETH 1.1 Ethernet Block @@ -10256,12 +10263,12 @@ the counter from the value in the WDOGLOAD Register 0x00002000 registers - + Ethernet 36 - - ETH - + + ETH + MAC_CONFIG @@ -10274,99 +10281,99 @@ the counter from the value in the WDOGLOAD Register WD Watchdog disable [23:23] - + JD Jabber Disable [22:22] - + BE Frame Burst Enable [21:21] - + JE Jumbo Frame Enable [20:20] - + IFG Inter-Frame Gap [19:17] - + DCRS Disable Carrier Sense During Transmission [16:16] - + PS Port Select [15:15] - + FES Speed [14:14] - + DRO Disable Receive Own [13:13] - + LM Loopback Mode [12:12] - + DM Duplex Mode [11:11] - + IPC Checksum Offload [10:10] - + DR Disable Retry [9:9] - + ACS Automatic Pad, or CRC Stripping [7:7] - + BL Back-Off-Limit [6:5] - + DC Deferral Check [4:4] - + TE Transmitter Enable [3:3] - + RE Receiver Enable [2:2] - + PRELEN Preamble Length for Transmit frames [1:0] - - - + + + MAC_FRAME_FLTR Contains the frame filtering controls @@ -10378,69 +10385,69 @@ the counter from the value in the WDOGLOAD Register RA Receive All [31:31] - + DNTU Drop non TCP/UDP over IP Frames [21:21] - + VFTE VLAN Tag Filter Enable [16:16] - + HDF Hash or Perfect Filter [10:10] - + SAF Source Address Filter Enable [9:9] - + SAIF SA Inverse Filtering [8:8] - + PCF Pass Control Frames [7:6] - + DBF Disable Broadcast Frames [5:5] - + PM Pass All Multicast [4:4] - + DAIF DA Inverse Filtering [3:3] - + HMC Hash Multicast [2:2] - + HUC Hash Unicast [1:1] - + PR Promiscuous Mode [0:0] - - - + + + MAC_GMII_ADDR Controls the management cycles to an external PHY @@ -10452,29 +10459,29 @@ the counter from the value in the WDOGLOAD Register PA Physical Layer Address [15:11] - + GR GMII Register [10:6] - + CR CSR Clock Range [5:2] - + GW GMII Write/Read [1:1] - + GB GMII Busy [0:0] - - - + + + MAC_GMII_DATA Contains the data to be written to or read from the PHY register @@ -10486,9 +10493,9 @@ the counter from the value in the WDOGLOAD Register GD GMII Data [15:0] - - - + + + MAC_FLOW_CTRL Controls the generation of control frames @@ -10500,7 +10507,7 @@ the counter from the value in the WDOGLOAD Register PT Pause time [31:16] - + DZPQ Disable Zero-Quanta Pause @@ -10530,8 +10537,8 @@ the counter from the value in the WDOGLOAD Register FCB_BPA Flow Control Busy or Backpressure Activate [0:0] - - + + MAC_VLAN_TAG @@ -10544,23 +10551,23 @@ the counter from the value in the WDOGLOAD Register ESVL Enable S-VLAN [18:18] - + VTIM VLAN Tag Inverse Match Enable [17:17] - + ETV Enable 12-Bit VLAN Tag Comparison [16:16] - + VL VLAN Tag identifier for Receive Frames [15:0] - - + + MAC_DEBUG @@ -10573,7 +10580,7 @@ the counter from the value in the WDOGLOAD Register TXSTSFSTS MTL TxStatus FIFO Full Status [25:25] - + TXFSTS MTL Tx FIFO Not Empty Status @@ -10628,9 +10635,9 @@ the counter from the value in the WDOGLOAD Register RPESTS MAC GMII or MII Receive Protocol Engine Status [0:0] - - - + + + MAC_INTR_STAT Contains the interrupt status @@ -10663,8 +10670,8 @@ the counter from the value in the WDOGLOAD Register MMC Interrupt Status [4:4] - - + + MAC_INTR_MASK Contains the masks for generating interrupt @@ -10677,8 +10684,8 @@ the counter from the value in the WDOGLOAD Register Timestamp Interrupt Mask [9:9] - - + + MAC_ADDR_H Contains the high 16-bits of the first MAC Address @@ -10690,15 +10697,15 @@ the counter from the value in the WDOGLOAD Register AE Address Enable, This bit is always set to 1 [31:31] - read-only - + read-only + ADDRHI MAC Address0[47:32] [15:0] - read-only - - + read-only + + MAC_ADDR_L @@ -10711,10 +10718,10 @@ the counter from the value in the WDOGLOAD Register ADDRLO MAC Address0[31:0] [31:0] - read-only - - - + read-only + + + MAC_WDOG_TO Controls the watchdog time-out for received frames @@ -10726,15 +10733,15 @@ the counter from the value in the WDOGLOAD Register PWE Programmable Watchdog Enable [16:16] - + WTO Watchdog Timeout [13:0] - - - - + + + + MMC_CNTRL MMC Control Register @@ -10776,9 +10783,9 @@ the counter from the value in the WDOGLOAD Register CNTRST Counters Reset [0:0] - - - + + + MMC_INTR_RX MMC Receive Interrupt Register @@ -10910,14 +10917,14 @@ the counter from the value in the WDOGLOAD Register RXGBOCTIS MMC Receive Good Bad Octet Counter Interrupt Status [1:1] - + RXGBFRMIS MMC Receive Good Bad Frame Counter Interrupt Status [0:0] - - - + + + MMC_INTR_TX MMC Transmit Interrupt Register @@ -11049,14 +11056,14 @@ the counter from the value in the WDOGLOAD Register TXGBFRMIS MMC Transmit Good Bad Frame Counter Interrupt Status [1:1] - + TXGBOCTIS MMC Transmit Good Bad Octet Counter Interrupt Status [0:0] - - + + MMC_INTR_MASK_RX MMC Receive Interrupt Mask Register @@ -11193,9 +11200,9 @@ the counter from the value in the WDOGLOAD Register RXGBFRMIM MMC Receive Good Bad Frame Counter Interrupt Mask [0:0] - - - + + + MMC_INTR_MASK_TX MMC Transmit Interrupt Mask Register @@ -11332,9 +11339,9 @@ the counter from the value in the WDOGLOAD Register TXGBOCTIM MMC Transmit Good Bad Octet Counter Interrupt Mask [0:0] - - - + + + TXOCTETCOUNT_GB MMC Transmit Count @@ -11347,8 +11354,8 @@ the counter from the value in the WDOGLOAD Register Number of bytes [31:0] - - + + TXFRAMECOUNT_GB MMC Frame Count Register @@ -11361,8 +11368,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXBCASTFRAMES_G MMC Good Broadcast Frames Register @@ -11375,8 +11382,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXMCASTFRAMES_G MMC Good Multicast Frames Register @@ -11389,8 +11396,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TX64OCT_GB MMC Good and bad Frames transmitted with length 64 @@ -11403,8 +11410,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TX65TO127OCT_GB MMC Good and bad Frames transmitted with length 65 to 127 @@ -11417,9 +11424,9 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - + - + TX128TO255OCT_GB MMC Good and bad Frames transmitted with length 128 to 255 0x012c @@ -11431,7 +11438,7 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - + TX256TO511OCT_GB @@ -11445,8 +11452,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TX512TO1023OCT_GB MMC Good and bad Frames transmitted with length 512 to 1023 @@ -11459,8 +11466,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TX1024MAXOCT_GB MMC Good and bad Frames transmitted with length 1024 to max bytes @@ -11473,8 +11480,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXUCASTFRAME_GB MMC number of good and bad unicast frames transmitted @@ -11487,8 +11494,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXMCASTFRAME_GB MMC number of good and bad MULTIcast frames transmitted @@ -11501,8 +11508,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXBCASTFRAME_GB MMC number of good and bad broadcast frames transmitted @@ -11515,8 +11522,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXUNDERERR MMC number of frames aborted because of frame underflow error @@ -11529,8 +11536,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXSINGLECOL_G MMC Number of successfully transmitted frames after a single collision @@ -11543,8 +11550,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXMULTICOL_G MMC Number of successfully transmitted frames after multiple collisions @@ -11557,8 +11564,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXDEFERRED MMC Number of successfully transmitted frames after a deferral @@ -11571,8 +11578,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXLATECOL MMC Number of aborted frames because of late collision error @@ -11585,8 +11592,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXEXESSCOL MMC Number of aborted frames because of excessive collision errors @@ -11599,8 +11606,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXCARRIERERROR MMC Number of aborted frames because of carrier sense error @@ -11613,8 +11620,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXOCTETCOUNT_G MMC Number of bytes transmitted frames only in good frames @@ -11627,8 +11634,8 @@ the counter from the value in the WDOGLOAD Register Number of bytes [31:0] - - + + TXFRAMECOUNT_G MMC Number of good frames transmitted @@ -11641,9 +11648,9 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - - + + + TXEXCESSDEF MMC Number of frames aborted because of excessive deferral error 0x016c @@ -11655,8 +11662,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXPAUSEFRAMES MMC Number of good pause frames transmitted @@ -11669,8 +11676,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXLANFRAMES_G MMC Number of good VLAN frames transmitted @@ -11683,8 +11690,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + TXOVERSIZE_G MMC Number of frames transmitted without errors @@ -11697,8 +11704,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXFRAMECOUNT_GB MMC Number of good and bad frames received @@ -11711,8 +11718,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXOCTETCOUNT_GB MMC Number of bytes received in good and bad frames @@ -11725,8 +11732,8 @@ the counter from the value in the WDOGLOAD Register Number of bytes [31:0] - - + + RXOCTETCOUNT_G MMC Number of bytes received in good frames only @@ -11739,8 +11746,8 @@ the counter from the value in the WDOGLOAD Register Number of bytes [31:0] - - + + RXBCASTFRAMES_G MMC Number of good broadcast frames received @@ -11753,8 +11760,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXMCASTFRAMES_G MMC Number of good multicast frames received @@ -11767,8 +11774,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXCRCERROR MMC Number of frames received with CRC error @@ -11781,8 +11788,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXALIGNERROR MMC Number of frames received with alignment error @@ -11795,8 +11802,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXRUNTERROR MMC Number of frames received with runt error @@ -11809,8 +11816,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXJABBERERROR MMC Number of giant frames received with length greater than 1518 bytes and with CRC error @@ -11823,8 +11830,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXUNDERSIZE_G MMC Number of frames received with length less than 64 bytes @@ -11837,8 +11844,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXOVERSIZE_G MMC Number of frames received without errors with length greater than the max size @@ -11851,8 +11858,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RX64OCTETS_GB MMC Number of good and bad frames received with length 64 bytes @@ -11865,8 +11872,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RX65TO127OCT_GB MMC Number of good and bad frames received with length between 65 and 127 bytes @@ -11879,8 +11886,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RX128TO255OCT_GB MMC Number of good and bad frames received with length between 128 and 255 bytes @@ -11893,8 +11900,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RX256TO511OCT_GB MMC Number of good and bad frames received with length between 256 and 511 bytes @@ -11907,8 +11914,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RX512TO1023OCT_GB MMC Number of good and bad frames received with length between 512 and 1023 bytes @@ -11921,8 +11928,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RX1024MAXOCT_GB MMC Number of good and bad frames received with length between 1024 and max size bytes @@ -11935,8 +11942,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXUCASTFRAMES_G MMC Number of received good unicast frames @@ -11949,8 +11956,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + RXLENGTHERROR MMC Number of frames received with length error @@ -11963,9 +11970,9 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - - + + + RXOUTRANGETYPE MMC Number of frames received with length field not equal to the valid frame size 0x01CC @@ -11977,9 +11984,9 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - + - + RXPAUSEFRAMES MMC Number of good and valid Pause frames received 0x01D0 @@ -11991,9 +11998,9 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - - + + + RXFIFOOVERFLOW MMC Number of missed received frames because of FIFO overflow 0x01D4 @@ -12005,9 +12012,9 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - - + + + RXVLANFRAMES_GB MMC Number of good and bad VLAN frames received 0x01D8 @@ -12019,9 +12026,9 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - - + + + RXWDOGERROR MMC Number of frames received with error because of watchdog timeout error 0x01DC @@ -12033,9 +12040,9 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - - + + + RXRCVERROR MMC Number of frames received with Receive error or Frame Extension error 0x01E0 @@ -12047,9 +12054,9 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - - + + + RXCTRLFRAMES_G MMC Number of received good control frames 0x01E4 @@ -12061,8 +12068,8 @@ the counter from the value in the WDOGLOAD Register Number of frames [31:0] - - + + VLAN_INCREPLACE Holds the VLAN Tag for insertion into or replacement in the transmit frames @@ -12074,7 +12081,7 @@ the counter from the value in the WDOGLOAD Register CSVL C-VLAN or S-VLAN [19:19] - + VLP VLAN Priority Control @@ -12089,9 +12096,9 @@ the counter from the value in the WDOGLOAD Register VLT VLAN Tag for Transmit Frames [15:0] - - - + + + VLAN_HASHTABLE Holds the VLAN Hash Table @@ -12103,9 +12110,9 @@ the counter from the value in the WDOGLOAD Register VLHT VLAN Hash Table [15:0] - - - + + + TIMESTAMP_CTRL Controls the IEEE 1588 timestamp generation and update logic @@ -12122,104 +12129,104 @@ the counter from the value in the WDOGLOAD Register ATSEN2 Auxiliary Snapshot 2 Enable [27:27] - + ATSEN1 Auxiliary Snapshot 1 Enable [26:26] - + ATSEN0 Auxiliary Snapshot 0 Enable [25:25] - + ATSFC Auxiliary Snapshot FIFO Clear [24:24] - + TSENMACADDR Enable MAC address for PTP Frame Filtering [18:18] - + SNAPTYPSEL Select PTP packets for Taking Snapshots [17:16] - + TSMSTRENA Enable Snapshot for Messages Relevant to Master [15:15] - + TSEVNTENA Enable Timestamp Snapshot for Event Messages [14:14] - + TSIPV4ENA Enable Processing of PTP Frames Sent over IPv4-UDP [13:13] - + TSIPV6ENA Enable Processing of PTP Frames Sent over IPv6-UDP [12:12] - + TSIPENA Enable Processing of PTP over Ethernet Frames [11:11] - + TSVER2ENA Enable PTP packet Processing for Version 2 Format [10:10] - + TSCTRLSSR Timestamp Digital or Binary Rollover Control [9:9] - + TSENALL Enable Timestamp for All Frames [8:8] - + TSADDRREG Addend Reg Update [5:5] - + TSTRIG Timestamp Interrupt Trigger Enable [4:4] - + TSUPDT Timestamp Update [3:3] - + TSINIT Timestamp Initialize [2:2] - + TSCFUPDT Timestamp Fine or Coarse Update [1:1] - + TSENA Timestamp Enable [0:0] - - - + + + SUBSEC_INC Holds the 8-bit value by which the Sub-Second register is incremented @@ -12231,9 +12238,9 @@ the counter from the value in the WDOGLOAD Register SSINC Sub-Second Increment Valuee [7:0] - - - + + + SYSTIME_SECONDS Holds the lower 32 bits of the second field of the system time @@ -12245,9 +12252,9 @@ the counter from the value in the WDOGLOAD Register TSS Timestamp Second [31:0] - - - + + + SYSTIME_NANOSEC Holds 32 bits of the nano-second field of the system time @@ -12259,9 +12266,9 @@ the counter from the value in the WDOGLOAD Register TSSS Timestamp Sub Seconds [30:0] - - - + + + SYSTIME_SECSUPDAT Holds the lower 32 bits of the second field to be written to, added to, or subtracted from the system time value @@ -12273,9 +12280,9 @@ the counter from the value in the WDOGLOAD Register TSS Timestamp Second [31:0] - - - + + + SYSTIME_NSECUP Holds 32 bits of the nano-second field to be written to, added to, or subtracted from the system time value @@ -12292,9 +12299,9 @@ the counter from the value in the WDOGLOAD Register TSSS Timestamp Sub Seconds [30:0] - - - + + + TIMESTAMPADDEND This register is used by software to re-adjust the clock frequency linearly to match the Master clock frequency @@ -12306,9 +12313,9 @@ the counter from the value in the WDOGLOAD Register TSAR Timestamp Addend Register [31:0] - - - + + + TARGET_TIME_SECS Holds the high 32-bits of time to be compared with the system time @@ -12320,9 +12327,9 @@ the counter from the value in the WDOGLOAD Register TSTR Target Time Seconds Registe [31:0] - - - + + + TARGET_TIME_NSEC Holds the lower 32-bits of time to be compared with the system time @@ -12334,15 +12341,15 @@ the counter from the value in the WDOGLOAD Register TRGTBUSY 32 Bits of Hash Table [31:31] - + TTSLO Target Timestamp Low Register [30:0] - - + + - + DMA_BUS_MODE Controls the DMA Host Interface Mode @@ -12354,74 +12361,74 @@ the counter from the value in the WDOGLOAD Register RIB Rebuild INCRx Burst [31:31] - + PRWG Channel Priority Weights [29:28] - + TXPR Transmit Priority [27:27] - + MB Mixed Burst [26:26] - + AAL Address-Aligned Beats [25:25] - + PBLx8 PBLx8 Mode [24:24] - + USP Use Separate PBL [23:23] - + RPBL Rx DMA PBL [22:17] - + FB Fixed Burste [16:16] - + PR Priority Ratio [15:14] - + PBL Programmable Burst Lengthe [13:8] - + DSL Descriptor Skip Length [6:2] - + DA DMA Arbitration Scheme [1:1] - + SWR Software Reset (Read, Write Set, and Self Clear) [0:0] - - - + + + DMA_TX_POLL_DEMAND Used by the host to instruct the DMA to poll the transmit Descriptor list @@ -12433,9 +12440,9 @@ the counter from the value in the WDOGLOAD Register TPD Transmit Poll Demand (Read Only and Write Trigger) [31:0] - - - + + + DMA_RX_POLL_DEMAND Used by the host to instruct the DMA to poll the Receive Descriptor list @@ -12447,9 +12454,9 @@ the counter from the value in the WDOGLOAD Register RPD Receive Poll Demand (Read Only and Write Trigger) [31:0] - - - + + + DMA_RX_DESC_LIST_ADDR Points the DMA to the start of the Receive Descriptor list @@ -12461,9 +12468,9 @@ the counter from the value in the WDOGLOAD Register RDESLA Start of Receive List [31:0] - - - + + + DMA_TX_DESC_LIST_ADDR Points the DMA to the start of the Transmit Descriptor list @@ -12475,9 +12482,9 @@ the counter from the value in the WDOGLOAD Register TDESLA Start of Transmit List [31:0] - - - + + + DMA_STATUS Used to determine the status of the DMA @@ -12579,14 +12586,14 @@ the counter from the value in the WDOGLOAD Register TPS Transmit Process Stopped [1:1] - + TI Transmit Interrupt [0:0] - - - + + + DMA_OPER_MODE Sets the Receive and Transmit operation mode and command @@ -12598,79 +12605,79 @@ the counter from the value in the WDOGLOAD Register DT Disable Dropping of TCP/IP Checksum Error Frames [26:26] - + RSF Receive Store and Forward [25:25] - + DFF Disable Flushing of Received Frames [24:24] - + TSF Transmit Store and Forward [21:21] - + FTF Flush Transmit FIFO [20:20] - + TTC Transmit Threshold Control [16:14] - + ST Start or Stop Transmission Command [13:13] - + RFD Threshold for Deactivating Flow Control [12:11] - + RFA Threshold for Activating Flow Control [10:9] - + FEF Forward Error Frames [7:7] - + FUF Forward Undersized Good Frames [6:6] - + DGF Drop Giant Frames [5:5] - + RTC Receive Threshold Control [4:3] - + OSF Operate on Second Frame [2:2] - + SR Start or Stop Receive [1:1] - - - + + + DMA_INTR_EN Enables the interrupts reported in the status register @@ -12682,7 +12689,7 @@ the counter from the value in the WDOGLOAD Register NIE Normal Interrupt Summary Enable [16:16] - + AIE Abnormal Interrupt Summary Enable @@ -12752,9 +12759,9 @@ the counter from the value in the WDOGLOAD Register TIE Transmit Interrupt Enable [0:0] - - - + + + DMA_MISS_OVER_COUNTER Contains the counters for discarded frames because no Receive Descriptor is available @@ -12782,8 +12789,8 @@ the counter from the value in the WDOGLOAD Register This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. [15:0] - - + + DMA_RX_INTR_WDOG_TIMER Watchdog timeout for Receive Interrupt from DMA @@ -12795,9 +12802,9 @@ the counter from the value in the WDOGLOAD Register RIWT These bits indicate the number of system clock cycles x 256 for which the watchdog timer is set. [7:0] - - - + + + DMA_AHB_STATUS Provides the active status of the read and write channels of the AHB master interface @@ -12810,8 +12817,8 @@ the counter from the value in the WDOGLOAD Register When high, indicates that the AHB master interface FSMs are in the non-idle state [0:0] - - + + DMA_CURR_TX_DESC Contains the start address of the current Transmit Descriptor read by the DMA @@ -12823,9 +12830,9 @@ the counter from the value in the WDOGLOAD Register CURTDESAPTR Cleared on Reset. Pointer updated by the DMA during operation. [31:0] - - - + + + DMA_CURR_RX_DESC Contains the start address of the current Receive Descriptor read by the DMA @@ -12837,9 +12844,9 @@ the counter from the value in the WDOGLOAD Register CURRDESAPTR Cleared on Reset. Pointer updated by the DMA during operation. [31:0] - - - + + + DMA_CURR_TX_BUFR_ADDR Contains the start address of the current Receive Descriptor read by the DMA @@ -12851,9 +12858,9 @@ the counter from the value in the WDOGLOAD Register CURTBUFAPTR Cleared on Reset. Pointer updated by the DMA during operation. [31:0] - - - + + + DMA_CURR_RX_BUFR_ADDR Contains the current Receive Buffer address read by the DMA @@ -12865,10 +12872,10 @@ the counter from the value in the WDOGLOAD Register CURTBUFAPTR Cleared on Reset. Pointer updated by the DMA during operation. [31:0] - - - + + + - +