Rework library structure
Changed: - Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) which is mostly re-exported in this crate. - Overhaul and simplification of several HAL APIs. The system configuration and IRQ router peripheral instance generally does not need to be passed to HAL API anymore. - All HAL drivers are now type erased. The constructors will still expect and consume the PAC singleton component for resource management purposes, but are not cached anymore. - Refactoring of GPIO library to be more inline with embassy GPIO API. Added: - I2C clock timeout feature support.
This commit is contained in:
@ -1,10 +1,10 @@
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//! API for using the [crate::pac::Clkgen] peripheral.
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//!
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//! It also includes functionality to enable the peripheral clocks.
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//! Calling [ClkgenExt::constrain] on the [crate::pac::Clkgen] peripheral generates the
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//! [ClkgenCfgr] structure which can be used to configure and set up the clock.
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//! Calling [ClockConfigurator::new] returns a builder structure which allows
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//! setting up the clock.
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//!
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//! Calling [ClkgenCfgr::freeze] returns the frozen clock configuration inside the [Clocks]
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//! Calling [ClockConfigurator::freeze] returns the frozen clock configuration inside the [Clocks]
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//! structure. This structure can also be used to configure other structures provided by this HAL.
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//!
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//! # Examples
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@ -15,48 +15,11 @@ use crate::adc::ADC_MAX_CLK;
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use crate::pac;
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use crate::time::Hertz;
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pub use vorago_shared_periphs::clock::{Clocks, HBO_FREQ};
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use vorago_shared_periphs::{enable_peripheral_clock, PeripheralSelect};
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pub const HBO_FREQ: Hertz = Hertz::from_raw(20_000_000);
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pub const XTAL_OSC_TSTART_MS: u32 = 15;
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#[derive(Debug, Copy, Clone, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum PeripheralSelect {
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Spi0 = 0,
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Spi1 = 1,
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Spi2 = 2,
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Spi3 = 3,
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Uart0 = 4,
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Uart1 = 5,
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Uart2 = 6,
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I2c0 = 7,
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I2c1 = 8,
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I2c2 = 9,
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Can0 = 10,
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Can1 = 11,
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Rng = 12,
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Adc = 13,
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Dac = 14,
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Dma = 15,
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Ebi = 16,
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Eth = 17,
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Spw = 18,
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Clkgen = 19,
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IrqRouter = 20,
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IoConfig = 21,
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Utility = 22,
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Watchdog = 23,
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PortA = 24,
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PortB = 25,
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PortC = 26,
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PortD = 27,
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PortE = 28,
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PortF = 29,
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PortG = 30,
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}
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pub type PeripheralClock = PeripheralSelect;
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum FilterClkSel {
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@ -70,81 +33,6 @@ pub enum FilterClkSel {
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Clk7 = 7,
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}
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#[inline(always)]
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pub fn enable_peripheral_clock(syscfg: &mut pac::Sysconfig, clock: PeripheralSelect) {
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syscfg
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.peripheral_clk_enable()
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.modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
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}
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#[inline(always)]
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pub fn disable_peripheral_clock(syscfg: &mut pac::Sysconfig, clock: PeripheralSelect) {
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syscfg
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.peripheral_clk_enable()
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.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) });
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}
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#[inline(always)]
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pub fn assert_periph_reset(syscfg: &mut pac::Sysconfig, periph: PeripheralSelect) {
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syscfg
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.peripheral_reset()
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.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << periph as u8)) });
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}
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#[inline(always)]
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pub fn deassert_periph_reset(syscfg: &mut pac::Sysconfig, periph: PeripheralSelect) {
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syscfg
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.peripheral_reset()
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.modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph as u8)) });
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}
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#[inline(always)]
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fn assert_periph_reset_for_two_cycles(syscfg: &mut pac::Sysconfig, periph: PeripheralSelect) {
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assert_periph_reset(syscfg, periph);
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cortex_m::asm::nop();
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cortex_m::asm::nop();
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deassert_periph_reset(syscfg, periph);
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}
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pub trait SyscfgExt {
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fn enable_peripheral_clock(&mut self, clock: PeripheralClock);
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fn disable_peripheral_clock(&mut self, clock: PeripheralClock);
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fn assert_periph_reset(&mut self, periph: PeripheralSelect);
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fn deassert_periph_reset(&mut self, periph: PeripheralSelect);
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fn assert_periph_reset_for_two_cycles(&mut self, periph: PeripheralSelect);
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}
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impl SyscfgExt for pac::Sysconfig {
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#[inline(always)]
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fn enable_peripheral_clock(&mut self, clock: PeripheralClock) {
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enable_peripheral_clock(self, clock)
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}
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#[inline(always)]
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fn disable_peripheral_clock(&mut self, clock: PeripheralClock) {
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disable_peripheral_clock(self, clock)
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}
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#[inline(always)]
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fn assert_periph_reset(&mut self, clock: PeripheralSelect) {
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assert_periph_reset(self, clock)
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}
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#[inline(always)]
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fn deassert_periph_reset(&mut self, clock: PeripheralSelect) {
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deassert_periph_reset(self, clock)
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}
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#[inline(always)]
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fn assert_periph_reset_for_two_cycles(&mut self, periph: PeripheralSelect) {
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assert_periph_reset_for_two_cycles(self, periph)
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}
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}
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/// Refer to chapter 8 (p.57) of the programmers guide for detailed information.
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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@ -223,12 +111,12 @@ pub fn pll_setup_delay() {
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}
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pub trait ClkgenExt {
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fn constrain(self) -> ClkgenCfgr;
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fn constrain(self) -> ClockConfigurator;
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}
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impl ClkgenExt for pac::Clkgen {
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fn constrain(self) -> ClkgenCfgr {
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ClkgenCfgr {
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fn constrain(self) -> ClockConfigurator {
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ClockConfigurator {
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source_clk: None,
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ref_clk_sel: RefClkSel::None,
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clksel_sys: ClkselSys::Hbo,
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@ -241,21 +129,6 @@ impl ClkgenExt for pac::Clkgen {
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}
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}
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pub struct ClkgenCfgr {
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ref_clk_sel: RefClkSel,
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clksel_sys: ClkselSys,
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clk_div_sel: ClkDivSel,
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/// The source clock frequency which is either an external clock connected to XTAL_N, or a
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/// crystal connected to the XTAL_OSC input.
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source_clk: Option<Hertz>,
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pll_cfg: Option<PllCfg>,
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clk_lost_detection: bool,
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/// Feature only works on revision B of the board.
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#[cfg(feature = "revb")]
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pll_lock_lost_detection: bool,
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clkgen: pac::Clkgen,
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}
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#[derive(Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct ClkSourceFreqNotSet;
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@ -269,6 +142,21 @@ pub enum ClkCfgError {
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InconsistentCfg,
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}
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pub struct ClockConfigurator {
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ref_clk_sel: RefClkSel,
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clksel_sys: ClkselSys,
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clk_div_sel: ClkDivSel,
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/// The source clock frequency which is either an external clock connected to XTAL_N, or a
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/// crystal connected to the XTAL_OSC input.
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source_clk: Option<Hertz>,
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pll_cfg: Option<PllCfg>,
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clk_lost_detection: bool,
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/// Feature only works on revision B of the board.
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#[cfg(feature = "revb")]
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pll_lock_lost_detection: bool,
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clkgen: pac::Clkgen,
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}
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/// Delays a given amount of milliseconds.
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///
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/// Taken from the HAL implementation. This implementation is probably not precise and it
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@ -283,7 +171,30 @@ pub fn hbo_clock_delay_ms(ms: u32) {
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}
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}
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impl ClkgenCfgr {
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impl ClockConfigurator {
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/// Create a new clock configuration instance.
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pub fn new(clkgen: pac::Clkgen) -> Self {
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ClockConfigurator {
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source_clk: None,
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ref_clk_sel: RefClkSel::None,
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clksel_sys: ClkselSys::Hbo,
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clk_div_sel: ClkDivSel::Div1,
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clk_lost_detection: false,
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pll_lock_lost_detection: false,
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pll_cfg: None,
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clkgen,
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}
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}
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/// Steals a new [ClockConfigurator] instance.
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///
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/// # Safety
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///
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/// Circumvents HAL ownership rules.
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pub unsafe fn steal() -> Self {
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Self::new(unsafe { pac::Clkgen::steal() })
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}
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#[inline]
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pub fn source_clk(mut self, src_clk: Hertz) -> Self {
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self.source_clk = Some(src_clk);
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@ -334,7 +245,7 @@ impl ClkgenCfgr {
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/// might have had a reason for those, so I am going to keep them. Chances are, this
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/// process only has to be performed once, and it does not matter if it takes a few
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/// microseconds or milliseconds longer.
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pub fn freeze(self, syscfg: &mut pac::Sysconfig) -> Result<Clocks, ClkCfgError> {
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pub fn freeze(self) -> Result<Clocks, ClkCfgError> {
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// Sanitize configuration.
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if self.source_clk.is_none() {
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return Err(ClkCfgError::ClkSourceFreqNotSet);
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@ -349,7 +260,7 @@ impl ClkgenCfgr {
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return Err(ClkCfgError::PllConfigNotSet);
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}
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syscfg.enable_peripheral_clock(PeripheralSelect::Clkgen);
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enable_peripheral_clock(PeripheralSelect::Clkgen);
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let mut final_sysclk = self.source_clk.unwrap();
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// The HAL forces back the HBO clock here with a delay.. Even though this is
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// not stricly necessary when coming from a fresh start, it could be still become relevant
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@ -458,13 +369,11 @@ impl ClkgenCfgr {
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.ctrl0()
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.modify(|_, w| unsafe { w.clksel_sys().bits(self.clksel_sys as u8) });
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Ok(Clocks {
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sysclk: final_sysclk,
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apb1: final_sysclk / 2,
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apb2: final_sysclk / 4,
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Ok(Clocks::__new(
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final_sysclk,
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#[cfg(not(feature = "va41628"))]
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adc_clk: self.cfg_adc_clk_div(final_sysclk),
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})
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self.cfg_adc_clk_div(final_sysclk),
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))
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}
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#[cfg(not(feature = "va41628"))]
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@ -487,54 +396,6 @@ impl ClkgenCfgr {
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}
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}
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/// Frozen clock frequencies
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///
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/// The existence of this value indicates that the clock configuration can no longer be changed.
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/// The [self] module documentation gives some more information on how to retrieve an instance
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/// of this structure.
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#[derive(Copy, Clone, PartialEq, Eq, Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct Clocks {
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sysclk: Hertz,
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apb1: Hertz,
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apb2: Hertz,
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#[cfg(not(feature = "va41628"))]
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adc_clk: Hertz,
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}
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impl Clocks {
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/// Returns the frequency of the HBO clock
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pub const fn hbo(&self) -> Hertz {
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HBO_FREQ
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}
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/// Returns the frequency of the APB0 which is equal to the system clock.
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pub const fn apb0(&self) -> Hertz {
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self.sysclk()
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}
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/// Returns system clock divied by 2.
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pub const fn apb1(&self) -> Hertz {
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self.apb1
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}
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/// Returns system clock divied by 4.
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pub const fn apb2(&self) -> Hertz {
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self.apb2
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}
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/// Returns the system (core) frequency
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pub const fn sysclk(&self) -> Hertz {
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self.sysclk
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}
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/// Returns the ADC clock frequency which has a separate divider.
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#[cfg(not(feature = "va41628"))]
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pub const fn adc_clk(&self) -> Hertz {
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self.adc_clk
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}
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}
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pub fn rearm_sysclk_lost() {
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rearm_sysclk_lost_with_periph(&unsafe { pac::Clkgen::steal() })
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}
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