Updates and fixes
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All checks were successful
Rust/va416xx-rs/pipeline/pr-main This commit looks good
- Improve and fix SPI HAL and example - Fix RTIC example
This commit is contained in:
parent
dfab81a813
commit
9bda3f29f4
@ -41,4 +41,4 @@ debug-assertions = false # <-
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lto = true
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opt-level = 'z' # <-
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overflow-checks = false # <-
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# strip = true # Automatically strip symbols from the binary.
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strip = true # Automatically strip symbols from the binary.
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@ -99,9 +99,9 @@ example.
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### Using VS Code
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Assuming a working debug connection to your VA108xx board, you can debug using VS Code with
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the [`Cortex-Debug` plugin](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug). Please make sure that
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[`objdump-multiarch` and `nm-multiarch`](https://forums.raspberrypi.com/viewtopic.php?t=333146)
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Assuming a working debug connection to your VA416xx board, you can debug using VS Code with
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the [`Cortex-Debug` plugin](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug).
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Please make sure that [`objdump-multiarch` and `nm-multiarch`](https://forums.raspberrypi.com/viewtopic.php?t=333146)
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are installed as well.
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Some sample configuration files for VS code were provided and can be used by running
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@ -8,8 +8,13 @@ cortex-m = "0.7"
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cortex-m-rt = "0.7"
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embedded-hal = "1"
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panic-rtt-target = { version = "0.1.3" }
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panic-halt = { version = "0.2" }
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rtt-target = { version = "0.5" }
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crc = "3"
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[dependencies.va416xx-hal]
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path = "../va416xx-hal"
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[features]
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default = ["rtt-panic"]
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rtt-panic = []
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@ -19,6 +19,9 @@
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use cortex_m_rt::entry;
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use crc::{Crc, CRC_32_ISO_HDLC};
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#[cfg(not(feature = "rtt-panic"))]
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use panic_halt as _;
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#[cfg(feature = "rtt-panic")]
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use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use va416xx_hal::{
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@ -42,6 +45,9 @@ const DEBUG_PRINTOUTS: bool = true;
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// self-flash itself. It is recommended that you use a tool like probe-rs, Keil IDE, or a flash
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// loader to boot a bootloader without this feature.
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const FLASH_SELF: bool = false;
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// Useful for debugging and see what the bootloader is doing. Enabled currently, because
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// the binary stays small enough.
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const RTT_PRINTOUT: bool = true;
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// Important bootloader addresses and offsets, vector table information.
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@ -88,8 +94,10 @@ impl WdtInterface for OptWdt {
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#[entry]
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fn main() -> ! {
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rtt_init_print!();
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rprintln!("-- VA416xx bootloader --");
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if RTT_PRINTOUT {
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rtt_init_print!();
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rprintln!("-- VA416xx bootloader --");
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}
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let mut dp = pac::Peripherals::take().unwrap();
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let cp = cortex_m::Peripherals::take().unwrap();
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// Disable ROM protection.
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@ -133,18 +141,24 @@ fn main() -> ! {
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nvm.write_data(0x0, &first_four_bytes);
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nvm.write_data(0x4, bootloader_data);
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if let Err(e) = nvm.verify_data(0x0, &first_four_bytes) {
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rprintln!("verification of self-flash to NVM failed: {:?}", e);
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if RTT_PRINTOUT {
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rprintln!("verification of self-flash to NVM failed: {:?}", e);
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}
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}
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if let Err(e) = nvm.verify_data(0x4, bootloader_data) {
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rprintln!("verification of self-flash to NVM failed: {:?}", e);
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if RTT_PRINTOUT {
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rprintln!("verification of self-flash to NVM failed: {:?}", e);
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}
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}
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nvm.write_data(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes());
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if let Err(e) = nvm.verify_data(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes()) {
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rprintln!(
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"error: CRC verification for bootloader self-flash failed: {:?}",
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e
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);
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if RTT_PRINTOUT {
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rprintln!(
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"error: CRC verification for bootloader self-flash failed: {:?}",
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e
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);
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}
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}
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}
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@ -156,7 +170,7 @@ fn main() -> ! {
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} else if check_app_crc(AppSel::B, &opt_wdt) {
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boot_app(AppSel::B, &cp)
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} else {
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if DEBUG_PRINTOUTS {
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if DEBUG_PRINTOUTS && RTT_PRINTOUT {
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rprintln!("both images corrupt! booting image A");
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}
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// TODO: Shift a CCSDS packet out to inform host/OBC about image corruption.
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@ -184,7 +198,7 @@ fn check_own_crc(wdt: &OptWdt, nvm: &Nvm, cp: &cortex_m::Peripherals) {
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let crc_calc = digest.finalize();
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wdt.feed();
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if crc_exp == 0x0000 || crc_exp == 0xffff {
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if DEBUG_PRINTOUTS {
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if DEBUG_PRINTOUTS && RTT_PRINTOUT {
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rprintln!("BL CRC blank - prog new CRC");
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}
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// Blank CRC, write it to NVM.
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@ -194,7 +208,7 @@ fn check_own_crc(wdt: &OptWdt, nvm: &Nvm, cp: &cortex_m::Peripherals) {
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// cortex_m::peripheral::SCB::sys_reset();
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} else if crc_exp != crc_calc {
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// Bootloader is corrupted. Try to run App A.
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if DEBUG_PRINTOUTS {
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if DEBUG_PRINTOUTS && RTT_PRINTOUT {
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rprintln!(
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"bootloader CRC corrupt, read {} and expected {}. booting image A immediately",
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crc_calc,
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@ -217,7 +231,7 @@ fn read_four_bytes_at_addr_zero(buf: &mut [u8; 4]) {
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}
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}
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fn check_app_crc(app_sel: AppSel, wdt: &OptWdt) -> bool {
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if DEBUG_PRINTOUTS {
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if DEBUG_PRINTOUTS && RTT_PRINTOUT {
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rprintln!("Checking image {:?}", app_sel);
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}
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if app_sel == AppSel::A {
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@ -237,7 +251,9 @@ fn check_app_given_addr(
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let image_size = unsafe { (image_size_addr as *const u32).read_unaligned().to_be() };
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// Sanity check.
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if image_size > APP_A_END_ADDR - APP_A_START_ADDR - 8 {
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rprintln!("detected invalid app size {}", image_size);
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if RTT_PRINTOUT {
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rprintln!("detected invalid app size {}", image_size);
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}
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return false;
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}
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wdt.feed();
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@ -252,7 +268,7 @@ fn check_app_given_addr(
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}
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fn boot_app(app_sel: AppSel, cp: &cortex_m::Peripherals) -> ! {
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if DEBUG_PRINTOUTS {
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if DEBUG_PRINTOUTS && RTT_PRINTOUT {
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rprintln!("booting app {:?}", app_sel);
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}
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let clkgen = unsafe { pac::Clkgen::steal() };
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@ -2,8 +2,13 @@
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#![no_main]
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#![no_std]
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use va416xx_hal::time::Hertz;
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const EXTCLK_FREQ: Hertz = Hertz::from_raw(40_000_000);
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#[rtic::app(device = pac, dispatchers = [U1, U2, U3])]
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mod app {
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use super::*;
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use cortex_m::asm;
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use embedded_hal::digital::StatefulOutputPin;
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use panic_rtt_target as _;
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@ -13,6 +18,7 @@ mod app {
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use va416xx_hal::{
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gpio::{OutputReadablePushPull, Pin, PinsG, PG5},
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pac,
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prelude::*,
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};
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#[local]
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@ -23,14 +29,22 @@ mod app {
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#[shared]
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struct Shared {}
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rtic_monotonics::systick_monotonic!(Mono, 10_000);
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rtic_monotonics::systick_monotonic!(Mono, 1_000);
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#[init]
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fn init(_ctx: init::Context) -> (Shared, Local) {
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fn init(mut cx: init::Context) -> (Shared, Local) {
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rtt_init_default!();
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rprintln!("-- Vorago RTIC template --");
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let mut dp = pac::Peripherals::take().unwrap();
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let portg = PinsG::new(&mut dp.sysconfig, dp.portg);
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rprintln!("-- Vorago RTIC example application --");
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// Use the external clock connected to XTAL_N.
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let clocks = cx
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.device
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.clkgen
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.constrain()
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.xtal_n_clk_with_src_freq(EXTCLK_FREQ)
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.freeze(&mut cx.device.sysconfig)
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.unwrap();
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Mono::start(cx.core.SYST, clocks.sysclk().raw());
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let portg = PinsG::new(&mut cx.device.sysconfig, cx.device.portg);
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let led = portg.pg5.into_readable_push_pull_output();
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blinky::spawn().ok();
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(Shared {}, Local { led })
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@ -3,13 +3,12 @@
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//! If you do not use the loopback mode, MOSI and MISO need to be tied together on the board.
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#![no_main]
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#![no_std]
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use cortex_m_rt::entry;
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use embedded_hal::spi::{Mode, SpiBus, MODE_0};
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use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use simple_examples::peb1;
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use va416xx_hal::spi::{clk_div_for_target_clock, Spi, TransferConfig};
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use va416xx_hal::spi::{Spi, SpiClkConfig, TransferConfigWithHwcs};
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use va416xx_hal::{
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gpio::{PinsB, PinsC},
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pac,
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@ -22,9 +21,8 @@ use va416xx_hal::{
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pub enum ExampleSelect {
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// Enter loopback mode. It is not necessary to tie MOSI/MISO together for this
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Loopback,
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// Send a test buffer and print everything received. You need to tie together MOSI/MISO in this
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// mode.
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TestBuffer,
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// You need to tie together MOSI/MISO in this mode.
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MosiMisoTiedTogether,
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}
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const EXAMPLE_SEL: ExampleSelect = ExampleSelect::Loopback;
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@ -50,21 +48,21 @@ fn main() -> ! {
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let pins_b = PinsB::new(&mut dp.sysconfig, dp.portb);
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let pins_c = PinsC::new(&mut dp.sysconfig, dp.portc);
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// Configure SPI1 pins.
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// Configure SPI0 pins.
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let (sck, miso, mosi) = (
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pins_b.pb15.into_funsel_1(),
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pins_c.pc0.into_funsel_1(),
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pins_c.pc1.into_funsel_1(),
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);
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let mut spi_cfg = SpiConfig::default().clk_div(
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clk_div_for_target_clock(Hertz::from_raw(SPI_SPEED_KHZ), &clocks)
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let mut spi_cfg = SpiConfig::default().clk_cfg(
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SpiClkConfig::from_clk(Hertz::from_raw(SPI_SPEED_KHZ), &clocks)
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.expect("invalid target clock"),
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);
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if EXAMPLE_SEL == ExampleSelect::Loopback {
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spi_cfg = spi_cfg.loopback(true)
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}
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let transfer_cfg = TransferConfig::new_no_hw_cs(None, Some(SPI_MODE), BLOCKMODE, false);
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let transfer_cfg = TransferConfigWithHwcs::new_no_hw_cs(None, Some(SPI_MODE), BLOCKMODE, false);
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// Create SPI peripheral.
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let mut spi0 = Spi::new(
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&mut dp.sysconfig,
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@ -77,24 +75,24 @@ fn main() -> ! {
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.expect("creating SPI peripheral failed");
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spi0.set_fill_word(FILL_WORD);
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loop {
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let mut tx_buf: [u8; 3] = [1, 2, 3];
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let mut rx_buf: [u8; 3] = [0; 3];
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// Can't really verify correct reply here.
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spi0.write(&[0x42]).expect("write failed");
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// Need small delay.. otherwise we will read back the sent byte (which we don't want here).
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// The write function will return as soon as all bytes were shifted out, ignoring the
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// reply bytes.
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delay_sysclk.delay_us(50);
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// Because of the loopback mode, we should get back the fill word here.
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spi0.read(&mut rx_buf[0..1]).unwrap();
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assert_eq!(rx_buf[0], FILL_WORD);
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let tx_buf: [u8; 4] = [1, 2, 3, 0];
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let mut rx_buf: [u8; 4] = [0; 4];
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// Can't really verify correct behaviour here. Just verify nothing crazy happens or it hangs up.
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spi0.write(&[0x42, 0x43]).expect("write failed");
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spi0.transfer_in_place(&mut tx_buf)
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// Can't really verify correct behaviour here. Just verify nothing crazy happens or it hangs up.
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spi0.read(&mut rx_buf[0..2]).unwrap();
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// If the pins are tied together, we should received exactly what we send.
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let mut inplace_buf = tx_buf;
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spi0.transfer_in_place(&mut inplace_buf)
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.expect("SPI transfer_in_place failed");
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assert_eq!([1, 2, 3], tx_buf);
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assert_eq!([1, 2, 3, 0], inplace_buf);
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spi0.transfer(&mut rx_buf, &tx_buf)
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.expect("SPI transfer failed");
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assert_eq!(rx_buf, tx_buf);
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assert_eq!(rx_buf, [1, 2, 3, 0]);
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delay_sysclk.delay_ms(500);
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}
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}
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@ -8,6 +8,16 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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# [unreleased]
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## Changed
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- Simplification of clock configuration API for SPI HAL.
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## Fixed
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- Fixes for SPI peripheral: Flush implementation was incorrect and should now flush properly.
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- Fixes for SPI example
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- Fixes for RTIC example
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# [v0.2.0] 2024-09-18
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- Documentation improvements
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@ -228,30 +228,23 @@ pub trait TransferConfigProvider {
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fn sod(&mut self, sod: bool);
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fn blockmode(&mut self, blockmode: bool);
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fn mode(&mut self, mode: Mode);
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fn clk_div(&mut self, clk_div: u16);
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fn clk_cfg(&mut self, clk_cfg: SpiClkConfig);
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fn hw_cs_id(&self) -> u8;
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}
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/// This struct contains all configuration parameter which are transfer specific
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/// and might change for transfers to different SPI slaves
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#[derive(Copy, Clone)]
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pub struct TransferConfig<HwCs> {
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pub clk_div: Option<u16>,
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pub mode: Option<Mode>,
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/// This only works if the Slave Output Disable (SOD) bit of the [`SpiConfig`] is set to
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/// false
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#[derive(Copy, Clone, Debug)]
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pub struct TransferConfigWithHwcs<HwCs> {
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pub hw_cs: Option<HwCs>,
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pub sod: bool,
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/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
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/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
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/// duration of multiple data words
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pub blockmode: bool,
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pub cfg: TransferConfig,
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}
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/// Type erased variant of the transfer configuration. This is required to avoid generics in
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/// the SPI constructor.
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pub struct ErasedTransferConfig {
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pub clk_div: Option<u16>,
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#[derive(Copy, Clone, Debug)]
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pub struct TransferConfig {
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pub clk_cfg: Option<SpiClkConfig>,
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pub mode: Option<Mode>,
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pub sod: bool,
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/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
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@ -261,67 +254,67 @@ pub struct ErasedTransferConfig {
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pub hw_cs: HwChipSelectId,
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}
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impl TransferConfig<NoneT> {
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impl TransferConfigWithHwcs<NoneT> {
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pub fn new_no_hw_cs(
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clk_div: Option<u16>,
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clk_cfg: Option<SpiClkConfig>,
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mode: Option<Mode>,
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blockmode: bool,
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sod: bool,
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) -> Self {
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TransferConfig {
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clk_div,
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mode,
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TransferConfigWithHwcs {
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hw_cs: None,
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sod,
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blockmode,
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cfg: TransferConfig {
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clk_cfg,
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mode,
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sod,
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blockmode,
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hw_cs: HwChipSelectId::Invalid,
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},
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}
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}
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}
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impl<HwCs: HwCsProvider> TransferConfig<HwCs> {
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impl<HwCs: HwCsProvider> TransferConfigWithHwcs<HwCs> {
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pub fn new(
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clk_div: Option<u16>,
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clk_cfg: Option<SpiClkConfig>,
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mode: Option<Mode>,
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hw_cs: Option<HwCs>,
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blockmode: bool,
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sod: bool,
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) -> Self {
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TransferConfig {
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clk_div,
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mode,
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TransferConfigWithHwcs {
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hw_cs,
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sod,
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blockmode,
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cfg: TransferConfig {
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clk_cfg,
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mode,
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sod,
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blockmode,
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hw_cs: HwCs::CS_ID,
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},
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}
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}
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pub fn downgrade(self) -> ErasedTransferConfig {
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ErasedTransferConfig {
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clk_div: self.clk_div,
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mode: self.mode,
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sod: self.sod,
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blockmode: self.blockmode,
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hw_cs: HwCs::CS_ID,
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}
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pub fn downgrade(self) -> TransferConfig {
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self.cfg
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}
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}
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impl<HwCs: HwCsProvider> TransferConfigProvider for TransferConfig<HwCs> {
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impl<HwCs: HwCsProvider> TransferConfigProvider for TransferConfigWithHwcs<HwCs> {
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/// Slave Output Disable
|
||||
fn sod(&mut self, sod: bool) {
|
||||
self.sod = sod;
|
||||
self.cfg.sod = sod;
|
||||
}
|
||||
|
||||
fn blockmode(&mut self, blockmode: bool) {
|
||||
self.blockmode = blockmode;
|
||||
self.cfg.blockmode = blockmode;
|
||||
}
|
||||
|
||||
fn mode(&mut self, mode: Mode) {
|
||||
self.mode = Some(mode);
|
||||
self.cfg.mode = Some(mode);
|
||||
}
|
||||
|
||||
fn clk_div(&mut self, clk_div: u16) {
|
||||
self.clk_div = Some(clk_div);
|
||||
fn clk_cfg(&mut self, clk_cfg: SpiClkConfig) {
|
||||
self.cfg.clk_cfg = Some(clk_cfg);
|
||||
}
|
||||
|
||||
fn hw_cs_id(&self) -> u8 {
|
||||
@ -331,7 +324,7 @@ impl<HwCs: HwCsProvider> TransferConfigProvider for TransferConfig<HwCs> {
|
||||
|
||||
/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
|
||||
pub struct SpiConfig {
|
||||
clk_div: u16,
|
||||
clk: SpiClkConfig,
|
||||
/// By default, configure SPI for master mode (ms == false)
|
||||
ms: bool,
|
||||
/// Slave output disable. Useful if separate GPIO pins or decoders are used for CS control
|
||||
@ -345,7 +338,8 @@ pub struct SpiConfig {
|
||||
impl Default for SpiConfig {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
clk_div: DEFAULT_CLK_DIV,
|
||||
// Default value is definitely valid.
|
||||
clk: SpiClkConfig::from_div(DEFAULT_CLK_DIV).unwrap(),
|
||||
ms: Default::default(),
|
||||
slave_output_disable: Default::default(),
|
||||
loopback_mode: Default::default(),
|
||||
@ -360,8 +354,8 @@ impl SpiConfig {
|
||||
self
|
||||
}
|
||||
|
||||
pub fn clk_div(mut self, clk_div: u16) -> Self {
|
||||
self.clk_div = clk_div;
|
||||
pub fn clk_cfg(mut self, clk_cfg: SpiClkConfig) -> Self {
|
||||
self.clk = clk_cfg;
|
||||
self
|
||||
}
|
||||
|
||||
@ -479,7 +473,8 @@ pub fn mode_to_cpo_cph_bit(mode: embedded_hal::spi::Mode) -> (bool, bool) {
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
pub struct SpiClkConfig {
|
||||
prescale_val: u16,
|
||||
scrdv: u8,
|
||||
@ -494,6 +489,23 @@ impl SpiClkConfig {
|
||||
}
|
||||
}
|
||||
|
||||
impl SpiClkConfig {
|
||||
pub fn new(prescale_val: u16, scrdv: u8) -> Self {
|
||||
Self {
|
||||
prescale_val,
|
||||
scrdv,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn from_div(div: u16) -> Result<Self, SpiClkConfigError> {
|
||||
spi_clk_config_from_div(div)
|
||||
}
|
||||
|
||||
pub fn from_clk(spi_clk: Hertz, clocks: &Clocks) -> Option<Self> {
|
||||
clk_div_for_target_clock(spi_clk, clocks).map(|div| spi_clk_config_from_div(div).unwrap())
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub enum SpiClkConfigError {
|
||||
DivIsZero,
|
||||
@ -566,27 +578,21 @@ where
|
||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||
{
|
||||
#[inline]
|
||||
pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError> {
|
||||
let val = spi_clk_config_from_div(div)?;
|
||||
self.spi_instance()
|
||||
pub fn cfg_clock(&mut self, cfg: SpiClkConfig) {
|
||||
self.spi
|
||||
.ctrl0()
|
||||
.modify(|_, w| unsafe { w.scrdv().bits(val.scrdv as u8) });
|
||||
self.spi_instance()
|
||||
.clkprescale()
|
||||
.write(|w| unsafe { w.bits(val.prescale_val as u32) });
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/*
|
||||
#[inline]
|
||||
pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
|
||||
let clk_prescale =
|
||||
self.apb1_clk.raw() / (spi_clk.into().raw() * (self.cfg.ser_clock_rate_div as u32 + 1));
|
||||
.modify(|_, w| unsafe { w.scrdv().bits(cfg.scrdv) });
|
||||
self.spi
|
||||
.clkprescale()
|
||||
.write(|w| unsafe { w.bits(clk_prescale) });
|
||||
.write(|w| unsafe { w.bits(cfg.prescale_val as u32) });
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError> {
|
||||
let val = spi_clk_config_from_div(div)?;
|
||||
self.cfg_clock(val);
|
||||
Ok(())
|
||||
}
|
||||
*/
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_mode(&mut self, mode: Mode) {
|
||||
@ -646,17 +652,17 @@ where
|
||||
|
||||
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiInstance>>(
|
||||
&mut self,
|
||||
transfer_cfg: &TransferConfig<HwCs>,
|
||||
transfer_cfg: &TransferConfigWithHwcs<HwCs>,
|
||||
) -> Result<(), SpiClkConfigError> {
|
||||
if let Some(trans_clk_div) = transfer_cfg.clk_div {
|
||||
self.cfg_clock_from_div(trans_clk_div)?;
|
||||
if let Some(trans_clk_div) = transfer_cfg.cfg.clk_cfg {
|
||||
self.cfg_clock(trans_clk_div);
|
||||
}
|
||||
if let Some(mode) = transfer_cfg.mode {
|
||||
if let Some(mode) = transfer_cfg.cfg.mode {
|
||||
self.cfg_mode(mode);
|
||||
}
|
||||
self.blockmode = transfer_cfg.blockmode;
|
||||
self.blockmode = transfer_cfg.cfg.blockmode;
|
||||
self.spi.ctrl1().modify(|_, w| {
|
||||
if transfer_cfg.sod {
|
||||
if transfer_cfg.cfg.sod {
|
||||
w.sod().set_bit();
|
||||
} else if transfer_cfg.hw_cs.is_some() {
|
||||
w.sod().clear_bit();
|
||||
@ -666,7 +672,7 @@ where
|
||||
} else {
|
||||
w.sod().clear_bit();
|
||||
}
|
||||
if transfer_cfg.blockmode {
|
||||
if transfer_cfg.cfg.blockmode {
|
||||
w.blockmode().set_bit();
|
||||
} else {
|
||||
w.blockmode().clear_bit();
|
||||
@ -676,6 +682,19 @@ where
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn flush_internal(&self) {
|
||||
let mut status_reg = self.spi.status().read();
|
||||
while status_reg.tfe().bit_is_clear()
|
||||
|| status_reg.rne().bit_is_set()
|
||||
|| status_reg.busy().bit_is_set()
|
||||
{
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.read_single_word();
|
||||
}
|
||||
status_reg = self.spi.status().read();
|
||||
}
|
||||
}
|
||||
|
||||
/// Sends a word to the slave
|
||||
#[inline(always)]
|
||||
fn send_blocking(&self, word: Word) {
|
||||
@ -708,30 +727,35 @@ where
|
||||
if words.is_empty() {
|
||||
return Ok(());
|
||||
}
|
||||
let mut status_reg = self.spi.status().read();
|
||||
// Wait until all bytes have been transferred.
|
||||
while status_reg.tfe().bit_is_clear() {
|
||||
// Ignore all received read words.
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.clear_rx_fifo();
|
||||
}
|
||||
status_reg = self.spi.status().read();
|
||||
}
|
||||
// Ignore all received read words.
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.clear_rx_fifo();
|
||||
}
|
||||
self.flush_internal();
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn initial_send_fifo_pumping(&self, words: Option<&[Word]>) -> usize {
|
||||
// Returns the actual bytes sent.
|
||||
fn initial_send_fifo_pumping_with_words(&self, words: &[Word]) -> usize {
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
|
||||
}
|
||||
// Fill the first half of the write FIFO
|
||||
let mut current_write_idx = 0;
|
||||
for _ in 0..core::cmp::min(FILL_DEPTH, words.map_or(0, |words| words.len())) {
|
||||
self.send_blocking(words.map_or(self.fill_word, |words| words[current_write_idx]));
|
||||
for _ in 0..core::cmp::min(FILL_DEPTH, words.len()) {
|
||||
self.send_blocking(words[current_write_idx]);
|
||||
current_write_idx += 1;
|
||||
}
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().clear_bit())
|
||||
}
|
||||
current_write_idx
|
||||
}
|
||||
|
||||
fn initial_send_fifo_pumping_with_fill_words(&self, send_len: usize) -> usize {
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
|
||||
}
|
||||
// Fill the first half of the write FIFO
|
||||
let mut current_write_idx = 0;
|
||||
for _ in 0..core::cmp::min(FILL_DEPTH, send_len) {
|
||||
self.send_blocking(self.fill_word);
|
||||
current_write_idx += 1;
|
||||
}
|
||||
if self.blockmode {
|
||||
@ -772,13 +796,13 @@ where
|
||||
spi: SpiI,
|
||||
pins: (Sck, Miso, Mosi),
|
||||
spi_cfg: SpiConfig,
|
||||
transfer_cfg: Option<&ErasedTransferConfig>,
|
||||
transfer_cfg: Option<&TransferConfig>,
|
||||
) -> Result<Self, SpiClkConfigError> {
|
||||
crate::clock::enable_peripheral_clock(syscfg, SpiI::PERIPH_SEL);
|
||||
// This is done in the C HAL.
|
||||
syscfg.assert_periph_reset_for_two_cycles(SpiI::PERIPH_SEL);
|
||||
let SpiConfig {
|
||||
clk_div,
|
||||
clk,
|
||||
ms,
|
||||
slave_output_disable,
|
||||
loopback_mode,
|
||||
@ -792,19 +816,17 @@ where
|
||||
if let Some(mode) = transfer_cfg.mode {
|
||||
init_mode = mode;
|
||||
}
|
||||
//self.cfg_clock_from_div(transfer_cfg.clk_div);
|
||||
if transfer_cfg.hw_cs != HwChipSelectId::Invalid {
|
||||
ss = transfer_cfg.hw_cs as u8;
|
||||
}
|
||||
init_blockmode = transfer_cfg.blockmode;
|
||||
}
|
||||
|
||||
let spi_clk_cfg = spi_clk_config_from_div(clk_div)?;
|
||||
let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(init_mode);
|
||||
spi.ctrl0().write(|w| {
|
||||
unsafe {
|
||||
w.size().bits(Word::word_reg());
|
||||
w.scrdv().bits(spi_clk_cfg.scrdv);
|
||||
w.scrdv().bits(clk.scrdv);
|
||||
// Clear clock phase and polarity. Will be set to correct value for each
|
||||
// transfer
|
||||
w.spo().bit(cpo_bit);
|
||||
@ -820,7 +842,7 @@ where
|
||||
unsafe { w.ss().bits(ss) }
|
||||
});
|
||||
spi.clkprescale()
|
||||
.write(|w| unsafe { w.bits(spi_clk_cfg.prescale_val as u32) });
|
||||
.write(|w| unsafe { w.bits(clk.prescale_val as u32) });
|
||||
|
||||
spi.fifo_clr().write(|w| {
|
||||
w.rxfifo().set_bit();
|
||||
@ -844,6 +866,9 @@ where
|
||||
|
||||
delegate::delegate! {
|
||||
to self.inner {
|
||||
#[inline]
|
||||
pub fn cfg_clock(&mut self, cfg: SpiClkConfig);
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError>;
|
||||
|
||||
@ -857,7 +882,7 @@ where
|
||||
pub fn perid(&self) -> u32;
|
||||
|
||||
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiI>>(
|
||||
&mut self, transfer_cfg: &TransferConfig<HwCs>
|
||||
&mut self, transfer_cfg: &TransferConfigWithHwcs<HwCs>
|
||||
) -> Result<(), SpiClkConfigError>;
|
||||
}
|
||||
}
|
||||
@ -941,7 +966,7 @@ where
|
||||
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(None);
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_fill_words(words.len());
|
||||
loop {
|
||||
if current_write_idx < words.len() {
|
||||
self.send_blocking(self.fill_word);
|
||||
@ -960,7 +985,7 @@ where
|
||||
|
||||
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(Some(words));
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
|
||||
while current_write_idx < words.len() {
|
||||
self.send_blocking(words[current_write_idx]);
|
||||
current_write_idx += 1;
|
||||
@ -975,7 +1000,7 @@ where
|
||||
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(write)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(Some(write));
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(write);
|
||||
while current_read_idx < read.len() || current_write_idx < write.len() {
|
||||
if current_write_idx < write.len() {
|
||||
self.send_blocking(write[current_write_idx]);
|
||||
@ -993,7 +1018,7 @@ where
|
||||
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||
self.transfer_preparation(words)?;
|
||||
let mut current_read_idx = 0;
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping(Some(words));
|
||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
|
||||
|
||||
while current_read_idx < words.len() || current_write_idx < words.len() {
|
||||
if current_write_idx < words.len() {
|
||||
@ -1009,12 +1034,7 @@ where
|
||||
}
|
||||
|
||||
fn flush(&mut self) -> Result<(), Self::Error> {
|
||||
let status_reg = self.spi.status().read();
|
||||
while status_reg.tfe().bit_is_clear() || status_reg.rne().bit_is_set() {
|
||||
if status_reg.rne().bit_is_set() {
|
||||
self.read_single_word();
|
||||
}
|
||||
}
|
||||
self.flush_internal();
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user