Device specific support and UART Improvements
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@ -10,6 +10,7 @@
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//! # Examples
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//!
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//! - [UART example on the PEB1 board](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs)
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#[cfg(not(feature = "va41628"))]
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use crate::adc::ADC_MAX_CLK;
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use crate::pac;
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@ -447,11 +448,22 @@ impl ClkgenCfgr {
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.ctrl0()
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.modify(|_, w| unsafe { w.clksel_sys().bits(self.clksel_sys as u8) });
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Ok(Clocks {
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sysclk: final_sysclk,
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apb1: final_sysclk / 2,
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apb2: final_sysclk / 4,
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#[cfg(not(feature = "va41628"))]
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adc_clk: self.cfg_adc_clk_div(final_sysclk),
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})
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}
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#[cfg(not(feature = "va41628"))]
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fn cfg_adc_clk_div(&self, final_sysclk: Hertz) -> Hertz {
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// I will just do the ADC stuff like Vorago does it.
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// ADC clock (must be 2-12.5 MHz)
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// NOTE: Not using divide by 1 or /2 ratio in REVA silicon because of triggering issue
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// For this reason, keep SYSCLK above 8MHz to have the ADC /4 ratio in range)
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let adc_clk = if final_sysclk.raw() <= ADC_MAX_CLK.raw() * 4 {
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if final_sysclk.raw() <= ADC_MAX_CLK.raw() * 4 {
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self.clkgen
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.ctrl1()
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.modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div4 as u8) });
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@ -461,14 +473,7 @@ impl ClkgenCfgr {
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.ctrl1()
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.modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div8 as u8) });
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final_sysclk / 8
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};
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Ok(Clocks {
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sysclk: final_sysclk,
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apb1: final_sysclk / 2,
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apb2: final_sysclk / 4,
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adc_clk,
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})
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}
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}
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}
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@ -483,6 +488,7 @@ pub struct Clocks {
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sysclk: Hertz,
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apb1: Hertz,
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apb2: Hertz,
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#[cfg(not(feature = "va41628"))]
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adc_clk: Hertz,
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}
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@ -513,6 +519,7 @@ impl Clocks {
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}
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/// Returns the ADC clock frequency which has a separate divider.
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#[cfg(not(feature = "va41628"))]
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pub fn adc_clk(&self) -> Hertz {
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self.adc_clk
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}
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@ -295,12 +295,17 @@ pub trait PinId: Sealed {
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}
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macro_rules! pin_id {
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($Group:ident, $Id:ident, $NUM:literal) => {
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($Group:ident, $Id:ident, $NUM:literal $(, $meta: meta)?) => {
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// Need paste macro to use ident in doc attribute
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paste::paste! {
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$(#[$meta])?
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#[doc = "Pin ID representing pin " $Id]
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pub enum $Id {}
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$(#[$meta])?
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impl Sealed for $Id {}
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$(#[$meta])?
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impl PinId for $Id {
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const DYN: DynPinId = DynPinId {
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group: DynGroup::$Group,
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@ -689,13 +694,14 @@ impl<I: PinId> Registers<I> {
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macro_rules! pins {
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(
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$Port:ident, $PinsName:ident, $($Id:ident,)+,
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$Port:ident, $PinsName:ident, $($Id:ident $(, $meta:meta)?)+,
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) => {
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paste::paste!(
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/// Collection of all the individual [`Pin`]s for a given port (PORTA or PORTB)
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pub struct $PinsName {
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port: $Port,
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$(
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$(#[$meta])?
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#[doc = "Pin " $Id]
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pub [<$Id:lower>]: Pin<$Id, Reset>,
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)+
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@ -718,6 +724,7 @@ macro_rules! pins {
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port,
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// Safe because we only create one `Pin` per `PinId`
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$(
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$(#[$meta])?
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[<$Id:lower>]: unsafe { Pin::new() },
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)+
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}
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@ -739,13 +746,15 @@ macro_rules! pins {
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}
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}
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//$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal $(, $meta:meta)?)),+]
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//$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal, $meta: meta),)+]
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macro_rules! declare_pins {
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(
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$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal),)+]
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$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal $(, $meta:meta)?)),+]
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) => {
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pins!($Port, $PinsName, $($Id,)+,);
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pins!($Port, $PinsName, $($Id $(, $meta)?)+,);
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$(
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pin_id!($Group, $Id, $NUM);
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pin_id!($Group, $Id, $NUM $(, $meta)?);
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)+
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}
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}
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@ -770,7 +779,7 @@ declare_pins!(
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(PA12, 12),
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(PA13, 13),
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(PA14, 14),
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(PA15, 15),
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(PA15, 15)
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]
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);
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@ -784,17 +793,17 @@ declare_pins!(
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(PB2, 2),
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(PB3, 3),
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(PB4, 4),
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(PB5, 5),
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(PB6, 6),
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(PB7, 7),
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(PB8, 8),
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(PB9, 9),
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(PB10, 10),
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(PB11, 11),
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(PB5, 5, cfg(not(feature = "va41628"))),
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(PB6, 6, cfg(not(feature = "va41628"))),
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(PB7, 7, cfg(not(feature = "va41628"))),
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(PB8, 8, cfg(not(feature = "va41628"))),
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(PB9, 9, cfg(not(feature = "va41628"))),
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(PB10, 10, cfg(not(feature = "va41628"))),
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(PB11, 11, cfg(not(feature = "va41628"))),
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(PB12, 12),
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(PB13, 13),
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(PB14, 14),
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(PB15, 15),
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(PB15, 15)
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]
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);
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@ -816,9 +825,9 @@ declare_pins!(
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(PC10, 10),
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(PC11, 11),
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(PC12, 12),
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(PC13, 13),
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(PC13, 13, cfg(not(feature = "va41628"))),
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(PC14, 14),
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(PC15, 15),
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(PC15, 15, cfg(not(feature = "va41628")))
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]
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);
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@ -827,22 +836,22 @@ declare_pins!(
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PinsD,
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Portd,
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[
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(PD0, 0),
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(PD1, 1),
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(PD2, 2),
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(PD3, 3),
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(PD4, 4),
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(PD5, 5),
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(PD6, 6),
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(PD7, 7),
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(PD8, 8),
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(PD9, 9),
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(PD0, 0, cfg(not(feature = "va41628"))),
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(PD1, 1, cfg(not(feature = "va41628"))),
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(PD2, 2, cfg(not(feature = "va41628"))),
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(PD3, 3, cfg(not(feature = "va41628"))),
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(PD4, 4, cfg(not(feature = "va41628"))),
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(PD5, 5, cfg(not(feature = "va41628"))),
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(PD6, 6, cfg(not(feature = "va41628"))),
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(PD7, 7, cfg(not(feature = "va41628"))),
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(PD8, 8, cfg(not(feature = "va41628"))),
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(PD9, 9, cfg(not(feature = "va41628"))),
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(PD10, 10),
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(PD11, 11),
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(PD12, 12),
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(PD13, 13),
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(PD14, 14),
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(PD15, 15),
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(PD15, 15)
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]
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);
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@ -861,12 +870,12 @@ declare_pins!(
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(PE7, 7),
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(PE8, 8),
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(PE9, 9),
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(PE10, 10),
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(PE11, 11),
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(PE10, 10, cfg(not(feature = "va41628"))),
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(PE11, 11, cfg(not(feature = "va41628"))),
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(PE12, 12),
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(PE13, 13),
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(PE14, 14),
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(PE15, 15),
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(PE15, 15)
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]
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);
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@ -877,20 +886,20 @@ declare_pins!(
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[
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(PF0, 0),
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(PF1, 1),
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(PF2, 2),
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(PF3, 3),
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(PF4, 4),
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(PF5, 5),
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(PF6, 6),
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(PF7, 7),
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(PF8, 8),
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(PF2, 2, cfg(not(feature = "va41628"))),
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(PF3, 3, cfg(not(feature = "va41628"))),
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(PF4, 4, cfg(not(feature = "va41628"))),
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(PF5, 5, cfg(not(feature = "va41628"))),
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(PF6, 6, cfg(not(feature = "va41628"))),
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(PF7, 7, cfg(not(feature = "va41628"))),
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(PF8, 8, cfg(not(feature = "va41628"))),
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(PF9, 9),
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(PF10, 10),
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(PF10, 10, cfg(not(feature = "va41628"))),
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(PF11, 11),
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(PF12, 12),
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(PF13, 13),
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(PF14, 14),
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(PF15, 15),
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(PF15, 15)
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]
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);
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@ -906,6 +915,6 @@ declare_pins!(
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(PG4, 4),
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(PG5, 5),
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(PG6, 6),
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(PG7, 7),
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(PG7, 7)
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]
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);
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@ -3,14 +3,21 @@
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#[cfg(test)]
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extern crate std;
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#[cfg(not(feature = "device-selected"))]
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compile_error!(
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"This crate requires one of the following device features enabled:
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va41630
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va41629
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va41628
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"
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);
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pub use va416xx as device;
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pub use va416xx as pac;
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pub mod prelude;
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pub mod adc;
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pub mod clock;
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pub mod dac;
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pub mod dma;
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pub mod gpio;
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pub mod i2c;
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@ -22,6 +29,11 @@ pub mod typelevel;
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pub mod uart;
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pub mod wdt;
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#[cfg(not(feature = "va41628"))]
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pub mod adc;
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#[cfg(not(feature = "va41628"))]
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pub mod dac;
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#[derive(Debug, Eq, Copy, Clone, PartialEq)]
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pub enum FunSel {
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Sel0 = 0b00,
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@ -11,15 +11,17 @@ use crate::{
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clock::{PeripheralSelect, SyscfgExt},
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gpio::{
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AltFunc1, AltFunc2, AltFunc3, Pin, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PB0,
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PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PC0, PC1,
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PC10, PC11, PC7, PC8, PC9, PE10, PE11, PE12, PE13, PE14, PE15, PE5, PE6, PE7, PE8, PE9,
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PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PG2, PG3, PG4,
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PB1, PB12, PB13, PB14, PB15, PB2, PB3, PB4, PC0, PC1, PC10, PC11, PC7, PC8, PC9, PE12,
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PE13, PE14, PE15, PE5, PE6, PE7, PE8, PE9, PF0, PF1, PG2, PG3, PG4,
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},
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pac,
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time::Hertz,
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typelevel::{NoneT, Sealed},
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};
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#[cfg(not(feature = "va41628"))]
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use crate::gpio::{PB10, PB11, PB5, PB6, PB7, PB8, PB9, PE10, PE11, PF2, PF3, PF4, PF5, PF6, PF7};
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//==================================================================================================
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// Defintions
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//==================================================================================================
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@ -75,15 +77,20 @@ pub trait OptionalHwCs<Spi>: HwCsProvider + Sealed {}
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macro_rules! hw_cs_pins {
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($SPIx:path, $portId: path:
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$(
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($PXx:ident, $AFx:ident, $HwCsIdent:path, $typedef:ident),
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($PXx:ident, $AFx:ident, $HwCsIdent:path, $typedef:ident $(, $meta: meta)?),
|
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)+
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) => {
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$(
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$(#[$meta])?
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impl HwCsProvider for Pin<$PXx, $AFx> {
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const CS_ID: HwChipSelectId = $HwCsIdent;
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const SPI_ID: SpiId = $portId;
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}
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$(#[$meta])?
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impl OptionalHwCs<$SPIx> for Pin<$PXx, $AFx> {}
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$(#[$meta])?
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pub type $typedef = Pin<$PXx, $AFx>;
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)+
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};
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@ -106,9 +113,11 @@ impl PinMosi<pac::Spi0> for Pin<PC1, AltFunc1> {}
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impl PinMiso<pac::Spi0> for Pin<PC0, AltFunc1> {}
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// SPI 1
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#[cfg(not(feature = "va41628"))]
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impl PinSck<pac::Spi1> for Pin<PB8, AltFunc3> {}
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#[cfg(not(feature = "va41628"))]
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impl PinMosi<pac::Spi1> for Pin<PB10, AltFunc3> {}
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#[cfg(not(feature = "va41628"))]
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impl PinMiso<pac::Spi1> for Pin<PB9, AltFunc3> {}
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impl PinSck<pac::Spi1> for Pin<PC9, AltFunc2> {}
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@ -122,8 +131,11 @@ impl PinSck<pac::Spi1> for Pin<PE13, AltFunc2> {}
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impl PinMosi<pac::Spi1> for Pin<PE15, AltFunc2> {}
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impl PinMiso<pac::Spi1> for Pin<PE14, AltFunc2> {}
|
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#[cfg(not(feature = "va41628"))]
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impl PinSck<pac::Spi1> for Pin<PF3, AltFunc1> {}
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#[cfg(not(feature = "va41628"))]
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impl PinMosi<pac::Spi1> for Pin<PF5, AltFunc1> {}
|
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#[cfg(not(feature = "va41628"))]
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impl PinMiso<pac::Spi1> for Pin<PF4, AltFunc1> {}
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|
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// SPI 2
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@ -132,8 +144,11 @@ impl PinSck<pac::Spi2> for Pin<PA5, AltFunc2> {}
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impl PinMosi<pac::Spi2> for Pin<PA7, AltFunc2> {}
|
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impl PinMiso<pac::Spi2> for Pin<PA6, AltFunc2> {}
|
||||
|
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#[cfg(not(feature = "va41628"))]
|
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impl PinSck<pac::Spi2> for Pin<PF5, AltFunc2> {}
|
||||
#[cfg(not(feature = "va41628"))]
|
||||
impl PinMosi<pac::Spi2> for Pin<PF7, AltFunc2> {}
|
||||
#[cfg(not(feature = "va41628"))]
|
||||
impl PinMiso<pac::Spi2> for Pin<PF6, AltFunc2> {}
|
||||
|
||||
// SPI3 is shared with the ROM SPI pins and has its own dedicated pins.
|
||||
@ -145,14 +160,14 @@ hw_cs_pins!(
|
||||
(PB14, AltFunc1, HwChipSelectId::Id0, HwCs0Spi0),
|
||||
(PB13, AltFunc1, HwChipSelectId::Id1, HwCs1Spi0),
|
||||
(PB12, AltFunc1, HwChipSelectId::Id2, HwCs2Spi0),
|
||||
(PB11, AltFunc1, HwChipSelectId::Id3, HwCs3Spi0),
|
||||
(PB11, AltFunc1, HwChipSelectId::Id3, HwCs3Spi0, cfg(not(feature="va41628"))),
|
||||
);
|
||||
|
||||
hw_cs_pins!(
|
||||
pac::Spi1, SpiId::Spi1:
|
||||
(PB7, AltFunc3, HwChipSelectId::Id0, HwCs0Spi1Pb),
|
||||
(PB6, AltFunc3, HwChipSelectId::Id1, HwCs1Spi1Pb),
|
||||
(PB5, AltFunc3, HwChipSelectId::Id2, HwCs2Spi1Pb),
|
||||
(PB7, AltFunc3, HwChipSelectId::Id0, HwCs0Spi1Pb, cfg(not(feature="va41628"))),
|
||||
(PB6, AltFunc3, HwChipSelectId::Id1, HwCs1Spi1Pb, cfg(not(feature="va41628"))),
|
||||
(PB5, AltFunc3, HwChipSelectId::Id2, HwCs2Spi1Pb, cfg(not(feature="va41628"))),
|
||||
(PB4, AltFunc3, HwChipSelectId::Id3, HwCs3Spi1Pb),
|
||||
(PB3, AltFunc3, HwChipSelectId::Id4, HwCs4Spi1Pb),
|
||||
(PB2, AltFunc3, HwChipSelectId::Id5, HwCs5Spi1Pb),
|
||||
@ -161,14 +176,14 @@ hw_cs_pins!(
|
||||
(PC8, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pc),
|
||||
(PC7, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pc),
|
||||
(PE12, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pe),
|
||||
(PE11, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pe),
|
||||
(PE10, AltFunc2, HwChipSelectId::Id2, HwCs2Spi1Pe),
|
||||
(PE11, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pe, cfg(not(feature="va41628"))),
|
||||
(PE10, AltFunc2, HwChipSelectId::Id2, HwCs2Spi1Pe, cfg(not(feature="va41628"))),
|
||||
(PE9, AltFunc2, HwChipSelectId::Id3, HwCs3Spi1Pe),
|
||||
(PE8, AltFunc2, HwChipSelectId::Id4, HwCs4Spi1Pe),
|
||||
(PE7, AltFunc3, HwChipSelectId::Id5, HwCs5Spi1Pe),
|
||||
(PE6, AltFunc3, HwChipSelectId::Id6, HwCs6Spi1Pe),
|
||||
(PE5, AltFunc3, HwChipSelectId::Id7, HwCs7Spi1Pe),
|
||||
(PF2, AltFunc1, HwChipSelectId::Id0, HwCs0Spi1Pf),
|
||||
(PF2, AltFunc1, HwChipSelectId::Id0, HwCs0Spi1Pf, cfg(not(feature="va41628"))),
|
||||
(PG2, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pg),
|
||||
);
|
||||
|
||||
@ -183,9 +198,9 @@ hw_cs_pins!(
|
||||
(PA9, AltFunc2, HwChipSelectId::Id5, HwCs5Spi2Pa),
|
||||
(PF0, AltFunc2, HwChipSelectId::Id4, HwCs4Spi2Pf),
|
||||
(PF1, AltFunc2, HwChipSelectId::Id3, HwCs3Spi2Pf),
|
||||
(PF2, AltFunc2, HwChipSelectId::Id2, HwCs2Spi2Pf),
|
||||
(PF3, AltFunc2, HwChipSelectId::Id1, HwCs1Spi2Pf),
|
||||
(PF4, AltFunc2, HwChipSelectId::Id0, HwCs0Spi2Pf),
|
||||
(PF2, AltFunc2, HwChipSelectId::Id2, HwCs2Spi2Pf, cfg(not(feature="va41628"))),
|
||||
(PF3, AltFunc2, HwChipSelectId::Id1, HwCs1Spi2Pf, cfg(not(feature="va41628"))),
|
||||
(PF4, AltFunc2, HwChipSelectId::Id0, HwCs0Spi2Pf, cfg(not(feature="va41628"))),
|
||||
);
|
||||
|
||||
//==================================================================================================
|
||||
|
||||
@ -10,12 +10,17 @@ use cortex_m::interrupt::Mutex;
|
||||
use crate::clock::Clocks;
|
||||
use crate::gpio::{
|
||||
AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14,
|
||||
PA15, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB2, PB3,
|
||||
PB4, PB5, PB6, PB7, PB8, PB9, PC0, PC1, PD0, PD1, PD10, PD11, PD12, PD13, PD14, PD15, PD2, PD3,
|
||||
PD4, PD5, PD6, PD7, PD8, PD9, PE0, PE1, PE10, PE11, PE12, PE13, PE14, PE15, PE2, PE3, PE4, PE5,
|
||||
PE6, PE7, PE8, PE9, PF0, PF1, PF10, PF11, PF12, PF13, PF14, PF15, PF2, PF3, PF4, PF5, PF6, PF7,
|
||||
PF8, PF9, PG0, PG1, PG2, PG3, PG6,
|
||||
PA15, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PB12, PB13, PB14, PB15, PB2, PB3, PB4, PC0, PC1,
|
||||
PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE12, PE13, PE14, PE15, PE2, PE3, PE4, PE5, PE6,
|
||||
PE7, PE8, PE9, PF0, PF1, PF11, PF12, PF13, PF14, PF15, PF9, PG0, PG1, PG2, PG3, PG6,
|
||||
};
|
||||
|
||||
#[cfg(not(feature = "va41628"))]
|
||||
use crate::gpio::{
|
||||
PB10, PB11, PB5, PB6, PB7, PB8, PB9, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PE10,
|
||||
PE11, PF10, PF2, PF3, PF4, PF5, PF6, PF7, PF8,
|
||||
};
|
||||
|
||||
use crate::time::Hertz;
|
||||
use crate::typelevel::Sealed;
|
||||
use crate::{disable_interrupt, prelude::*};
|
||||
@ -196,10 +201,11 @@ pub trait ValidTimAndPin<Pin: TimPin, Tim: ValidTim>: Sealed {}
|
||||
macro_rules! valid_pin_and_tims {
|
||||
(
|
||||
$(
|
||||
($PinX:ident, $AltFunc:ident, $TimX:path),
|
||||
($PinX:ident, $AltFunc:ident, $TimX:path $(, $meta: meta)?),
|
||||
)+
|
||||
) => {
|
||||
$(
|
||||
$(#[$meta])?
|
||||
impl TimPin for Pin<$PinX, $AltFunc>
|
||||
where
|
||||
$PinX: PinId,
|
||||
@ -207,6 +213,7 @@ macro_rules! valid_pin_and_tims {
|
||||
const DYN: DynPinId = $PinX::DYN;
|
||||
}
|
||||
|
||||
$(#[$meta])?
|
||||
impl<
|
||||
PinInstance: TimPin,
|
||||
Tim: ValidTim
|
||||
@ -217,6 +224,7 @@ macro_rules! valid_pin_and_tims {
|
||||
{
|
||||
}
|
||||
|
||||
$(#[$meta])?
|
||||
impl Sealed for (Pin<$PinX, $AltFunc>, $TimX) {}
|
||||
)+
|
||||
};
|
||||
@ -242,29 +250,29 @@ valid_pin_and_tims!(
|
||||
(PB2, AltFunc2, pac::Tim15),
|
||||
(PB3, AltFunc2, pac::Tim14),
|
||||
(PB4, AltFunc2, pac::Tim13),
|
||||
(PB5, AltFunc2, pac::Tim12),
|
||||
(PB6, AltFunc2, pac::Tim11),
|
||||
(PB7, AltFunc2, pac::Tim10),
|
||||
(PB8, AltFunc2, pac::Tim9),
|
||||
(PB9, AltFunc2, pac::Tim8),
|
||||
(PB10, AltFunc2, pac::Tim7),
|
||||
(PB11, AltFunc2, pac::Tim6),
|
||||
(PB5, AltFunc2, pac::Tim12, cfg(not(feature = "va41628"))),
|
||||
(PB6, AltFunc2, pac::Tim11, cfg(not(feature = "va41628"))),
|
||||
(PB7, AltFunc2, pac::Tim10, cfg(not(feature = "va41628"))),
|
||||
(PB8, AltFunc2, pac::Tim9, cfg(not(feature = "va41628"))),
|
||||
(PB9, AltFunc2, pac::Tim8, cfg(not(feature = "va41628"))),
|
||||
(PB10, AltFunc2, pac::Tim7, cfg(not(feature = "va41628"))),
|
||||
(PB11, AltFunc2, pac::Tim6, cfg(not(feature = "va41628"))),
|
||||
(PB12, AltFunc2, pac::Tim5),
|
||||
(PB13, AltFunc2, pac::Tim4),
|
||||
(PB14, AltFunc2, pac::Tim3),
|
||||
(PB15, AltFunc2, pac::Tim2),
|
||||
(PC0, AltFunc2, pac::Tim1),
|
||||
(PC1, AltFunc2, pac::Tim0),
|
||||
(PD0, AltFunc2, pac::Tim0),
|
||||
(PD1, AltFunc2, pac::Tim1),
|
||||
(PD2, AltFunc2, pac::Tim2),
|
||||
(PD3, AltFunc2, pac::Tim3),
|
||||
(PD4, AltFunc2, pac::Tim4),
|
||||
(PD5, AltFunc2, pac::Tim5),
|
||||
(PD6, AltFunc2, pac::Tim6),
|
||||
(PD7, AltFunc2, pac::Tim7),
|
||||
(PD8, AltFunc2, pac::Tim8),
|
||||
(PD9, AltFunc2, pac::Tim9),
|
||||
(PD0, AltFunc2, pac::Tim0, cfg(not(feature = "va41628"))),
|
||||
(PD1, AltFunc2, pac::Tim1, cfg(not(feature = "va41628"))),
|
||||
(PD2, AltFunc2, pac::Tim2, cfg(not(feature = "va41628"))),
|
||||
(PD3, AltFunc2, pac::Tim3, cfg(not(feature = "va41628"))),
|
||||
(PD4, AltFunc2, pac::Tim4, cfg(not(feature = "va41628"))),
|
||||
(PD5, AltFunc2, pac::Tim5, cfg(not(feature = "va41628"))),
|
||||
(PD6, AltFunc2, pac::Tim6, cfg(not(feature = "va41628"))),
|
||||
(PD7, AltFunc2, pac::Tim7, cfg(not(feature = "va41628"))),
|
||||
(PD8, AltFunc2, pac::Tim8, cfg(not(feature = "va41628"))),
|
||||
(PD9, AltFunc2, pac::Tim9, cfg(not(feature = "va41628"))),
|
||||
(PD10, AltFunc2, pac::Tim10),
|
||||
(PD11, AltFunc2, pac::Tim11),
|
||||
(PD12, AltFunc2, pac::Tim12),
|
||||
@ -281,23 +289,23 @@ valid_pin_and_tims!(
|
||||
(PE7, AltFunc2, pac::Tim23),
|
||||
(PE8, AltFunc3, pac::Tim16),
|
||||
(PE9, AltFunc3, pac::Tim17),
|
||||
(PE10, AltFunc3, pac::Tim18),
|
||||
(PE11, AltFunc3, pac::Tim19),
|
||||
(PE10, AltFunc3, pac::Tim18, cfg(not(feature = "va41628"))),
|
||||
(PE11, AltFunc3, pac::Tim19, cfg(not(feature = "va41628"))),
|
||||
(PE12, AltFunc3, pac::Tim20),
|
||||
(PE13, AltFunc3, pac::Tim21),
|
||||
(PE14, AltFunc3, pac::Tim22),
|
||||
(PE15, AltFunc3, pac::Tim23),
|
||||
(PF0, AltFunc3, pac::Tim0),
|
||||
(PF1, AltFunc3, pac::Tim1),
|
||||
(PF2, AltFunc3, pac::Tim2),
|
||||
(PF3, AltFunc3, pac::Tim3),
|
||||
(PF4, AltFunc3, pac::Tim4),
|
||||
(PF5, AltFunc3, pac::Tim5),
|
||||
(PF6, AltFunc3, pac::Tim6),
|
||||
(PF7, AltFunc3, pac::Tim7),
|
||||
(PF8, AltFunc3, pac::Tim8),
|
||||
(PF2, AltFunc3, pac::Tim2, cfg(not(feature = "va41628"))),
|
||||
(PF3, AltFunc3, pac::Tim3, cfg(not(feature = "va41628"))),
|
||||
(PF4, AltFunc3, pac::Tim4, cfg(not(feature = "va41628"))),
|
||||
(PF5, AltFunc3, pac::Tim5, cfg(not(feature = "va41628"))),
|
||||
(PF6, AltFunc3, pac::Tim6, cfg(not(feature = "va41628"))),
|
||||
(PF7, AltFunc3, pac::Tim7, cfg(not(feature = "va41628"))),
|
||||
(PF8, AltFunc3, pac::Tim8, cfg(not(feature = "va41628"))),
|
||||
(PF9, AltFunc3, pac::Tim9),
|
||||
(PF10, AltFunc3, pac::Tim10),
|
||||
(PF10, AltFunc3, pac::Tim10, cfg(not(feature = "va41628"))),
|
||||
(PF11, AltFunc3, pac::Tim11),
|
||||
(PF12, AltFunc3, pac::Tim12),
|
||||
(PF13, AltFunc2, pac::Tim19),
|
||||
|
||||
@ -10,31 +10,55 @@ use embedded_hal_nb::serial::Read;
|
||||
use fugit::RateExtU32;
|
||||
|
||||
use crate::clock::{Clocks, PeripheralSelect, SyscfgExt};
|
||||
use crate::gpio::{AltFunc1, Pin, PD11, PD12, PE2, PE3, PF11, PF12, PF8, PF9, PG0, PG1};
|
||||
use crate::gpio::PF13;
|
||||
use crate::time::Hertz;
|
||||
use crate::{disable_interrupt, enable_interrupt};
|
||||
use crate::{
|
||||
gpio::{AltFunc2, AltFunc3, PA2, PA3, PB14, PB15, PC14, PC15, PC4, PC5},
|
||||
gpio::{
|
||||
AltFunc1, AltFunc2, AltFunc3, Pin, PA2, PA3, PB14, PB15, PC14, PC4, PC5, PD11, PD12, PE2,
|
||||
PE3, PF12, PF9, PG0, PG1,
|
||||
},
|
||||
pac::{self, uart0 as uart_base, Uart0, Uart1, Uart2},
|
||||
};
|
||||
|
||||
#[cfg(not(feature = "va41628"))]
|
||||
use crate::gpio::{PC15, PF8};
|
||||
|
||||
//==================================================================================================
|
||||
// Type-Level support
|
||||
//==================================================================================================
|
||||
|
||||
pub trait TxRxPins<Uart> {}
|
||||
pub trait RxPin<Uart> {}
|
||||
pub trait TxPin<Uart> {}
|
||||
|
||||
impl TxRxPins<Uart0> for (Pin<PA2, AltFunc3>, Pin<PA3, AltFunc3>) {}
|
||||
impl TxRxPins<Uart0> for (Pin<PC4, AltFunc2>, Pin<PC5, AltFunc2>) {}
|
||||
impl TxRxPins<Uart0> for (Pin<PE2, AltFunc3>, Pin<PE3, AltFunc3>) {}
|
||||
impl TxRxPins<Uart0> for (Pin<PG0, AltFunc1>, Pin<PG1, AltFunc1>) {}
|
||||
impl TxPin<Uart0> for Pin<PA2, AltFunc3> {}
|
||||
impl RxPin<Uart0> for Pin<PA3, AltFunc3> {}
|
||||
|
||||
impl TxRxPins<Uart1> for (Pin<PB14, AltFunc3>, Pin<PB15, AltFunc3>) {}
|
||||
impl TxRxPins<Uart1> for (Pin<PD11, AltFunc3>, Pin<PD12, AltFunc3>) {}
|
||||
impl TxRxPins<Uart1> for (Pin<PF11, AltFunc1>, Pin<PF12, AltFunc1>) {}
|
||||
impl TxPin<Uart0> for Pin<PC4, AltFunc2> {}
|
||||
impl RxPin<Uart0> for Pin<PC5, AltFunc2> {}
|
||||
|
||||
impl TxRxPins<Uart2> for (Pin<PC14, AltFunc2>, Pin<PC15, AltFunc2>) {}
|
||||
impl TxRxPins<Uart2> for (Pin<PF8, AltFunc1>, Pin<PF9, AltFunc1>) {}
|
||||
impl TxPin<Uart0> for Pin<PE2, AltFunc3> {}
|
||||
impl RxPin<Uart0> for Pin<PE3, AltFunc3> {}
|
||||
|
||||
impl TxPin<Uart0> for Pin<PG0, AltFunc1> {}
|
||||
impl RxPin<Uart0> for Pin<PG1, AltFunc1> {}
|
||||
|
||||
impl TxPin<Uart1> for Pin<PB14, AltFunc3> {}
|
||||
impl RxPin<Uart1> for Pin<PB15, AltFunc3> {}
|
||||
|
||||
impl TxPin<Uart1> for Pin<PD11, AltFunc3> {}
|
||||
impl RxPin<Uart1> for Pin<PD12, AltFunc3> {}
|
||||
|
||||
impl TxPin<Uart1> for Pin<PF12, AltFunc1> {}
|
||||
impl RxPin<Uart1> for Pin<PF13, AltFunc1> {}
|
||||
|
||||
impl TxPin<Uart2> for Pin<PC14, AltFunc2> {}
|
||||
#[cfg(not(feature = "va41628"))]
|
||||
impl RxPin<Uart2> for Pin<PC15, AltFunc2> {}
|
||||
|
||||
#[cfg(not(feature = "va41628"))]
|
||||
impl TxPin<Uart2> for Pin<PF8, AltFunc1> {}
|
||||
impl RxPin<Uart2> for Pin<PF9, AltFunc1> {}
|
||||
|
||||
//==================================================================================================
|
||||
// Regular Definitions
|
||||
@ -511,10 +535,12 @@ impl<Uart: Instance> UartBase<Uart> {
|
||||
}
|
||||
}
|
||||
|
||||
impl<UartInstance: Instance, Pins> Uart<UartInstance, Pins> {
|
||||
impl<TxPinInst: TxPin<UartInstance>, RxPinInst: RxPin<UartInstance>, UartInstance: Instance>
|
||||
Uart<UartInstance, (TxPinInst, RxPinInst)>
|
||||
{
|
||||
pub fn new(
|
||||
uart: UartInstance,
|
||||
pins: Pins,
|
||||
pins: (TxPinInst, RxPinInst),
|
||||
config: impl Into<Config>,
|
||||
syscfg: &mut va416xx::Sysconfig,
|
||||
clocks: &Clocks,
|
||||
@ -535,7 +561,7 @@ impl<UartInstance: Instance, Pins> Uart<UartInstance, Pins> {
|
||||
|
||||
pub fn new_with_clock_freq(
|
||||
uart: UartInstance,
|
||||
pins: Pins,
|
||||
pins: (TxPinInst, RxPinInst),
|
||||
config: impl Into<Config>,
|
||||
syscfg: &mut va416xx::Sysconfig,
|
||||
clock: impl Into<Hertz>,
|
||||
@ -567,7 +593,7 @@ impl<UartInstance: Instance, Pins> Uart<UartInstance, Pins> {
|
||||
|
||||
/// If the IRQ capabilities of the peripheral are used, the UART needs to be converted
|
||||
/// with this function
|
||||
pub fn into_uart_with_irq(self) -> UartWithIrq<UartInstance, Pins> {
|
||||
pub fn into_uart_with_irq(self) -> UartWithIrq<UartInstance, (TxPinInst, RxPinInst)> {
|
||||
let (inner, pins) = self.downgrade_internal();
|
||||
UartWithIrq {
|
||||
pins,
|
||||
@ -608,7 +634,7 @@ impl<UartInstance: Instance, Pins> Uart<UartInstance, Pins> {
|
||||
}
|
||||
}
|
||||
|
||||
fn downgrade_internal(self) -> (UartBase<UartInstance>, Pins) {
|
||||
fn downgrade_internal(self) -> (UartBase<UartInstance>, (TxPinInst, RxPinInst)) {
|
||||
let base = UartBase {
|
||||
uart: self.inner.uart,
|
||||
tx: self.inner.tx,
|
||||
@ -625,7 +651,7 @@ impl<UartInstance: Instance, Pins> Uart<UartInstance, Pins> {
|
||||
}
|
||||
}
|
||||
|
||||
pub fn release(self) -> (UartInstance, Pins) {
|
||||
pub fn release(self) -> (UartInstance, (TxPinInst, RxPinInst)) {
|
||||
(self.inner.release(), self.pins)
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user