UART error handling update

This commit is contained in:
2025-03-07 17:02:46 +01:00
parent 016c421cb8
commit a3c6366e98
13 changed files with 104 additions and 141 deletions

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@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
# [unreleased]
# [v0.1.2] 2025-03-07
- Bump allowed HAL version to v0.5
# [v0.1.1] 2025-02-18
- Bump allowed HAL version to v0.4
@ -15,3 +19,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
# [v0.1.0] 2024-10-01
- Initial release
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.2...HEAD
[v0.1.2]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.1...vorago-peb1-v0.1.2
[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.0...vorago-peb1-v0.1.1
[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/tag/vorago-peb1-v0.1.0

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@ -16,7 +16,7 @@ cortex-m-rt = "0.7"
embedded-hal = "1"
lis2dh12 = { version = "0.7", features = ["out_f32"] }
va416xx-hal = { version = ">=0.3, <=0.4", features = ["va41630"] }
va416xx-hal = { version = ">=0.3, <=0.5", features = ["va41630"] }
[features]
rt = ["va416xx-hal/rt"]