UART error handling update
This commit is contained in:
@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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# [unreleased]
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# [v0.1.2] 2025-03-07
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- Bump allowed HAL version to v0.5
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# [v0.1.1] 2025-02-18
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- Bump allowed HAL version to v0.4
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@ -15,3 +19,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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# [v0.1.0] 2024-10-01
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- Initial release
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[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.2...HEAD
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[v0.1.2]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.1...vorago-peb1-v0.1.2
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[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.0...vorago-peb1-v0.1.1
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[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/tag/vorago-peb1-v0.1.0
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@ -16,7 +16,7 @@ cortex-m-rt = "0.7"
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embedded-hal = "1"
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lis2dh12 = { version = "0.7", features = ["out_f32"] }
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va416xx-hal = { version = ">=0.3, <=0.4", features = ["va41630"] }
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va416xx-hal = { version = ">=0.3, <=0.5", features = ["va41630"] }
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[features]
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rt = ["va416xx-hal/rt"]
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