Updates and fixes

- Improve and fix SPI HAL and example
- Fix RTIC example

examples/simple/examples/spi.rs

@@ -3,13 +3,12 @@
 //! If you do not use the loopback mode, MOSI and MISO need to be tied together on the board.
 #![no_main]
 #![no_std]
-
 use cortex_m_rt::entry;
 use embedded_hal::spi::{Mode, SpiBus, MODE_0};
 use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
 use simple_examples::peb1;
-use va416xx_hal::spi::{clk_div_for_target_clock, Spi, TransferConfig};
+use va416xx_hal::spi::{Spi, SpiClkConfig};
 use va416xx_hal::{
     gpio::{PinsB, PinsC},
     pac,
@@ -22,9 +21,8 @@ use va416xx_hal::{
 pub enum ExampleSelect {
     // Enter loopback mode. It is not necessary to tie MOSI/MISO together for this
     Loopback,
-    // Send a test buffer and print everything received. You need to tie together MOSI/MISO in this
-    // mode.
-    TestBuffer,
+    // You need to tie together MOSI/MISO in this mode.
+    MosiMisoTiedTogether,
 }
 
 const EXAMPLE_SEL: ExampleSelect = ExampleSelect::Loopback;
@@ -50,21 +48,23 @@ fn main() -> ! {
 
     let pins_b = PinsB::new(&mut dp.sysconfig, dp.portb);
     let pins_c = PinsC::new(&mut dp.sysconfig, dp.portc);
-    // Configure SPI1 pins.
+    // Configure SPI0 pins.
     let (sck, miso, mosi) = (
         pins_b.pb15.into_funsel_1(),
         pins_c.pc0.into_funsel_1(),
         pins_c.pc1.into_funsel_1(),
     );
 
-    let mut spi_cfg = SpiConfig::default().clk_div(
-        clk_div_for_target_clock(Hertz::from_raw(SPI_SPEED_KHZ), &clocks)
-            .expect("invalid target clock"),
-    );
+    let mut spi_cfg = SpiConfig::default()
+        .clk_cfg(
+            SpiClkConfig::from_clk(Hertz::from_raw(SPI_SPEED_KHZ), &clocks)
+                .expect("invalid target clock"),
+        )
+        .mode(SPI_MODE)
+        .blockmode(BLOCKMODE);
     if EXAMPLE_SEL == ExampleSelect::Loopback {
         spi_cfg = spi_cfg.loopback(true)
     }
-    let transfer_cfg = TransferConfig::new_no_hw_cs(None, Some(SPI_MODE), BLOCKMODE, false);
     // Create SPI peripheral.
     let mut spi0 = Spi::new(
         &mut dp.sysconfig,
@@ -72,29 +72,27 @@ fn main() -> ! {
         dp.spi0,
         (sck, miso, mosi),
         spi_cfg,
-        Some(&transfer_cfg.downgrade()),
-    )
-    .expect("creating SPI peripheral failed");
+    );
     spi0.set_fill_word(FILL_WORD);
     loop {
-        let mut tx_buf: [u8; 3] = [1, 2, 3];
-        let mut rx_buf: [u8; 3] = [0; 3];
-        // Can't really verify correct reply here.
-        spi0.write(&[0x42]).expect("write failed");
-        // Need small delay.. otherwise we will read back the sent byte (which we don't want here).
-        // The write function will return as soon as all bytes were shifted out, ignoring the
-        // reply bytes.
-        delay_sysclk.delay_us(50);
-        // Because of the loopback mode, we should get back the fill word here.
-        spi0.read(&mut rx_buf[0..1]).unwrap();
-        assert_eq!(rx_buf[0], FILL_WORD);
+        let tx_buf: [u8; 4] = [1, 2, 3, 0];
+        let mut rx_buf: [u8; 4] = [0; 4];
+        // Can't really verify correct behaviour here. Just verify nothing crazy happens or it hangs up.
+        spi0.write(&[0x42, 0x43]).expect("write failed");
 
-        spi0.transfer_in_place(&mut tx_buf)
+        // Can't really verify correct behaviour here. Just verify nothing crazy happens or it hangs up.
+        spi0.read(&mut rx_buf[0..2]).unwrap();
+
+        // If the pins are tied together, we should received exactly what we send.
+
+        let mut inplace_buf = tx_buf;
+        spi0.transfer_in_place(&mut inplace_buf)
             .expect("SPI transfer_in_place failed");
-        assert_eq!([1, 2, 3], tx_buf);
+        assert_eq!([1, 2, 3, 0], inplace_buf);
+
         spi0.transfer(&mut rx_buf, &tx_buf)
             .expect("SPI transfer failed");
-        assert_eq!(rx_buf, tx_buf);
+        assert_eq!(rx_buf, [1, 2, 3, 0]);
         delay_sysclk.delay_ms(500);
     }
 }