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- Improve and fix SPI HAL and example
- Fix RTIC example
This commit is contained in:
Robin Müller 2024-09-18 22:39:22 +02:00
parent dfab81a813
commit aa1ed2a20d
8 changed files with 562 additions and 352 deletions

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@ -41,4 +41,4 @@ debug-assertions = false # <-
lto = true lto = true
opt-level = 'z' # <- opt-level = 'z' # <-
overflow-checks = false # <- overflow-checks = false # <-
# strip = true # Automatically strip symbols from the binary. strip = true # Automatically strip symbols from the binary.

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@ -99,9 +99,9 @@ example.
### Using VS Code ### Using VS Code
Assuming a working debug connection to your VA108xx board, you can debug using VS Code with Assuming a working debug connection to your VA416xx board, you can debug using VS Code with
the [`Cortex-Debug` plugin](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug). Please make sure that the [`Cortex-Debug` plugin](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug).
[`objdump-multiarch` and `nm-multiarch`](https://forums.raspberrypi.com/viewtopic.php?t=333146) Please make sure that [`objdump-multiarch` and `nm-multiarch`](https://forums.raspberrypi.com/viewtopic.php?t=333146)
are installed as well. are installed as well.
Some sample configuration files for VS code were provided and can be used by running Some sample configuration files for VS code were provided and can be used by running

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@ -8,8 +8,13 @@ cortex-m = "0.7"
cortex-m-rt = "0.7" cortex-m-rt = "0.7"
embedded-hal = "1" embedded-hal = "1"
panic-rtt-target = { version = "0.1.3" } panic-rtt-target = { version = "0.1.3" }
panic-halt = { version = "0.2" }
rtt-target = { version = "0.5" } rtt-target = { version = "0.5" }
crc = "3" crc = "3"
[dependencies.va416xx-hal] [dependencies.va416xx-hal]
path = "../va416xx-hal" path = "../va416xx-hal"
[features]
default = []
rtt-panic = []

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@ -1,17 +1,5 @@
//! Vorago bootloader which can boot from two images. //! Vorago bootloader which can boot from two images.
//! //!
//! Bootloader memory map
//!
//! * <0x0> Bootloader start <code up to 0x3FFE bytes>
//! * <0x3FFE> Bootloader CRC <halfword>
//! * <0x4000> App image A start <code up to 0x1DFFC (~120K) bytes>
//! * <0x21FFC> App image A CRC check length <halfword>
//! * <0x21FFE> App image A CRC check value <halfword>
//! * <0x22000> App image B start <code up to 0x1DFFC (~120K) bytes>
//! * <0x3FFFC> App image B CRC check length <halfword>
//! * <0x3FFFE> App image B CRC check value <halfword>
//! * <0x40000> <end>
//!
//! As opposed to the Vorago example code, this bootloader assumes a 40 MHz external clock //! As opposed to the Vorago example code, this bootloader assumes a 40 MHz external clock
//! but does not scale that clock up. //! but does not scale that clock up.
#![no_main] #![no_main]
@ -19,6 +7,9 @@
use cortex_m_rt::entry; use cortex_m_rt::entry;
use crc::{Crc, CRC_32_ISO_HDLC}; use crc::{Crc, CRC_32_ISO_HDLC};
#[cfg(not(feature = "rtt-panic"))]
use panic_halt as _;
#[cfg(feature = "rtt-panic")]
use panic_rtt_target as _; use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print}; use rtt_target::{rprintln, rtt_init_print};
use va416xx_hal::{ use va416xx_hal::{
@ -42,6 +33,9 @@ const DEBUG_PRINTOUTS: bool = true;
// self-flash itself. It is recommended that you use a tool like probe-rs, Keil IDE, or a flash // self-flash itself. It is recommended that you use a tool like probe-rs, Keil IDE, or a flash
// loader to boot a bootloader without this feature. // loader to boot a bootloader without this feature.
const FLASH_SELF: bool = false; const FLASH_SELF: bool = false;
// Useful for debugging and see what the bootloader is doing. Enabled currently, because
// the binary stays small enough.
const RTT_PRINTOUT: bool = true;
// Important bootloader addresses and offsets, vector table information. // Important bootloader addresses and offsets, vector table information.
@ -88,8 +82,10 @@ impl WdtInterface for OptWdt {
#[entry] #[entry]
fn main() -> ! { fn main() -> ! {
if RTT_PRINTOUT {
rtt_init_print!(); rtt_init_print!();
rprintln!("-- VA416xx bootloader --"); rprintln!("-- VA416xx bootloader --");
}
let mut dp = pac::Peripherals::take().unwrap(); let mut dp = pac::Peripherals::take().unwrap();
let cp = cortex_m::Peripherals::take().unwrap(); let cp = cortex_m::Peripherals::take().unwrap();
// Disable ROM protection. // Disable ROM protection.
@ -133,20 +129,26 @@ fn main() -> ! {
nvm.write_data(0x0, &first_four_bytes); nvm.write_data(0x0, &first_four_bytes);
nvm.write_data(0x4, bootloader_data); nvm.write_data(0x4, bootloader_data);
if let Err(e) = nvm.verify_data(0x0, &first_four_bytes) { if let Err(e) = nvm.verify_data(0x0, &first_four_bytes) {
if RTT_PRINTOUT {
rprintln!("verification of self-flash to NVM failed: {:?}", e); rprintln!("verification of self-flash to NVM failed: {:?}", e);
} }
}
if let Err(e) = nvm.verify_data(0x4, bootloader_data) { if let Err(e) = nvm.verify_data(0x4, bootloader_data) {
if RTT_PRINTOUT {
rprintln!("verification of self-flash to NVM failed: {:?}", e); rprintln!("verification of self-flash to NVM failed: {:?}", e);
} }
}
nvm.write_data(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes()); nvm.write_data(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes());
if let Err(e) = nvm.verify_data(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes()) { if let Err(e) = nvm.verify_data(BOOTLOADER_CRC_ADDR, &bootloader_crc.to_be_bytes()) {
if RTT_PRINTOUT {
rprintln!( rprintln!(
"error: CRC verification for bootloader self-flash failed: {:?}", "error: CRC verification for bootloader self-flash failed: {:?}",
e e
); );
} }
} }
}
// Check bootloader's CRC (and write it if blank) // Check bootloader's CRC (and write it if blank)
check_own_crc(&opt_wdt, &nvm, &cp); check_own_crc(&opt_wdt, &nvm, &cp);
@ -156,7 +158,7 @@ fn main() -> ! {
} else if check_app_crc(AppSel::B, &opt_wdt) { } else if check_app_crc(AppSel::B, &opt_wdt) {
boot_app(AppSel::B, &cp) boot_app(AppSel::B, &cp)
} else { } else {
if DEBUG_PRINTOUTS { if DEBUG_PRINTOUTS && RTT_PRINTOUT {
rprintln!("both images corrupt! booting image A"); rprintln!("both images corrupt! booting image A");
} }
// TODO: Shift a CCSDS packet out to inform host/OBC about image corruption. // TODO: Shift a CCSDS packet out to inform host/OBC about image corruption.
@ -184,7 +186,7 @@ fn check_own_crc(wdt: &OptWdt, nvm: &Nvm, cp: &cortex_m::Peripherals) {
let crc_calc = digest.finalize(); let crc_calc = digest.finalize();
wdt.feed(); wdt.feed();
if crc_exp == 0x0000 || crc_exp == 0xffff { if crc_exp == 0x0000 || crc_exp == 0xffff {
if DEBUG_PRINTOUTS { if DEBUG_PRINTOUTS && RTT_PRINTOUT {
rprintln!("BL CRC blank - prog new CRC"); rprintln!("BL CRC blank - prog new CRC");
} }
// Blank CRC, write it to NVM. // Blank CRC, write it to NVM.
@ -194,7 +196,7 @@ fn check_own_crc(wdt: &OptWdt, nvm: &Nvm, cp: &cortex_m::Peripherals) {
// cortex_m::peripheral::SCB::sys_reset(); // cortex_m::peripheral::SCB::sys_reset();
} else if crc_exp != crc_calc { } else if crc_exp != crc_calc {
// Bootloader is corrupted. Try to run App A. // Bootloader is corrupted. Try to run App A.
if DEBUG_PRINTOUTS { if DEBUG_PRINTOUTS && RTT_PRINTOUT {
rprintln!( rprintln!(
"bootloader CRC corrupt, read {} and expected {}. booting image A immediately", "bootloader CRC corrupt, read {} and expected {}. booting image A immediately",
crc_calc, crc_calc,
@ -217,7 +219,7 @@ fn read_four_bytes_at_addr_zero(buf: &mut [u8; 4]) {
} }
} }
fn check_app_crc(app_sel: AppSel, wdt: &OptWdt) -> bool { fn check_app_crc(app_sel: AppSel, wdt: &OptWdt) -> bool {
if DEBUG_PRINTOUTS { if DEBUG_PRINTOUTS && RTT_PRINTOUT {
rprintln!("Checking image {:?}", app_sel); rprintln!("Checking image {:?}", app_sel);
} }
if app_sel == AppSel::A { if app_sel == AppSel::A {
@ -237,7 +239,9 @@ fn check_app_given_addr(
let image_size = unsafe { (image_size_addr as *const u32).read_unaligned().to_be() }; let image_size = unsafe { (image_size_addr as *const u32).read_unaligned().to_be() };
// Sanity check. // Sanity check.
if image_size > APP_A_END_ADDR - APP_A_START_ADDR - 8 { if image_size > APP_A_END_ADDR - APP_A_START_ADDR - 8 {
if RTT_PRINTOUT {
rprintln!("detected invalid app size {}", image_size); rprintln!("detected invalid app size {}", image_size);
}
return false; return false;
} }
wdt.feed(); wdt.feed();
@ -252,7 +256,7 @@ fn check_app_given_addr(
} }
fn boot_app(app_sel: AppSel, cp: &cortex_m::Peripherals) -> ! { fn boot_app(app_sel: AppSel, cp: &cortex_m::Peripherals) -> ! {
if DEBUG_PRINTOUTS { if DEBUG_PRINTOUTS && RTT_PRINTOUT {
rprintln!("booting app {:?}", app_sel); rprintln!("booting app {:?}", app_sel);
} }
let clkgen = unsafe { pac::Clkgen::steal() }; let clkgen = unsafe { pac::Clkgen::steal() };

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@ -2,8 +2,13 @@
#![no_main] #![no_main]
#![no_std] #![no_std]
use va416xx_hal::time::Hertz;
const EXTCLK_FREQ: Hertz = Hertz::from_raw(40_000_000);
#[rtic::app(device = pac, dispatchers = [U1, U2, U3])] #[rtic::app(device = pac, dispatchers = [U1, U2, U3])]
mod app { mod app {
use super::*;
use cortex_m::asm; use cortex_m::asm;
use embedded_hal::digital::StatefulOutputPin; use embedded_hal::digital::StatefulOutputPin;
use panic_rtt_target as _; use panic_rtt_target as _;
@ -13,6 +18,7 @@ mod app {
use va416xx_hal::{ use va416xx_hal::{
gpio::{OutputReadablePushPull, Pin, PinsG, PG5}, gpio::{OutputReadablePushPull, Pin, PinsG, PG5},
pac, pac,
prelude::*,
}; };
#[local] #[local]
@ -23,14 +29,22 @@ mod app {
#[shared] #[shared]
struct Shared {} struct Shared {}
rtic_monotonics::systick_monotonic!(Mono, 10_000); rtic_monotonics::systick_monotonic!(Mono, 1_000);
#[init] #[init]
fn init(_ctx: init::Context) -> (Shared, Local) { fn init(mut cx: init::Context) -> (Shared, Local) {
rtt_init_default!(); rtt_init_default!();
rprintln!("-- Vorago RTIC template --"); rprintln!("-- Vorago RTIC example application --");
let mut dp = pac::Peripherals::take().unwrap(); // Use the external clock connected to XTAL_N.
let portg = PinsG::new(&mut dp.sysconfig, dp.portg); let clocks = cx
.device
.clkgen
.constrain()
.xtal_n_clk_with_src_freq(EXTCLK_FREQ)
.freeze(&mut cx.device.sysconfig)
.unwrap();
Mono::start(cx.core.SYST, clocks.sysclk().raw());
let portg = PinsG::new(&mut cx.device.sysconfig, cx.device.portg);
let led = portg.pg5.into_readable_push_pull_output(); let led = portg.pg5.into_readable_push_pull_output();
blinky::spawn().ok(); blinky::spawn().ok();
(Shared {}, Local { led }) (Shared {}, Local { led })

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@ -3,13 +3,12 @@
//! If you do not use the loopback mode, MOSI and MISO need to be tied together on the board. //! If you do not use the loopback mode, MOSI and MISO need to be tied together on the board.
#![no_main] #![no_main]
#![no_std] #![no_std]
use cortex_m_rt::entry; use cortex_m_rt::entry;
use embedded_hal::spi::{Mode, SpiBus, MODE_0}; use embedded_hal::spi::{Mode, SpiBus, MODE_0};
use panic_rtt_target as _; use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print}; use rtt_target::{rprintln, rtt_init_print};
use simple_examples::peb1; use simple_examples::peb1;
use va416xx_hal::spi::{clk_div_for_target_clock, Spi, TransferConfig}; use va416xx_hal::spi::{Spi, SpiClkConfig};
use va416xx_hal::{ use va416xx_hal::{
gpio::{PinsB, PinsC}, gpio::{PinsB, PinsC},
pac, pac,
@ -22,9 +21,8 @@ use va416xx_hal::{
pub enum ExampleSelect { pub enum ExampleSelect {
// Enter loopback mode. It is not necessary to tie MOSI/MISO together for this // Enter loopback mode. It is not necessary to tie MOSI/MISO together for this
Loopback, Loopback,
// Send a test buffer and print everything received. You need to tie together MOSI/MISO in this // You need to tie together MOSI/MISO in this mode.
// mode. MosiMisoTiedTogether,
TestBuffer,
} }
const EXAMPLE_SEL: ExampleSelect = ExampleSelect::Loopback; const EXAMPLE_SEL: ExampleSelect = ExampleSelect::Loopback;
@ -50,21 +48,23 @@ fn main() -> ! {
let pins_b = PinsB::new(&mut dp.sysconfig, dp.portb); let pins_b = PinsB::new(&mut dp.sysconfig, dp.portb);
let pins_c = PinsC::new(&mut dp.sysconfig, dp.portc); let pins_c = PinsC::new(&mut dp.sysconfig, dp.portc);
// Configure SPI1 pins. // Configure SPI0 pins.
let (sck, miso, mosi) = ( let (sck, miso, mosi) = (
pins_b.pb15.into_funsel_1(), pins_b.pb15.into_funsel_1(),
pins_c.pc0.into_funsel_1(), pins_c.pc0.into_funsel_1(),
pins_c.pc1.into_funsel_1(), pins_c.pc1.into_funsel_1(),
); );
let mut spi_cfg = SpiConfig::default().clk_div( let mut spi_cfg = SpiConfig::default()
clk_div_for_target_clock(Hertz::from_raw(SPI_SPEED_KHZ), &clocks) .clk_cfg(
SpiClkConfig::from_clk(Hertz::from_raw(SPI_SPEED_KHZ), &clocks)
.expect("invalid target clock"), .expect("invalid target clock"),
); )
.mode(SPI_MODE)
.blockmode(BLOCKMODE);
if EXAMPLE_SEL == ExampleSelect::Loopback { if EXAMPLE_SEL == ExampleSelect::Loopback {
spi_cfg = spi_cfg.loopback(true) spi_cfg = spi_cfg.loopback(true)
} }
let transfer_cfg = TransferConfig::new_no_hw_cs(None, Some(SPI_MODE), BLOCKMODE, false);
// Create SPI peripheral. // Create SPI peripheral.
let mut spi0 = Spi::new( let mut spi0 = Spi::new(
&mut dp.sysconfig, &mut dp.sysconfig,
@ -72,29 +72,27 @@ fn main() -> ! {
dp.spi0, dp.spi0,
(sck, miso, mosi), (sck, miso, mosi),
spi_cfg, spi_cfg,
Some(&transfer_cfg.downgrade()), );
)
.expect("creating SPI peripheral failed");
spi0.set_fill_word(FILL_WORD); spi0.set_fill_word(FILL_WORD);
loop { loop {
let mut tx_buf: [u8; 3] = [1, 2, 3]; let tx_buf: [u8; 4] = [1, 2, 3, 0];
let mut rx_buf: [u8; 3] = [0; 3]; let mut rx_buf: [u8; 4] = [0; 4];
// Can't really verify correct reply here. // Can't really verify correct behaviour here. Just verify nothing crazy happens or it hangs up.
spi0.write(&[0x42]).expect("write failed"); spi0.write(&[0x42, 0x43]).expect("write failed");
// Need small delay.. otherwise we will read back the sent byte (which we don't want here).
// The write function will return as soon as all bytes were shifted out, ignoring the
// reply bytes.
delay_sysclk.delay_us(50);
// Because of the loopback mode, we should get back the fill word here.
spi0.read(&mut rx_buf[0..1]).unwrap();
assert_eq!(rx_buf[0], FILL_WORD);
spi0.transfer_in_place(&mut tx_buf) // Can't really verify correct behaviour here. Just verify nothing crazy happens or it hangs up.
spi0.read(&mut rx_buf[0..2]).unwrap();
// If the pins are tied together, we should received exactly what we send.
let mut inplace_buf = tx_buf;
spi0.transfer_in_place(&mut inplace_buf)
.expect("SPI transfer_in_place failed"); .expect("SPI transfer_in_place failed");
assert_eq!([1, 2, 3], tx_buf); assert_eq!([1, 2, 3, 0], inplace_buf);
spi0.transfer(&mut rx_buf, &tx_buf) spi0.transfer(&mut rx_buf, &tx_buf)
.expect("SPI transfer failed"); .expect("SPI transfer failed");
assert_eq!(rx_buf, tx_buf); assert_eq!(rx_buf, [1, 2, 3, 0]);
delay_sysclk.delay_ms(500); delay_sysclk.delay_ms(500);
} }
} }

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@ -8,6 +8,18 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
# [unreleased] # [unreleased]
## Changed
- Improve and fix SPI abstractions. Add new low level interface. The primary SPI constructor now
only expects a configuration structure and the transfer configuration needs to be applied in a
separate step.
## Fixed
- Fixes for SPI peripheral: Flush implementation was incorrect and should now flush properly.
- Fixes for SPI example
- Fixes for RTIC example
# [v0.2.0] 2024-09-18 # [v0.2.0] 2024-09-18
- Documentation improvements - Documentation improvements

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