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regenerate PAC

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This commit is contained in:
Robin Müller
2025-02-13 15:58:05 +01:00
parent 0c040515fe
commit ab66e1a8aa
515 changed files with 1371 additions and 2391 deletions
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3
va416xx/src/tim0/cascade0.rs
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@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:7 - Cascade Selection"]
#[inline(always)]
#[must_use]
pub fn cassel(&mut self) -> CasselW<Cascade0Spec> {
CasselW::new(self, 0)
}
}
#[doc = "Cascade Enable Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cascade0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cascade0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Cascade Enable Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`cascade0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cascade0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct Cascade0Spec;
impl crate::RegisterSpec for Cascade0Spec {
type Ux = u32;

2
va416xx/src/tim0/cnt_value.rs
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@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "The current value of the counter\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cnt_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cnt_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "The current value of the counter\n\nYou can [`read`](crate::Reg::read) this register and get [`cnt_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CntValueSpec;
impl crate::RegisterSpec for CntValueSpec {
type Ux = u32;

12
va416xx/src/tim0/csd_ctrl.rs
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@ -97,66 +97,56 @@ impl R {
impl W {
#[doc = "Bit 0 - Cascade 0 Enable"]
#[inline(always)]
#[must_use]
pub fn csden0(&mut self) -> Csden0W<CsdCtrlSpec> {
Csden0W::new(self, 0)
}
#[doc = "Bit 1 - Cascade 0 Invert"]
#[inline(always)]
#[must_use]
pub fn csdinv0(&mut self) -> Csdinv0W<CsdCtrlSpec> {
Csdinv0W::new(self, 1)
}
#[doc = "Bit 2 - Cascade 1 Enable"]
#[inline(always)]
#[must_use]
pub fn csden1(&mut self) -> Csden1W<CsdCtrlSpec> {
Csden1W::new(self, 2)
}
#[doc = "Bit 3 - Cascade 1 Invert"]
#[inline(always)]
#[must_use]
pub fn csdinv1(&mut self) -> Csdinv1W<CsdCtrlSpec> {
Csdinv1W::new(self, 3)
}
#[doc = "Bit 4 - Dual Cascade Operation (0:AND, 1:OR)"]
#[inline(always)]
#[must_use]
pub fn dcasop(&mut self) -> DcasopW<CsdCtrlSpec> {
DcasopW::new(self, 4)
}
#[doc = "Bit 6 - Cascade 0 Enabled as Trigger"]
#[inline(always)]
#[must_use]
pub fn csdtrg0(&mut self) -> Csdtrg0W<CsdCtrlSpec> {
Csdtrg0W::new(self, 6)
}
#[doc = "Bit 7 - Cascade 1 Enabled as Trigger"]
#[inline(always)]
#[must_use]
pub fn csdtrg1(&mut self) -> Csdtrg1W<CsdCtrlSpec> {
Csdtrg1W::new(self, 7)
}
#[doc = "Bit 8 - Cascade 2 Enable"]
#[inline(always)]
#[must_use]
pub fn csden2(&mut self) -> Csden2W<CsdCtrlSpec> {
Csden2W::new(self, 8)
}
#[doc = "Bit 9 - Cascade 2 Invert"]
#[inline(always)]
#[must_use]
pub fn csdinv2(&mut self) -> Csdinv2W<CsdCtrlSpec> {
Csdinv2W::new(self, 9)
}
#[doc = "Bit 10 - Cascade 2 Trigger mode"]
#[inline(always)]
#[must_use]
pub fn csdtrg2(&mut self) -> Csdtrg2W<CsdCtrlSpec> {
Csdtrg2W::new(self, 10)
}
}
#[doc = "The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csd_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csd_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "The Cascade Control Register. Controls the counter external enable signals\n\nYou can [`read`](crate::Reg::read) this register and get [`csd_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`csd_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CsdCtrlSpec;
impl crate::RegisterSpec for CsdCtrlSpec {
type Ux = u32;

21
va416xx/src/tim0/ctrl.rs
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@ -32,11 +32,11 @@ pub enum StatusSel {
Toggle = 2,
#[doc = "3: Selects the Pulse Width Modulated output. It 1 when the counter value is >= the PWMA_VALUE"]
Pwma = 3,
#[doc = "4: Selects the Pulse Width Modulated output. It 1 when the counter value is &lt; the PWMA_VALUE and value is > PWMA_VALUE"]
#[doc = "4: Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
Pwmb = 4,
#[doc = "5: Returns the counter ENABLED bit"]
Enabled = 5,
#[doc = "6: Selects the Pulse Width Modulated output. It 1 when the counter value is &lt;= the PWMA_VALUE and value is >= 0"]
#[doc = "6: Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
PwmaActive = 6,
}
impl From<StatusSel> for u8 {
@ -86,7 +86,7 @@ impl StatusSelR {
pub fn is_pwma(&self) -> bool {
*self == StatusSel::Pwma
}
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is &lt; the PWMA_VALUE and value is > PWMA_VALUE"]
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
#[inline(always)]
pub fn is_pwmb(&self) -> bool {
*self == StatusSel::Pwmb
@ -96,7 +96,7 @@ impl StatusSelR {
pub fn is_enabled(&self) -> bool {
*self == StatusSel::Enabled
}
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is &lt;= the PWMA_VALUE and value is >= 0"]
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
#[inline(always)]
pub fn is_pwma_active(&self) -> bool {
*self == StatusSel::PwmaActive
@ -129,7 +129,7 @@ where
pub fn pwma(self) -> &'a mut crate::W<REG> {
self.variant(StatusSel::Pwma)
}
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is &lt; the PWMA_VALUE and value is > PWMA_VALUE"]
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is < the PWMA_VALUE and value is > PWMA_VALUE"]
#[inline(always)]
pub fn pwmb(self) -> &'a mut crate::W<REG> {
self.variant(StatusSel::Pwmb)
@ -139,7 +139,7 @@ where
pub fn enabled(self) -> &'a mut crate::W<REG> {
self.variant(StatusSel::Enabled)
}
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is &lt;= the PWMA_VALUE and value is >= 0"]
#[doc = "Selects the Pulse Width Modulated output. It 1 when the counter value is <= the PWMA_VALUE and value is >= 0"]
#[inline(always)]
pub fn pwma_active(self) -> &'a mut crate::W<REG> {
self.variant(StatusSel::PwmaActive)
@ -198,48 +198,41 @@ impl R {
impl W {
#[doc = "Bit 0 - Counter Enable"]
#[inline(always)]
#[must_use]
pub fn enable(&mut self) -> EnableW<CtrlSpec> {
EnableW::new(self, 0)
}
#[doc = "Bit 2 - Auto Disables the counter (set ENABLE to 0) when the count reaches 0"]
#[inline(always)]
#[must_use]
pub fn auto_disable(&mut self) -> AutoDisableW<CtrlSpec> {
AutoDisableW::new(self, 2)
}
#[doc = "Bit 3 - Auto Deactivate the counter (set ACTIVE to 0) when the count reaches 0"]
#[inline(always)]
#[must_use]
pub fn auto_deactivate(&mut self) -> AutoDeactivateW<CtrlSpec> {
AutoDeactivateW::new(self, 3)
}
#[doc = "Bit 4 - Interrupt Enable"]
#[inline(always)]
#[must_use]
pub fn irq_enb(&mut self) -> IrqEnbW<CtrlSpec> {
IrqEnbW::new(self, 4)
}
#[doc = "Bits 5:7 - Counter Status Selection"]
#[inline(always)]
#[must_use]
pub fn status_sel(&mut self) -> StatusSelW<CtrlSpec> {
StatusSelW::new(self, 5)
}
#[doc = "Bit 8 - Invert the Output Status"]
#[inline(always)]
#[must_use]
pub fn status_inv(&mut self) -> StatusInvW<CtrlSpec> {
StatusInvW::new(self, 8)
}
#[doc = "Bit 9 - Stop Request"]
#[inline(always)]
#[must_use]
pub fn req_stop(&mut self) -> ReqStopW<CtrlSpec> {
ReqStopW::new(self, 9)
}
}
#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec;
impl crate::RegisterSpec for CtrlSpec {
type Ux = u32;

3
va416xx/src/tim0/enable.rs
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@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bit 0 - Counter Enable"]
#[inline(always)]
#[must_use]
pub fn enable(&mut self) -> EnableW<EnableSpec> {
EnableW::new(self, 0)
}
}
#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Alternate access to the Counter ENABLE bit in the CTRL Register\n\nYou can [`read`](crate::Reg::read) this register and get [`enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EnableSpec;
impl crate::RegisterSpec for EnableSpec {
type Ux = u32;

2
va416xx/src/tim0/perid.rs
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@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;

2
va416xx/src/tim0/pwm_value.rs
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@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "The Pulse Width Modulation Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "The Pulse Width Modulation Value\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PwmValueSpec;
impl crate::RegisterSpec for PwmValueSpec {
type Ux = u32;

2
va416xx/src/tim0/pwma_value.rs
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@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwma_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwma_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "The Pulse Width Modulation ValueA\n\nYou can [`read`](crate::Reg::read) this register and get [`pwma_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwma_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PwmaValueSpec;
impl crate::RegisterSpec for PwmaValueSpec {
type Ux = u32;

2
va416xx/src/tim0/pwmb_value.rs
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@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwmb_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwmb_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "The Pulse Width Modulation ValueB\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmb_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmb_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PwmbValueSpec;
impl crate::RegisterSpec for PwmbValueSpec {
type Ux = u32;

2
va416xx/src/tim0/rst_value.rs
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@ -8,7 +8,7 @@ impl core::fmt::Debug for R {
}
}
impl W {}
#[doc = "The value that counter start from after reaching 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rst_value::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rst_value::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "The value that counter start from after reaching 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`rst_value::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rst_value::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RstValueSpec;
impl crate::RegisterSpec for RstValueSpec {
type Ux = u32;