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should work now..
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Robin Müller
2024-09-17 12:23:30 +02:00
parent 9b26f79bed
commit adc0e68ebd
2 changed files with 29 additions and 29 deletions
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9
va416xx-hal/src/timer.rs
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@ -5,6 +5,7 @@
//! - [Timer MS and Second Tick Example](https://github.com/us-irs/va416xx-rs/blob/main/examples/simple/examples/timer-ticks.rs)
use core::cell::Cell;
use cortex_m::asm;
use critical_section::Mutex;
use crate::clock::Clocks;
@ -349,6 +350,14 @@ pub fn deassert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) {
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << tim_id as u32)) })
}
#[inline]
pub fn assert_tim_reset_for_two_cycles(syscfg: &mut pac::Sysconfig, tim_id: u8) {
assert_tim_reset(syscfg, tim_id);
asm::nop();
asm::nop();
deassert_tim_reset(syscfg, tim_id);
}
pub type TimRegBlock = pac::tim0::RegisterBlock;
/// Register interface.