rust/va416xx-rs
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should work now..
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This commit is contained in:
Robin Müller 2024-09-17 12:23:30 +02:00
parent 9b26f79bed
commit adc0e68ebd
Signed by: muellerr
GPG Key ID: A649FB78196E3849
2 changed files with 29 additions and 29 deletions
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49
examples/embassy/src/lib.rs
View File

@ -3,6 +3,7 @@ use core::{
cell::Cell,
mem, ptr,
sync::atomic::{AtomicU32, AtomicU8, Ordering},
time,
};
use critical_section::CriticalSection;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
@ -14,7 +15,10 @@ use va416xx_hal::{
enable_interrupt,
irq_router::enable_and_init_irq_router,
pac::{self, interrupt},
pwm::{assert_tim_reset, deassert_tim_reset, enable_tim_clk, ValidTim},
pwm::{
assert_tim_reset, assert_tim_reset_for_two_cycles, deassert_tim_reset, enable_tim_clk,
ValidTim,
},
};
pub type TimekeeperClk = pac::Tim15;
@ -92,33 +96,25 @@ impl TimerDriverEmbassy {
clocks: &Clocks,
) {
enable_tim_clk(syscfg, TimekeeperClk::TIM_ID);
assert_tim_reset(syscfg, TimekeeperClk::TIM_ID);
cortex_m::asm::nop();
cortex_m::asm::nop();
deassert_tim_reset(syscfg, TimekeeperClk::TIM_ID);
assert_tim_reset_for_two_cycles(syscfg, TimekeeperClk::TIM_ID);
let rst_value = TimekeeperClk::clock(clocks).raw() / TICK_HZ as u32 - 1;
// Safety: We have a valid instance of the tim peripheral.
timekeeper
.rst_value()
.write(|w| unsafe { w.bits(rst_value) });
//timekeeper
//.cnt_value()
//.write(|w| unsafe { w.bits(rst_value) });
timekeeper
.cnt_value()
.write(|w| unsafe { w.bits(rst_value) });
// Switch on. Timekeeping should always be done.
timekeeper.ctrl().modify(|_, w| {
w.irq_enb().set_bit();
w.enable().set_bit()
});
unsafe {
enable_interrupt(TimekeeperClk::IRQ);
}
timekeeper.ctrl().modify(|_, w| w.irq_enb().set_bit());
timekeeper.enable().write(|w| unsafe { w.bits(1) });
enable_tim_clk(syscfg, AlarmClk0::TIM_ID);
assert_tim_reset(syscfg, AlarmClk0::TIM_ID);
cortex_m::asm::nop();
cortex_m::asm::nop();
deassert_tim_reset(syscfg, AlarmClk0::TIM_ID);
assert_tim_reset_for_two_cycles(syscfg, AlarmClk0::TIM_ID);
// Explicitely disable alarm timer until needed.
alarm_tim.ctrl().modify(|_, w| {
@ -147,15 +143,12 @@ impl TimerDriverEmbassy {
let at = alarm.timestamp.get();
let t = (period as u64) << 32;
if at < t + TIMER_MARGIN {
//let rst_val = alarm_tim(i).rst_value().read().bits();
// alarm_tim(i).cnt_value()
//alarm_tim(i)
//.cnt_value()
//.write(|w| unsafe { w.bits(rst_val) });
alarm_tim(i).ctrl().modify(|_, w| {
w.irq_enb().set_bit();
w.enable().set_bit()
});
let rst_val = alarm_tim(i).rst_value().read().bits();
alarm_tim(i)
.cnt_value()
.write(|w| unsafe { w.bits(rst_val) });
alarm_tim(i).ctrl().modify(|_, w| w.irq_enb().set_bit());
alarm_tim(i).enable().write(|w| unsafe { w.bits(1) })
}
}
})
@ -271,10 +264,8 @@ impl Driver for TimerDriverEmbassy {
let diff = timestamp - t;
if diff < TIMER_MARGIN {
alarm_tim.ctrl().modify(|_, w| {
w.irq_enb().set_bit();
w.enable().set_bit()
});
alarm_tim.ctrl().modify(|_, w| w.irq_enb().set_bit());
alarm_tim.enable().write(|w| unsafe { w.bits(1) });
} else {
// If it's too far in the future, don't enable timer yet.
// It will be enabled later by `next_period`.

9
va416xx-hal/src/timer.rs
View File

@ -5,6 +5,7 @@
//! - [Timer MS and Second Tick Example](https://github.com/us-irs/va416xx-rs/blob/main/examples/simple/examples/timer-ticks.rs)
use core::cell::Cell;
use cortex_m::asm;
use critical_section::Mutex;
use crate::clock::Clocks;
@ -349,6 +350,14 @@ pub fn deassert_tim_reset(syscfg: &mut pac::Sysconfig, tim_id: u8) {
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << tim_id as u32)) })
}
#[inline]
pub fn assert_tim_reset_for_two_cycles(syscfg: &mut pac::Sysconfig, tim_id: u8) {
assert_tim_reset(syscfg, tim_id);
asm::nop();
asm::nop();
deassert_tim_reset(syscfg, tim_id);
}
pub type TimRegBlock = pac::tim0::RegisterBlock;
/// Register interface.