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Merge pull request 'last naming updates' (#76) from naming-updates-hal-release-prep into main

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Reviewed-on: #76
This commit is contained in:
Robin Müller
2025-09-03 20:16:34 +02:00
parent dc31996c34 1b98de324e
commit c439bfff29
12 changed files with 103 additions and 158 deletions
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2
.github/workflows/ci.yml vendored
View File

@@ -13,7 +13,7 @@ jobs:
- run: cargo check --target thumbv7em-none-eabihf
- run: cargo check --target thumbv7em-none-eabihf --examples
- run: cargo check -p va416xx --target thumbv7em-none-eabihf --all-features
- run: cargo check -p va416xx-hal --target thumbv7em-none-eabihf --examples --features "defmt va41630"
- run: cargo check -p va416xx-hal --target thumbv7em-none-eabihf --features "defmt va41630"
test:
name: Run Tests

6
bootloader/src/main.rs
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@@ -10,7 +10,7 @@ use crc::{Crc, CRC_32_ISO_HDLC};
use defmt_rtt as _;
use panic_probe as _;
use va416xx_hal::{
clock::{pll_setup_delay, ClkDivSel, ClkselSys, ClockConfigurator},
clock::{pll_setup_delay, ClockConfigurator, ClockDivisorSelect, ClockSelect},
edac,
nvm::Nvm,
pac::{self, interrupt},
@@ -266,11 +266,11 @@ fn boot_app(app_sel: AppSel, cp: &cortex_m::Peripherals) -> ! {
let clkgen = unsafe { pac::Clkgen::steal() };
clkgen
.ctrl0()
.modify(|_, w| unsafe { w.clksel_sys().bits(ClkselSys::Hbo as u8) });
.modify(|_, w| unsafe { w.clksel_sys().bits(ClockSelect::Hbo as u8) });
pll_setup_delay();
clkgen
.ctrl0()
.modify(|_, w| unsafe { w.clk_div_sel().bits(ClkDivSel::Div1 as u8) });
.modify(|_, w| unsafe { w.clk_div_sel().bits(ClockDivisorSelect::Div1 as u8) });
// Clear all interrupts set.
unsafe {
cp.NVIC.icer[0].write(0xFFFFFFFF);

4
examples/simple/examples/dma.rs
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@@ -14,7 +14,7 @@ use cortex_m_rt::entry;
use critical_section::Mutex;
use embedded_hal::delay::DelayNs;
use simple_examples::peb1;
use va416xx_hal::dma::{Dma, DmaCfg, DmaChannel, DmaCtrlBlock};
use va416xx_hal::dma::{Dma, DmaChannel, DmaConfig, DmaCtrlBlock};
use va416xx_hal::irq_router::enable_and_init_irq_router;
use va416xx_hal::pac::{self, interrupt};
use va416xx_hal::timer::CountdownTimer;
@@ -49,7 +49,7 @@ fn main() -> ! {
// statically.
let dma = Dma::new(
dp.dma,
DmaCfg::default(),
DmaConfig::default(),
core::ptr::addr_of_mut!(DMA_CTRL_BLOCK),
)
.expect("error creating DMA");

4
va416xx-hal/CHANGELOG.md
View File

@@ -13,6 +13,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Use `vorago-shared-hal` dependency to provide shared peripherals.
- Bump `va416xx` to v0.5
## Changed
- Replaced `*Cfg`, `*Clk`, `*Sel` abbreviations in names by written out variant.
# [v0.5.1] 2025-03-10
## Fixed

1
va416xx-hal/src/adc.rs
View File

@@ -54,6 +54,7 @@ pub enum ChannelSelect {
bitflags::bitflags! {
/// This structure is used by the ADC multi-select API to
/// allow selecting multiple channels in a convenient manner.
#[derive(Debug)]
pub struct MultiChannelSelect: u16 {
const AnIn0 = 1;
const AnIn1 = 1 << 1;

5
va416xx-hal/src/can/ll.rs
View File

@@ -3,7 +3,8 @@ use embedded_can::Frame;
use super::{
regs::{
self, BaseId, BufStatusAndControl, BufferState, ExtendedId, MmioCanMsgBuf, TwoBytesData,
self, BaseId, BufStatusAndControl, BufferState, ExtendedId, MmioCanMessageBuffer,
TwoBytesData,
},
CanFrame, CanFrameNormal, CanFrameRtr, CanId, InvalidBufferIndexError,
};
@@ -12,7 +13,7 @@ pub struct CanChannelLowLevel {
id: CanId,
/// Message buffer index.
idx: usize,
msg_buf: MmioCanMsgBuf<'static>,
msg_buf: MmioCanMessageBuffer<'static>,
}
impl core::fmt::Debug for CanChannelLowLevel {

12
va416xx-hal/src/can/mod.rs
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@@ -50,6 +50,7 @@ pub const MAX_BITRATE_DEVIATION: f32 = 0.005;
static CHANNELS_TAKEN: [AtomicBool; 2] = [AtomicBool::new(false), AtomicBool::new(false)];
#[derive(Debug, PartialEq, Eq, Clone, Copy)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum CanId {
Can0 = 0,
Can1 = 1,
@@ -85,6 +86,7 @@ pub const fn calculate_sample_point(tseg1: u8, tseg2: u8) -> f32 {
}
#[derive(Debug, Clone, Copy)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct ClockConfig {
prescaler: u8,
tseg1: u8,
@@ -280,19 +282,19 @@ pub const fn calculate_bitrate_deviation(actual_bitrate: f32, target_bitrate: He
(actual_bitrate - target_bitrate.raw() as f32).abs() / target_bitrate.raw() as f32
}
pub trait CanMarker {
pub trait CanInstance {
const ID: CanId;
const IRQ: va416xx::Interrupt;
const PERIPH_SEL: PeripheralSelect;
}
impl CanMarker for va416xx::Can0 {
impl CanInstance for va416xx::Can0 {
const ID: CanId = CanId::Can0;
const IRQ: va416xx::Interrupt = va416xx::Interrupt::CAN0;
const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Can0;
}
impl CanMarker for va416xx::Can1 {
impl CanInstance for va416xx::Can1 {
const ID: CanId = CanId::Can1;
const IRQ: va416xx::Interrupt = va416xx::Interrupt::CAN1;
const PERIPH_SEL: PeripheralSelect = PeripheralSelect::Can1;
@@ -310,12 +312,14 @@ pub struct InvalidSjwError(u8);
#[derive(Debug, thiserror::Error)]
#[error("invalid sample point {sample_point}")]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct InvalidSamplePointError {
/// Sample point, should be larger than 0.5 (50 %) but was not.
sample_point: f32,
}
#[derive(Debug, thiserror::Error)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum ClockConfigError {
#[error("invalid sjw: {0}")]
InvalidSjw(#[from] InvalidSjwError),
@@ -342,7 +346,7 @@ pub struct Can {
}
impl Can {
pub fn new<CanI: CanMarker>(_can: CanI, clk_config: ClockConfig) -> Self {
pub fn new<CanI: CanInstance>(_can: CanI, clk_config: ClockConfig) -> Self {
enable_peripheral_clock(CanI::PERIPH_SEL);
let id = CanI::ID;
let mut regs = if id == CanId::Can0 {

70
va416xx-hal/src/can/regs.rs
View File

@@ -37,8 +37,7 @@ pub enum BufferState {
}
/// Status control register for individual message buffers.
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))]
pub struct BufStatusAndControl {
/// Data length code.
#[bits(12..=15, rw)]
@@ -65,8 +64,7 @@ impl Timestamp {
}
}
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))]
pub struct TwoBytesData {
#[bits(0..=7, rw)]
data_lower_byte: u8,
@@ -76,7 +74,7 @@ pub struct TwoBytesData {
#[derive(derive_mmio::Mmio)]
#[repr(C)]
pub struct CanMsgBuf {
pub struct CanMessageBuffer {
stat_ctrl: BufStatusAndControl,
timestamp: Timestamp,
data3: TwoBytesData,
@@ -87,9 +85,9 @@ pub struct CanMsgBuf {
id1: BaseId,
}
static_assertions::const_assert_eq!(core::mem::size_of::<CanMsgBuf>(), 0x20);
static_assertions::const_assert_eq!(core::mem::size_of::<CanMessageBuffer>(), 0x20);
impl MmioCanMsgBuf<'_> {
impl MmioCanMessageBuffer<'_> {
pub fn reset(&mut self) {
self.write_stat_ctrl(BufStatusAndControl::new_with_raw_value(0));
self.write_timestamp(Timestamp::new(0));
@@ -104,6 +102,7 @@ impl MmioCanMsgBuf<'_> {
#[bitbybit::bitenum(u1, exhaustive = true)]
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum PinLogicLevel {
DominantIsZero = 0b0,
DominantIsOne = 0b1,
@@ -111,6 +110,7 @@ pub enum PinLogicLevel {
#[bitbybit::bitenum(u1, exhaustive = true)]
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum ErrorInterruptType {
/// EIPND bit is set on every error.
EveryError = 0b0,
@@ -121,12 +121,13 @@ pub enum ErrorInterruptType {
#[bitbybit::bitenum(u1, exhaustive = true)]
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum DataDirection {
FirstByteAtHighestAddr = 0b0,
LastByteAtHighestAddr = 0b1,
}
#[bitbybit::bitfield(u32)]
#[bitbybit::bitfield(u32, debug, defmt_fields(feature = "defmt"))]
pub struct Control {
#[bit(11, rw)]
error_interrupt_type: ErrorInterruptType,
@@ -160,8 +161,7 @@ pub struct Control {
enable: bool,
}
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))]
pub struct TimingConfig {
#[bits(0..=2, rw)]
tseg2: u3,
@@ -209,9 +209,7 @@ pub enum CanInterruptId {
Buffer(usize),
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
pub struct StatusPending {
#[bits(5..=7, r)]
ns: u3,
@@ -237,8 +235,7 @@ impl StatusPending {
}
}
#[bitbybit::bitfield(u32)]
#[derive(Debug)]
#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
pub struct ErrorCounter {
#[bits(0..=7, r)]
transmit: u8,
@@ -247,8 +244,7 @@ pub struct ErrorCounter {
}
/// This register is unused for standard frames.
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))]
pub struct ExtendedId {
/// Mask for ID bits \[14:0\] of extended frames.
#[bits(1..=15, rw)]
@@ -258,8 +254,7 @@ pub struct ExtendedId {
xrtr: bool,
}
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_bitfields(feature = "defmt"))]
pub struct BaseId {
/// This will contain ID\[10:0\] for standard frames and bits \[28:18\] for extended frames.
#[bits(5..=15, rw)]
@@ -297,7 +292,7 @@ pub enum ErrorFieldId {
Crc = 0b1111,
}
#[bitbybit::bitfield(u32)]
#[bitbybit::bitfield(u32, debug, defmt_bitfields(feature = "defmt"))]
pub struct DiagnosticRegister {
/// Shows the output value on the CAN TX pin at the time of the error.
#[bit(14, r)]
@@ -322,46 +317,15 @@ pub struct DiagnosticRegister {
efid: ErrorFieldId,
}
impl core::fmt::Debug for DiagnosticRegister {
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
f.debug_struct("DiagnosticRegister")
.field("efid", &self.efid())
.field("ebid", &self.ebid())
.field("txe", &self.txe())
.field("stuff", &self.stuff())
.field("crc", &self.crc())
.field("mon", &self.mon())
.field("drive", &self.drive())
.finish()
}
}
#[cfg(feature = "defmt")]
impl defmt::Format for DiagnosticRegister {
fn format(&self, fmt: defmt::Formatter) {
defmt::write!(
fmt,
"DiagnosticRegister {{ efid: {}, ebid: {}, txe: {}, stuff: {}, crc: {}, mon: {}, drive: {} }}",
self.efid(),
self.ebid(),
self.txe(),
self.stuff(),
self.crc(),
self.mon(),
self.drive()
)
}
}
#[derive(derive_mmio::Mmio)]
#[mmio(const_inner)]
#[repr(C)]
pub struct Can {
#[mmio(Inner)]
cmbs: [CanMsgBuf; 15],
cmbs: [CanMessageBuffer; 15],
/// Hidden CAN message buffer. Only allowed to be used internally by the peripheral.
#[mmio(Inner)]
_hcmb: CanMsgBuf,
_hcmb: CanMessageBuffer,
control: Control,
timing: TimingConfig,
/// Global mask extension used for buffers 0 to 13.

104
va416xx-hal/src/clock.rs
View File

@@ -22,7 +22,7 @@ pub const XTAL_OSC_TSTART_MS: u32 = 15;
#[derive(Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum FilterClkSel {
pub enum FilterClockSelect {
SysClk = 0,
Clk1 = 1,
Clk2 = 2,
@@ -36,7 +36,7 @@ pub enum FilterClkSel {
/// Refer to chapter 8 (p.57) of the programmers guide for detailed information.
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum ClkselSys {
pub enum ClockSelect {
// Internal Heart-Beat Osciallator. Not tightly controlled (+/-20 %). Not recommended as the regular clock!
Hbo = 0b00,
// External clock signal on XTAL_N line, 1-100 MHz
@@ -55,7 +55,7 @@ pub enum ClkselSys {
/// Refer to chapter 8 (p.57) of the programmers guide for detailed information.
#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum RefClkSel {
pub enum ReferenceClockSelect {
#[default]
None = 0b00,
XtalOsc = 0b01,
@@ -64,7 +64,7 @@ pub enum RefClkSel {
#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum ClkDivSel {
pub enum ClockDivisorSelect {
#[default]
Div1 = 0b00,
Div2 = 0b01,
@@ -74,7 +74,7 @@ pub enum ClkDivSel {
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum AdcClkDivSel {
pub enum AdcClockDivisorSelect {
Div8 = 0b00,
Div4 = 0b01,
Div2 = 0b10,
@@ -83,7 +83,7 @@ pub enum AdcClkDivSel {
#[derive(Debug, Default, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct PllCfg {
pub struct PllConfig {
/// Reference clock divider.
pub clkr: u8,
/// Clock divider on feedback path
@@ -94,12 +94,13 @@ pub struct PllCfg {
pub bwadj: u8,
}
pub fn clk_after_div(clk: Hertz, div_sel: ClkDivSel) -> Hertz {
#[inline]
pub const fn clock_after_division(clk: Hertz, div_sel: ClockDivisorSelect) -> Hertz {
match div_sel {
ClkDivSel::Div1 => clk,
ClkDivSel::Div2 => clk / 2,
ClkDivSel::Div4 => clk / 4,
ClkDivSel::Div8 => clk / 8,
ClockDivisorSelect::Div1 => clk,
ClockDivisorSelect::Div2 => Hertz::from_raw(clk.raw() / 2),
ClockDivisorSelect::Div4 => Hertz::from_raw(clk.raw() / 4),
ClockDivisorSelect::Div8 => Hertz::from_raw(clk.raw() / 8),
}
}
@@ -118,9 +119,9 @@ impl ClkgenExt for pac::Clkgen {
fn constrain(self) -> ClockConfigurator {
ClockConfigurator {
source_clk: None,
ref_clk_sel: RefClkSel::None,
clksel_sys: ClkselSys::Hbo,
clk_div_sel: ClkDivSel::Div1,
ref_clk_sel: ReferenceClockSelect::None,
clksel_sys: ClockSelect::Hbo,
clk_div_sel: ClockDivisorSelect::Div1,
clk_lost_detection: false,
pll_lock_lost_detection: false,
pll_cfg: None,
@@ -131,11 +132,11 @@ impl ClkgenExt for pac::Clkgen {
#[derive(Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct ClkSourceFreqNotSet;
pub struct ClockSourceFrequencyNotSet;
#[derive(Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum ClkCfgError {
pub enum ClockConfigError {
ClkSourceFreqNotSet,
PllConfigNotSet,
PllInitError,
@@ -143,13 +144,13 @@ pub enum ClkCfgError {
}
pub struct ClockConfigurator {
ref_clk_sel: RefClkSel,
clksel_sys: ClkselSys,
clk_div_sel: ClkDivSel,
ref_clk_sel: ReferenceClockSelect,
clksel_sys: ClockSelect,
clk_div_sel: ClockDivisorSelect,
/// The source clock frequency which is either an external clock connected to XTAL_N, or a
/// crystal connected to the XTAL_OSC input.
source_clk: Option<Hertz>,
pll_cfg: Option<PllCfg>,
pll_cfg: Option<PllConfig>,
clk_lost_detection: bool,
/// Feature only works on revision B of the board.
#[cfg(feature = "revb")]
@@ -176,9 +177,9 @@ impl ClockConfigurator {
pub fn new(clkgen: pac::Clkgen) -> Self {
ClockConfigurator {
source_clk: None,
ref_clk_sel: RefClkSel::None,
clksel_sys: ClkselSys::Hbo,
clk_div_sel: ClkDivSel::Div1,
ref_clk_sel: ReferenceClockSelect::None,
clksel_sys: ClockSelect::Hbo,
clk_div_sel: ClockDivisorSelect::Div1,
clk_lost_detection: false,
pll_lock_lost_detection: false,
pll_cfg: None,
@@ -207,8 +208,8 @@ impl ClockConfigurator {
/// It sets the internal configuration to [ClkselSys::XtalN] and [RefClkSel::XtalN].
#[inline]
pub fn xtal_n_clk(mut self) -> Self {
self.clksel_sys = ClkselSys::XtalN;
self.ref_clk_sel = RefClkSel::XtalN;
self.clksel_sys = ClockSelect::XtalN;
self.ref_clk_sel = ReferenceClockSelect::XtalN;
self
}
@@ -219,19 +220,19 @@ impl ClockConfigurator {
}
#[inline]
pub fn clksel_sys(mut self, clksel_sys: ClkselSys) -> Self {
pub fn clksel_sys(mut self, clksel_sys: ClockSelect) -> Self {
self.clksel_sys = clksel_sys;
self
}
#[inline]
pub fn pll_cfg(mut self, pll_cfg: PllCfg) -> Self {
pub fn pll_cfg(mut self, pll_cfg: PllConfig) -> Self {
self.pll_cfg = Some(pll_cfg);
self
}
#[inline]
pub fn ref_clk_sel(mut self, ref_clk_sel: RefClkSel) -> Self {
pub fn ref_clk_sel(mut self, ref_clk_sel: ReferenceClockSelect) -> Self {
self.ref_clk_sel = ref_clk_sel;
self
}
@@ -245,19 +246,22 @@ impl ClockConfigurator {
/// might have had a reason for those, so I am going to keep them. Chances are, this
/// process only has to be performed once, and it does not matter if it takes a few
/// microseconds or milliseconds longer.
pub fn freeze(self) -> Result<Clocks, ClkCfgError> {
pub fn freeze(self) -> Result<Clocks, ClockConfigError> {
// Sanitize configuration.
if self.source_clk.is_none() {
return Err(ClkCfgError::ClkSourceFreqNotSet);
return Err(ClockConfigError::ClkSourceFreqNotSet);
}
if self.clksel_sys == ClkselSys::XtalOsc && self.ref_clk_sel != RefClkSel::XtalOsc {
return Err(ClkCfgError::InconsistentCfg);
if self.clksel_sys == ClockSelect::XtalOsc
&& self.ref_clk_sel != ReferenceClockSelect::XtalOsc
{
return Err(ClockConfigError::InconsistentCfg);
}
if self.clksel_sys == ClkselSys::XtalN && self.ref_clk_sel != RefClkSel::XtalN {
return Err(ClkCfgError::InconsistentCfg);
if self.clksel_sys == ClockSelect::XtalN && self.ref_clk_sel != ReferenceClockSelect::XtalN
{
return Err(ClockConfigError::InconsistentCfg);
}
if self.clksel_sys == ClkselSys::Pll && self.pll_cfg.is_none() {
return Err(ClkCfgError::PllConfigNotSet);
if self.clksel_sys == ClockSelect::Pll && self.pll_cfg.is_none() {
return Err(ClockConfigError::PllConfigNotSet);
}
enable_peripheral_clock(PeripheralSelect::Clkgen);
@@ -268,11 +272,11 @@ impl ClockConfigurator {
// Therefore, we do it here as well.
self.clkgen
.ctrl0()
.modify(|_, w| unsafe { w.clksel_sys().bits(ClkselSys::Hbo as u8) });
.modify(|_, w| unsafe { w.clksel_sys().bits(ClockSelect::Hbo as u8) });
pll_setup_delay();
self.clkgen
.ctrl0()
.modify(|_, w| unsafe { w.clk_div_sel().bits(ClkDivSel::Div1 as u8) });
.modify(|_, w| unsafe { w.clk_div_sel().bits(ClockDivisorSelect::Div1 as u8) });
// Set up oscillator and PLL input clock.
self.clkgen
@@ -284,12 +288,12 @@ impl ClockConfigurator {
w
});
match self.ref_clk_sel {
RefClkSel::None => pll_setup_delay(),
RefClkSel::XtalOsc => {
ReferenceClockSelect::None => pll_setup_delay(),
ReferenceClockSelect::XtalOsc => {
self.clkgen.ctrl1().modify(|_, w| w.xtal_en().set_bit());
hbo_clock_delay_ms(XTAL_OSC_TSTART_MS);
}
RefClkSel::XtalN => {
ReferenceClockSelect::XtalN => {
self.clkgen.ctrl1().modify(|_, w| w.xtal_n_en().set_bit());
pll_setup_delay()
}
@@ -340,7 +344,7 @@ impl ClockConfigurator {
// This is what the HAL does. We could continue, but then we would at least
// have to somehow report a partial error.. Chances are, the user does not
// want to continue with a broken PLL clock.
return Err(ClkCfgError::PllInitError);
return Err(ClockConfigError::PllInitError);
}
}
}
@@ -360,7 +364,7 @@ impl ClockConfigurator {
self.clkgen
.ctrl0()
.modify(|_, w| unsafe { w.clk_div_sel().bits(self.clk_div_sel as u8) });
final_sysclk = clk_after_div(final_sysclk, self.clk_div_sel);
final_sysclk = clock_after_division(final_sysclk, self.clk_div_sel);
// The HAL does this. I don't know why..
pll_setup_delay();
@@ -383,14 +387,14 @@ impl ClockConfigurator {
// NOTE: Not using divide by 1 or /2 ratio in REVA silicon because of triggering issue
// For this reason, keep SYSCLK above 8MHz to have the ADC /4 ratio in range)
if final_sysclk.raw() <= ADC_MAX_CLK.raw() * 4 {
self.clkgen
.ctrl1()
.modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div4 as u8) });
self.clkgen.ctrl1().modify(|_, w| unsafe {
w.adc_clk_div_sel().bits(AdcClockDivisorSelect::Div4 as u8)
});
final_sysclk / 4
} else {
self.clkgen
.ctrl1()
.modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div8 as u8) });
self.clkgen.ctrl1().modify(|_, w| unsafe {
w.adc_clk_div_sel().bits(AdcClockDivisorSelect::Div8 as u8)
});
final_sysclk / 8
}
}
@@ -433,7 +437,7 @@ mod tests {
#[test]
fn test_basic_div() {
assert_eq!(
clk_after_div(Hertz::from_raw(10_000_000), super::ClkDivSel::Div2),
clock_after_division(Hertz::from_raw(10_000_000), super::ClockDivisorSelect::Div2),
Hertz::from_raw(5_000_000)
);
}

8
va416xx-hal/src/dac.rs
View File

@@ -16,13 +16,13 @@ pub type DacRegisterBlock = pac::dac0::RegisterBlock;
/// Common trait implemented by all PAC peripheral access structures. The register block
/// format is the same for all DAC blocks.
pub trait DacMarker: Deref<Target = DacRegisterBlock> {
pub trait DacInstance: Deref<Target = DacRegisterBlock> {
const IDX: u8;
fn ptr() -> *const DacRegisterBlock;
}
impl DacMarker for pac::Dac0 {
impl DacInstance for pac::Dac0 {
const IDX: u8 = 0;
#[inline(always)]
@@ -31,7 +31,7 @@ impl DacMarker for pac::Dac0 {
}
}
impl DacMarker for pac::Dac1 {
impl DacInstance for pac::Dac1 {
const IDX: u8 = 1;
#[inline(always)]
@@ -62,7 +62,7 @@ impl Dac {
/// Create a new [Dac] driver instance.
///
/// The [Clocks] structure is expected here as well to ensure the clock was set up properly.
pub fn new<Dac: DacMarker>(dac: Dac, dac_settling: DacSettling, _clocks: &Clocks) -> Self {
pub fn new<Dac: DacInstance>(dac: Dac, dac_settling: DacSettling, _clocks: &Clocks) -> Self {
enable_peripheral_clock(PeripheralSelect::Dac);
dac.ctrl1().write(|w| {

42
va416xx-hal/src/dma.rs
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@@ -89,41 +89,7 @@ pub enum RPower {
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct InvalidCtrlBlockAddrError;
/*
bitfield::bitfield! {
#[repr(transparent)]
#[derive(Clone, Copy)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct ChannelConfig(u32);
impl Debug;
u32;
pub raw, set_raw: 31,0;
u8;
pub dst_inc, set_dst_inc: 31, 30;
u8;
pub dst_size, set_dst_size: 29, 28;
u8;
pub src_inc, set_src_inc: 27, 26;
u8;
pub src_size, set_src_size: 25, 24;
u8;
pub dest_prot_ctrl, set_dest_prot_ctrl: 23, 21;
u8;
pub src_prot_ctrl, set_src_prot_ctrl: 20, 18;
u8;
pub r_power, set_r_power: 17, 14;
u16;
pub n_minus_1, set_n_minus_1: 13, 4;
bool;
pub next_useburst, set_next_useburst: 3;
u8;
pub cycle_ctrl, set_cycle_ctr: 2, 0;
}
*/
#[bitbybit::bitfield(u32, default = 0x0)]
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[bitbybit::bitfield(u32, default = 0x0, debug, defmt_fields(feature = "defmt"))]
pub struct ChannelConfig {
#[bits(30..=31, rw)]
dst_inc: AddrIncrement,
@@ -229,7 +195,7 @@ pub enum DmaTransferInitError {
#[derive(Debug, Clone, Copy, Default)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct DmaCfg {
pub struct DmaConfig {
pub bufferable: bool,
pub cacheable: bool,
pub privileged: bool,
@@ -531,7 +497,7 @@ impl Dma {
/// control block at a specific address.
pub fn new(
dma: pac::Dma,
cfg: DmaCfg,
cfg: DmaConfig,
ctrl_block: *mut DmaCtrlBlock,
) -> Result<Self, InvalidCtrlBlockAddrError> {
// The conversion to u32 is safe here because we are on a 32-bit system.
@@ -561,7 +527,7 @@ impl Dma {
}
#[inline(always)]
pub fn set_protection_bits(&self, cfg: &DmaCfg) {
pub fn set_protection_bits(&self, cfg: &DmaConfig) {
self.dma.cfg().write(|w| unsafe {
w.chnl_prot_ctrl().bits(
cfg.privileged as u8 | ((cfg.bufferable as u8) << 1) | ((cfg.cacheable as u8) << 2),

3
va416xx-hal/src/nvm.rs
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@@ -31,7 +31,8 @@ pub const FRAM_WRITE: u8 = 0x02;
pub const FRAM_RDID: u8 = 0x9F;
pub const FRAM_SLEEP: u8 = 0xB9;
/* Address Masks */
// Address Masks
const ADDR_MSB_MASK: u32 = 0xFF0000;
const ADDR_MID_MASK: u32 = 0x00FF00;
const ADDR_LSB_MASK: u32 = 0x0000FF;