Merge pull request 'Device specific support and UART Improvements' (#23) from device-specific-support into main
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Reviewed-on: #23
This commit is contained in:
Robin Müller 2024-07-19 06:47:25 +02:00
commit deebc88042
13 changed files with 261 additions and 129 deletions

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@ -21,7 +21,7 @@ jobs:
- uses: dtolnay/rust-toolchain@stable - uses: dtolnay/rust-toolchain@stable
- name: Install nextest - name: Install nextest
uses: taiki-e/install-action@nextest uses: taiki-e/install-action@nextest
- run: cargo nextest run --all-features -p va416xx-hal - run: cargo nextest run --features va41630 -p va416xx-hal
# I think we can skip those on an embedded crate.. # I think we can skip those on an embedded crate..
# - run: cargo test --doc -p va108xx-hal # - run: cargo test --doc -p va108xx-hal
@ -39,7 +39,7 @@ jobs:
steps: steps:
- uses: actions/checkout@v4 - uses: actions/checkout@v4
- uses: dtolnay/rust-toolchain@nightly - uses: dtolnay/rust-toolchain@nightly
- run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc --all-features - run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc --features va41630
clippy: clippy:
name: Clippy name: Clippy

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@ -36,7 +36,9 @@ pipeline {
} }
stage('Check Examples') { stage('Check Examples') {
steps { steps {
sh 'cargo check --target thumbv7em-none-eabihf --examples' sh """
cargo check --target thumbv7em-none-eabihf --examples
"""
} }
} }
} }

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@ -5,7 +5,6 @@ edition = "2021"
[dependencies] [dependencies]
cortex-m-rt = "0.7" cortex-m-rt = "0.7"
va416xx-hal = { path = "../../va416xx-hal" }
panic-rtt-target = { version = "0.1.3" } panic-rtt-target = { version = "0.1.3" }
rtt-target = { version = "0.5" } rtt-target = { version = "0.5" }
cortex-m = { version = "0.7", features = ["critical-section-single-core"] } cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
@ -14,5 +13,30 @@ embedded-hal-nb = "1"
nb = "1" nb = "1"
embedded-io = "0.6" embedded-io = "0.6"
panic-halt = "0.2" panic-halt = "0.2"
vorago-peb1 = { path = "../../vorago-peb1" }
accelerometer = "0.12" accelerometer = "0.12"
[dependencies.va416xx-hal]
path = "../../va416xx-hal"
[dependencies.vorago-peb1]
path = "../../vorago-peb1"
optional = true
[features]
default = []
va41630 = ["va416xx-hal/va41630", "has-adc-dac"]
va41629 = ["va416xx-hal/va41629", "has-adc-dac"]
va41628 = ["va416xx-hal/va41628"]
has-adc-dac = []
[[example]]
name = "peb1-accelerometer"
required-features = ["vorago-peb1"]
[[example]]
name = "dac-adc"
required-features = ["has-adc-dac"]
[[example]]
name = "adc"
required-features = ["has-adc-dac"]

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@ -6,14 +6,26 @@ All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/) The format is based on [Keep a Changelog](http://keepachangelog.com/)
and this project adheres to [Semantic Versioning](http://semver.org/). and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased] # [unreleased]
## [v0.2.0] # [v0.2.0]
- Documentation improvements - Documentation improvements
- Improved UART typing support: Validity of passed pins is now checked properly
## Changed
- Added `va41620`, `va41630`, `va41628` and `va41629` device features. A device now has to be
selected for HAL compilation to work properly
## Fixed
- Small fixes and improvements for ADC drivers - Small fixes and improvements for ADC drivers
## Added
- Added basic DMA driver - Added basic DMA driver
## [v0.1.0] 2024-07-01 # [v0.1.0] 2024-07-01
- Initial release with basic HAL drivers - Initial release with basic HAL drivers

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@ -1,6 +1,6 @@
[package] [package]
name = "va416xx-hal" name = "va416xx-hal"
version = "0.1.0" version = "0.2.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"] authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021" edition = "2021"
description = "HAL for the Vorago VA416xx family of MCUs" description = "HAL for the Vorago VA416xx family of MCUs"
@ -38,8 +38,16 @@ features = ["critical-section"]
default = ["rt", "revb"] default = ["rt", "revb"]
rt = ["va416xx/rt"] rt = ["va416xx/rt"]
defmt = ["dep:defmt", "fugit/defmt"] defmt = ["dep:defmt", "fugit/defmt"]
va41630 = ["device-selected"]
va41620 = ["device-selected"]
va41629 = ["device-selected"]
va41628 = ["device-selected"]
device-selected = []
revb = [] revb = []
[package.metadata.docs.rs] [package.metadata.docs.rs]
all-features = true features = ["va41630", "defmt"]
rustdoc-args = ["--generate-link-to-definition"] rustdoc-args = ["--generate-link-to-definition"]

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@ -11,6 +11,14 @@ raw PAC. This crate also implements traits specified by the
[embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with [embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with
various drivers in the embedded rust ecosystem. various drivers in the embedded rust ecosystem.
You have to enable one of the following device features to use this crate depending on
which chip you are using:
- `va41630`
- `va41629`
- `va41628`
- `va41620`
## Building ## Building
Building an application requires the `thumbv7em-none-eabihf` cross-compiler toolchain. Building an application requires the `thumbv7em-none-eabihf` cross-compiler toolchain.
@ -56,7 +64,7 @@ is contained within the
[dependencies.va416xx-hal] [dependencies.va416xx-hal]
version = "<Most Recent Version>" version = "<Most Recent Version>"
features = ["rt"] features = ["va41630"]
``` ```
6. Build the application with `cargo build` 6. Build the application with `cargo build`

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@ -10,6 +10,7 @@
//! # Examples //! # Examples
//! //!
//! - [UART example on the PEB1 board](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs) //! - [UART example on the PEB1 board](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/uart.rs)
#[cfg(not(feature = "va41628"))]
use crate::adc::ADC_MAX_CLK; use crate::adc::ADC_MAX_CLK;
use crate::pac; use crate::pac;
@ -447,11 +448,22 @@ impl ClkgenCfgr {
.ctrl0() .ctrl0()
.modify(|_, w| unsafe { w.clksel_sys().bits(self.clksel_sys as u8) }); .modify(|_, w| unsafe { w.clksel_sys().bits(self.clksel_sys as u8) });
Ok(Clocks {
sysclk: final_sysclk,
apb1: final_sysclk / 2,
apb2: final_sysclk / 4,
#[cfg(not(feature = "va41628"))]
adc_clk: self.cfg_adc_clk_div(final_sysclk),
})
}
#[cfg(not(feature = "va41628"))]
fn cfg_adc_clk_div(&self, final_sysclk: Hertz) -> Hertz {
// I will just do the ADC stuff like Vorago does it. // I will just do the ADC stuff like Vorago does it.
// ADC clock (must be 2-12.5 MHz) // ADC clock (must be 2-12.5 MHz)
// NOTE: Not using divide by 1 or /2 ratio in REVA silicon because of triggering issue // NOTE: Not using divide by 1 or /2 ratio in REVA silicon because of triggering issue
// For this reason, keep SYSCLK above 8MHz to have the ADC /4 ratio in range) // For this reason, keep SYSCLK above 8MHz to have the ADC /4 ratio in range)
let adc_clk = if final_sysclk.raw() <= ADC_MAX_CLK.raw() * 4 { if final_sysclk.raw() <= ADC_MAX_CLK.raw() * 4 {
self.clkgen self.clkgen
.ctrl1() .ctrl1()
.modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div4 as u8) }); .modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div4 as u8) });
@ -461,14 +473,7 @@ impl ClkgenCfgr {
.ctrl1() .ctrl1()
.modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div8 as u8) }); .modify(|_, w| unsafe { w.adc_clk_div_sel().bits(AdcClkDivSel::Div8 as u8) });
final_sysclk / 8 final_sysclk / 8
}; }
Ok(Clocks {
sysclk: final_sysclk,
apb1: final_sysclk / 2,
apb2: final_sysclk / 4,
adc_clk,
})
} }
} }
@ -483,6 +488,7 @@ pub struct Clocks {
sysclk: Hertz, sysclk: Hertz,
apb1: Hertz, apb1: Hertz,
apb2: Hertz, apb2: Hertz,
#[cfg(not(feature = "va41628"))]
adc_clk: Hertz, adc_clk: Hertz,
} }
@ -513,6 +519,7 @@ impl Clocks {
} }
/// Returns the ADC clock frequency which has a separate divider. /// Returns the ADC clock frequency which has a separate divider.
#[cfg(not(feature = "va41628"))]
pub fn adc_clk(&self) -> Hertz { pub fn adc_clk(&self) -> Hertz {
self.adc_clk self.adc_clk
} }

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@ -295,12 +295,17 @@ pub trait PinId: Sealed {
} }
macro_rules! pin_id { macro_rules! pin_id {
($Group:ident, $Id:ident, $NUM:literal) => { ($Group:ident, $Id:ident, $NUM:literal $(, $meta: meta)?) => {
// Need paste macro to use ident in doc attribute // Need paste macro to use ident in doc attribute
paste::paste! { paste::paste! {
$(#[$meta])?
#[doc = "Pin ID representing pin " $Id] #[doc = "Pin ID representing pin " $Id]
pub enum $Id {} pub enum $Id {}
$(#[$meta])?
impl Sealed for $Id {} impl Sealed for $Id {}
$(#[$meta])?
impl PinId for $Id { impl PinId for $Id {
const DYN: DynPinId = DynPinId { const DYN: DynPinId = DynPinId {
group: DynGroup::$Group, group: DynGroup::$Group,
@ -689,13 +694,14 @@ impl<I: PinId> Registers<I> {
macro_rules! pins { macro_rules! pins {
( (
$Port:ident, $PinsName:ident, $($Id:ident,)+, $Port:ident, $PinsName:ident, $($Id:ident $(, $meta:meta)?)+,
) => { ) => {
paste::paste!( paste::paste!(
/// Collection of all the individual [`Pin`]s for a given port (PORTA or PORTB) /// Collection of all the individual [`Pin`]s for a given port (PORTA or PORTB)
pub struct $PinsName { pub struct $PinsName {
port: $Port, port: $Port,
$( $(
$(#[$meta])?
#[doc = "Pin " $Id] #[doc = "Pin " $Id]
pub [<$Id:lower>]: Pin<$Id, Reset>, pub [<$Id:lower>]: Pin<$Id, Reset>,
)+ )+
@ -718,6 +724,7 @@ macro_rules! pins {
port, port,
// Safe because we only create one `Pin` per `PinId` // Safe because we only create one `Pin` per `PinId`
$( $(
$(#[$meta])?
[<$Id:lower>]: unsafe { Pin::new() }, [<$Id:lower>]: unsafe { Pin::new() },
)+ )+
} }
@ -739,13 +746,15 @@ macro_rules! pins {
} }
} }
//$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal $(, $meta:meta)?)),+]
//$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal, $meta: meta),)+]
macro_rules! declare_pins { macro_rules! declare_pins {
( (
$Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal),)+] $Group:ident, $PinsName:ident, $Port:ident, [$(($Id:ident, $NUM:literal $(, $meta:meta)?)),+]
) => { ) => {
pins!($Port, $PinsName, $($Id,)+,); pins!($Port, $PinsName, $($Id $(, $meta)?)+,);
$( $(
pin_id!($Group, $Id, $NUM); pin_id!($Group, $Id, $NUM $(, $meta)?);
)+ )+
} }
} }
@ -770,7 +779,7 @@ declare_pins!(
(PA12, 12), (PA12, 12),
(PA13, 13), (PA13, 13),
(PA14, 14), (PA14, 14),
(PA15, 15), (PA15, 15)
] ]
); );
@ -784,17 +793,17 @@ declare_pins!(
(PB2, 2), (PB2, 2),
(PB3, 3), (PB3, 3),
(PB4, 4), (PB4, 4),
(PB5, 5), (PB5, 5, cfg(not(feature = "va41628"))),
(PB6, 6), (PB6, 6, cfg(not(feature = "va41628"))),
(PB7, 7), (PB7, 7, cfg(not(feature = "va41628"))),
(PB8, 8), (PB8, 8, cfg(not(feature = "va41628"))),
(PB9, 9), (PB9, 9, cfg(not(feature = "va41628"))),
(PB10, 10), (PB10, 10, cfg(not(feature = "va41628"))),
(PB11, 11), (PB11, 11, cfg(not(feature = "va41628"))),
(PB12, 12), (PB12, 12),
(PB13, 13), (PB13, 13),
(PB14, 14), (PB14, 14),
(PB15, 15), (PB15, 15)
] ]
); );
@ -816,9 +825,9 @@ declare_pins!(
(PC10, 10), (PC10, 10),
(PC11, 11), (PC11, 11),
(PC12, 12), (PC12, 12),
(PC13, 13), (PC13, 13, cfg(not(feature = "va41628"))),
(PC14, 14), (PC14, 14),
(PC15, 15), (PC15, 15, cfg(not(feature = "va41628")))
] ]
); );
@ -827,22 +836,22 @@ declare_pins!(
PinsD, PinsD,
Portd, Portd,
[ [
(PD0, 0), (PD0, 0, cfg(not(feature = "va41628"))),
(PD1, 1), (PD1, 1, cfg(not(feature = "va41628"))),
(PD2, 2), (PD2, 2, cfg(not(feature = "va41628"))),
(PD3, 3), (PD3, 3, cfg(not(feature = "va41628"))),
(PD4, 4), (PD4, 4, cfg(not(feature = "va41628"))),
(PD5, 5), (PD5, 5, cfg(not(feature = "va41628"))),
(PD6, 6), (PD6, 6, cfg(not(feature = "va41628"))),
(PD7, 7), (PD7, 7, cfg(not(feature = "va41628"))),
(PD8, 8), (PD8, 8, cfg(not(feature = "va41628"))),
(PD9, 9), (PD9, 9, cfg(not(feature = "va41628"))),
(PD10, 10), (PD10, 10),
(PD11, 11), (PD11, 11),
(PD12, 12), (PD12, 12),
(PD13, 13), (PD13, 13),
(PD14, 14), (PD14, 14),
(PD15, 15), (PD15, 15)
] ]
); );
@ -861,12 +870,12 @@ declare_pins!(
(PE7, 7), (PE7, 7),
(PE8, 8), (PE8, 8),
(PE9, 9), (PE9, 9),
(PE10, 10), (PE10, 10, cfg(not(feature = "va41628"))),
(PE11, 11), (PE11, 11, cfg(not(feature = "va41628"))),
(PE12, 12), (PE12, 12),
(PE13, 13), (PE13, 13),
(PE14, 14), (PE14, 14),
(PE15, 15), (PE15, 15)
] ]
); );
@ -877,20 +886,20 @@ declare_pins!(
[ [
(PF0, 0), (PF0, 0),
(PF1, 1), (PF1, 1),
(PF2, 2), (PF2, 2, cfg(not(feature = "va41628"))),
(PF3, 3), (PF3, 3, cfg(not(feature = "va41628"))),
(PF4, 4), (PF4, 4, cfg(not(feature = "va41628"))),
(PF5, 5), (PF5, 5, cfg(not(feature = "va41628"))),
(PF6, 6), (PF6, 6, cfg(not(feature = "va41628"))),
(PF7, 7), (PF7, 7, cfg(not(feature = "va41628"))),
(PF8, 8), (PF8, 8, cfg(not(feature = "va41628"))),
(PF9, 9), (PF9, 9),
(PF10, 10), (PF10, 10, cfg(not(feature = "va41628"))),
(PF11, 11), (PF11, 11),
(PF12, 12), (PF12, 12),
(PF13, 13), (PF13, 13),
(PF14, 14), (PF14, 14),
(PF15, 15), (PF15, 15)
] ]
); );
@ -906,6 +915,6 @@ declare_pins!(
(PG4, 4), (PG4, 4),
(PG5, 5), (PG5, 5),
(PG6, 6), (PG6, 6),
(PG7, 7), (PG7, 7)
] ]
); );

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@ -3,14 +3,21 @@
#[cfg(test)] #[cfg(test)]
extern crate std; extern crate std;
#[cfg(not(feature = "device-selected"))]
compile_error!(
"This crate requires one of the following device features enabled:
va41630
va41629
va41628
"
);
pub use va416xx as device; pub use va416xx as device;
pub use va416xx as pac; pub use va416xx as pac;
pub mod prelude; pub mod prelude;
pub mod adc;
pub mod clock; pub mod clock;
pub mod dac;
pub mod dma; pub mod dma;
pub mod gpio; pub mod gpio;
pub mod i2c; pub mod i2c;
@ -22,6 +29,11 @@ pub mod typelevel;
pub mod uart; pub mod uart;
pub mod wdt; pub mod wdt;
#[cfg(not(feature = "va41628"))]
pub mod adc;
#[cfg(not(feature = "va41628"))]
pub mod dac;
#[derive(Debug, Eq, Copy, Clone, PartialEq)] #[derive(Debug, Eq, Copy, Clone, PartialEq)]
pub enum FunSel { pub enum FunSel {
Sel0 = 0b00, Sel0 = 0b00,

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@ -11,15 +11,17 @@ use crate::{
clock::{PeripheralSelect, SyscfgExt}, clock::{PeripheralSelect, SyscfgExt},
gpio::{ gpio::{
AltFunc1, AltFunc2, AltFunc3, Pin, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PB0, AltFunc1, AltFunc2, AltFunc3, Pin, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PB0,
PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PC0, PC1, PB1, PB12, PB13, PB14, PB15, PB2, PB3, PB4, PC0, PC1, PC10, PC11, PC7, PC8, PC9, PE12,
PC10, PC11, PC7, PC8, PC9, PE10, PE11, PE12, PE13, PE14, PE15, PE5, PE6, PE7, PE8, PE9, PE13, PE14, PE15, PE5, PE6, PE7, PE8, PE9, PF0, PF1, PG2, PG3, PG4,
PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PG2, PG3, PG4,
}, },
pac, pac,
time::Hertz, time::Hertz,
typelevel::{NoneT, Sealed}, typelevel::{NoneT, Sealed},
}; };
#[cfg(not(feature = "va41628"))]
use crate::gpio::{PB10, PB11, PB5, PB6, PB7, PB8, PB9, PE10, PE11, PF2, PF3, PF4, PF5, PF6, PF7};
//================================================================================================== //==================================================================================================
// Defintions // Defintions
//================================================================================================== //==================================================================================================
@ -75,15 +77,20 @@ pub trait OptionalHwCs<Spi>: HwCsProvider + Sealed {}
macro_rules! hw_cs_pins { macro_rules! hw_cs_pins {
($SPIx:path, $portId: path: ($SPIx:path, $portId: path:
$( $(
($PXx:ident, $AFx:ident, $HwCsIdent:path, $typedef:ident), ($PXx:ident, $AFx:ident, $HwCsIdent:path, $typedef:ident $(, $meta: meta)?),
)+ )+
) => { ) => {
$( $(
$(#[$meta])?
impl HwCsProvider for Pin<$PXx, $AFx> { impl HwCsProvider for Pin<$PXx, $AFx> {
const CS_ID: HwChipSelectId = $HwCsIdent; const CS_ID: HwChipSelectId = $HwCsIdent;
const SPI_ID: SpiId = $portId; const SPI_ID: SpiId = $portId;
} }
$(#[$meta])?
impl OptionalHwCs<$SPIx> for Pin<$PXx, $AFx> {} impl OptionalHwCs<$SPIx> for Pin<$PXx, $AFx> {}
$(#[$meta])?
pub type $typedef = Pin<$PXx, $AFx>; pub type $typedef = Pin<$PXx, $AFx>;
)+ )+
}; };
@ -106,9 +113,11 @@ impl PinMosi<pac::Spi0> for Pin<PC1, AltFunc1> {}
impl PinMiso<pac::Spi0> for Pin<PC0, AltFunc1> {} impl PinMiso<pac::Spi0> for Pin<PC0, AltFunc1> {}
// SPI 1 // SPI 1
#[cfg(not(feature = "va41628"))]
impl PinSck<pac::Spi1> for Pin<PB8, AltFunc3> {} impl PinSck<pac::Spi1> for Pin<PB8, AltFunc3> {}
#[cfg(not(feature = "va41628"))]
impl PinMosi<pac::Spi1> for Pin<PB10, AltFunc3> {} impl PinMosi<pac::Spi1> for Pin<PB10, AltFunc3> {}
#[cfg(not(feature = "va41628"))]
impl PinMiso<pac::Spi1> for Pin<PB9, AltFunc3> {} impl PinMiso<pac::Spi1> for Pin<PB9, AltFunc3> {}
impl PinSck<pac::Spi1> for Pin<PC9, AltFunc2> {} impl PinSck<pac::Spi1> for Pin<PC9, AltFunc2> {}
@ -122,8 +131,11 @@ impl PinSck<pac::Spi1> for Pin<PE13, AltFunc2> {}
impl PinMosi<pac::Spi1> for Pin<PE15, AltFunc2> {} impl PinMosi<pac::Spi1> for Pin<PE15, AltFunc2> {}
impl PinMiso<pac::Spi1> for Pin<PE14, AltFunc2> {} impl PinMiso<pac::Spi1> for Pin<PE14, AltFunc2> {}
#[cfg(not(feature = "va41628"))]
impl PinSck<pac::Spi1> for Pin<PF3, AltFunc1> {} impl PinSck<pac::Spi1> for Pin<PF3, AltFunc1> {}
#[cfg(not(feature = "va41628"))]
impl PinMosi<pac::Spi1> for Pin<PF5, AltFunc1> {} impl PinMosi<pac::Spi1> for Pin<PF5, AltFunc1> {}
#[cfg(not(feature = "va41628"))]
impl PinMiso<pac::Spi1> for Pin<PF4, AltFunc1> {} impl PinMiso<pac::Spi1> for Pin<PF4, AltFunc1> {}
// SPI 2 // SPI 2
@ -132,8 +144,11 @@ impl PinSck<pac::Spi2> for Pin<PA5, AltFunc2> {}
impl PinMosi<pac::Spi2> for Pin<PA7, AltFunc2> {} impl PinMosi<pac::Spi2> for Pin<PA7, AltFunc2> {}
impl PinMiso<pac::Spi2> for Pin<PA6, AltFunc2> {} impl PinMiso<pac::Spi2> for Pin<PA6, AltFunc2> {}
#[cfg(not(feature = "va41628"))]
impl PinSck<pac::Spi2> for Pin<PF5, AltFunc2> {} impl PinSck<pac::Spi2> for Pin<PF5, AltFunc2> {}
#[cfg(not(feature = "va41628"))]
impl PinMosi<pac::Spi2> for Pin<PF7, AltFunc2> {} impl PinMosi<pac::Spi2> for Pin<PF7, AltFunc2> {}
#[cfg(not(feature = "va41628"))]
impl PinMiso<pac::Spi2> for Pin<PF6, AltFunc2> {} impl PinMiso<pac::Spi2> for Pin<PF6, AltFunc2> {}
// SPI3 is shared with the ROM SPI pins and has its own dedicated pins. // SPI3 is shared with the ROM SPI pins and has its own dedicated pins.
@ -145,14 +160,14 @@ hw_cs_pins!(
(PB14, AltFunc1, HwChipSelectId::Id0, HwCs0Spi0), (PB14, AltFunc1, HwChipSelectId::Id0, HwCs0Spi0),
(PB13, AltFunc1, HwChipSelectId::Id1, HwCs1Spi0), (PB13, AltFunc1, HwChipSelectId::Id1, HwCs1Spi0),
(PB12, AltFunc1, HwChipSelectId::Id2, HwCs2Spi0), (PB12, AltFunc1, HwChipSelectId::Id2, HwCs2Spi0),
(PB11, AltFunc1, HwChipSelectId::Id3, HwCs3Spi0), (PB11, AltFunc1, HwChipSelectId::Id3, HwCs3Spi0, cfg(not(feature="va41628"))),
); );
hw_cs_pins!( hw_cs_pins!(
pac::Spi1, SpiId::Spi1: pac::Spi1, SpiId::Spi1:
(PB7, AltFunc3, HwChipSelectId::Id0, HwCs0Spi1Pb), (PB7, AltFunc3, HwChipSelectId::Id0, HwCs0Spi1Pb, cfg(not(feature="va41628"))),
(PB6, AltFunc3, HwChipSelectId::Id1, HwCs1Spi1Pb), (PB6, AltFunc3, HwChipSelectId::Id1, HwCs1Spi1Pb, cfg(not(feature="va41628"))),
(PB5, AltFunc3, HwChipSelectId::Id2, HwCs2Spi1Pb), (PB5, AltFunc3, HwChipSelectId::Id2, HwCs2Spi1Pb, cfg(not(feature="va41628"))),
(PB4, AltFunc3, HwChipSelectId::Id3, HwCs3Spi1Pb), (PB4, AltFunc3, HwChipSelectId::Id3, HwCs3Spi1Pb),
(PB3, AltFunc3, HwChipSelectId::Id4, HwCs4Spi1Pb), (PB3, AltFunc3, HwChipSelectId::Id4, HwCs4Spi1Pb),
(PB2, AltFunc3, HwChipSelectId::Id5, HwCs5Spi1Pb), (PB2, AltFunc3, HwChipSelectId::Id5, HwCs5Spi1Pb),
@ -161,14 +176,14 @@ hw_cs_pins!(
(PC8, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pc), (PC8, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pc),
(PC7, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pc), (PC7, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pc),
(PE12, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pe), (PE12, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pe),
(PE11, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pe), (PE11, AltFunc2, HwChipSelectId::Id1, HwCs1Spi1Pe, cfg(not(feature="va41628"))),
(PE10, AltFunc2, HwChipSelectId::Id2, HwCs2Spi1Pe), (PE10, AltFunc2, HwChipSelectId::Id2, HwCs2Spi1Pe, cfg(not(feature="va41628"))),
(PE9, AltFunc2, HwChipSelectId::Id3, HwCs3Spi1Pe), (PE9, AltFunc2, HwChipSelectId::Id3, HwCs3Spi1Pe),
(PE8, AltFunc2, HwChipSelectId::Id4, HwCs4Spi1Pe), (PE8, AltFunc2, HwChipSelectId::Id4, HwCs4Spi1Pe),
(PE7, AltFunc3, HwChipSelectId::Id5, HwCs5Spi1Pe), (PE7, AltFunc3, HwChipSelectId::Id5, HwCs5Spi1Pe),
(PE6, AltFunc3, HwChipSelectId::Id6, HwCs6Spi1Pe), (PE6, AltFunc3, HwChipSelectId::Id6, HwCs6Spi1Pe),
(PE5, AltFunc3, HwChipSelectId::Id7, HwCs7Spi1Pe), (PE5, AltFunc3, HwChipSelectId::Id7, HwCs7Spi1Pe),
(PF2, AltFunc1, HwChipSelectId::Id0, HwCs0Spi1Pf), (PF2, AltFunc1, HwChipSelectId::Id0, HwCs0Spi1Pf, cfg(not(feature="va41628"))),
(PG2, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pg), (PG2, AltFunc2, HwChipSelectId::Id0, HwCs0Spi1Pg),
); );
@ -183,9 +198,9 @@ hw_cs_pins!(
(PA9, AltFunc2, HwChipSelectId::Id5, HwCs5Spi2Pa), (PA9, AltFunc2, HwChipSelectId::Id5, HwCs5Spi2Pa),
(PF0, AltFunc2, HwChipSelectId::Id4, HwCs4Spi2Pf), (PF0, AltFunc2, HwChipSelectId::Id4, HwCs4Spi2Pf),
(PF1, AltFunc2, HwChipSelectId::Id3, HwCs3Spi2Pf), (PF1, AltFunc2, HwChipSelectId::Id3, HwCs3Spi2Pf),
(PF2, AltFunc2, HwChipSelectId::Id2, HwCs2Spi2Pf), (PF2, AltFunc2, HwChipSelectId::Id2, HwCs2Spi2Pf, cfg(not(feature="va41628"))),
(PF3, AltFunc2, HwChipSelectId::Id1, HwCs1Spi2Pf), (PF3, AltFunc2, HwChipSelectId::Id1, HwCs1Spi2Pf, cfg(not(feature="va41628"))),
(PF4, AltFunc2, HwChipSelectId::Id0, HwCs0Spi2Pf), (PF4, AltFunc2, HwChipSelectId::Id0, HwCs0Spi2Pf, cfg(not(feature="va41628"))),
); );
//================================================================================================== //==================================================================================================

View File

@ -10,12 +10,17 @@ use cortex_m::interrupt::Mutex;
use crate::clock::Clocks; use crate::clock::Clocks;
use crate::gpio::{ use crate::gpio::{
AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14, AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14,
PA15, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PB10, PB11, PB12, PB13, PB14, PB15, PB2, PB3, PA15, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PB12, PB13, PB14, PB15, PB2, PB3, PB4, PC0, PC1,
PB4, PB5, PB6, PB7, PB8, PB9, PC0, PC1, PD0, PD1, PD10, PD11, PD12, PD13, PD14, PD15, PD2, PD3, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE12, PE13, PE14, PE15, PE2, PE3, PE4, PE5, PE6,
PD4, PD5, PD6, PD7, PD8, PD9, PE0, PE1, PE10, PE11, PE12, PE13, PE14, PE15, PE2, PE3, PE4, PE5, PE7, PE8, PE9, PF0, PF1, PF11, PF12, PF13, PF14, PF15, PF9, PG0, PG1, PG2, PG3, PG6,
PE6, PE7, PE8, PE9, PF0, PF1, PF10, PF11, PF12, PF13, PF14, PF15, PF2, PF3, PF4, PF5, PF6, PF7,
PF8, PF9, PG0, PG1, PG2, PG3, PG6,
}; };
#[cfg(not(feature = "va41628"))]
use crate::gpio::{
PB10, PB11, PB5, PB6, PB7, PB8, PB9, PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PE10,
PE11, PF10, PF2, PF3, PF4, PF5, PF6, PF7, PF8,
};
use crate::time::Hertz; use crate::time::Hertz;
use crate::typelevel::Sealed; use crate::typelevel::Sealed;
use crate::{disable_interrupt, prelude::*}; use crate::{disable_interrupt, prelude::*};
@ -196,10 +201,11 @@ pub trait ValidTimAndPin<Pin: TimPin, Tim: ValidTim>: Sealed {}
macro_rules! valid_pin_and_tims { macro_rules! valid_pin_and_tims {
( (
$( $(
($PinX:ident, $AltFunc:ident, $TimX:path), ($PinX:ident, $AltFunc:ident, $TimX:path $(, $meta: meta)?),
)+ )+
) => { ) => {
$( $(
$(#[$meta])?
impl TimPin for Pin<$PinX, $AltFunc> impl TimPin for Pin<$PinX, $AltFunc>
where where
$PinX: PinId, $PinX: PinId,
@ -207,6 +213,7 @@ macro_rules! valid_pin_and_tims {
const DYN: DynPinId = $PinX::DYN; const DYN: DynPinId = $PinX::DYN;
} }
$(#[$meta])?
impl< impl<
PinInstance: TimPin, PinInstance: TimPin,
Tim: ValidTim Tim: ValidTim
@ -217,6 +224,7 @@ macro_rules! valid_pin_and_tims {
{ {
} }
$(#[$meta])?
impl Sealed for (Pin<$PinX, $AltFunc>, $TimX) {} impl Sealed for (Pin<$PinX, $AltFunc>, $TimX) {}
)+ )+
}; };
@ -242,29 +250,29 @@ valid_pin_and_tims!(
(PB2, AltFunc2, pac::Tim15), (PB2, AltFunc2, pac::Tim15),
(PB3, AltFunc2, pac::Tim14), (PB3, AltFunc2, pac::Tim14),
(PB4, AltFunc2, pac::Tim13), (PB4, AltFunc2, pac::Tim13),
(PB5, AltFunc2, pac::Tim12), (PB5, AltFunc2, pac::Tim12, cfg(not(feature = "va41628"))),
(PB6, AltFunc2, pac::Tim11), (PB6, AltFunc2, pac::Tim11, cfg(not(feature = "va41628"))),
(PB7, AltFunc2, pac::Tim10), (PB7, AltFunc2, pac::Tim10, cfg(not(feature = "va41628"))),
(PB8, AltFunc2, pac::Tim9), (PB8, AltFunc2, pac::Tim9, cfg(not(feature = "va41628"))),
(PB9, AltFunc2, pac::Tim8), (PB9, AltFunc2, pac::Tim8, cfg(not(feature = "va41628"))),
(PB10, AltFunc2, pac::Tim7), (PB10, AltFunc2, pac::Tim7, cfg(not(feature = "va41628"))),
(PB11, AltFunc2, pac::Tim6), (PB11, AltFunc2, pac::Tim6, cfg(not(feature = "va41628"))),
(PB12, AltFunc2, pac::Tim5), (PB12, AltFunc2, pac::Tim5),
(PB13, AltFunc2, pac::Tim4), (PB13, AltFunc2, pac::Tim4),
(PB14, AltFunc2, pac::Tim3), (PB14, AltFunc2, pac::Tim3),
(PB15, AltFunc2, pac::Tim2), (PB15, AltFunc2, pac::Tim2),
(PC0, AltFunc2, pac::Tim1), (PC0, AltFunc2, pac::Tim1),
(PC1, AltFunc2, pac::Tim0), (PC1, AltFunc2, pac::Tim0),
(PD0, AltFunc2, pac::Tim0), (PD0, AltFunc2, pac::Tim0, cfg(not(feature = "va41628"))),
(PD1, AltFunc2, pac::Tim1), (PD1, AltFunc2, pac::Tim1, cfg(not(feature = "va41628"))),
(PD2, AltFunc2, pac::Tim2), (PD2, AltFunc2, pac::Tim2, cfg(not(feature = "va41628"))),
(PD3, AltFunc2, pac::Tim3), (PD3, AltFunc2, pac::Tim3, cfg(not(feature = "va41628"))),
(PD4, AltFunc2, pac::Tim4), (PD4, AltFunc2, pac::Tim4, cfg(not(feature = "va41628"))),
(PD5, AltFunc2, pac::Tim5), (PD5, AltFunc2, pac::Tim5, cfg(not(feature = "va41628"))),
(PD6, AltFunc2, pac::Tim6), (PD6, AltFunc2, pac::Tim6, cfg(not(feature = "va41628"))),
(PD7, AltFunc2, pac::Tim7), (PD7, AltFunc2, pac::Tim7, cfg(not(feature = "va41628"))),
(PD8, AltFunc2, pac::Tim8), (PD8, AltFunc2, pac::Tim8, cfg(not(feature = "va41628"))),
(PD9, AltFunc2, pac::Tim9), (PD9, AltFunc2, pac::Tim9, cfg(not(feature = "va41628"))),
(PD10, AltFunc2, pac::Tim10), (PD10, AltFunc2, pac::Tim10),
(PD11, AltFunc2, pac::Tim11), (PD11, AltFunc2, pac::Tim11),
(PD12, AltFunc2, pac::Tim12), (PD12, AltFunc2, pac::Tim12),
@ -281,23 +289,23 @@ valid_pin_and_tims!(
(PE7, AltFunc2, pac::Tim23), (PE7, AltFunc2, pac::Tim23),
(PE8, AltFunc3, pac::Tim16), (PE8, AltFunc3, pac::Tim16),
(PE9, AltFunc3, pac::Tim17), (PE9, AltFunc3, pac::Tim17),
(PE10, AltFunc3, pac::Tim18), (PE10, AltFunc3, pac::Tim18, cfg(not(feature = "va41628"))),
(PE11, AltFunc3, pac::Tim19), (PE11, AltFunc3, pac::Tim19, cfg(not(feature = "va41628"))),
(PE12, AltFunc3, pac::Tim20), (PE12, AltFunc3, pac::Tim20),
(PE13, AltFunc3, pac::Tim21), (PE13, AltFunc3, pac::Tim21),
(PE14, AltFunc3, pac::Tim22), (PE14, AltFunc3, pac::Tim22),
(PE15, AltFunc3, pac::Tim23), (PE15, AltFunc3, pac::Tim23),
(PF0, AltFunc3, pac::Tim0), (PF0, AltFunc3, pac::Tim0),
(PF1, AltFunc3, pac::Tim1), (PF1, AltFunc3, pac::Tim1),
(PF2, AltFunc3, pac::Tim2), (PF2, AltFunc3, pac::Tim2, cfg(not(feature = "va41628"))),
(PF3, AltFunc3, pac::Tim3), (PF3, AltFunc3, pac::Tim3, cfg(not(feature = "va41628"))),
(PF4, AltFunc3, pac::Tim4), (PF4, AltFunc3, pac::Tim4, cfg(not(feature = "va41628"))),
(PF5, AltFunc3, pac::Tim5), (PF5, AltFunc3, pac::Tim5, cfg(not(feature = "va41628"))),
(PF6, AltFunc3, pac::Tim6), (PF6, AltFunc3, pac::Tim6, cfg(not(feature = "va41628"))),
(PF7, AltFunc3, pac::Tim7), (PF7, AltFunc3, pac::Tim7, cfg(not(feature = "va41628"))),
(PF8, AltFunc3, pac::Tim8), (PF8, AltFunc3, pac::Tim8, cfg(not(feature = "va41628"))),
(PF9, AltFunc3, pac::Tim9), (PF9, AltFunc3, pac::Tim9),
(PF10, AltFunc3, pac::Tim10), (PF10, AltFunc3, pac::Tim10, cfg(not(feature = "va41628"))),
(PF11, AltFunc3, pac::Tim11), (PF11, AltFunc3, pac::Tim11),
(PF12, AltFunc3, pac::Tim12), (PF12, AltFunc3, pac::Tim12),
(PF13, AltFunc2, pac::Tim19), (PF13, AltFunc2, pac::Tim19),

View File

@ -10,31 +10,55 @@ use embedded_hal_nb::serial::Read;
use fugit::RateExtU32; use fugit::RateExtU32;
use crate::clock::{Clocks, PeripheralSelect, SyscfgExt}; use crate::clock::{Clocks, PeripheralSelect, SyscfgExt};
use crate::gpio::{AltFunc1, Pin, PD11, PD12, PE2, PE3, PF11, PF12, PF8, PF9, PG0, PG1}; use crate::gpio::PF13;
use crate::time::Hertz; use crate::time::Hertz;
use crate::{disable_interrupt, enable_interrupt}; use crate::{disable_interrupt, enable_interrupt};
use crate::{ use crate::{
gpio::{AltFunc2, AltFunc3, PA2, PA3, PB14, PB15, PC14, PC15, PC4, PC5}, gpio::{
AltFunc1, AltFunc2, AltFunc3, Pin, PA2, PA3, PB14, PB15, PC14, PC4, PC5, PD11, PD12, PE2,
PE3, PF12, PF9, PG0, PG1,
},
pac::{self, uart0 as uart_base, Uart0, Uart1, Uart2}, pac::{self, uart0 as uart_base, Uart0, Uart1, Uart2},
}; };
#[cfg(not(feature = "va41628"))]
use crate::gpio::{PC15, PF8};
//================================================================================================== //==================================================================================================
// Type-Level support // Type-Level support
//================================================================================================== //==================================================================================================
pub trait TxRxPins<Uart> {} pub trait RxPin<Uart> {}
pub trait TxPin<Uart> {}
impl TxRxPins<Uart0> for (Pin<PA2, AltFunc3>, Pin<PA3, AltFunc3>) {} impl TxPin<Uart0> for Pin<PA2, AltFunc3> {}
impl TxRxPins<Uart0> for (Pin<PC4, AltFunc2>, Pin<PC5, AltFunc2>) {} impl RxPin<Uart0> for Pin<PA3, AltFunc3> {}
impl TxRxPins<Uart0> for (Pin<PE2, AltFunc3>, Pin<PE3, AltFunc3>) {}
impl TxRxPins<Uart0> for (Pin<PG0, AltFunc1>, Pin<PG1, AltFunc1>) {}
impl TxRxPins<Uart1> for (Pin<PB14, AltFunc3>, Pin<PB15, AltFunc3>) {} impl TxPin<Uart0> for Pin<PC4, AltFunc2> {}
impl TxRxPins<Uart1> for (Pin<PD11, AltFunc3>, Pin<PD12, AltFunc3>) {} impl RxPin<Uart0> for Pin<PC5, AltFunc2> {}
impl TxRxPins<Uart1> for (Pin<PF11, AltFunc1>, Pin<PF12, AltFunc1>) {}
impl TxRxPins<Uart2> for (Pin<PC14, AltFunc2>, Pin<PC15, AltFunc2>) {} impl TxPin<Uart0> for Pin<PE2, AltFunc3> {}
impl TxRxPins<Uart2> for (Pin<PF8, AltFunc1>, Pin<PF9, AltFunc1>) {} impl RxPin<Uart0> for Pin<PE3, AltFunc3> {}
impl TxPin<Uart0> for Pin<PG0, AltFunc1> {}
impl RxPin<Uart0> for Pin<PG1, AltFunc1> {}
impl TxPin<Uart1> for Pin<PB14, AltFunc3> {}
impl RxPin<Uart1> for Pin<PB15, AltFunc3> {}
impl TxPin<Uart1> for Pin<PD11, AltFunc3> {}
impl RxPin<Uart1> for Pin<PD12, AltFunc3> {}
impl TxPin<Uart1> for Pin<PF12, AltFunc1> {}
impl RxPin<Uart1> for Pin<PF13, AltFunc1> {}
impl TxPin<Uart2> for Pin<PC14, AltFunc2> {}
#[cfg(not(feature = "va41628"))]
impl RxPin<Uart2> for Pin<PC15, AltFunc2> {}
#[cfg(not(feature = "va41628"))]
impl TxPin<Uart2> for Pin<PF8, AltFunc1> {}
impl RxPin<Uart2> for Pin<PF9, AltFunc1> {}
//================================================================================================== //==================================================================================================
// Regular Definitions // Regular Definitions
@ -511,10 +535,12 @@ impl<Uart: Instance> UartBase<Uart> {
} }
} }
impl<UartInstance: Instance, Pins> Uart<UartInstance, Pins> { impl<TxPinInst: TxPin<UartInstance>, RxPinInst: RxPin<UartInstance>, UartInstance: Instance>
Uart<UartInstance, (TxPinInst, RxPinInst)>
{
pub fn new( pub fn new(
uart: UartInstance, uart: UartInstance,
pins: Pins, pins: (TxPinInst, RxPinInst),
config: impl Into<Config>, config: impl Into<Config>,
syscfg: &mut va416xx::Sysconfig, syscfg: &mut va416xx::Sysconfig,
clocks: &Clocks, clocks: &Clocks,
@ -535,7 +561,7 @@ impl<UartInstance: Instance, Pins> Uart<UartInstance, Pins> {
pub fn new_with_clock_freq( pub fn new_with_clock_freq(
uart: UartInstance, uart: UartInstance,
pins: Pins, pins: (TxPinInst, RxPinInst),
config: impl Into<Config>, config: impl Into<Config>,
syscfg: &mut va416xx::Sysconfig, syscfg: &mut va416xx::Sysconfig,
clock: impl Into<Hertz>, clock: impl Into<Hertz>,
@ -567,7 +593,7 @@ impl<UartInstance: Instance, Pins> Uart<UartInstance, Pins> {
/// If the IRQ capabilities of the peripheral are used, the UART needs to be converted /// If the IRQ capabilities of the peripheral are used, the UART needs to be converted
/// with this function /// with this function
pub fn into_uart_with_irq(self) -> UartWithIrq<UartInstance, Pins> { pub fn into_uart_with_irq(self) -> UartWithIrq<UartInstance, (TxPinInst, RxPinInst)> {
let (inner, pins) = self.downgrade_internal(); let (inner, pins) = self.downgrade_internal();
UartWithIrq { UartWithIrq {
pins, pins,
@ -608,7 +634,7 @@ impl<UartInstance: Instance, Pins> Uart<UartInstance, Pins> {
} }
} }
fn downgrade_internal(self) -> (UartBase<UartInstance>, Pins) { fn downgrade_internal(self) -> (UartBase<UartInstance>, (TxPinInst, RxPinInst)) {
let base = UartBase { let base = UartBase {
uart: self.inner.uart, uart: self.inner.uart,
tx: self.inner.tx, tx: self.inner.tx,
@ -625,7 +651,7 @@ impl<UartInstance: Instance, Pins> Uart<UartInstance, Pins> {
} }
} }
pub fn release(self) -> (UartInstance, Pins) { pub fn release(self) -> (UartInstance, (TxPinInst, RxPinInst)) {
(self.inner.release(), self.pins) (self.inner.release(), self.pins)
} }
} }

View File

@ -17,7 +17,8 @@ embedded-hal = "1"
[dependencies.va416xx-hal] [dependencies.va416xx-hal]
path = "../va416xx-hal" path = "../va416xx-hal"
version = "0.1.0" features = ["va41630"]
version = "0.2.0"
[dependencies.lis2dh12] [dependencies.lis2dh12]
git = "https://github.com/us-irs/lis2dh12.git" git = "https://github.com/us-irs/lis2dh12.git"