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Author SHA1 Message Date
ac601d06cc
big progress
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2024-09-11 20:42:16 +02:00
daa181d1de
remove .cargo folder
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2024-09-11 18:55:31 +02:00
46937f5bf9
try to test this 2024-09-11 18:55:15 +02:00
1b313d21c4
implement CRC write
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2024-09-11 17:26:31 +02:00
1cc8645781
add original memory.x
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2024-07-12 10:56:05 +02:00
d7b01c12a4
update gitignore
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2024-07-12 10:51:47 +02:00
e8a18548b0
update config file 2024-07-12 10:51:30 +02:00
ac015d1473
continue flash loader
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2024-07-12 10:44:41 +02:00
c53702ee74
BL/FL progress
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2024-07-07 13:48:50 +02:00
bc0b18ab7c
stupid nvm 2024-07-05 13:40:58 +02:00
78b4bbcd49
bootloader and flashloader
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2024-07-04 15:23:49 +02:00
2 changed files with 6 additions and 7 deletions

View File

@ -3,7 +3,7 @@
Vorago VA416xx Rust Support
=========
This crate collection provides support to write Rust applications for the VA416XX family
This crate collection provided support to write Rust applications for the VA416XX family
of devices.
## List of crates

View File

@ -25,8 +25,7 @@ static DMA_ACTIVE_FLAG: Mutex<Cell<bool>> = Mutex::new(Cell::new(false));
#[link_section = ".sram1"]
static mut DMA_CTRL_BLOCK: DmaCtrlBlock = DmaCtrlBlock::new();
// We can use statically allocated buffers for DMA transfers as well, and we can also place
// those into SRAM1.
// We can use statically allocated buffers for DMA transfers as well.
#[link_section = ".sram1"]
static mut DMA_SRC_BUF: [u16; 36] = [0; 36];
#[link_section = ".sram1"]
@ -136,11 +135,10 @@ fn transfer_example_8_bit(
}
fn transfer_example_16_bit(dma0: &mut DmaChannel, delay_ms: &mut CountdownTimer<pac::Tim0>) {
let dest_buf_ref = unsafe { &mut *core::ptr::addr_of_mut!(DMA_DEST_BUF[0..33]) };
unsafe {
// Set values scaled from 0 to 65535 to verify this is really a 16-bit transfer.
(0..32).for_each(|i| {
DMA_SRC_BUF[i] = (i as u32 * u16::MAX as u32 / (dest_buf_ref.len() as u32 - 1)) as u16;
DMA_SRC_BUF[i] = (i as u32 * u16::MAX as u32 / (DMA_SRC_BUF.len() - 1) as u32) as u16;
});
}
cortex_m::interrupt::free(|cs| {
@ -149,11 +147,12 @@ fn transfer_example_16_bit(dma0: &mut DmaChannel, delay_ms: &mut CountdownTimer<
cortex_m::interrupt::free(|cs| {
DMA_ACTIVE_FLAG.borrow(cs).set(false);
});
let dest_buf_ref = unsafe { &mut *core::ptr::addr_of_mut!(DMA_DEST_BUF[0..32]) };
// Safety: The source and destination buffer are valid for the duration of the DMA transfer.
unsafe {
dma0.prepare_mem_to_mem_transfer_16_bit(
&*core::ptr::addr_of!(DMA_SRC_BUF[0..32]),
&mut dest_buf_ref[0..32],
dest_buf_ref,
)
.expect("error preparing transfer");
}
@ -188,7 +187,7 @@ fn transfer_example_16_bit(dma0: &mut DmaChannel, delay_ms: &mut CountdownTimer<
(0..32).for_each(|i| {
assert_eq!(
dest_buf_ref[i],
(i as u32 * u16::MAX as u32 / (dest_buf_ref.len() as u32 - 1)) as u16
(i as u32 * u16::MAX as u32 / (dest_buf_ref.len() - 1) as u32) as u16
);
});
// Sentinel value, should be 0.