Updates and fixes

- Improve and fix SPI HAL and example - Fix RTIC example
2024-09-20 10:51:08 +02:00
1 changed files with 0 additions and 12 deletions
--- a/bootloader/src/main.rs
+++ b/bootloader/src/main.rs
@ -1,17 +1,5 @@
 //! Vorago bootloader which can boot from two images.
 //!
 //! Bootloader memory map
 //!
 //! * <0x0>     Bootloader start                         <code up to 0x3FFE bytes>
 //! * <0x3FFE>  Bootloader CRC                           <halfword>
 //! * <0x4000>  App image A start                        <code up to 0x1DFFC (~120K) bytes>
 //! * <0x21FFC> App image A CRC check length             <halfword>
 //! * <0x21FFE> App image A CRC check value              <halfword>
 //! * <0x22000> App image B start                        <code up to 0x1DFFC (~120K) bytes>
 //! * <0x3FFFC> App image B CRC check length             <halfword>
 //! * <0x3FFFE> App image B CRC check value              <halfword>
 //! * <0x40000>                                          <end>
 //!
 //! As opposed to the Vorago example code, this bootloader assumes a 40 MHz external clock
 //! but does not scale that clock up.
 #![no_main]