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2 Commits
vorago-peb
...
b9e1185f86
Author | SHA1 | Date | |
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b9e1185f86
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a660b2ca26 |
@ -11,12 +11,10 @@ panic-rtt-target = { version = "0.1.3" }
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panic-halt = { version = "0.2" }
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panic-halt = { version = "0.2" }
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rtt-target = { version = "0.5" }
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rtt-target = { version = "0.5" }
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crc = "3"
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crc = "3"
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static_assertions = "1"
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[dependencies.va416xx-hal]
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[dependencies.va416xx-hal]
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path = "../va416xx-hal"
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path = "../va416xx-hal"
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features = ["va41630"]
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[features]
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[features]
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default = []
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default = ["rtt-panic"]
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rtt-panic = []
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rtt-panic = []
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@ -11,12 +11,12 @@ The bootloader uses the following memory map:
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| ------ | ---- | ---- |
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| ------ | ---- | ---- |
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| 0x0 | Bootloader start | code up to 0x3FFC bytes |
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| 0x0 | Bootloader start | code up to 0x3FFC bytes |
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| 0x3FFC | Bootloader CRC | word |
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| 0x3FFC | Bootloader CRC | word |
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| 0x4000 | App image A start | code up to 0x1DFF8 (~120K) bytes |
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| 0x4000 | App image A start | code up to 0x1DFFC (~120K) bytes |
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| 0x21FF8 | App image A CRC check length | word |
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| 0x21FFC | App image A CRC check length | word |
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| 0x21FFC | App image A CRC check value | word |
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| 0x21FFE | App image A CRC check value | word |
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| 0x22000 | App image B start | code up to 0x1DFF8 (~120K) bytes |
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| 0x22000 | App image B start | code up to 0x1DFFC (~120K) bytes |
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| 0x3FFF8 | App image B CRC check length | word |
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| 0x3FFFC | App image B CRC check length | word |
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| 0x3FFFC | App image B CRC check value | word |
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| 0x3FFFE | App image B CRC check value | word |
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| 0x40000 | End of NVM | end |
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| 0x40000 | End of NVM | end |
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## Additional Information
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## Additional Information
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@ -1,5 +1,17 @@
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//! Vorago bootloader which can boot from two images.
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//! Vorago bootloader which can boot from two images.
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//!
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//!
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//! Bootloader memory map
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//!
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//! * <0x0> Bootloader start <code up to 0x3FFE bytes>
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//! * <0x3FFE> Bootloader CRC <halfword>
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//! * <0x4000> App image A start <code up to 0x1DFFC (~120K) bytes>
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//! * <0x21FFC> App image A CRC check length <halfword>
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//! * <0x21FFE> App image A CRC check value <halfword>
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//! * <0x22000> App image B start <code up to 0x1DFFC (~120K) bytes>
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//! * <0x3FFFC> App image B CRC check length <halfword>
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//! * <0x3FFFE> App image B CRC check value <halfword>
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//! * <0x40000> <end>
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//!
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//! As opposed to the Vorago example code, this bootloader assumes a 40 MHz external clock
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//! As opposed to the Vorago example code, this bootloader assumes a 40 MHz external clock
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//! but does not scale that clock up.
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//! but does not scale that clock up.
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#![no_main]
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#![no_main]
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@ -39,36 +51,20 @@ const RTT_PRINTOUT: bool = true;
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// Important bootloader addresses and offsets, vector table information.
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// Important bootloader addresses and offsets, vector table information.
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const NVM_SIZE: u32 = 0x40000;
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const BOOTLOADER_START_ADDR: u32 = 0x0;
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const BOOTLOADER_START_ADDR: u32 = 0x0;
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const BOOTLOADER_CRC_ADDR: u32 = BOOTLOADER_END_ADDR - 4;
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const BOOTLOADER_END_ADDR: u32 = 0x4000;
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const BOOTLOADER_END_ADDR: u32 = 0x4000;
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const BOOTLOADER_CRC_ADDR: u32 = 0x3FFC;
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// 0x4000
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const APP_A_START_ADDR: u32 = 0x4000;
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const APP_A_START_ADDR: u32 = BOOTLOADER_END_ADDR;
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pub const APP_A_END_ADDR: u32 = 0x22000;
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// The actual size of the image which is relevant for CRC calculation will be store at this
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// The actual size of the image which is relevant for CRC calculation.
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// address.
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const APP_A_SIZE_ADDR: u32 = 0x21FF8;
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// 0x21FF8
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const APP_A_CRC_ADDR: u32 = 0x21FFC;
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const APP_A_SIZE_ADDR: u32 = APP_B_END_ADDR - 8;
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const APP_B_START_ADDR: u32 = 0x22000;
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// 0x21FFC
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pub const APP_B_END_ADDR: u32 = 0x40000;
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const APP_A_CRC_ADDR: u32 = APP_B_END_ADDR - 4;
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// The actual size of the image which is relevant for CRC calculation.
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pub const APP_A_END_ADDR: u32 = BOOTLOADER_END_ADDR + APP_IMG_SZ;
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const APP_B_SIZE_ADDR: u32 = 0x3FFF8;
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const APP_B_CRC_ADDR: u32 = 0x3FFFC;
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// 0x22000
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pub const APP_IMG_SZ: u32 = 0x1E000;
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const APP_B_START_ADDR: u32 = APP_A_END_ADDR;
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// The actual size of the image which is relevant for CRC calculation will be stored at this
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// address.
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// 0x3FFF8
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const APP_B_SIZE_ADDR: u32 = APP_B_END_ADDR - 8;
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// 0x3FFFC
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const APP_B_CRC_ADDR: u32 = APP_B_END_ADDR - 4;
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// 0x40000
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pub const APP_B_END_ADDR: u32 = NVM_SIZE;
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pub const APP_IMG_SZ: u32 = APP_B_END_ADDR - APP_A_START_ADDR / 2;
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static_assertions::const_assert!((APP_B_END_ADDR - BOOTLOADER_END_ADDR) % 2 == 0);
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pub const VECTOR_TABLE_OFFSET: u32 = 0x0;
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pub const VECTOR_TABLE_OFFSET: u32 = 0x0;
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pub const VECTOR_TABLE_LEN: u32 = 0x350;
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pub const VECTOR_TABLE_LEN: u32 = 0x350;
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@ -7,7 +7,6 @@ edition = "2021"
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cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
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cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
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cortex-m-rt = "0.7"
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cortex-m-rt = "0.7"
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embedded-hal = "1"
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embedded-hal = "1"
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embedded-io = "0.6"
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rtt-target = { version = "0.5" }
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rtt-target = { version = "0.5" }
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panic-rtt-target = { version = "0.1" }
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panic-rtt-target = { version = "0.1" }
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@ -17,10 +16,6 @@ embassy-sync = { version = "0.6.0" }
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embassy-time = { version = "0.3.2" }
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embassy-time = { version = "0.3.2" }
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embassy-time-driver = { version = "0.1" }
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embassy-time-driver = { version = "0.1" }
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[dependencies.ringbuf]
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version = "0.4"
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default-features = false
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[dependencies.once_cell]
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[dependencies.once_cell]
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version = "1"
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version = "1"
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default-features = false
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default-features = false
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@ -1,161 +0,0 @@
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//! This is an example of using the UART HAL abstraction with the IRQ support and embassy.
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//!
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//! It uses the UART0 for communication with another MCU or a host computer (recommended).
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//! You can connect a USB-to-Serial converter to the UART0 pins and then use a serial terminal
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//! application like picocom to send data to the microcontroller, which should be echoed
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//! back to the sender.
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//!
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//! This application uses the interrupt support of the VA416xx to read the data arriving
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//! on the UART without requiring polling.
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#![no_std]
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#![no_main]
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use core::cell::RefCell;
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use embassy_example::EXTCLK_FREQ;
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use embassy_executor::Spawner;
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use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
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use embassy_sync::blocking_mutex::Mutex;
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use embassy_time::{Duration, Ticker};
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use embedded_hal::digital::StatefulOutputPin;
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use embedded_io::Write;
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use panic_rtt_target as _;
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use ringbuf::{
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traits::{Consumer, Observer, Producer},
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StaticRb,
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};
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use rtt_target::{rprintln, rtt_init_print};
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use va416xx_hal::{
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gpio::{OutputReadablePushPull, Pin, PinsG, PG5},
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pac::{self, interrupt},
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prelude::*,
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time::Hertz,
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uart,
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};
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pub type SharedUart = Mutex<CriticalSectionRawMutex, RefCell<Option<uart::RxWithIrq<pac::Uart0>>>>;
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static RX: SharedUart = Mutex::new(RefCell::new(None));
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const BAUDRATE: u32 = 115200;
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// Ring buffer size.
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const RING_BUF_SIZE: usize = 2048;
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pub type SharedRingBuf =
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Mutex<CriticalSectionRawMutex, RefCell<Option<StaticRb<u8, RING_BUF_SIZE>>>>;
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// Ring buffers to handling variable sized telemetry
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static RINGBUF: SharedRingBuf = Mutex::new(RefCell::new(None));
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// See https://embassy.dev/book/#_sharing_using_a_mutex for background information about sharing
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// a peripheral with embassy.
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#[embassy_executor::main]
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async fn main(spawner: Spawner) {
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rtt_init_print!();
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rprintln!("VA416xx UART-Embassy Example");
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let mut dp = pac::Peripherals::take().unwrap();
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// Initialize the systick interrupt & obtain the token to prove that we did
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// Use the external clock connected to XTAL_N.
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let clocks = dp
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.clkgen
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.constrain()
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.xtal_n_clk_with_src_freq(Hertz::from_raw(EXTCLK_FREQ))
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.freeze(&mut dp.sysconfig)
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.unwrap();
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// Safety: Only called once here.
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unsafe {
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embassy_example::init(
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&mut dp.sysconfig,
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&dp.irq_router,
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dp.tim15,
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dp.tim14,
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&clocks,
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)
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};
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let portg = PinsG::new(&mut dp.sysconfig, dp.portg);
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let tx = portg.pg0.into_funsel_1();
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let rx = portg.pg1.into_funsel_1();
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let uart0 = uart::Uart::new(
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dp.uart0,
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(tx, rx),
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Hertz::from_raw(BAUDRATE),
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&mut dp.sysconfig,
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&clocks,
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);
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let (mut tx, rx) = uart0.split();
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let mut rx = rx.into_rx_with_irq();
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rx.start();
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RX.lock(|static_rx| {
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static_rx.borrow_mut().replace(rx);
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});
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RINGBUF.lock(|static_rb| {
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static_rb.borrow_mut().replace(StaticRb::default());
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});
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let led = portg.pg5.into_readable_push_pull_output();
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let mut ticker = Ticker::every(Duration::from_millis(50));
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let mut processing_buf: [u8; RING_BUF_SIZE] = [0; RING_BUF_SIZE];
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let mut read_bytes = 0;
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spawner.spawn(blinky(led)).expect("failed to spawn blinky");
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loop {
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RINGBUF.lock(|static_rb| {
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let mut rb_borrow = static_rb.borrow_mut();
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let rb_mut = rb_borrow.as_mut().unwrap();
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read_bytes = rb_mut.occupied_len();
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rb_mut.pop_slice(&mut processing_buf[0..read_bytes]);
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});
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// Simply send back all received data.
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tx.write_all(&processing_buf[0..read_bytes])
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.expect("sending back read data failed");
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ticker.next().await;
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}
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}
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#[embassy_executor::task]
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async fn blinky(mut led: Pin<PG5, OutputReadablePushPull>) {
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let mut ticker = Ticker::every(Duration::from_millis(500));
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loop {
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led.toggle().ok();
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ticker.next().await;
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}
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}
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#[interrupt]
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#[allow(non_snake_case)]
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fn UART0_RX() {
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let mut buf: [u8; 16] = [0; 16];
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let mut read_len: usize = 0;
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let mut errors = None;
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RX.lock(|static_rx| {
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let mut rx_borrow = static_rx.borrow_mut();
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let rx_mut_ref = rx_borrow.as_mut().unwrap();
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let result = rx_mut_ref.irq_handler(&mut buf);
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read_len = result.bytes_read;
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if result.errors.is_some() {
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errors = result.errors;
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}
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});
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let mut ringbuf_full = false;
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if read_len > 0 {
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// Send the received buffer to the main thread for processing via a ring buffer.
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RINGBUF.lock(|static_rb| {
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let mut rb_borrow = static_rb.borrow_mut();
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let rb_mut_ref = rb_borrow.as_mut().unwrap();
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if rb_mut_ref.vacant_len() < read_len {
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ringbuf_full = true;
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for _ in rb_mut_ref.pop_iter() {}
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}
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rb_mut_ref.push_slice(&buf[0..read_len]);
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});
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}
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if errors.is_some() {
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rprintln!("UART error: {:?}", errors);
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}
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if ringbuf_full {
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rprintln!("ringbuffer is full, deleted oldest data");
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}
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}
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@ -1,6 +1,4 @@
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#![no_std]
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#![no_std]
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pub mod time_driver;
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pub mod time_driver;
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pub const EXTCLK_FREQ: u32 = 40_000_000;
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pub use time_driver::init;
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pub use time_driver::init;
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@ -1,6 +1,5 @@
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#![no_std]
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#![no_std]
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#![no_main]
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#![no_main]
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use embassy_example::EXTCLK_FREQ;
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use embassy_executor::Spawner;
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use embassy_executor::Spawner;
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use embassy_time::{Duration, Instant, Ticker};
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use embassy_time::{Duration, Instant, Ticker};
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use embedded_hal::digital::StatefulOutputPin;
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use embedded_hal::digital::StatefulOutputPin;
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@ -8,6 +7,8 @@ use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use rtt_target::{rprintln, rtt_init_print};
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use va416xx_hal::{gpio::PinsG, pac, prelude::*, time::Hertz};
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use va416xx_hal::{gpio::PinsG, pac, prelude::*, time::Hertz};
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const EXTCLK_FREQ: u32 = 40_000_000;
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// main is itself an async function.
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// main is itself an async function.
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#[embassy_executor::main]
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#[embassy_executor::main]
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||||||
async fn main(_spawner: Spawner) {
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async fn main(_spawner: Spawner) {
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@ -17,7 +17,7 @@ use va416xx_hal::{
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enable_interrupt,
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enable_interrupt,
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irq_router::enable_and_init_irq_router,
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irq_router::enable_and_init_irq_router,
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pac::{self, interrupt},
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pac::{self, interrupt},
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timer::{assert_tim_reset_for_two_cycles, enable_tim_clk, ValidTim},
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pwm::{assert_tim_reset_for_two_cycles, enable_tim_clk, ValidTim},
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||||||
};
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};
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||||||
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|
||||||
pub type TimekeeperClk = pac::Tim15;
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pub type TimekeeperClk = pac::Tim15;
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||||||
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@ -12,7 +12,7 @@ use rtt_target::{rprintln, rtt_init_print};
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|||||||
use simple_examples::peb1;
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use simple_examples::peb1;
|
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use va416xx_hal::dma::{Dma, DmaCfg, DmaChannel, DmaCtrlBlock};
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use va416xx_hal::dma::{Dma, DmaCfg, DmaChannel, DmaCtrlBlock};
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||||||
use va416xx_hal::irq_router::enable_and_init_irq_router;
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use va416xx_hal::irq_router::enable_and_init_irq_router;
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||||||
use va416xx_hal::timer::CountdownTimer;
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use va416xx_hal::pwm::CountdownTimer;
|
||||||
use va416xx_hal::{
|
use va416xx_hal::{
|
||||||
pac::{self, interrupt},
|
pac::{self, interrupt},
|
||||||
prelude::*,
|
prelude::*,
|
||||||
|
@ -11,8 +11,7 @@ use va416xx_hal::{
|
|||||||
gpio::PinsA,
|
gpio::PinsA,
|
||||||
pac,
|
pac,
|
||||||
prelude::*,
|
prelude::*,
|
||||||
pwm::{self, get_duty_from_percent, PwmA, PwmB, ReducedPwmPin},
|
pwm::{self, get_duty_from_percent, CountdownTimer, PwmA, PwmB, ReducedPwmPin},
|
||||||
timer::CountdownTimer,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#[entry]
|
#[entry]
|
||||||
|
@ -8,7 +8,7 @@ use embedded_hal::spi::{Mode, SpiBus, MODE_0};
|
|||||||
use panic_rtt_target as _;
|
use panic_rtt_target as _;
|
||||||
use rtt_target::{rprintln, rtt_init_print};
|
use rtt_target::{rprintln, rtt_init_print};
|
||||||
use simple_examples::peb1;
|
use simple_examples::peb1;
|
||||||
use va416xx_hal::spi::{Spi, SpiClkConfig};
|
use va416xx_hal::spi::{Spi, SpiClkConfig, TransferConfigWithHwcs};
|
||||||
use va416xx_hal::{
|
use va416xx_hal::{
|
||||||
gpio::{PinsB, PinsC},
|
gpio::{PinsB, PinsC},
|
||||||
pac,
|
pac,
|
||||||
@ -55,16 +55,14 @@ fn main() -> ! {
|
|||||||
pins_c.pc1.into_funsel_1(),
|
pins_c.pc1.into_funsel_1(),
|
||||||
);
|
);
|
||||||
|
|
||||||
let mut spi_cfg = SpiConfig::default()
|
let mut spi_cfg = SpiConfig::default().clk_cfg(
|
||||||
.clk_cfg(
|
SpiClkConfig::from_clk(Hertz::from_raw(SPI_SPEED_KHZ), &clocks)
|
||||||
SpiClkConfig::from_clk(Hertz::from_raw(SPI_SPEED_KHZ), &clocks)
|
.expect("invalid target clock"),
|
||||||
.expect("invalid target clock"),
|
);
|
||||||
)
|
|
||||||
.mode(SPI_MODE)
|
|
||||||
.blockmode(BLOCKMODE);
|
|
||||||
if EXAMPLE_SEL == ExampleSelect::Loopback {
|
if EXAMPLE_SEL == ExampleSelect::Loopback {
|
||||||
spi_cfg = spi_cfg.loopback(true)
|
spi_cfg = spi_cfg.loopback(true)
|
||||||
}
|
}
|
||||||
|
let transfer_cfg = TransferConfigWithHwcs::new_no_hw_cs(None, Some(SPI_MODE), BLOCKMODE, false);
|
||||||
// Create SPI peripheral.
|
// Create SPI peripheral.
|
||||||
let mut spi0 = Spi::new(
|
let mut spi0 = Spi::new(
|
||||||
&mut dp.sysconfig,
|
&mut dp.sysconfig,
|
||||||
@ -72,7 +70,9 @@ fn main() -> ! {
|
|||||||
dp.spi0,
|
dp.spi0,
|
||||||
(sck, miso, mosi),
|
(sck, miso, mosi),
|
||||||
spi_cfg,
|
spi_cfg,
|
||||||
);
|
Some(&transfer_cfg.downgrade()),
|
||||||
|
)
|
||||||
|
.expect("creating SPI peripheral failed");
|
||||||
spi0.set_fill_word(FILL_WORD);
|
spi0.set_fill_word(FILL_WORD);
|
||||||
loop {
|
loop {
|
||||||
let tx_buf: [u8; 4] = [1, 2, 3, 0];
|
let tx_buf: [u8; 4] = [1, 2, 3, 0];
|
||||||
@ -83,8 +83,6 @@ fn main() -> ! {
|
|||||||
// Can't really verify correct behaviour here. Just verify nothing crazy happens or it hangs up.
|
// Can't really verify correct behaviour here. Just verify nothing crazy happens or it hangs up.
|
||||||
spi0.read(&mut rx_buf[0..2]).unwrap();
|
spi0.read(&mut rx_buf[0..2]).unwrap();
|
||||||
|
|
||||||
// If the pins are tied together, we should received exactly what we send.
|
|
||||||
|
|
||||||
let mut inplace_buf = tx_buf;
|
let mut inplace_buf = tx_buf;
|
||||||
spi0.transfer_in_place(&mut inplace_buf)
|
spi0.transfer_in_place(&mut inplace_buf)
|
||||||
.expect("SPI transfer_in_place failed");
|
.expect("SPI transfer_in_place failed");
|
||||||
|
@ -6,18 +6,12 @@ a simple PUS (CCSDS) interface to update the software. It also provides a Python
|
|||||||
called the `image-loader.py` which can be used to upload compiled images to the flashloader
|
called the `image-loader.py` which can be used to upload compiled images to the flashloader
|
||||||
application to write them to the NVM.
|
application to write them to the NVM.
|
||||||
|
|
||||||
Please note that the both the application and the image loader are tailored towards usage
|
|
||||||
with the [bootloader provided by this repository](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/bootloader).
|
|
||||||
|
|
||||||
The software can quickly be adapted to interface with a real primary on-board software instead of
|
The software can quickly be adapted to interface with a real primary on-board software instead of
|
||||||
the Python script provided here to upload images because it uses a low-level CCSDS based packet
|
the Python script provided here to upload images because it uses a low-level CCSDS based packet
|
||||||
interface.
|
interface.
|
||||||
|
|
||||||
## Using the Python image loader
|
## Using the Python image loader
|
||||||
|
|
||||||
The Python image loader communicates with the Rust flashload application using a dedicated serial
|
|
||||||
port with a baudrate of 115200.
|
|
||||||
|
|
||||||
It is recommended to run the script in a dedicated virtual environment. For example, on UNIX
|
It is recommended to run the script in a dedicated virtual environment. For example, on UNIX
|
||||||
systems you can use `python3 -m venv venv` and then `source venv/bin/activate` to create
|
systems you can use `python3 -m venv venv` and then `source venv/bin/activate` to create
|
||||||
and activate a virtual environment.
|
and activate a virtual environment.
|
||||||
|
@ -1,8 +1,6 @@
|
|||||||
#!/usr/bin/env python3
|
#!/usr/bin/env python3
|
||||||
from typing import List, Tuple
|
|
||||||
from spacepackets.ecss.defs import PusService
|
from spacepackets.ecss.defs import PusService
|
||||||
from spacepackets.ecss.tm import PusTm
|
from spacepackets.ecss.tm import PusTm
|
||||||
from tmtccmd.com import ComInterface
|
|
||||||
import toml
|
import toml
|
||||||
import struct
|
import struct
|
||||||
import logging
|
import logging
|
||||||
@ -23,27 +21,20 @@ from elftools.elf.elffile import ELFFile
|
|||||||
|
|
||||||
|
|
||||||
BAUD_RATE = 115200
|
BAUD_RATE = 115200
|
||||||
|
|
||||||
BOOTLOADER_START_ADDR = 0x0
|
BOOTLOADER_START_ADDR = 0x0
|
||||||
BOOTLOADER_END_ADDR = 0x4000
|
BOOTLOADER_END_ADDR = 0x4000
|
||||||
BOOTLOADER_CRC_ADDR = BOOTLOADER_END_ADDR - 4
|
BOOTLOADER_CRC_ADDR = 0x3FFC
|
||||||
BOOTLOADER_MAX_SIZE = BOOTLOADER_END_ADDR - BOOTLOADER_START_ADDR - 4
|
|
||||||
|
|
||||||
APP_A_START_ADDR = 0x4000
|
APP_A_START_ADDR = 0x4000
|
||||||
APP_A_END_ADDR = 0x22000
|
APP_A_END_ADDR = 0x22000
|
||||||
# The actual size of the image which is relevant for CRC calculation.
|
# The actual size of the image which is relevant for CRC calculation.
|
||||||
APP_A_SIZE_ADDR = APP_A_END_ADDR - 8
|
APP_A_SIZE_ADDR = 0x21FF8
|
||||||
APP_A_CRC_ADDR = APP_A_END_ADDR - 4
|
APP_A_CRC_ADDR = 0x21FFC
|
||||||
APP_A_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8
|
|
||||||
|
|
||||||
APP_B_START_ADDR = 0x22000
|
APP_B_START_ADDR = 0x22000
|
||||||
APP_B_END_ADDR = 0x40000
|
APP_B_END_ADDR = 0x40000
|
||||||
# The actual size of the image which is relevant for CRC calculation.
|
# The actual size of the image which is relevant for CRC calculation.
|
||||||
APP_B_SIZE_ADDR = APP_B_END_ADDR - 8
|
APP_B_SIZE_ADDR = 0x3FFF8
|
||||||
APP_B_CRC_ADDR = APP_B_END_ADDR - 4
|
APP_B_CRC_ADDR = 0x3FFFC
|
||||||
APP_B_MAX_SIZE = APP_A_END_ADDR - APP_A_START_ADDR - 8
|
APP_IMG_SZ = 0x1E000
|
||||||
|
|
||||||
APP_IMG_SZ = (APP_B_END_ADDR - APP_A_START_ADDR) // 2
|
|
||||||
|
|
||||||
CHUNK_SIZE = 896
|
CHUNK_SIZE = 896
|
||||||
|
|
||||||
@ -61,7 +52,6 @@ class ActionId(enum.IntEnum):
|
|||||||
|
|
||||||
|
|
||||||
_LOGGER = logging.getLogger(__name__)
|
_LOGGER = logging.getLogger(__name__)
|
||||||
SEQ_PROVIDER = SeqCountProvider(bit_width=14)
|
|
||||||
|
|
||||||
|
|
||||||
@dataclasses.dataclass
|
@dataclasses.dataclass
|
||||||
@ -72,174 +62,7 @@ class LoadableSegment:
|
|||||||
data: bytes
|
data: bytes
|
||||||
|
|
||||||
|
|
||||||
class Target(enum.Enum):
|
SEQ_PROVIDER = SeqCountProvider(bit_width=14)
|
||||||
BOOTLOADER = 0
|
|
||||||
APP_A = 1
|
|
||||||
APP_B = 2
|
|
||||||
|
|
||||||
|
|
||||||
class ImageLoader:
|
|
||||||
def __init__(self, com_if: ComInterface, verificator: PusVerificator) -> None:
|
|
||||||
self.com_if = com_if
|
|
||||||
self.verificator = verificator
|
|
||||||
|
|
||||||
def handle_ping_cmd(self):
|
|
||||||
_LOGGER.info("Sending ping command")
|
|
||||||
ping_tc = PusTc(
|
|
||||||
apid=0x00,
|
|
||||||
service=PusService.S17_TEST,
|
|
||||||
subservice=1,
|
|
||||||
seq_count=SEQ_PROVIDER.get_and_increment(),
|
|
||||||
app_data=bytes(PING_PAYLOAD_SIZE),
|
|
||||||
)
|
|
||||||
self.verificator.add_tc(ping_tc)
|
|
||||||
self.com_if.send(bytes(ping_tc.pack()))
|
|
||||||
|
|
||||||
data_available = self.com_if.data_available(0.4)
|
|
||||||
if not data_available:
|
|
||||||
_LOGGER.warning("no ping reply received")
|
|
||||||
for reply in self.com_if.receive():
|
|
||||||
result = self.verificator.add_tm(
|
|
||||||
Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0))
|
|
||||||
)
|
|
||||||
if result is not None and result.completed:
|
|
||||||
_LOGGER.info("received ping completion reply")
|
|
||||||
|
|
||||||
def handle_corruption_cmd(self, target: Target):
|
|
||||||
|
|
||||||
if target == Target.BOOTLOADER:
|
|
||||||
_LOGGER.error("can not corrupt bootloader")
|
|
||||||
if target == Target.APP_A:
|
|
||||||
self.send_tc(
|
|
||||||
PusTc(
|
|
||||||
apid=0,
|
|
||||||
service=ACTION_SERVICE,
|
|
||||||
subservice=ActionId.CORRUPT_APP_A,
|
|
||||||
),
|
|
||||||
)
|
|
||||||
if target == Target.APP_B:
|
|
||||||
self.send_tc(
|
|
||||||
PusTc(
|
|
||||||
apid=0,
|
|
||||||
service=ACTION_SERVICE,
|
|
||||||
subservice=ActionId.CORRUPT_APP_B,
|
|
||||||
),
|
|
||||||
)
|
|
||||||
|
|
||||||
def handle_flash_cmd(self, target: Target, file_path: Path) -> int:
|
|
||||||
loadable_segments = []
|
|
||||||
_LOGGER.info("Parsing ELF file for loadable sections")
|
|
||||||
total_size = 0
|
|
||||||
loadable_segments, total_size = create_loadable_segments(target, file_path)
|
|
||||||
segments_info_str(target, loadable_segments, total_size, file_path)
|
|
||||||
result = self._perform_flashing_algorithm(loadable_segments)
|
|
||||||
if result != 0:
|
|
||||||
return result
|
|
||||||
self._crc_and_app_size_postprocessing(target, total_size, loadable_segments)
|
|
||||||
return 0
|
|
||||||
|
|
||||||
def _perform_flashing_algorithm(
|
|
||||||
self,
|
|
||||||
loadable_segments: List[LoadableSegment],
|
|
||||||
) -> int:
|
|
||||||
# Perform the flashing algorithm.
|
|
||||||
for segment in loadable_segments:
|
|
||||||
segment_end = segment.offset + segment.size
|
|
||||||
current_addr = segment.offset
|
|
||||||
pos_in_segment = 0
|
|
||||||
while pos_in_segment < segment.size:
|
|
||||||
next_chunk_size = min(segment_end - current_addr, CHUNK_SIZE)
|
|
||||||
data = segment.data[pos_in_segment : pos_in_segment + next_chunk_size]
|
|
||||||
next_packet = pack_memory_write_command(current_addr, data)
|
|
||||||
_LOGGER.info(
|
|
||||||
f"Sending memory write command for address {current_addr:#08x} and data with "
|
|
||||||
f"length {len(data)}"
|
|
||||||
)
|
|
||||||
self.verificator.add_tc(next_packet)
|
|
||||||
self.com_if.send(bytes(next_packet.pack()))
|
|
||||||
current_addr += next_chunk_size
|
|
||||||
pos_in_segment += next_chunk_size
|
|
||||||
start_time = time.time()
|
|
||||||
while True:
|
|
||||||
if time.time() - start_time > 1.0:
|
|
||||||
_LOGGER.error("Timeout while waiting for reply")
|
|
||||||
return -1
|
|
||||||
data_available = self.com_if.data_available(0.1)
|
|
||||||
done = False
|
|
||||||
if not data_available:
|
|
||||||
continue
|
|
||||||
replies = self.com_if.receive()
|
|
||||||
for reply in replies:
|
|
||||||
tm = PusTm.unpack(reply, 0)
|
|
||||||
if tm.service != 1:
|
|
||||||
continue
|
|
||||||
service_1_tm = Service1Tm.from_tm(tm, UnpackParams(0))
|
|
||||||
check_result = self.verificator.add_tm(service_1_tm)
|
|
||||||
# We could send after we have received the step reply, but that can
|
|
||||||
# somehow lead to overrun errors. I think it's okay to do it like
|
|
||||||
# this as long as the flash loader only uses polling..
|
|
||||||
if (
|
|
||||||
check_result is not None
|
|
||||||
and check_result.status.completed == StatusField.SUCCESS
|
|
||||||
):
|
|
||||||
done = True
|
|
||||||
|
|
||||||
# This is an optimized variant, but I think the small delay is not an issue.
|
|
||||||
"""
|
|
||||||
if (
|
|
||||||
check_result is not None
|
|
||||||
and check_result.status.step == StatusField.SUCCESS
|
|
||||||
and len(check_result.status.step_list) == 1
|
|
||||||
):
|
|
||||||
done = True
|
|
||||||
"""
|
|
||||||
self.verificator.remove_completed_entries()
|
|
||||||
if done:
|
|
||||||
break
|
|
||||||
return 0
|
|
||||||
|
|
||||||
def _crc_and_app_size_postprocessing(
|
|
||||||
self,
|
|
||||||
target: Target,
|
|
||||||
total_size: int,
|
|
||||||
loadable_segments: List[LoadableSegment],
|
|
||||||
):
|
|
||||||
if target == Target.BOOTLOADER:
|
|
||||||
_LOGGER.info("Blanking the bootloader checksum")
|
|
||||||
# Blank the checksum. For the bootloader, the bootloader will calculate the
|
|
||||||
# checksum itself on the initial run.
|
|
||||||
checksum_write_packet = pack_memory_write_command(
|
|
||||||
BOOTLOADER_CRC_ADDR, bytes([0x00, 0x00, 0x00, 0x00])
|
|
||||||
)
|
|
||||||
self.send_tc(checksum_write_packet)
|
|
||||||
else:
|
|
||||||
crc_addr = None
|
|
||||||
size_addr = None
|
|
||||||
if target == Target.APP_A:
|
|
||||||
crc_addr = APP_A_CRC_ADDR
|
|
||||||
size_addr = APP_A_SIZE_ADDR
|
|
||||||
elif target == Target.APP_B:
|
|
||||||
crc_addr = APP_B_CRC_ADDR
|
|
||||||
size_addr = APP_B_SIZE_ADDR
|
|
||||||
assert crc_addr is not None
|
|
||||||
assert size_addr is not None
|
|
||||||
_LOGGER.info(f"Writing app size {total_size} at address {size_addr:#08x}")
|
|
||||||
size_write_packet = pack_memory_write_command(
|
|
||||||
size_addr, struct.pack("!I", total_size)
|
|
||||||
)
|
|
||||||
self.com_if.send(bytes(size_write_packet.pack()))
|
|
||||||
time.sleep(0.2)
|
|
||||||
crc_calc = PredefinedCrc("crc-32")
|
|
||||||
for segment in loadable_segments:
|
|
||||||
crc_calc.update(segment.data)
|
|
||||||
checksum = crc_calc.digest()
|
|
||||||
_LOGGER.info(
|
|
||||||
f"Writing checksum 0x[{checksum.hex(sep=',')}] at address {crc_addr:#08x}"
|
|
||||||
)
|
|
||||||
self.send_tc(pack_memory_write_command(crc_addr, checksum))
|
|
||||||
|
|
||||||
def send_tc(self, tc: PusTc):
|
|
||||||
self.com_if.send(bytes(tc.pack()))
|
|
||||||
|
|
||||||
|
|
||||||
def main() -> int:
|
def main() -> int:
|
||||||
@ -279,134 +102,213 @@ def main() -> int:
|
|||||||
verificator = PusVerificator()
|
verificator = PusVerificator()
|
||||||
com_if = SerialCobsComIF(serial_cfg)
|
com_if = SerialCobsComIF(serial_cfg)
|
||||||
com_if.open()
|
com_if.open()
|
||||||
target = None
|
|
||||||
if args.target == "bl":
|
|
||||||
target = Target.BOOTLOADER
|
|
||||||
elif args.target == "a":
|
|
||||||
target = Target.APP_A
|
|
||||||
elif args.target == "b":
|
|
||||||
target = Target.APP_B
|
|
||||||
image_loader = ImageLoader(com_if, verificator)
|
|
||||||
file_path = None
|
file_path = None
|
||||||
result = -1
|
|
||||||
if args.ping:
|
if args.ping:
|
||||||
image_loader.handle_ping_cmd()
|
_LOGGER.info("Sending ping command")
|
||||||
com_if.close()
|
ping_tc = PusTc(
|
||||||
return 0
|
apid=0x00,
|
||||||
if target:
|
service=PusService.S17_TEST,
|
||||||
|
subservice=1,
|
||||||
|
seq_count=SEQ_PROVIDER.get_and_increment(),
|
||||||
|
app_data=bytes(PING_PAYLOAD_SIZE),
|
||||||
|
)
|
||||||
|
verificator.add_tc(ping_tc)
|
||||||
|
com_if.send(ping_tc.pack())
|
||||||
|
|
||||||
|
data_available = com_if.data_available(0.4)
|
||||||
|
if not data_available:
|
||||||
|
_LOGGER.warning("no ping reply received")
|
||||||
|
for reply in com_if.receive():
|
||||||
|
result = verificator.add_tm(
|
||||||
|
Service1Tm.from_tm(PusTm.unpack(reply, 0), UnpackParams(0))
|
||||||
|
)
|
||||||
|
if result is not None and result.completed:
|
||||||
|
_LOGGER.info("received ping completion reply")
|
||||||
|
if not args.target:
|
||||||
|
return 0
|
||||||
|
if args.target:
|
||||||
if not args.corrupt:
|
if not args.corrupt:
|
||||||
if not args.path:
|
if not args.path:
|
||||||
_LOGGER.error("App Path needs to be specified for the flash process")
|
_LOGGER.error("App Path needs to be specified for the flash process")
|
||||||
|
return -1
|
||||||
file_path = Path(args.path)
|
file_path = Path(args.path)
|
||||||
if not file_path.exists():
|
if not file_path.exists():
|
||||||
_LOGGER.error("File does not exist")
|
_LOGGER.error("File does not exist")
|
||||||
|
return -1
|
||||||
if args.corrupt:
|
if args.corrupt:
|
||||||
if not target:
|
if not args.target:
|
||||||
_LOGGER.error("target for corruption command required")
|
_LOGGER.error("target for corruption command required")
|
||||||
com_if.close()
|
|
||||||
return -1
|
return -1
|
||||||
image_loader.handle_corruption_cmd(target)
|
if args.target == "bl":
|
||||||
|
_LOGGER.error("can not corrupt bootloader")
|
||||||
|
if args.target == "a":
|
||||||
|
packet = PusTc(
|
||||||
|
apid=0,
|
||||||
|
service=ACTION_SERVICE,
|
||||||
|
subservice=ActionId.CORRUPT_APP_A,
|
||||||
|
)
|
||||||
|
com_if.send(packet.pack())
|
||||||
|
if args.target == "b":
|
||||||
|
packet = PusTc(
|
||||||
|
apid=0,
|
||||||
|
service=ACTION_SERVICE,
|
||||||
|
subservice=ActionId.CORRUPT_APP_B,
|
||||||
|
)
|
||||||
|
com_if.send(packet.pack())
|
||||||
else:
|
else:
|
||||||
assert file_path is not None
|
assert file_path is not None
|
||||||
assert target is not None
|
loadable_segments = []
|
||||||
result = image_loader.handle_flash_cmd(target, file_path)
|
_LOGGER.info("Parsing ELF file for loadable sections")
|
||||||
|
total_size = 0
|
||||||
|
with open(file_path, "rb") as app_file:
|
||||||
|
elf_file = ELFFile(app_file)
|
||||||
|
|
||||||
com_if.close()
|
for (idx, segment) in enumerate(elf_file.iter_segments("PT_LOAD")):
|
||||||
return result
|
if segment.header.p_filesz == 0:
|
||||||
|
continue
|
||||||
|
# Basic validity checks of the base addresses.
|
||||||
def create_loadable_segments(
|
if idx == 0:
|
||||||
target: Target, file_path: Path
|
if (
|
||||||
) -> Tuple[List[LoadableSegment], int]:
|
args.target == "bl"
|
||||||
loadable_segments = []
|
and segment.header.p_paddr != BOOTLOADER_START_ADDR
|
||||||
total_size = 0
|
):
|
||||||
with open(file_path, "rb") as app_file:
|
raise ValueError(
|
||||||
elf_file = ELFFile(app_file)
|
f"detected possibly invalid start address {segment.header.p_paddr:#08x} for "
|
||||||
|
f"bootloader, expected {BOOTLOADER_START_ADDR}"
|
||||||
for idx, segment in enumerate(elf_file.iter_segments("PT_LOAD")):
|
)
|
||||||
if segment.header.p_filesz == 0:
|
if (
|
||||||
continue
|
args.target == "a"
|
||||||
# Basic validity checks of the base addresses.
|
and segment.header.p_paddr != APP_A_START_ADDR
|
||||||
if idx == 0:
|
):
|
||||||
if (
|
raise ValueError(
|
||||||
target == Target.BOOTLOADER
|
f"detected possibly invalid start address {segment.header.p_paddr:#08x} for "
|
||||||
and segment.header.p_paddr != BOOTLOADER_START_ADDR
|
f"App A, expected {APP_A_START_ADDR}"
|
||||||
):
|
)
|
||||||
raise ValueError(
|
if (
|
||||||
f"detected possibly invalid start address {segment.header.p_paddr:#08x} for "
|
args.target == "b"
|
||||||
f"bootloader, expected {BOOTLOADER_START_ADDR}"
|
and segment.header.p_paddr != APP_B_START_ADDR
|
||||||
|
):
|
||||||
|
raise ValueError(
|
||||||
|
f"detected possibly invalid start address {segment.header.p_paddr:#08x} for "
|
||||||
|
f"App B, expected {APP_B_START_ADDR}"
|
||||||
|
)
|
||||||
|
name = None
|
||||||
|
for section in elf_file.iter_sections():
|
||||||
|
if (
|
||||||
|
section.header.sh_offset == segment.header.p_offset
|
||||||
|
and section.header.sh_size > 0
|
||||||
|
):
|
||||||
|
name = section.name
|
||||||
|
if name is None:
|
||||||
|
_LOGGER.warning("no fitting section found for segment")
|
||||||
|
continue
|
||||||
|
# print(f"Segment Addr: {segment.header.p_paddr}")
|
||||||
|
# print(f"Segment Offset: {segment.header.p_offset}")
|
||||||
|
# print(f"Segment Filesize: {segment.header.p_filesz}")
|
||||||
|
loadable_segments.append(
|
||||||
|
LoadableSegment(
|
||||||
|
name=name,
|
||||||
|
offset=segment.header.p_paddr,
|
||||||
|
size=segment.header.p_filesz,
|
||||||
|
data=segment.data(),
|
||||||
)
|
)
|
||||||
if (
|
|
||||||
target == Target.APP_A
|
|
||||||
and segment.header.p_paddr != APP_A_START_ADDR
|
|
||||||
):
|
|
||||||
raise ValueError(
|
|
||||||
f"detected possibly invalid start address {segment.header.p_paddr:#08x} for "
|
|
||||||
f"App A, expected {APP_A_START_ADDR}"
|
|
||||||
)
|
|
||||||
if (
|
|
||||||
target == Target.APP_B
|
|
||||||
and segment.header.p_paddr != APP_B_START_ADDR
|
|
||||||
):
|
|
||||||
raise ValueError(
|
|
||||||
f"detected possibly invalid start address {segment.header.p_paddr:#08x} for "
|
|
||||||
f"App B, expected {APP_B_START_ADDR}"
|
|
||||||
)
|
|
||||||
name = None
|
|
||||||
for section in elf_file.iter_sections():
|
|
||||||
if (
|
|
||||||
section.header.sh_offset == segment.header.p_offset
|
|
||||||
and section.header.sh_size > 0
|
|
||||||
):
|
|
||||||
name = section.name
|
|
||||||
if name is None:
|
|
||||||
_LOGGER.warning("no fitting section found for segment")
|
|
||||||
continue
|
|
||||||
# print(f"Segment Addr: {segment.header.p_paddr}")
|
|
||||||
# print(f"Segment Offset: {segment.header.p_offset}")
|
|
||||||
# print(f"Segment Filesize: {segment.header.p_filesz}")
|
|
||||||
loadable_segments.append(
|
|
||||||
LoadableSegment(
|
|
||||||
name=name,
|
|
||||||
offset=segment.header.p_paddr,
|
|
||||||
size=segment.header.p_filesz,
|
|
||||||
data=segment.data(),
|
|
||||||
)
|
)
|
||||||
|
total_size += segment.header.p_filesz
|
||||||
|
context_str = None
|
||||||
|
if args.target == "bl":
|
||||||
|
context_str = "Bootloader"
|
||||||
|
elif args.target == "a":
|
||||||
|
context_str = "App Slot A"
|
||||||
|
elif args.target == "b":
|
||||||
|
context_str = "App Slot B"
|
||||||
|
_LOGGER.info(
|
||||||
|
f"Flashing {context_str} with image {file_path} (size {total_size})"
|
||||||
)
|
)
|
||||||
total_size += segment.header.p_filesz
|
for idx, segment in enumerate(loadable_segments):
|
||||||
return loadable_segments, total_size
|
_LOGGER.info(
|
||||||
|
f"Loadable section {idx} {segment.name} with offset {segment.offset:#08x} and size {segment.size}"
|
||||||
|
)
|
||||||
def segments_info_str(
|
for segment in loadable_segments:
|
||||||
target: Target,
|
segment_end = segment.offset + segment.size
|
||||||
loadable_segments: List[LoadableSegment],
|
current_addr = segment.offset
|
||||||
total_size: int,
|
pos_in_segment = 0
|
||||||
file_path: Path,
|
while pos_in_segment < segment.size:
|
||||||
):
|
next_chunk_size = min(segment_end - current_addr, CHUNK_SIZE)
|
||||||
# Set context string and perform basic sanity checks.
|
data = segment.data[
|
||||||
if target == Target.BOOTLOADER:
|
pos_in_segment : pos_in_segment + next_chunk_size
|
||||||
if total_size > BOOTLOADER_MAX_SIZE:
|
]
|
||||||
_LOGGER.error(
|
next_packet = pack_memory_write_command(current_addr, data)
|
||||||
f"provided bootloader app larger than allowed {total_size} bytes"
|
_LOGGER.info(
|
||||||
)
|
f"Sending memory write command for address {current_addr:#08x} and data with "
|
||||||
return -1
|
f"length {len(data)}"
|
||||||
context_str = "Bootloader"
|
)
|
||||||
elif target == Target.APP_A:
|
verificator.add_tc(next_packet)
|
||||||
if total_size > APP_A_MAX_SIZE:
|
com_if.send(next_packet.pack())
|
||||||
_LOGGER.error(f"provided App A larger than allowed {total_size} bytes")
|
current_addr += next_chunk_size
|
||||||
return -1
|
pos_in_segment += next_chunk_size
|
||||||
context_str = "App Slot A"
|
while True:
|
||||||
elif target == Target.APP_B:
|
data_available = com_if.data_available(0.1)
|
||||||
if total_size > APP_B_MAX_SIZE:
|
done = False
|
||||||
_LOGGER.error(f"provided App B larger than allowed {total_size} bytes")
|
if not data_available:
|
||||||
return -1
|
continue
|
||||||
context_str = "App Slot B"
|
replies = com_if.receive()
|
||||||
_LOGGER.info(f"Flashing {context_str} with image {file_path} (size {total_size})")
|
for reply in replies:
|
||||||
for idx, segment in enumerate(loadable_segments):
|
tm = PusTm.unpack(reply, 0)
|
||||||
_LOGGER.info(
|
if tm.service != 1:
|
||||||
f"Loadable section {idx} {segment.name} with offset {segment.offset:#08x} and "
|
continue
|
||||||
f"size {segment.size}"
|
service_1_tm = Service1Tm.from_tm(tm, UnpackParams(0))
|
||||||
)
|
check_result = verificator.add_tm(service_1_tm)
|
||||||
|
# We could send after we have received the step reply, but that can
|
||||||
|
# somehow lead to overrun errors. I think it's okay to do it like
|
||||||
|
# this as long as the flash loader only uses polling..
|
||||||
|
if (
|
||||||
|
check_result is not None
|
||||||
|
and check_result.status.completed == StatusField.SUCCESS
|
||||||
|
):
|
||||||
|
done = True
|
||||||
|
# Still keep a small delay
|
||||||
|
# time.sleep(0.05)
|
||||||
|
verificator.remove_completed_entries()
|
||||||
|
if done:
|
||||||
|
break
|
||||||
|
if args.target == "bl":
|
||||||
|
_LOGGER.info("Blanking the bootloader checksum")
|
||||||
|
# Blank the checksum. For the bootloader, the bootloader will calculate the
|
||||||
|
# checksum itself on the initial run.
|
||||||
|
checksum_write_packet = pack_memory_write_command(
|
||||||
|
BOOTLOADER_CRC_ADDR, bytes([0x00, 0x00, 0x00, 0x00])
|
||||||
|
)
|
||||||
|
com_if.send(checksum_write_packet.pack())
|
||||||
|
else:
|
||||||
|
crc_addr = None
|
||||||
|
size_addr = None
|
||||||
|
if args.target == "a":
|
||||||
|
crc_addr = APP_A_CRC_ADDR
|
||||||
|
size_addr = APP_A_SIZE_ADDR
|
||||||
|
elif args.target == "b":
|
||||||
|
crc_addr = APP_B_CRC_ADDR
|
||||||
|
size_addr = APP_B_SIZE_ADDR
|
||||||
|
assert crc_addr is not None
|
||||||
|
assert size_addr is not None
|
||||||
|
_LOGGER.info(
|
||||||
|
f"Writing app size {total_size} at address {size_addr:#08x}"
|
||||||
|
)
|
||||||
|
size_write_packet = pack_memory_write_command(
|
||||||
|
size_addr, struct.pack("!I", total_size)
|
||||||
|
)
|
||||||
|
com_if.send(size_write_packet.pack())
|
||||||
|
time.sleep(0.2)
|
||||||
|
crc_calc = PredefinedCrc("crc-32")
|
||||||
|
for segment in loadable_segments:
|
||||||
|
crc_calc.update(segment.data)
|
||||||
|
checksum = crc_calc.digest()
|
||||||
|
_LOGGER.info(
|
||||||
|
f"Writing checksum 0x[{checksum.hex(sep=',')}] at address {crc_addr:#08x}"
|
||||||
|
)
|
||||||
|
checksum_write_packet = pack_memory_write_command(crc_addr, checksum)
|
||||||
|
com_if.send(checksum_write_packet.pack())
|
||||||
|
com_if.close()
|
||||||
|
return 0
|
||||||
|
|
||||||
|
|
||||||
def pack_memory_write_command(addr: int, data: bytes) -> PusTc:
|
def pack_memory_write_command(addr: int, data: bytes) -> PusTc:
|
||||||
@ -422,7 +324,7 @@ def pack_memory_write_command(addr: int, data: bytes) -> PusTc:
|
|||||||
service=MEMORY_SERVICE,
|
service=MEMORY_SERVICE,
|
||||||
subservice=RAW_MEMORY_WRITE_SUBSERVICE,
|
subservice=RAW_MEMORY_WRITE_SUBSERVICE,
|
||||||
seq_count=SEQ_PROVIDER.get_and_increment(),
|
seq_count=SEQ_PROVIDER.get_and_increment(),
|
||||||
app_data=bytes(app_data),
|
app_data=app_data,
|
||||||
)
|
)
|
||||||
|
|
||||||
|
|
||||||
|
@ -7,11 +7,11 @@ edition = "2021"
|
|||||||
|
|
||||||
[dependencies]
|
[dependencies]
|
||||||
cortex-m-rt = "0.7"
|
cortex-m-rt = "0.7"
|
||||||
|
va416xx-hal = { path = "../../va416xx-hal" }
|
||||||
panic-rtt-target = { version = "0.1.3" }
|
panic-rtt-target = { version = "0.1.3" }
|
||||||
rtt-target = { version = "0.5" }
|
rtt-target = { version = "0.5" }
|
||||||
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
|
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
|
||||||
embedded-hal = "1"
|
embedded-hal = "1"
|
||||||
va416xx-hal = { path = "../../va416xx-hal", features = ["va41630"] }
|
|
||||||
|
|
||||||
[profile.dev]
|
[profile.dev]
|
||||||
codegen-units = 1
|
codegen-units = 1
|
||||||
|
@ -7,11 +7,11 @@ edition = "2021"
|
|||||||
|
|
||||||
[dependencies]
|
[dependencies]
|
||||||
cortex-m-rt = "0.7"
|
cortex-m-rt = "0.7"
|
||||||
|
va416xx-hal = { path = "../../va416xx-hal" }
|
||||||
panic-rtt-target = { version = "0.1.3" }
|
panic-rtt-target = { version = "0.1.3" }
|
||||||
rtt-target = { version = "0.5" }
|
rtt-target = { version = "0.5" }
|
||||||
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
|
cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
|
||||||
embedded-hal = "1"
|
embedded-hal = "1"
|
||||||
va416xx-hal = { path = "../../va416xx-hal", features = ["va41630"] }
|
|
||||||
|
|
||||||
[profile.dev]
|
[profile.dev]
|
||||||
codegen-units = 1
|
codegen-units = 1
|
||||||
|
@ -109,7 +109,6 @@ mod app {
|
|||||||
tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket,
|
tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket,
|
||||||
};
|
};
|
||||||
use va416xx_hal::irq_router::enable_and_init_irq_router;
|
use va416xx_hal::irq_router::enable_and_init_irq_router;
|
||||||
use va416xx_hal::uart::IrqContextTimeoutOrMaxSize;
|
|
||||||
use va416xx_hal::{
|
use va416xx_hal::{
|
||||||
clock::ClkgenExt,
|
clock::ClkgenExt,
|
||||||
edac,
|
edac,
|
||||||
@ -133,7 +132,6 @@ mod app {
|
|||||||
struct Local {
|
struct Local {
|
||||||
uart_rx: uart::RxWithIrq<pac::Uart0>,
|
uart_rx: uart::RxWithIrq<pac::Uart0>,
|
||||||
uart_tx: uart::Tx<pac::Uart0>,
|
uart_tx: uart::Tx<pac::Uart0>,
|
||||||
rx_context: IrqContextTimeoutOrMaxSize,
|
|
||||||
rom_spi: Option<pac::Spi3>,
|
rom_spi: Option<pac::Spi3>,
|
||||||
// We handle all TM in one task.
|
// We handle all TM in one task.
|
||||||
tm_cons: DataConsumer<BUF_RB_SIZE_TM, SIZES_RB_SIZE_TM>,
|
tm_cons: DataConsumer<BUF_RB_SIZE_TM, SIZES_RB_SIZE_TM>,
|
||||||
@ -169,9 +167,9 @@ mod app {
|
|||||||
enable_and_init_irq_router(&mut cx.device.sysconfig, &cx.device.irq_router);
|
enable_and_init_irq_router(&mut cx.device.sysconfig, &cx.device.irq_router);
|
||||||
setup_edac(&mut cx.device.sysconfig);
|
setup_edac(&mut cx.device.sysconfig);
|
||||||
|
|
||||||
let gpiog = PinsG::new(&mut cx.device.sysconfig, cx.device.portg);
|
let gpiob = PinsG::new(&mut cx.device.sysconfig, cx.device.portg);
|
||||||
let tx = gpiog.pg0.into_funsel_1();
|
let tx = gpiob.pg0.into_funsel_1();
|
||||||
let rx = gpiog.pg1.into_funsel_1();
|
let rx = gpiob.pg1.into_funsel_1();
|
||||||
|
|
||||||
let uart0 = Uart::new(
|
let uart0 = Uart::new(
|
||||||
cx.device.uart0,
|
cx.device.uart0,
|
||||||
@ -180,7 +178,7 @@ mod app {
|
|||||||
&mut cx.device.sysconfig,
|
&mut cx.device.sysconfig,
|
||||||
&clocks,
|
&clocks,
|
||||||
);
|
);
|
||||||
let (tx, rx) = uart0.split();
|
let (tx, mut rx, _) = uart0.split_with_irq();
|
||||||
|
|
||||||
let verif_reporter = VerificationReportCreator::new(0).unwrap();
|
let verif_reporter = VerificationReportCreator::new(0).unwrap();
|
||||||
|
|
||||||
@ -193,9 +191,7 @@ mod app {
|
|||||||
Mono::start(cx.core.SYST, clocks.sysclk().raw());
|
Mono::start(cx.core.SYST, clocks.sysclk().raw());
|
||||||
CLOCKS.set(clocks).unwrap();
|
CLOCKS.set(clocks).unwrap();
|
||||||
|
|
||||||
let mut rx = rx.into_rx_with_irq();
|
rx.read_fixed_len_using_irq(MAX_TC_FRAME_SIZE, true)
|
||||||
let mut rx_context = IrqContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE);
|
|
||||||
rx.read_fixed_len_or_timeout_based_using_irq(&mut rx_context)
|
|
||||||
.expect("initiating UART RX failed");
|
.expect("initiating UART RX failed");
|
||||||
pus_tc_handler::spawn().unwrap();
|
pus_tc_handler::spawn().unwrap();
|
||||||
pus_tm_tx_handler::spawn().unwrap();
|
pus_tm_tx_handler::spawn().unwrap();
|
||||||
@ -209,7 +205,6 @@ mod app {
|
|||||||
Local {
|
Local {
|
||||||
uart_rx: rx,
|
uart_rx: rx,
|
||||||
uart_tx: tx,
|
uart_tx: tx,
|
||||||
rx_context,
|
|
||||||
rom_spi: Some(cx.device.spi3),
|
rom_spi: Some(cx.device.spi3),
|
||||||
tm_cons: DataConsumer {
|
tm_cons: DataConsumer {
|
||||||
buf_cons: buf_cons_tm,
|
buf_cons: buf_cons_tm,
|
||||||
@ -236,26 +231,20 @@ mod app {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// This is the interrupt handler to read all bytes received on the UART0.
|
|
||||||
#[task(
|
#[task(
|
||||||
binds = UART0_RX,
|
binds = UART0_RX,
|
||||||
local = [
|
local = [
|
||||||
cnt: u32 = 0,
|
cnt: u32 = 0,
|
||||||
rx_buf: [u8; MAX_TC_FRAME_SIZE] = [0; MAX_TC_FRAME_SIZE],
|
rx_buf: [u8; MAX_TC_FRAME_SIZE] = [0; MAX_TC_FRAME_SIZE],
|
||||||
rx_context,
|
|
||||||
uart_rx,
|
uart_rx,
|
||||||
tc_prod
|
tc_prod
|
||||||
],
|
],
|
||||||
)]
|
)]
|
||||||
fn uart_rx_irq(cx: uart_rx_irq::Context) {
|
fn uart_rx_irq(cx: uart_rx_irq::Context) {
|
||||||
match cx
|
match cx.local.uart_rx.irq_handler(cx.local.rx_buf) {
|
||||||
.local
|
|
||||||
.uart_rx
|
|
||||||
.irq_handler_max_size_or_timeout_based(cx.local.rx_context, cx.local.rx_buf)
|
|
||||||
{
|
|
||||||
Ok(result) => {
|
Ok(result) => {
|
||||||
if RX_DEBUGGING {
|
if RX_DEBUGGING {
|
||||||
log::debug!("RX Info: {:?}", cx.local.rx_context);
|
log::debug!("RX Info: {:?}", cx.local.uart_rx.irq_info());
|
||||||
log::debug!("RX Result: {:?}", result);
|
log::debug!("RX Result: {:?}", result);
|
||||||
}
|
}
|
||||||
if result.complete() {
|
if result.complete() {
|
||||||
@ -290,11 +279,11 @@ mod app {
|
|||||||
// Initiate next transfer.
|
// Initiate next transfer.
|
||||||
cx.local
|
cx.local
|
||||||
.uart_rx
|
.uart_rx
|
||||||
.read_fixed_len_or_timeout_based_using_irq(cx.local.rx_context)
|
.read_fixed_len_using_irq(MAX_TC_FRAME_SIZE, true)
|
||||||
.expect("read operation failed");
|
.expect("read operation failed");
|
||||||
}
|
}
|
||||||
if result.has_errors() {
|
if result.error() {
|
||||||
log::warn!("UART error: {:?}", result.errors.unwrap());
|
log::warn!("UART error: {:?}", result.error());
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
Err(e) => {
|
Err(e) => {
|
||||||
@ -449,12 +438,7 @@ mod app {
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
let data = &app_data[10..10 + data_len as usize];
|
let data = &app_data[10..10 + data_len as usize];
|
||||||
log::info!(
|
log::info!("writing {} bytes at offset {} to NVM", data_len, offset);
|
||||||
target: "TC Handler",
|
|
||||||
"writing {} bytes at offset {} to NVM",
|
|
||||||
data_len,
|
|
||||||
offset
|
|
||||||
);
|
|
||||||
// Safety: We only use this for NVM handling and we only do NVM
|
// Safety: We only use this for NVM handling and we only do NVM
|
||||||
// handling here.
|
// handling here.
|
||||||
let mut sys_cfg = unsafe { pac::Sysconfig::steal() };
|
let mut sys_cfg = unsafe { pac::Sysconfig::steal() };
|
||||||
@ -471,9 +455,7 @@ mod app {
|
|||||||
.completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
|
.completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
|
||||||
.expect("completion success failed");
|
.expect("completion success failed");
|
||||||
write_and_send(&tm);
|
write_and_send(&tm);
|
||||||
log::info!(
|
log::info!("NVM operation done");
|
||||||
target: "TC Handler",
|
|
||||||
"NVM operation done");
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1,7 +1,7 @@
|
|||||||
/* Special linker script for application slot A with an offset at address 0x4000 */
|
/* Special linker script for application slot A with an offset at address 0x4000 */
|
||||||
MEMORY
|
MEMORY
|
||||||
{
|
{
|
||||||
FLASH : ORIGIN = 0x00004000, LENGTH = 0x1DFF8
|
FLASH : ORIGIN = 0x00004000, LENGTH = 256K
|
||||||
/* RAM is a mandatory region. This RAM refers to the SRAM_0 */
|
/* RAM is a mandatory region. This RAM refers to the SRAM_0 */
|
||||||
RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K
|
RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K
|
||||||
SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K
|
SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K
|
||||||
|
@ -1,7 +1,7 @@
|
|||||||
/* Special linker script for application slot B with an offset at address 0x22000 */
|
/* Special linker script for application slot B with an offset at address 0x22000 */
|
||||||
MEMORY
|
MEMORY
|
||||||
{
|
{
|
||||||
FLASH : ORIGIN = 0x00022000, LENGTH = 0x1DFF8
|
FLASH : ORIGIN = 0x00022000, LENGTH = 256K
|
||||||
/* RAM is a mandatory region. This RAM refers to the SRAM_0 */
|
/* RAM is a mandatory region. This RAM refers to the SRAM_0 */
|
||||||
RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K
|
RAM : ORIGIN = 0x1FFF8000, LENGTH = 32K
|
||||||
SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K
|
SRAM_1 : ORIGIN = 0x20000000, LENGTH = 32K
|
||||||
|
@ -8,18 +8,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
|
|||||||
|
|
||||||
# [unreleased]
|
# [unreleased]
|
||||||
|
|
||||||
# [v0.3.0] 2024-30-09
|
|
||||||
|
|
||||||
## Changed
|
## Changed
|
||||||
|
|
||||||
- Improve and fix SPI abstractions. Add new low level interface. The primary SPI constructor now
|
- Simplification of clock configuration API for SPI HAL.
|
||||||
only expects a configuration structure and the transfer configuration needs to be applied in a
|
|
||||||
separate step.
|
|
||||||
- Added an additional way to read the UART RX with IRQs. The module documentation provides
|
|
||||||
more information.
|
|
||||||
- Made the UART with IRQ API more flexible for future additions.
|
|
||||||
- Improved UART API result and error handling, added low level API to read from and write
|
|
||||||
to the FIFO directly
|
|
||||||
|
|
||||||
## Fixed
|
## Fixed
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
[package]
|
[package]
|
||||||
name = "va416xx-hal"
|
name = "va416xx-hal"
|
||||||
version = "0.3.0"
|
version = "0.2.0"
|
||||||
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
|
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
|
||||||
edition = "2021"
|
edition = "2021"
|
||||||
description = "HAL for the Vorago VA416xx family of MCUs"
|
description = "HAL for the Vorago VA416xx family of MCUs"
|
||||||
|
@ -113,6 +113,14 @@ pub(super) unsafe trait RegisterInterface {
|
|||||||
/// this type.
|
/// this type.
|
||||||
fn id(&self) -> DynPinId;
|
fn id(&self) -> DynPinId;
|
||||||
|
|
||||||
|
const PORTA: *const PortRegisterBlock = Porta::ptr();
|
||||||
|
const PORTB: *const PortRegisterBlock = Portb::ptr();
|
||||||
|
const PORTC: *const PortRegisterBlock = Portc::ptr();
|
||||||
|
const PORTD: *const PortRegisterBlock = Portd::ptr();
|
||||||
|
const PORTE: *const PortRegisterBlock = Porte::ptr();
|
||||||
|
const PORTF: *const PortRegisterBlock = Portf::ptr();
|
||||||
|
const PORTG: *const PortRegisterBlock = Portg::ptr();
|
||||||
|
|
||||||
/// Change the pin mode
|
/// Change the pin mode
|
||||||
#[inline]
|
#[inline]
|
||||||
fn change_mode(&mut self, mode: DynPinMode) {
|
fn change_mode(&mut self, mode: DynPinMode) {
|
||||||
@ -147,13 +155,13 @@ pub(super) unsafe trait RegisterInterface {
|
|||||||
#[inline]
|
#[inline]
|
||||||
fn port_reg(&self) -> &PortRegisterBlock {
|
fn port_reg(&self) -> &PortRegisterBlock {
|
||||||
match self.id().group {
|
match self.id().group {
|
||||||
DynGroup::A => unsafe { &(*Porta::ptr()) },
|
DynGroup::A => unsafe { &(*Self::PORTA) },
|
||||||
DynGroup::B => unsafe { &(*Portb::ptr()) },
|
DynGroup::B => unsafe { &(*Self::PORTB) },
|
||||||
DynGroup::C => unsafe { &(*Portc::ptr()) },
|
DynGroup::C => unsafe { &(*Self::PORTC) },
|
||||||
DynGroup::D => unsafe { &(*Portd::ptr()) },
|
DynGroup::D => unsafe { &(*Self::PORTD) },
|
||||||
DynGroup::E => unsafe { &(*Porte::ptr()) },
|
DynGroup::E => unsafe { &(*Self::PORTE) },
|
||||||
DynGroup::F => unsafe { &(*Portf::ptr()) },
|
DynGroup::F => unsafe { &(*Self::PORTF) },
|
||||||
DynGroup::G => unsafe { &(*Portg::ptr()) },
|
DynGroup::G => unsafe { &(*Self::PORTG) },
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -9,10 +9,8 @@ use core::convert::Infallible;
|
|||||||
use core::marker::PhantomData;
|
use core::marker::PhantomData;
|
||||||
|
|
||||||
use crate::pac;
|
use crate::pac;
|
||||||
use crate::time::Hertz;
|
|
||||||
pub use crate::timer::ValidTim;
|
|
||||||
use crate::timer::{TimAndPinRegister, TimDynRegister, TimPin, TimRegInterface, ValidTimAndPin};
|
|
||||||
use crate::{clock::Clocks, gpio::DynPinId};
|
use crate::{clock::Clocks, gpio::DynPinId};
|
||||||
|
pub use crate::{gpio::PinId, time::Hertz, timer::*};
|
||||||
|
|
||||||
const DUTY_MAX: u16 = u16::MAX;
|
const DUTY_MAX: u16 = u16::MAX;
|
||||||
|
|
||||||
|
@ -1,15 +1,11 @@
|
|||||||
//! API for the SPI peripheral
|
//! API for the SPI peripheral
|
||||||
//!
|
//!
|
||||||
//! The main abstraction provided by this module are the [Spi] and the [SpiBase] structure.
|
|
||||||
//! These provide the [embedded_hal::spi] traits, but also offer a low level interface
|
|
||||||
//! via the [SpiLowLevel] trait.
|
|
||||||
//!
|
|
||||||
//! ## Examples
|
//! ## Examples
|
||||||
//!
|
//!
|
||||||
//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/spi.rs)
|
//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/spi.rs)
|
||||||
use core::{convert::Infallible, marker::PhantomData, ops::Deref};
|
use core::{convert::Infallible, marker::PhantomData, ops::Deref};
|
||||||
|
|
||||||
use embedded_hal::spi::{Mode, MODE_0};
|
use embedded_hal::spi::Mode;
|
||||||
|
|
||||||
use crate::{
|
use crate::{
|
||||||
clock::{Clocks, PeripheralSelect, SyscfgExt},
|
clock::{Clocks, PeripheralSelect, SyscfgExt},
|
||||||
@ -255,9 +251,6 @@ pub struct TransferConfig {
|
|||||||
/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
|
/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
|
||||||
/// duration of multiple data words
|
/// duration of multiple data words
|
||||||
pub blockmode: bool,
|
pub blockmode: bool,
|
||||||
/// Only used when blockmode is used. The SCK will be stalled until an explicit stop bit
|
|
||||||
/// is set on a written word.
|
|
||||||
pub bmstall: bool,
|
|
||||||
pub hw_cs: HwChipSelectId,
|
pub hw_cs: HwChipSelectId,
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -266,7 +259,6 @@ impl TransferConfigWithHwcs<NoneT> {
|
|||||||
clk_cfg: Option<SpiClkConfig>,
|
clk_cfg: Option<SpiClkConfig>,
|
||||||
mode: Option<Mode>,
|
mode: Option<Mode>,
|
||||||
blockmode: bool,
|
blockmode: bool,
|
||||||
bmstall: bool,
|
|
||||||
sod: bool,
|
sod: bool,
|
||||||
) -> Self {
|
) -> Self {
|
||||||
TransferConfigWithHwcs {
|
TransferConfigWithHwcs {
|
||||||
@ -276,7 +268,6 @@ impl TransferConfigWithHwcs<NoneT> {
|
|||||||
mode,
|
mode,
|
||||||
sod,
|
sod,
|
||||||
blockmode,
|
blockmode,
|
||||||
bmstall,
|
|
||||||
hw_cs: HwChipSelectId::Invalid,
|
hw_cs: HwChipSelectId::Invalid,
|
||||||
},
|
},
|
||||||
}
|
}
|
||||||
@ -289,7 +280,6 @@ impl<HwCs: HwCsProvider> TransferConfigWithHwcs<HwCs> {
|
|||||||
mode: Option<Mode>,
|
mode: Option<Mode>,
|
||||||
hw_cs: Option<HwCs>,
|
hw_cs: Option<HwCs>,
|
||||||
blockmode: bool,
|
blockmode: bool,
|
||||||
bmstall: bool,
|
|
||||||
sod: bool,
|
sod: bool,
|
||||||
) -> Self {
|
) -> Self {
|
||||||
TransferConfigWithHwcs {
|
TransferConfigWithHwcs {
|
||||||
@ -299,7 +289,6 @@ impl<HwCs: HwCsProvider> TransferConfigWithHwcs<HwCs> {
|
|||||||
mode,
|
mode,
|
||||||
sod,
|
sod,
|
||||||
blockmode,
|
blockmode,
|
||||||
bmstall,
|
|
||||||
hw_cs: HwCs::CS_ID,
|
hw_cs: HwCs::CS_ID,
|
||||||
},
|
},
|
||||||
}
|
}
|
||||||
@ -336,15 +325,6 @@ impl<HwCs: HwCsProvider> TransferConfigProvider for TransferConfigWithHwcs<HwCs>
|
|||||||
/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
|
/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
|
||||||
pub struct SpiConfig {
|
pub struct SpiConfig {
|
||||||
clk: SpiClkConfig,
|
clk: SpiClkConfig,
|
||||||
// SPI mode configuration
|
|
||||||
pub init_mode: Mode,
|
|
||||||
/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
|
|
||||||
/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
|
|
||||||
/// duration of multiple data words. Defaults to true.
|
|
||||||
pub blockmode: bool,
|
|
||||||
/// This enables the stalling of the SPI SCK if in blockmode and the FIFO is empty.
|
|
||||||
/// Currently enabled by default.
|
|
||||||
pub bmstall: bool,
|
|
||||||
/// By default, configure SPI for master mode (ms == false)
|
/// By default, configure SPI for master mode (ms == false)
|
||||||
ms: bool,
|
ms: bool,
|
||||||
/// Slave output disable. Useful if separate GPIO pins or decoders are used for CS control
|
/// Slave output disable. Useful if separate GPIO pins or decoders are used for CS control
|
||||||
@ -358,9 +338,6 @@ pub struct SpiConfig {
|
|||||||
impl Default for SpiConfig {
|
impl Default for SpiConfig {
|
||||||
fn default() -> Self {
|
fn default() -> Self {
|
||||||
Self {
|
Self {
|
||||||
init_mode: MODE_0,
|
|
||||||
blockmode: true,
|
|
||||||
bmstall: true,
|
|
||||||
// Default value is definitely valid.
|
// Default value is definitely valid.
|
||||||
clk: SpiClkConfig::from_div(DEFAULT_CLK_DIV).unwrap(),
|
clk: SpiClkConfig::from_div(DEFAULT_CLK_DIV).unwrap(),
|
||||||
ms: Default::default(),
|
ms: Default::default(),
|
||||||
@ -377,21 +354,6 @@ impl SpiConfig {
|
|||||||
self
|
self
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn blockmode(mut self, enable: bool) -> Self {
|
|
||||||
self.blockmode = enable;
|
|
||||||
self
|
|
||||||
}
|
|
||||||
|
|
||||||
pub fn bmstall(mut self, enable: bool) -> Self {
|
|
||||||
self.bmstall = enable;
|
|
||||||
self
|
|
||||||
}
|
|
||||||
|
|
||||||
pub fn mode(mut self, mode: Mode) -> Self {
|
|
||||||
self.init_mode = mode;
|
|
||||||
self
|
|
||||||
}
|
|
||||||
|
|
||||||
pub fn clk_cfg(mut self, clk_cfg: SpiClkConfig) -> Self {
|
pub fn clk_cfg(mut self, clk_cfg: SpiClkConfig) -> Self {
|
||||||
self.clk = clk_cfg;
|
self.clk = clk_cfg;
|
||||||
self
|
self
|
||||||
@ -487,36 +449,6 @@ impl Instance for pac::Spi3 {
|
|||||||
// Spi
|
// Spi
|
||||||
//==================================================================================================
|
//==================================================================================================
|
||||||
|
|
||||||
/// Low level access trait for the SPI peripheral.
|
|
||||||
pub trait SpiLowLevel {
|
|
||||||
/// Low level function to write a word to the SPI FIFO but also checks whether
|
|
||||||
/// there is actually data in the FIFO.
|
|
||||||
///
|
|
||||||
/// Uses the [nb] API to allow usage in blocking and non-blocking contexts.
|
|
||||||
fn write_fifo(&self, data: u32) -> nb::Result<(), Infallible>;
|
|
||||||
|
|
||||||
/// Low level function to write a word to the SPI FIFO without checking whether
|
|
||||||
/// there FIFO is full.
|
|
||||||
///
|
|
||||||
/// This does not necesarily mean there is a space in the FIFO available.
|
|
||||||
/// Use [Self::write_fifo] function to write a word into the FIFO reliably.
|
|
||||||
fn write_fifo_unchecked(&self, data: u32);
|
|
||||||
|
|
||||||
/// Low level function to read a word from the SPI FIFO. Must be preceeded by a
|
|
||||||
/// [Self::write_fifo] call.
|
|
||||||
///
|
|
||||||
/// Uses the [nb] API to allow usage in blocking and non-blocking contexts.
|
|
||||||
fn read_fifo(&self) -> nb::Result<u32, Infallible>;
|
|
||||||
|
|
||||||
/// Low level function to read a word from from the SPI FIFO.
|
|
||||||
///
|
|
||||||
/// This does not necesarily mean there is a word in the FIFO available.
|
|
||||||
/// Use the [Self::read_fifo] function to read a word from the FIFO reliably using the [nb]
|
|
||||||
/// API.
|
|
||||||
/// You might also need to mask the value to ignore the BMSTART/BMSTOP bit.
|
|
||||||
fn read_fifo_unchecked(&self) -> u32;
|
|
||||||
}
|
|
||||||
|
|
||||||
pub struct SpiBase<SpiInstance, Word = u8> {
|
pub struct SpiBase<SpiInstance, Word = u8> {
|
||||||
spi: SpiInstance,
|
spi: SpiInstance,
|
||||||
cfg: SpiConfig,
|
cfg: SpiConfig,
|
||||||
@ -524,7 +456,6 @@ pub struct SpiBase<SpiInstance, Word = u8> {
|
|||||||
/// Fill word for read-only SPI transactions.
|
/// Fill word for read-only SPI transactions.
|
||||||
pub fill_word: Word,
|
pub fill_word: Word,
|
||||||
blockmode: bool,
|
blockmode: bool,
|
||||||
bmstall: bool,
|
|
||||||
word: PhantomData<Word>,
|
word: PhantomData<Word>,
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -673,7 +604,7 @@ where
|
|||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn spi(&self) -> &SpiInstance {
|
pub fn spi_instance(&self) -> &SpiInstance {
|
||||||
&self.spi
|
&self.spi
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -722,7 +653,7 @@ where
|
|||||||
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiInstance>>(
|
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiInstance>>(
|
||||||
&mut self,
|
&mut self,
|
||||||
transfer_cfg: &TransferConfigWithHwcs<HwCs>,
|
transfer_cfg: &TransferConfigWithHwcs<HwCs>,
|
||||||
) {
|
) -> Result<(), SpiClkConfigError> {
|
||||||
if let Some(trans_clk_div) = transfer_cfg.cfg.clk_cfg {
|
if let Some(trans_clk_div) = transfer_cfg.cfg.clk_cfg {
|
||||||
self.cfg_clock(trans_clk_div);
|
self.cfg_clock(trans_clk_div);
|
||||||
}
|
}
|
||||||
@ -741,57 +672,16 @@ where
|
|||||||
} else {
|
} else {
|
||||||
w.sod().clear_bit();
|
w.sod().clear_bit();
|
||||||
}
|
}
|
||||||
w.blockmode().bit(transfer_cfg.cfg.blockmode);
|
if transfer_cfg.cfg.blockmode {
|
||||||
w.bmstall().bit(transfer_cfg.cfg.bmstall)
|
w.blockmode().set_bit();
|
||||||
|
} else {
|
||||||
|
w.blockmode().clear_bit();
|
||||||
|
}
|
||||||
|
w
|
||||||
});
|
});
|
||||||
}
|
|
||||||
|
|
||||||
/// Low level function to write a word to the SPI FIFO but also checks whether
|
|
||||||
/// there is actually data in the FIFO.
|
|
||||||
///
|
|
||||||
/// Uses the [nb] API to allow usage in blocking and non-blocking contexts.
|
|
||||||
#[inline(always)]
|
|
||||||
pub fn write_fifo(&self, data: u32) -> nb::Result<(), Infallible> {
|
|
||||||
if self.spi.status().read().tnf().bit_is_clear() {
|
|
||||||
return Err(nb::Error::WouldBlock);
|
|
||||||
}
|
|
||||||
self.write_fifo_unchecked(data);
|
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Low level function to write a word to the SPI FIFO without checking whether
|
|
||||||
/// there FIFO is full.
|
|
||||||
///
|
|
||||||
/// This does not necesarily mean there is a space in the FIFO available.
|
|
||||||
/// Use [Self::write_fifo] function to write a word into the FIFO reliably.
|
|
||||||
#[inline(always)]
|
|
||||||
pub fn write_fifo_unchecked(&self, data: u32) {
|
|
||||||
self.spi.data().write(|w| unsafe { w.bits(data) });
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Low level function to read a word from the SPI FIFO. Must be preceeded by a
|
|
||||||
/// [Self::write_fifo] call.
|
|
||||||
///
|
|
||||||
/// Uses the [nb] API to allow usage in blocking and non-blocking contexts.
|
|
||||||
#[inline(always)]
|
|
||||||
pub fn read_fifo(&self) -> nb::Result<u32, Infallible> {
|
|
||||||
if self.spi.status().read().rne().bit_is_clear() {
|
|
||||||
return Err(nb::Error::WouldBlock);
|
|
||||||
}
|
|
||||||
Ok(self.read_fifo_unchecked())
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Low level function to read a word from from the SPI FIFO.
|
|
||||||
///
|
|
||||||
/// This does not necesarily mean there is a word in the FIFO available.
|
|
||||||
/// Use the [Self::read_fifo] function to read a word from the FIFO reliably using the [nb]
|
|
||||||
/// API.
|
|
||||||
/// You might also need to mask the value to ignore the BMSTART/BMSTOP bit.
|
|
||||||
#[inline(always)]
|
|
||||||
pub fn read_fifo_unchecked(&self) -> u32 {
|
|
||||||
self.spi.data().read().bits()
|
|
||||||
}
|
|
||||||
|
|
||||||
fn flush_internal(&self) {
|
fn flush_internal(&self) {
|
||||||
let mut status_reg = self.spi.status().read();
|
let mut status_reg = self.spi.status().read();
|
||||||
while status_reg.tfe().bit_is_clear()
|
while status_reg.tfe().bit_is_clear()
|
||||||
@ -799,12 +689,40 @@ where
|
|||||||
|| status_reg.busy().bit_is_set()
|
|| status_reg.busy().bit_is_set()
|
||||||
{
|
{
|
||||||
if status_reg.rne().bit_is_set() {
|
if status_reg.rne().bit_is_set() {
|
||||||
self.read_fifo_unchecked();
|
self.read_single_word();
|
||||||
}
|
}
|
||||||
status_reg = self.spi.status().read();
|
status_reg = self.spi.status().read();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/// Sends a word to the slave
|
||||||
|
#[inline(always)]
|
||||||
|
fn send_blocking(&self, word: Word) {
|
||||||
|
// TODO: Upper limit for wait cycles to avoid complete hangups?
|
||||||
|
while self.spi.status().read().tnf().bit_is_clear() {}
|
||||||
|
self.send(word)
|
||||||
|
}
|
||||||
|
|
||||||
|
#[inline(always)]
|
||||||
|
fn send(&self, word: Word) {
|
||||||
|
self.spi.data().write(|w| unsafe { w.bits(word.into()) });
|
||||||
|
}
|
||||||
|
|
||||||
|
/// Read a word from the slave. Must be preceeded by a [`send`](Self::send) call
|
||||||
|
#[inline(always)]
|
||||||
|
fn read_blocking(&self) -> Word {
|
||||||
|
// TODO: Upper limit for wait cycles to avoid complete hangups?
|
||||||
|
while self.spi.status().read().rne().bit_is_clear() {}
|
||||||
|
self.read_single_word()
|
||||||
|
}
|
||||||
|
|
||||||
|
#[inline(always)]
|
||||||
|
fn read_single_word(&self) -> Word {
|
||||||
|
(self.spi.data().read().bits() & Word::MASK)
|
||||||
|
.try_into()
|
||||||
|
.unwrap()
|
||||||
|
}
|
||||||
|
|
||||||
fn transfer_preparation(&self, words: &[Word]) -> Result<(), Infallible> {
|
fn transfer_preparation(&self, words: &[Word]) -> Result<(), Infallible> {
|
||||||
if words.is_empty() {
|
if words.is_empty() {
|
||||||
return Ok(());
|
return Ok(());
|
||||||
@ -813,21 +731,15 @@ where
|
|||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
// The FIFO can hold a guaranteed amount of data, so we can pump it on transfer
|
// Returns the actual bytes sent.
|
||||||
// initialization. Returns the amount of written bytes.
|
|
||||||
fn initial_send_fifo_pumping_with_words(&self, words: &[Word]) -> usize {
|
fn initial_send_fifo_pumping_with_words(&self, words: &[Word]) -> usize {
|
||||||
if self.blockmode {
|
if self.blockmode {
|
||||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
|
self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
|
||||||
}
|
}
|
||||||
// Fill the first half of the write FIFO
|
// Fill the first half of the write FIFO
|
||||||
let mut current_write_idx = 0;
|
let mut current_write_idx = 0;
|
||||||
let smaller_idx = core::cmp::min(FILL_DEPTH, words.len());
|
for _ in 0..core::cmp::min(FILL_DEPTH, words.len()) {
|
||||||
for _ in 0..smaller_idx {
|
self.send_blocking(words[current_write_idx]);
|
||||||
if current_write_idx == smaller_idx.saturating_sub(1) && self.bmstall {
|
|
||||||
self.write_fifo_unchecked(words[current_write_idx].into() | BMSTART_BMSTOP_MASK);
|
|
||||||
} else {
|
|
||||||
self.write_fifo_unchecked(words[current_write_idx].into());
|
|
||||||
}
|
|
||||||
current_write_idx += 1;
|
current_write_idx += 1;
|
||||||
}
|
}
|
||||||
if self.blockmode {
|
if self.blockmode {
|
||||||
@ -836,21 +748,14 @@ where
|
|||||||
current_write_idx
|
current_write_idx
|
||||||
}
|
}
|
||||||
|
|
||||||
// The FIFO can hold a guaranteed amount of data, so we can pump it on transfer
|
|
||||||
// initialization.
|
|
||||||
fn initial_send_fifo_pumping_with_fill_words(&self, send_len: usize) -> usize {
|
fn initial_send_fifo_pumping_with_fill_words(&self, send_len: usize) -> usize {
|
||||||
if self.blockmode {
|
if self.blockmode {
|
||||||
self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
|
self.spi.ctrl1().modify(|_, w| w.mtxpause().set_bit())
|
||||||
}
|
}
|
||||||
// Fill the first half of the write FIFO
|
// Fill the first half of the write FIFO
|
||||||
let mut current_write_idx = 0;
|
let mut current_write_idx = 0;
|
||||||
let smaller_idx = core::cmp::min(FILL_DEPTH, send_len);
|
for _ in 0..core::cmp::min(FILL_DEPTH, send_len) {
|
||||||
for _ in 0..smaller_idx {
|
self.send_blocking(self.fill_word);
|
||||||
if current_write_idx == smaller_idx.saturating_sub(1) && self.bmstall {
|
|
||||||
self.write_fifo_unchecked(self.fill_word.into() | BMSTART_BMSTOP_MASK);
|
|
||||||
} else {
|
|
||||||
self.write_fifo_unchecked(self.fill_word.into());
|
|
||||||
}
|
|
||||||
current_write_idx += 1;
|
current_write_idx += 1;
|
||||||
}
|
}
|
||||||
if self.blockmode {
|
if self.blockmode {
|
||||||
@ -860,148 +765,6 @@ where
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
impl<SpiInstance: Instance, Word: WordProvider> SpiLowLevel for SpiBase<SpiInstance, Word>
|
|
||||||
where
|
|
||||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
|
||||||
{
|
|
||||||
#[inline(always)]
|
|
||||||
fn write_fifo(&self, data: u32) -> nb::Result<(), Infallible> {
|
|
||||||
if self.spi.status().read().tnf().bit_is_clear() {
|
|
||||||
return Err(nb::Error::WouldBlock);
|
|
||||||
}
|
|
||||||
self.write_fifo_unchecked(data);
|
|
||||||
Ok(())
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline(always)]
|
|
||||||
fn write_fifo_unchecked(&self, data: u32) {
|
|
||||||
self.spi.data().write(|w| unsafe { w.bits(data) });
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline(always)]
|
|
||||||
fn read_fifo(&self) -> nb::Result<u32, Infallible> {
|
|
||||||
if self.spi.status().read().rne().bit_is_clear() {
|
|
||||||
return Err(nb::Error::WouldBlock);
|
|
||||||
}
|
|
||||||
Ok(self.read_fifo_unchecked())
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline(always)]
|
|
||||||
fn read_fifo_unchecked(&self) -> u32 {
|
|
||||||
self.spi.data().read().bits()
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<SpiI: Instance, Word: WordProvider> embedded_hal::spi::ErrorType for SpiBase<SpiI, Word> {
|
|
||||||
type Error = Infallible;
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<SpiI: Instance, Word: WordProvider> embedded_hal::spi::SpiBus<Word> for SpiBase<SpiI, Word>
|
|
||||||
where
|
|
||||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
|
||||||
{
|
|
||||||
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
|
||||||
self.transfer_preparation(words)?;
|
|
||||||
let mut current_read_idx = 0;
|
|
||||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_fill_words(words.len());
|
|
||||||
loop {
|
|
||||||
if current_read_idx < words.len() {
|
|
||||||
words[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK)
|
|
||||||
.try_into()
|
|
||||||
.unwrap();
|
|
||||||
current_read_idx += 1;
|
|
||||||
}
|
|
||||||
if current_write_idx < words.len() {
|
|
||||||
if current_write_idx == words.len() - 1 && self.bmstall {
|
|
||||||
nb::block!(self.write_fifo(self.fill_word.into() | BMSTART_BMSTOP_MASK))?;
|
|
||||||
} else {
|
|
||||||
nb::block!(self.write_fifo(self.fill_word.into()))?;
|
|
||||||
}
|
|
||||||
current_write_idx += 1;
|
|
||||||
}
|
|
||||||
if current_read_idx >= words.len() && current_write_idx >= words.len() {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
Ok(())
|
|
||||||
}
|
|
||||||
|
|
||||||
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
|
|
||||||
self.transfer_preparation(words)?;
|
|
||||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
|
|
||||||
while current_write_idx < words.len() {
|
|
||||||
if current_write_idx == words.len() - 1 && self.bmstall {
|
|
||||||
nb::block!(self.write_fifo(words[current_write_idx].into() | BMSTART_BMSTOP_MASK))?;
|
|
||||||
} else {
|
|
||||||
nb::block!(self.write_fifo(words[current_write_idx].into()))?;
|
|
||||||
}
|
|
||||||
current_write_idx += 1;
|
|
||||||
// Ignore received words.
|
|
||||||
if self.spi.status().read().rne().bit_is_set() {
|
|
||||||
self.clear_rx_fifo();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
Ok(())
|
|
||||||
}
|
|
||||||
|
|
||||||
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
|
|
||||||
self.transfer_preparation(write)?;
|
|
||||||
let mut current_read_idx = 0;
|
|
||||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(write);
|
|
||||||
while current_read_idx < read.len() || current_write_idx < write.len() {
|
|
||||||
if current_write_idx < write.len() {
|
|
||||||
if current_write_idx == write.len() - 1 && self.bmstall {
|
|
||||||
nb::block!(
|
|
||||||
self.write_fifo(write[current_write_idx].into() | BMSTART_BMSTOP_MASK)
|
|
||||||
)?;
|
|
||||||
} else {
|
|
||||||
nb::block!(self.write_fifo(write[current_write_idx].into()))?;
|
|
||||||
}
|
|
||||||
current_write_idx += 1;
|
|
||||||
}
|
|
||||||
if current_read_idx < read.len() {
|
|
||||||
read[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK)
|
|
||||||
.try_into()
|
|
||||||
.unwrap();
|
|
||||||
current_read_idx += 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
Ok(())
|
|
||||||
}
|
|
||||||
|
|
||||||
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
|
||||||
self.transfer_preparation(words)?;
|
|
||||||
let mut current_read_idx = 0;
|
|
||||||
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
|
|
||||||
|
|
||||||
while current_read_idx < words.len() || current_write_idx < words.len() {
|
|
||||||
if current_write_idx < words.len() {
|
|
||||||
if current_write_idx == words.len() - 1 && self.bmstall {
|
|
||||||
nb::block!(
|
|
||||||
self.write_fifo(words[current_write_idx].into() | BMSTART_BMSTOP_MASK)
|
|
||||||
)?;
|
|
||||||
} else {
|
|
||||||
nb::block!(self.write_fifo(words[current_write_idx].into()))?;
|
|
||||||
}
|
|
||||||
current_write_idx += 1;
|
|
||||||
}
|
|
||||||
if current_read_idx < words.len() && current_read_idx < current_write_idx {
|
|
||||||
words[current_read_idx] = (nb::block!(self.read_fifo())? & Word::MASK)
|
|
||||||
.try_into()
|
|
||||||
.unwrap();
|
|
||||||
current_read_idx += 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
Ok(())
|
|
||||||
}
|
|
||||||
|
|
||||||
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
||||||
self.flush_internal();
|
|
||||||
Ok(())
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<
|
impl<
|
||||||
SpiI: Instance,
|
SpiI: Instance,
|
||||||
Sck: PinSck<SpiI>,
|
Sck: PinSck<SpiI>,
|
||||||
@ -1033,20 +796,31 @@ where
|
|||||||
spi: SpiI,
|
spi: SpiI,
|
||||||
pins: (Sck, Miso, Mosi),
|
pins: (Sck, Miso, Mosi),
|
||||||
spi_cfg: SpiConfig,
|
spi_cfg: SpiConfig,
|
||||||
) -> Self {
|
transfer_cfg: Option<&TransferConfig>,
|
||||||
|
) -> Result<Self, SpiClkConfigError> {
|
||||||
crate::clock::enable_peripheral_clock(syscfg, SpiI::PERIPH_SEL);
|
crate::clock::enable_peripheral_clock(syscfg, SpiI::PERIPH_SEL);
|
||||||
// This is done in the C HAL.
|
// This is done in the C HAL.
|
||||||
syscfg.assert_periph_reset_for_two_cycles(SpiI::PERIPH_SEL);
|
syscfg.assert_periph_reset_for_two_cycles(SpiI::PERIPH_SEL);
|
||||||
let SpiConfig {
|
let SpiConfig {
|
||||||
clk,
|
clk,
|
||||||
init_mode,
|
|
||||||
blockmode,
|
|
||||||
bmstall,
|
|
||||||
ms,
|
ms,
|
||||||
slave_output_disable,
|
slave_output_disable,
|
||||||
loopback_mode,
|
loopback_mode,
|
||||||
master_delayer_capture,
|
master_delayer_capture,
|
||||||
} = spi_cfg;
|
} = spi_cfg;
|
||||||
|
let mut init_mode = embedded_hal::spi::MODE_0;
|
||||||
|
let mut ss = 0;
|
||||||
|
let mut init_blockmode = false;
|
||||||
|
let apb1_clk = clocks.apb1();
|
||||||
|
if let Some(transfer_cfg) = transfer_cfg {
|
||||||
|
if let Some(mode) = transfer_cfg.mode {
|
||||||
|
init_mode = mode;
|
||||||
|
}
|
||||||
|
if transfer_cfg.hw_cs != HwChipSelectId::Invalid {
|
||||||
|
ss = transfer_cfg.hw_cs as u8;
|
||||||
|
}
|
||||||
|
init_blockmode = transfer_cfg.blockmode;
|
||||||
|
}
|
||||||
|
|
||||||
let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(init_mode);
|
let (cpo_bit, cph_bit) = mode_to_cpo_cph_bit(init_mode);
|
||||||
spi.ctrl0().write(|w| {
|
spi.ctrl0().write(|w| {
|
||||||
@ -1059,15 +833,13 @@ where
|
|||||||
w.sph().bit(cph_bit)
|
w.sph().bit(cph_bit)
|
||||||
}
|
}
|
||||||
});
|
});
|
||||||
|
|
||||||
spi.ctrl1().write(|w| {
|
spi.ctrl1().write(|w| {
|
||||||
w.lbm().bit(loopback_mode);
|
w.lbm().bit(loopback_mode);
|
||||||
w.sod().bit(slave_output_disable);
|
w.sod().bit(slave_output_disable);
|
||||||
w.ms().bit(ms);
|
w.ms().bit(ms);
|
||||||
w.mdlycap().bit(master_delayer_capture);
|
w.mdlycap().bit(master_delayer_capture);
|
||||||
w.blockmode().bit(blockmode);
|
w.blockmode().bit(init_blockmode);
|
||||||
w.bmstall().bit(bmstall);
|
unsafe { w.ss().bits(ss) }
|
||||||
unsafe { w.ss().bits(0) }
|
|
||||||
});
|
});
|
||||||
spi.clkprescale()
|
spi.clkprescale()
|
||||||
.write(|w| unsafe { w.bits(clk.prescale_val as u32) });
|
.write(|w| unsafe { w.bits(clk.prescale_val as u32) });
|
||||||
@ -1079,18 +851,17 @@ where
|
|||||||
// Enable the peripheral as the last step as recommended in the
|
// Enable the peripheral as the last step as recommended in the
|
||||||
// programmers guide
|
// programmers guide
|
||||||
spi.ctrl1().modify(|_, w| w.enable().set_bit());
|
spi.ctrl1().modify(|_, w| w.enable().set_bit());
|
||||||
Spi {
|
Ok(Spi {
|
||||||
inner: SpiBase {
|
inner: SpiBase {
|
||||||
spi,
|
spi,
|
||||||
cfg: spi_cfg,
|
cfg: spi_cfg,
|
||||||
apb1_clk: clocks.apb1(),
|
apb1_clk,
|
||||||
fill_word: Default::default(),
|
fill_word: Default::default(),
|
||||||
bmstall,
|
blockmode: init_blockmode,
|
||||||
blockmode,
|
|
||||||
word: PhantomData,
|
word: PhantomData,
|
||||||
},
|
},
|
||||||
pins,
|
pins,
|
||||||
}
|
})
|
||||||
}
|
}
|
||||||
|
|
||||||
delegate::delegate! {
|
delegate::delegate! {
|
||||||
@ -1102,7 +873,7 @@ where
|
|||||||
pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError>;
|
pub fn cfg_clock_from_div(&mut self, div: u16) -> Result<(), SpiClkConfigError>;
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn spi(&self) -> &SpiI;
|
pub fn spi_instance(&self) -> &SpiI;
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn cfg_mode(&mut self, mode: Mode);
|
pub fn cfg_mode(&mut self, mode: Mode);
|
||||||
@ -1112,7 +883,7 @@ where
|
|||||||
|
|
||||||
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiI>>(
|
pub fn cfg_transfer<HwCs: OptionalHwCs<SpiI>>(
|
||||||
&mut self, transfer_cfg: &TransferConfigWithHwcs<HwCs>
|
&mut self, transfer_cfg: &TransferConfigWithHwcs<HwCs>
|
||||||
);
|
) -> Result<(), SpiClkConfigError>;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1136,58 +907,6 @@ where
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
impl<
|
|
||||||
SpiI: Instance,
|
|
||||||
Sck: PinSck<SpiI>,
|
|
||||||
Miso: PinMiso<SpiI>,
|
|
||||||
Mosi: PinMosi<SpiI>,
|
|
||||||
Word: WordProvider,
|
|
||||||
> SpiLowLevel for Spi<SpiI, (Sck, Miso, Mosi), Word>
|
|
||||||
where
|
|
||||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
|
||||||
{
|
|
||||||
delegate::delegate! {
|
|
||||||
to self.inner {
|
|
||||||
fn write_fifo(&self, data: u32) -> nb::Result<(), Infallible>;
|
|
||||||
fn write_fifo_unchecked(&self, data: u32);
|
|
||||||
fn read_fifo(&self) -> nb::Result<u32, Infallible>;
|
|
||||||
fn read_fifo_unchecked(&self) -> u32;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<
|
|
||||||
SpiI: Instance,
|
|
||||||
Word: WordProvider,
|
|
||||||
Sck: PinSck<SpiI>,
|
|
||||||
Miso: PinMiso<SpiI>,
|
|
||||||
Mosi: PinMosi<SpiI>,
|
|
||||||
> embedded_hal::spi::ErrorType for Spi<SpiI, (Sck, Miso, Mosi), Word>
|
|
||||||
{
|
|
||||||
type Error = Infallible;
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<
|
|
||||||
SpiI: Instance,
|
|
||||||
Word: WordProvider,
|
|
||||||
Sck: PinSck<SpiI>,
|
|
||||||
Miso: PinMiso<SpiI>,
|
|
||||||
Mosi: PinMosi<SpiI>,
|
|
||||||
> embedded_hal::spi::SpiBus<Word> for Spi<SpiI, (Sck, Miso, Mosi), Word>
|
|
||||||
where
|
|
||||||
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
|
||||||
{
|
|
||||||
delegate::delegate! {
|
|
||||||
to self.inner {
|
|
||||||
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error>;
|
|
||||||
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error>;
|
|
||||||
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error>;
|
|
||||||
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error>;
|
|
||||||
fn flush(&mut self) -> Result<(), Self::Error>;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Changing the word size also requires a type conversion
|
/// Changing the word size also requires a type conversion
|
||||||
impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>>
|
impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>>
|
||||||
From<Spi<SpiI, (Sck, Miso, Mosi), u8>> for Spi<SpiI, (Sck, Miso, Mosi), u16>
|
From<Spi<SpiI, (Sck, Miso, Mosi), u8>> for Spi<SpiI, (Sck, Miso, Mosi), u16>
|
||||||
@ -1203,7 +922,6 @@ impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>
|
|||||||
spi: old_spi.inner.spi,
|
spi: old_spi.inner.spi,
|
||||||
cfg: old_spi.inner.cfg,
|
cfg: old_spi.inner.cfg,
|
||||||
blockmode: old_spi.inner.blockmode,
|
blockmode: old_spi.inner.blockmode,
|
||||||
bmstall: old_spi.inner.bmstall,
|
|
||||||
fill_word: Default::default(),
|
fill_word: Default::default(),
|
||||||
apb1_clk: old_spi.inner.apb1_clk,
|
apb1_clk: old_spi.inner.apb1_clk,
|
||||||
word: PhantomData,
|
word: PhantomData,
|
||||||
@ -1228,7 +946,6 @@ impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>
|
|||||||
spi: old_spi.inner.spi,
|
spi: old_spi.inner.spi,
|
||||||
cfg: old_spi.inner.cfg,
|
cfg: old_spi.inner.cfg,
|
||||||
blockmode: old_spi.inner.blockmode,
|
blockmode: old_spi.inner.blockmode,
|
||||||
bmstall: old_spi.inner.bmstall,
|
|
||||||
apb1_clk: old_spi.inner.apb1_clk,
|
apb1_clk: old_spi.inner.apb1_clk,
|
||||||
fill_word: Default::default(),
|
fill_word: Default::default(),
|
||||||
word: PhantomData,
|
word: PhantomData,
|
||||||
@ -1237,3 +954,129 @@ impl<SpiI: Instance, Sck: PinSck<SpiI>, Miso: PinMiso<SpiI>, Mosi: PinMosi<SpiI>
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
impl<SpiI: Instance, Word: WordProvider> embedded_hal::spi::ErrorType for SpiBase<SpiI, Word> {
|
||||||
|
type Error = Infallible;
|
||||||
|
}
|
||||||
|
|
||||||
|
impl<SpiI: Instance, Word: WordProvider> embedded_hal::spi::SpiBus<Word> for SpiBase<SpiI, Word>
|
||||||
|
where
|
||||||
|
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||||
|
{
|
||||||
|
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||||
|
self.transfer_preparation(words)?;
|
||||||
|
let mut current_read_idx = 0;
|
||||||
|
let mut current_write_idx = self.initial_send_fifo_pumping_with_fill_words(words.len());
|
||||||
|
loop {
|
||||||
|
if current_write_idx < words.len() {
|
||||||
|
self.send_blocking(self.fill_word);
|
||||||
|
current_write_idx += 1;
|
||||||
|
}
|
||||||
|
if current_read_idx < words.len() {
|
||||||
|
words[current_read_idx] = self.read_blocking();
|
||||||
|
current_read_idx += 1;
|
||||||
|
}
|
||||||
|
if current_read_idx >= words.len() && current_write_idx >= words.len() {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
|
||||||
|
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
|
||||||
|
self.transfer_preparation(words)?;
|
||||||
|
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
|
||||||
|
while current_write_idx < words.len() {
|
||||||
|
self.send_blocking(words[current_write_idx]);
|
||||||
|
current_write_idx += 1;
|
||||||
|
// Ignore received words.
|
||||||
|
if self.spi.status().read().rne().bit_is_set() {
|
||||||
|
self.clear_rx_fifo();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
|
||||||
|
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
|
||||||
|
self.transfer_preparation(write)?;
|
||||||
|
let mut current_read_idx = 0;
|
||||||
|
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(write);
|
||||||
|
while current_read_idx < read.len() || current_write_idx < write.len() {
|
||||||
|
if current_write_idx < write.len() {
|
||||||
|
self.send_blocking(write[current_write_idx]);
|
||||||
|
current_write_idx += 1;
|
||||||
|
}
|
||||||
|
if current_read_idx < read.len() {
|
||||||
|
read[current_read_idx] = self.read_blocking();
|
||||||
|
current_read_idx += 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
|
||||||
|
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||||
|
self.transfer_preparation(words)?;
|
||||||
|
let mut current_read_idx = 0;
|
||||||
|
let mut current_write_idx = self.initial_send_fifo_pumping_with_words(words);
|
||||||
|
|
||||||
|
while current_read_idx < words.len() || current_write_idx < words.len() {
|
||||||
|
if current_write_idx < words.len() {
|
||||||
|
self.send_blocking(words[current_write_idx]);
|
||||||
|
current_write_idx += 1;
|
||||||
|
}
|
||||||
|
if current_read_idx < words.len() && current_read_idx < current_write_idx {
|
||||||
|
words[current_read_idx] = self.read_blocking();
|
||||||
|
current_read_idx += 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
|
||||||
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
||||||
|
self.flush_internal();
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
impl<
|
||||||
|
SpiI: Instance,
|
||||||
|
Word: WordProvider,
|
||||||
|
Sck: PinSck<SpiI>,
|
||||||
|
Miso: PinMiso<SpiI>,
|
||||||
|
Mosi: PinMosi<SpiI>,
|
||||||
|
> embedded_hal::spi::ErrorType for Spi<SpiI, (Sck, Miso, Mosi), Word>
|
||||||
|
{
|
||||||
|
type Error = Infallible;
|
||||||
|
}
|
||||||
|
|
||||||
|
impl<
|
||||||
|
SpiI: Instance,
|
||||||
|
Word: WordProvider,
|
||||||
|
Sck: PinSck<SpiI>,
|
||||||
|
Miso: PinMiso<SpiI>,
|
||||||
|
Mosi: PinMosi<SpiI>,
|
||||||
|
> embedded_hal::spi::SpiBus<Word> for Spi<SpiI, (Sck, Miso, Mosi), Word>
|
||||||
|
where
|
||||||
|
<Word as TryFrom<u32>>::Error: core::fmt::Debug,
|
||||||
|
{
|
||||||
|
fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||||
|
self.inner.read(words)
|
||||||
|
}
|
||||||
|
|
||||||
|
fn write(&mut self, words: &[Word]) -> Result<(), Self::Error> {
|
||||||
|
self.inner.write(words)
|
||||||
|
}
|
||||||
|
|
||||||
|
fn transfer(&mut self, read: &mut [Word], write: &[Word]) -> Result<(), Self::Error> {
|
||||||
|
self.inner.transfer(read, write)
|
||||||
|
}
|
||||||
|
|
||||||
|
fn transfer_in_place(&mut self, words: &mut [Word]) -> Result<(), Self::Error> {
|
||||||
|
self.inner.transfer_in_place(words)
|
||||||
|
}
|
||||||
|
|
||||||
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
||||||
|
self.inner.flush()
|
||||||
|
}
|
||||||
|
}
|
||||||
|
File diff suppressed because it is too large
Load Diff
@ -1,13 +0,0 @@
|
|||||||
Change Log
|
|
||||||
=======
|
|
||||||
|
|
||||||
All notable changes to this project will be documented in this file.
|
|
||||||
|
|
||||||
The format is based on [Keep a Changelog](http://keepachangelog.com/)
|
|
||||||
and this project adheres to [Semantic Versioning](http://semver.org/).
|
|
||||||
|
|
||||||
# [unreleased]
|
|
||||||
|
|
||||||
# [v0.1.0] 2024-10-01
|
|
||||||
|
|
||||||
- Initial release
|
|
@ -16,10 +16,14 @@ cortex-m-rt = "0.7"
|
|||||||
embedded-hal = "1"
|
embedded-hal = "1"
|
||||||
|
|
||||||
[dependencies.va416xx-hal]
|
[dependencies.va416xx-hal]
|
||||||
|
path = "../va416xx-hal"
|
||||||
features = ["va41630"]
|
features = ["va41630"]
|
||||||
version = ">=0.3, <0.4"
|
version = "0.2.0"
|
||||||
|
|
||||||
[dependencies.lis2dh12]
|
[dependencies.lis2dh12]
|
||||||
|
git = "https://github.com/us-irs/lis2dh12.git"
|
||||||
|
# path = "../../lis2dh12"
|
||||||
|
branch = "all-features"
|
||||||
version = "0.7"
|
version = "0.7"
|
||||||
features = ["out_f32"]
|
features = ["out_f32"]
|
||||||
|
|
||||||
|
@ -1,12 +1,15 @@
|
|||||||
[](https://crates.io/crates/vorago-peb1)
|
|
||||||
[](https://docs.rs/vorago-peb1)
|
|
||||||
|
|
||||||
# Rust BSP for the Vorago PEB1 development board
|
# Rust BSP for the Vorago PEB1 development board
|
||||||
|
|
||||||
This is the Rust **B**oard **S**upport **P**ackage crate for the Vorago PEB1 development board.
|
## Using the `.cargo/config.toml` file
|
||||||
Its aim is to provide drivers for the board features of the PEB1 board.
|
|
||||||
|
|
||||||
The BSP builds on top of the [HAL crate for VA416xx devices](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx-hal).
|
Use the following command to have a starting `config.toml` file
|
||||||
|
|
||||||
|
```sh
|
||||||
|
cp .cargo/def-config.toml .cargo/config.toml
|
||||||
|
```
|
||||||
|
|
||||||
|
You then can adapt the `config.toml` to your needs. For example, you can configure runners
|
||||||
|
to conveniently flash with `cargo run`.
|
||||||
|
|
||||||
## Notes on board revisions
|
## Notes on board revisions
|
||||||
|
|
||||||
|
@ -5,10 +5,6 @@
|
|||||||
pub use lis2dh12;
|
pub use lis2dh12;
|
||||||
|
|
||||||
/// Support for the LIS2DH12 accelerometer on the GPIO board.
|
/// Support for the LIS2DH12 accelerometer on the GPIO board.
|
||||||
///
|
|
||||||
/// # Example
|
|
||||||
///
|
|
||||||
/// - [PEB1 Accelerometer](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/examples/simple/examples/peb1-accelerometer.rs)
|
|
||||||
pub mod accelerometer {
|
pub mod accelerometer {
|
||||||
|
|
||||||
use lis2dh12::{self, detect_i2c_addr, AddrDetectionError, Lis2dh12};
|
use lis2dh12::{self, detect_i2c_addr, AddrDetectionError, Lis2dh12};
|
||||||
|
@ -350,36 +350,6 @@
|
|||||||
]
|
]
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
{
|
|
||||||
"type": "cortex-debug",
|
|
||||||
"request": "launch",
|
|
||||||
"name": "UART Echo with IRQ",
|
|
||||||
"servertype": "jlink",
|
|
||||||
"jlinkscript": "${workspaceFolder}/jlink/JLinkSettings.JLinkScript",
|
|
||||||
"cwd": "${workspaceRoot}",
|
|
||||||
"device": "Cortex-M4",
|
|
||||||
"svdFile": "${workspaceFolder}/va416xx/svd/va416xx.svd.patched",
|
|
||||||
"preLaunchTask": "uart-echo-with-irq",
|
|
||||||
"overrideLaunchCommands": [
|
|
||||||
"monitor halt",
|
|
||||||
"monitor reset",
|
|
||||||
"load",
|
|
||||||
],
|
|
||||||
"executable": "${workspaceFolder}/target/thumbv7em-none-eabihf/debug/uart-echo-with-irq",
|
|
||||||
"interface": "swd",
|
|
||||||
"runToEntryPoint": "main",
|
|
||||||
"rttConfig": {
|
|
||||||
"enabled": true,
|
|
||||||
"address": "auto",
|
|
||||||
"decoders": [
|
|
||||||
{
|
|
||||||
"port": 0,
|
|
||||||
"timestamp": true,
|
|
||||||
"type": "console"
|
|
||||||
}
|
|
||||||
]
|
|
||||||
}
|
|
||||||
},
|
|
||||||
{
|
{
|
||||||
"type": "cortex-debug",
|
"type": "cortex-debug",
|
||||||
"request": "launch",
|
"request": "launch",
|
||||||
|
@ -95,19 +95,6 @@
|
|||||||
"kind": "build",
|
"kind": "build",
|
||||||
}
|
}
|
||||||
},
|
},
|
||||||
{
|
|
||||||
"label": "uart-echo-with-irq",
|
|
||||||
"type": "shell",
|
|
||||||
"command": "~/.cargo/bin/cargo", // note: full path to the cargo
|
|
||||||
"args": [
|
|
||||||
"build",
|
|
||||||
"--bin",
|
|
||||||
"uart-echo-with-irq"
|
|
||||||
],
|
|
||||||
"group": {
|
|
||||||
"kind": "build",
|
|
||||||
}
|
|
||||||
},
|
|
||||||
{
|
{
|
||||||
"label": "pwm-example",
|
"label": "pwm-example",
|
||||||
"type": "shell",
|
"type": "shell",
|
||||||
@ -213,4 +200,4 @@
|
|||||||
}
|
}
|
||||||
},
|
},
|
||||||
]
|
]
|
||||||
}
|
}
|
||||||
|
Reference in New Issue
Block a user